drivers/iommu/mtk_iommu_v1.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * IOMMU API for MTK architected m4u v1 implementations
   4  *
   5  * Copyright (c) 2015-2016 MediaTek Inc.
   6  * Author: Honghui Zhang <honghui.zhang@mediatek.com>
   7  *
   8  * Based on driver/iommu/mtk_iommu.c
   9  */
  10 #include <linux/bug.h>
  11 #include <linux/clk.h>
  12 #include <linux/component.h>
  13 #include <linux/device.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/err.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/iommu.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/list.h>
  21 #include <linux/module.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <linux/spinlock.h>
  28 #include <asm/barrier.h>
  29 #include <asm/dma-iommu.h>
  30 #include <dt-bindings/memory/mtk-memory-port.h>
  31 #include <dt-bindings/memory/mt2701-larb-port.h>
  32 #include <soc/mediatek/smi.h>
  33
  34 #define REG_MMU_PT_BASE_ADDR                    0x000
  35
  36 #define F_ALL_INVLD                             0x2
  37 #define F_MMU_INV_RANGE                         0x1
  38 #define F_INVLD_EN0                             BIT(0)
  39 #define F_INVLD_EN1                             BIT(1)
  40
  41 #define F_MMU_FAULT_VA_MSK                      0xfffff000
  42 #define MTK_PROTECT_PA_ALIGN                    128
  43
  44 #define REG_MMU_CTRL_REG                        0x210
  45 #define F_MMU_CTRL_COHERENT_EN                  BIT(8)
  46 #define REG_MMU_IVRP_PADDR                      0x214
  47 #define REG_MMU_INT_CONTROL                     0x220
  48 #define F_INT_TRANSLATION_FAULT                 BIT(0)
  49 #define F_INT_MAIN_MULTI_HIT_FAULT              BIT(1)
  50 #define F_INT_INVALID_PA_FAULT                  BIT(2)
  51 #define F_INT_ENTRY_REPLACEMENT_FAULT           BIT(3)
  52 #define F_INT_TABLE_WALK_FAULT                  BIT(4)
  53 #define F_INT_TLB_MISS_FAULT                    BIT(5)
  54 #define F_INT_PFH_DMA_FIFO_OVERFLOW             BIT(6)
  55 #define F_INT_MISS_DMA_FIFO_OVERFLOW            BIT(7)
  56
  57 #define F_MMU_TF_PROTECT_SEL(prot)              (((prot) & 0x3) << 5)
  58 #define F_INT_CLR_BIT                           BIT(12)
  59
  60 #define REG_MMU_FAULT_ST                        0x224
  61 #define REG_MMU_FAULT_VA                        0x228
  62 #define REG_MMU_INVLD_PA                        0x22C
  63 #define REG_MMU_INT_ID                          0x388
  64 #define REG_MMU_INVALIDATE                      0x5c0
  65 #define REG_MMU_INVLD_START_A                   0x5c4
  66 #define REG_MMU_INVLD_END_A                     0x5c8
  67
  68 #define REG_MMU_INV_SEL                         0x5d8
  69 #define REG_MMU_STANDARD_AXI_MODE               0x5e8
  70
  71 #define REG_MMU_DCM                             0x5f0
  72 #define F_MMU_DCM_ON                            BIT(1)
  73 #define REG_MMU_CPE_DONE                        0x60c
  74 #define F_DESC_VALID                            0x2
  75 #define F_DESC_NONSEC                           BIT(3)
  76 #define MT2701_M4U_TF_LARB(TF)                  (6 - (((TF) >> 13) & 0x7))
  77 #define MT2701_M4U_TF_PORT(TF)                  (((TF) >> 8) & 0xF)
  78 /* MTK generation one iommu HW only support 4K size mapping */
  79 #define MT2701_IOMMU_PAGE_SHIFT                 12
  80 #define MT2701_IOMMU_PAGE_SIZE                  (1UL << MT2701_IOMMU_PAGE_SHIFT)
  81 #define MT2701_LARB_NR_MAX                      3
  82
  83 /*
  84  * MTK m4u support 4GB iova address space, and only support 4K page
  85  * mapping. So the pagetable size should be exactly as 4M.
  86  */
  87 #define M2701_IOMMU_PGT_SIZE                    SZ_4M
  88
  89 struct mtk_iommu_v1_suspend_reg {
  90         u32                     standard_axi_mode;
  91         u32                     dcm_dis;
  92         u32                     ctrl_reg;
  93         u32                     int_control0;
  94 };
  95
  96 struct mtk_iommu_v1_data {
  97         void __iomem                    *base;
  98         int                             irq;
  99         struct device                   *dev;
 100         struct clk                      *bclk;
 101         phys_addr_t                     protect_base; /* protect memory base */
 102         struct mtk_iommu_v1_domain      *m4u_dom;
 103
 104         struct iommu_device             iommu;
 105         struct dma_iommu_mapping        *mapping;
 106         struct mtk_smi_larb_iommu       larb_imu[MTK_LARB_NR_MAX];
 107
 108         struct mtk_iommu_v1_suspend_reg reg;
 109 };
 110
 111 struct mtk_iommu_v1_domain {
 112         spinlock_t                      pgtlock; /* lock for page table */
 113         struct iommu_domain             domain;
 114         u32                             *pgt_va;
 115         dma_addr_t                      pgt_pa;
 116         struct mtk_iommu_v1_data        *data;
 117 };
 118
 119 static int mtk_iommu_v1_bind(struct device *dev)
 120 {
 121         struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
 122
 123         return component_bind_all(dev, &data->larb_imu);
 124 }
 125
 126 static void mtk_iommu_v1_unbind(struct device *dev)
 127 {
 128         struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
 129
 130         component_unbind_all(dev, &data->larb_imu);
 131 }
 132
 133 static struct mtk_iommu_v1_domain *to_mtk_domain(struct iommu_domain *dom)
 134 {
 135         return container_of(dom, struct mtk_iommu_v1_domain, domain);
 136 }
 137
 138 static const int mt2701_m4u_in_larb[] = {
 139         LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
 140         LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
 141 };
 142
 143 static inline int mt2701_m4u_to_larb(int id)
 144 {
 145         int i;
 146
 147         for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--)
 148                 if ((id) >= mt2701_m4u_in_larb[i])
 149                         return i;
 150
 151         return 0;
 152 }
 153
 154 static inline int mt2701_m4u_to_port(int id)
 155 {
 156         int larb = mt2701_m4u_to_larb(id);
 157
 158         return id - mt2701_m4u_in_larb[larb];
 159 }
 160
 161 static void mtk_iommu_v1_tlb_flush_all(struct mtk_iommu_v1_data *data)
 162 {
 163         writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 164                         data->base + REG_MMU_INV_SEL);
 165         writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
 166         wmb(); /* Make sure the tlb flush all done */
 167 }
 168
 169 static void mtk_iommu_v1_tlb_flush_range(struct mtk_iommu_v1_data *data,
 170                                          unsigned long iova, size_t size)
 171 {
 172         int ret;
 173         u32 tmp;
 174
 175         writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 176                 data->base + REG_MMU_INV_SEL);
 177         writel_relaxed(iova & F_MMU_FAULT_VA_MSK,
 178                 data->base + REG_MMU_INVLD_START_A);
 179         writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK,
 180                 data->base + REG_MMU_INVLD_END_A);
 181         writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
 182
 183         ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
 184                                 tmp, tmp != 0, 10, 100000);
 185         if (ret) {
 186                 dev_warn(data->dev,
 187                          "Partial TLB flush timed out, falling back to full flush\n");
 188                 mtk_iommu_v1_tlb_flush_all(data);
 189         }
 190         /* Clear the CPE status */
 191         writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
 192 }
 193
 194 static irqreturn_t mtk_iommu_v1_isr(int irq, void *dev_id)
 195 {
 196         struct mtk_iommu_v1_data *data = dev_id;
 197         struct mtk_iommu_v1_domain *dom = data->m4u_dom;
 198         u32 int_state, regval, fault_iova, fault_pa;
 199         unsigned int fault_larb, fault_port;
 200
 201         /* Read error information from registers */
 202         int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST);
 203         fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
 204
 205         fault_iova &= F_MMU_FAULT_VA_MSK;
 206         fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
 207         regval = readl_relaxed(data->base + REG_MMU_INT_ID);
 208         fault_larb = MT2701_M4U_TF_LARB(regval);
 209         fault_port = MT2701_M4U_TF_PORT(regval);
 210
 211         /*
 212          * MTK v1 iommu HW could not determine whether the fault is read or
 213          * write fault, report as read fault.
 214          */
 215         if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
 216                         IOMMU_FAULT_READ))
 217                 dev_err_ratelimited(data->dev,
 218                         "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n",
 219                         int_state, fault_iova, fault_pa,
 220                         fault_larb, fault_port);
 221
 222         /* Interrupt clear */
 223         regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL);
 224         regval |= F_INT_CLR_BIT;
 225         writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
 226
 227         mtk_iommu_v1_tlb_flush_all(data);
 228
 229         return IRQ_HANDLED;
 230 }
 231
 232 static void mtk_iommu_v1_config(struct mtk_iommu_v1_data *data,
 233                                 struct device *dev, bool enable)
 234 {
 235         struct mtk_smi_larb_iommu    *larb_mmu;
 236         unsigned int                 larbid, portid;
 237         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 238         int i;
 239
 240         for (i = 0; i < fwspec->num_ids; ++i) {
 241                 larbid = mt2701_m4u_to_larb(fwspec->ids[i]);
 242                 portid = mt2701_m4u_to_port(fwspec->ids[i]);
 243                 larb_mmu = &data->larb_imu[larbid];
 244
 245                 dev_dbg(dev, "%s iommu port: %d\n",
 246                         enable ? "enable" : "disable", portid);
 247
 248                 if (enable)
 249                         larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
 250                 else
 251                         larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
 252         }
 253 }
 254
 255 static int mtk_iommu_v1_domain_finalise(struct mtk_iommu_v1_data *data)
 256 {
 257         struct mtk_iommu_v1_domain *dom = data->m4u_dom;
 258
 259         spin_lock_init(&dom->pgtlock);
 260
 261         dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
 262                                          &dom->pgt_pa, GFP_KERNEL);
 263         if (!dom->pgt_va)
 264                 return -ENOMEM;
 265
 266         writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR);
 267
 268         dom->data = data;
 269
 270         return 0;
 271 }
 272
 273 static struct iommu_domain *mtk_iommu_v1_domain_alloc(unsigned type)
 274 {
 275         struct mtk_iommu_v1_domain *dom;
 276
 277         if (type != IOMMU_DOMAIN_UNMANAGED)
 278                 return NULL;
 279
 280         dom = kzalloc(sizeof(*dom), GFP_KERNEL);
 281         if (!dom)
 282                 return NULL;
 283
 284         return &dom->domain;
 285 }
 286
 287 static void mtk_iommu_v1_domain_free(struct iommu_domain *domain)
 288 {
 289         struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
 290         struct mtk_iommu_v1_data *data = dom->data;
 291
 292         dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
 293                         dom->pgt_va, dom->pgt_pa);
 294         kfree(to_mtk_domain(domain));
 295 }
 296
 297 static int mtk_iommu_v1_attach_device(struct iommu_domain *domain, struct device *dev)
 298 {
 299         struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev);
 300         struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
 301         struct dma_iommu_mapping *mtk_mapping;
 302         int ret;
 303
 304         /* Only allow the domain created internally. */
 305         mtk_mapping = data->mapping;
 306         if (mtk_mapping->domain != domain)
 307                 return 0;
 308
 309         if (!data->m4u_dom) {
 310                 data->m4u_dom = dom;
 311                 ret = mtk_iommu_v1_domain_finalise(data);
 312                 if (ret) {
 313                         data->m4u_dom = NULL;
 314                         return ret;
 315                 }
 316         }
 317
 318         mtk_iommu_v1_config(data, dev, true);
 319         return 0;
 320 }
 321
 322 static void mtk_iommu_v1_set_platform_dma(struct device *dev)
 323 {
 324         struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev);
 325
 326         mtk_iommu_v1_config(data, dev, false);
 327 }
 328
 329 static int mtk_iommu_v1_map(struct iommu_domain *domain, unsigned long iova,
 330                             phys_addr_t paddr, size_t pgsize, size_t pgcount,
 331                             int prot, gfp_t gfp, size_t *mapped)
 332 {
 333         struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
 334         unsigned long flags;
 335         unsigned int i;
 336         u32 *pgt_base_iova = dom->pgt_va + (iova  >> MT2701_IOMMU_PAGE_SHIFT);
 337         u32 pabase = (u32)paddr;
 338
 339         spin_lock_irqsave(&dom->pgtlock, flags);
 340         for (i = 0; i < pgcount; i++) {
 341                 if (pgt_base_iova[i])
 342                         break;
 343                 pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC;
 344                 pabase += MT2701_IOMMU_PAGE_SIZE;
 345         }
 346
 347         spin_unlock_irqrestore(&dom->pgtlock, flags);
 348
 349         *mapped = i * MT2701_IOMMU_PAGE_SIZE;
 350         mtk_iommu_v1_tlb_flush_range(dom->data, iova, *mapped);
 351
 352         return i == pgcount ? 0 : -EEXIST;
 353 }
 354
 355 static size_t mtk_iommu_v1_unmap(struct iommu_domain *domain, unsigned long iova,
 356                                  size_t pgsize, size_t pgcount,
 357                                  struct iommu_iotlb_gather *gather)
 358 {
 359         struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
 360         unsigned long flags;
 361         u32 *pgt_base_iova = dom->pgt_va + (iova  >> MT2701_IOMMU_PAGE_SHIFT);
 362         size_t size = pgcount * MT2701_IOMMU_PAGE_SIZE;
 363
 364         spin_lock_irqsave(&dom->pgtlock, flags);
 365         memset(pgt_base_iova, 0, pgcount * sizeof(u32));
 366         spin_unlock_irqrestore(&dom->pgtlock, flags);
 367
 368         mtk_iommu_v1_tlb_flush_range(dom->data, iova, size);
 369
 370         return size;
 371 }
 372
 373 static phys_addr_t mtk_iommu_v1_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova)
 374 {
 375         struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
 376         unsigned long flags;
 377         phys_addr_t pa;
 378
 379         spin_lock_irqsave(&dom->pgtlock, flags);
 380         pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT));
 381         pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1));
 382         spin_unlock_irqrestore(&dom->pgtlock, flags);
 383
 384         return pa;
 385 }
 386
 387 static const struct iommu_ops mtk_iommu_v1_ops;
 388
 389 /*
 390  * MTK generation one iommu HW only support one iommu domain, and all the client
 391  * sharing the same iova address space.
 392  */
 393 static int mtk_iommu_v1_create_mapping(struct device *dev, struct of_phandle_args *args)
 394 {
 395         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 396         struct mtk_iommu_v1_data *data;
 397         struct platform_device *m4updev;
 398         struct dma_iommu_mapping *mtk_mapping;
 399         int ret;
 400
 401         if (args->args_count != 1) {
 402                 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
 403                         args->args_count);
 404                 return -EINVAL;
 405         }
 406
 407         if (!fwspec) {
 408                 ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_v1_ops);
 409                 if (ret)
 410                         return ret;
 411                 fwspec = dev_iommu_fwspec_get(dev);
 412         } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_v1_ops) {
 413                 return -EINVAL;
 414         }
 415
 416         if (!dev_iommu_priv_get(dev)) {
 417                 /* Get the m4u device */
 418                 m4updev = of_find_device_by_node(args->np);
 419                 if (WARN_ON(!m4updev))
 420                         return -EINVAL;
 421
 422                 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
 423         }
 424
 425         ret = iommu_fwspec_add_ids(dev, args->args, 1);
 426         if (ret)
 427                 return ret;
 428
 429         data = dev_iommu_priv_get(dev);
 430         mtk_mapping = data->mapping;
 431         if (!mtk_mapping) {
 432                 /* MTK iommu support 4GB iova address space. */
 433                 mtk_mapping = arm_iommu_create_mapping(&platform_bus_type,
 434                                                 0, 1ULL << 32);
 435                 if (IS_ERR(mtk_mapping))
 436                         return PTR_ERR(mtk_mapping);
 437
 438                 data->mapping = mtk_mapping;
 439         }
 440
 441         return 0;
 442 }
 443
 444 static int mtk_iommu_v1_def_domain_type(struct device *dev)
 445 {
 446         return IOMMU_DOMAIN_UNMANAGED;
 447 }
 448
 449 static struct iommu_device *mtk_iommu_v1_probe_device(struct device *dev)
 450 {
 451         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 452         struct of_phandle_args iommu_spec;
 453         struct mtk_iommu_v1_data *data;
 454         int err, idx = 0, larbid, larbidx;
 455         struct device_link *link;
 456         struct device *larbdev;
 457
 458         /*
 459          * In the deferred case, free the existed fwspec.
 460          * Always initialize the fwspec internally.
 461          */
 462         if (fwspec) {
 463                 iommu_fwspec_free(dev);
 464                 fwspec = dev_iommu_fwspec_get(dev);
 465         }
 466
 467         while (!of_parse_phandle_with_args(dev->of_node, "iommus",
 468                                            "#iommu-cells",
 469                                            idx, &iommu_spec)) {
 470
 471                 err = mtk_iommu_v1_create_mapping(dev, &iommu_spec);
 472                 of_node_put(iommu_spec.np);
 473                 if (err)
 474                         return ERR_PTR(err);
 475
 476                 /* dev->iommu_fwspec might have changed */
 477                 fwspec = dev_iommu_fwspec_get(dev);
 478                 idx++;
 479         }
 480
 481         if (!fwspec || fwspec->ops != &mtk_iommu_v1_ops)
 482                 return ERR_PTR(-ENODEV); /* Not a iommu client device */
 483
 484         data = dev_iommu_priv_get(dev);
 485
 486         /* Link the consumer device with the smi-larb device(supplier) */
 487         larbid = mt2701_m4u_to_larb(fwspec->ids[0]);
 488         if (larbid >= MT2701_LARB_NR_MAX)
 489                 return ERR_PTR(-EINVAL);
 490
 491         for (idx = 1; idx < fwspec->num_ids; idx++) {
 492                 larbidx = mt2701_m4u_to_larb(fwspec->ids[idx]);
 493                 if (larbid != larbidx) {
 494                         dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n",
 495                                 larbid, larbidx);
 496                         return ERR_PTR(-EINVAL);
 497                 }
 498         }
 499
 500         larbdev = data->larb_imu[larbid].dev;
 501         if (!larbdev)
 502                 return ERR_PTR(-EINVAL);
 503
 504         link = device_link_add(dev, larbdev,
 505                                DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
 506         if (!link)
 507                 dev_err(dev, "Unable to link %s\n", dev_name(larbdev));
 508
 509         return &data->iommu;
 510 }
 511
 512 static void mtk_iommu_v1_probe_finalize(struct device *dev)
 513 {
 514         struct dma_iommu_mapping *mtk_mapping;
 515         struct mtk_iommu_v1_data *data;
 516         int err;
 517
 518         data        = dev_iommu_priv_get(dev);
 519         mtk_mapping = data->mapping;
 520
 521         err = arm_iommu_attach_device(dev, mtk_mapping);
 522         if (err)
 523                 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n");
 524 }
 525
 526 static void mtk_iommu_v1_release_device(struct device *dev)
 527 {
 528         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 529         struct mtk_iommu_v1_data *data;
 530         struct device *larbdev;
 531         unsigned int larbid;
 532
 533         data = dev_iommu_priv_get(dev);
 534         larbid = mt2701_m4u_to_larb(fwspec->ids[0]);
 535         larbdev = data->larb_imu[larbid].dev;
 536         device_link_remove(dev, larbdev);
 537 }
 538
 539 static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data)
 540 {
 541         u32 regval;
 542         int ret;
 543
 544         ret = clk_prepare_enable(data->bclk);
 545         if (ret) {
 546                 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
 547                 return ret;
 548         }
 549
 550         regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2);
 551         writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
 552
 553         regval = F_INT_TRANSLATION_FAULT |
 554                 F_INT_MAIN_MULTI_HIT_FAULT |
 555                 F_INT_INVALID_PA_FAULT |
 556                 F_INT_ENTRY_REPLACEMENT_FAULT |
 557                 F_INT_TABLE_WALK_FAULT |
 558                 F_INT_TLB_MISS_FAULT |
 559                 F_INT_PFH_DMA_FIFO_OVERFLOW |
 560                 F_INT_MISS_DMA_FIFO_OVERFLOW;
 561         writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
 562
 563         /* protect memory,hw will write here while translation fault */
 564         writel_relaxed(data->protect_base,
 565                         data->base + REG_MMU_IVRP_PADDR);
 566
 567         writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
 568
 569         if (devm_request_irq(data->dev, data->irq, mtk_iommu_v1_isr, 0,
 570                              dev_name(data->dev), (void *)data)) {
 571                 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
 572                 clk_disable_unprepare(data->bclk);
 573                 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
 574                 return -ENODEV;
 575         }
 576
 577         return 0;
 578 }
 579
 580 static const struct iommu_ops mtk_iommu_v1_ops = {
 581         .domain_alloc   = mtk_iommu_v1_domain_alloc,
 582         .probe_device   = mtk_iommu_v1_probe_device,
 583         .probe_finalize = mtk_iommu_v1_probe_finalize,
 584         .release_device = mtk_iommu_v1_release_device,
 585         .def_domain_type = mtk_iommu_v1_def_domain_type,
 586         .device_group   = generic_device_group,
 587         .pgsize_bitmap  = MT2701_IOMMU_PAGE_SIZE,
 588         .set_platform_dma_ops = mtk_iommu_v1_set_platform_dma,
 589         .owner          = THIS_MODULE,
 590         .default_domain_ops = &(const struct iommu_domain_ops) {
 591                 .attach_dev     = mtk_iommu_v1_attach_device,
 592                 .map_pages      = mtk_iommu_v1_map,
 593                 .unmap_pages    = mtk_iommu_v1_unmap,
 594                 .iova_to_phys   = mtk_iommu_v1_iova_to_phys,
 595                 .free           = mtk_iommu_v1_domain_free,
 596         }
 597 };
 598
 599 static const struct of_device_id mtk_iommu_v1_of_ids[] = {
 600         { .compatible = "mediatek,mt2701-m4u", },
 601         {}
 602 };
 603
 604 static const struct component_master_ops mtk_iommu_v1_com_ops = {
 605         .bind           = mtk_iommu_v1_bind,
 606         .unbind         = mtk_iommu_v1_unbind,
 607 };
 608
 609 static int mtk_iommu_v1_probe(struct platform_device *pdev)
 610 {
 611         struct device                   *dev = &pdev->dev;
 612         struct mtk_iommu_v1_data        *data;
 613         struct resource                 *res;
 614         struct component_match          *match = NULL;
 615         void                            *protect;
 616         int                             larb_nr, ret, i;
 617
 618         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 619         if (!data)
 620                 return -ENOMEM;
 621
 622         data->dev = dev;
 623
 624         /* Protect memory. HW will access here while translation fault.*/
 625         protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2,
 626                         GFP_KERNEL | GFP_DMA);
 627         if (!protect)
 628                 return -ENOMEM;
 629         data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
 630
 631         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 632         data->base = devm_ioremap_resource(dev, res);
 633         if (IS_ERR(data->base))
 634                 return PTR_ERR(data->base);
 635
 636         data->irq = platform_get_irq(pdev, 0);
 637         if (data->irq < 0)
 638                 return data->irq;
 639
 640         data->bclk = devm_clk_get(dev, "bclk");
 641         if (IS_ERR(data->bclk))
 642                 return PTR_ERR(data->bclk);
 643
 644         larb_nr = of_count_phandle_with_args(dev->of_node,
 645                                              "mediatek,larbs", NULL);
 646         if (larb_nr < 0)
 647                 return larb_nr;
 648
 649         for (i = 0; i < larb_nr; i++) {
 650                 struct device_node *larbnode;
 651                 struct platform_device *plarbdev;
 652
 653                 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
 654                 if (!larbnode)
 655                         return -EINVAL;
 656
 657                 if (!of_device_is_available(larbnode)) {
 658                         of_node_put(larbnode);
 659                         continue;
 660                 }
 661
 662                 plarbdev = of_find_device_by_node(larbnode);
 663                 if (!plarbdev) {
 664                         of_node_put(larbnode);
 665                         return -ENODEV;
 666                 }
 667                 if (!plarbdev->dev.driver) {
 668                         of_node_put(larbnode);
 669                         return -EPROBE_DEFER;
 670                 }
 671                 data->larb_imu[i].dev = &plarbdev->dev;
 672
 673                 component_match_add_release(dev, &match, component_release_of,
 674                                             component_compare_of, larbnode);
 675         }
 676
 677         platform_set_drvdata(pdev, data);
 678
 679         ret = mtk_iommu_v1_hw_init(data);
 680         if (ret)
 681                 return ret;
 682
 683         ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL,
 684                                      dev_name(&pdev->dev));
 685         if (ret)
 686                 goto out_clk_unprepare;
 687
 688         ret = iommu_device_register(&data->iommu, &mtk_iommu_v1_ops, dev);
 689         if (ret)
 690                 goto out_sysfs_remove;
 691
 692         ret = component_master_add_with_match(dev, &mtk_iommu_v1_com_ops, match);
 693         if (ret)
 694                 goto out_dev_unreg;
 695         return ret;
 696
 697 out_dev_unreg:
 698         iommu_device_unregister(&data->iommu);
 699 out_sysfs_remove:
 700         iommu_device_sysfs_remove(&data->iommu);
 701 out_clk_unprepare:
 702         clk_disable_unprepare(data->bclk);
 703         return ret;
 704 }
 705
 706 static void mtk_iommu_v1_remove(struct platform_device *pdev)
 707 {
 708         struct mtk_iommu_v1_data *data = platform_get_drvdata(pdev);
 709
 710         iommu_device_sysfs_remove(&data->iommu);
 711         iommu_device_unregister(&data->iommu);
 712
 713         clk_disable_unprepare(data->bclk);
 714         devm_free_irq(&pdev->dev, data->irq, data);
 715         component_master_del(&pdev->dev, &mtk_iommu_v1_com_ops);
 716 }
 717
 718 static int __maybe_unused mtk_iommu_v1_suspend(struct device *dev)
 719 {
 720         struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
 721         struct mtk_iommu_v1_suspend_reg *reg = &data->reg;
 722         void __iomem *base = data->base;
 723
 724         reg->standard_axi_mode = readl_relaxed(base +
 725                                                REG_MMU_STANDARD_AXI_MODE);
 726         reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM);
 727         reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
 728         reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL);
 729         return 0;
 730 }
 731
 732 static int __maybe_unused mtk_iommu_v1_resume(struct device *dev)
 733 {
 734         struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
 735         struct mtk_iommu_v1_suspend_reg *reg = &data->reg;
 736         void __iomem *base = data->base;
 737
 738         writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
 739         writel_relaxed(reg->standard_axi_mode,
 740                        base + REG_MMU_STANDARD_AXI_MODE);
 741         writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM);
 742         writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
 743         writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL);
 744         writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR);
 745         return 0;
 746 }
 747
 748 static const struct dev_pm_ops mtk_iommu_v1_pm_ops = {
 749         SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_v1_suspend, mtk_iommu_v1_resume)
 750 };
 751
 752 static struct platform_driver mtk_iommu_v1_driver = {
 753         .probe  = mtk_iommu_v1_probe,
 754         .remove_new = mtk_iommu_v1_remove,
 755         .driver = {
 756                 .name = "mtk-iommu-v1",
 757                 .of_match_table = mtk_iommu_v1_of_ids,
 758                 .pm = &mtk_iommu_v1_pm_ops,
 759         }
 760 };
 761 module_platform_driver(mtk_iommu_v1_driver);
 762
 763 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U v1 implementations");
 764 MODULE_LICENSE("GPL v2");