1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
4 * Author: Yong Wu <yong.wu@mediatek.com>
6 #include <linux/bitfield.h>
9 #include <linux/component.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/interrupt.h>
14 #include <linux/iommu.h>
15 #include <linux/iopoll.h>
16 #include <linux/io-pgtable.h>
17 #include <linux/list.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/regmap.h>
27 #include <linux/slab.h>
28 #include <linux/spinlock.h>
29 #include <linux/soc/mediatek/infracfg.h>
30 #include <asm/barrier.h>
31 #include <soc/mediatek/smi.h>
33 #include <dt-bindings/memory/mtk-memory-port.h>
35 #define REG_MMU_PT_BASE_ADDR 0x000
37 #define REG_MMU_INVALIDATE 0x020
38 #define F_ALL_INVLD 0x2
39 #define F_MMU_INV_RANGE 0x1
41 #define REG_MMU_INVLD_START_A 0x024
42 #define REG_MMU_INVLD_END_A 0x028
44 #define REG_MMU_INV_SEL_GEN2 0x02c
45 #define REG_MMU_INV_SEL_GEN1 0x038
46 #define F_INVLD_EN0 BIT(0)
47 #define F_INVLD_EN1 BIT(1)
49 #define REG_MMU_MISC_CTRL 0x048
50 #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17))
51 #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19))
53 #define REG_MMU_DCM_DIS 0x050
54 #define F_MMU_DCM BIT(8)
56 #define REG_MMU_WR_LEN_CTRL 0x054
57 #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21))
59 #define REG_MMU_CTRL_REG 0x110
60 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4)
61 #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
62 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5)
64 #define REG_MMU_IVRP_PADDR 0x114
66 #define REG_MMU_VLD_PA_RNG 0x118
67 #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA))
69 #define REG_MMU_INT_CONTROL0 0x120
70 #define F_L2_MULIT_HIT_EN BIT(0)
71 #define F_TABLE_WALK_FAULT_INT_EN BIT(1)
72 #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2)
73 #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3)
74 #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5)
75 #define F_MISS_FIFO_ERR_INT_EN BIT(6)
76 #define F_INT_CLR_BIT BIT(12)
78 #define REG_MMU_INT_MAIN_CONTROL 0x124
80 #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7))
81 #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8))
82 #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9))
83 #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10))
84 #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11))
85 #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12))
86 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13))
88 #define REG_MMU_CPE_DONE 0x12C
90 #define REG_MMU_FAULT_ST1 0x134
91 #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0)
92 #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)
94 #define REG_MMU0_FAULT_VA 0x13c
95 #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12)
96 #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9)
97 #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6)
98 #define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
99 #define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
101 #define REG_MMU0_INVLD_PA 0x140
102 #define REG_MMU1_FAULT_VA 0x144
103 #define REG_MMU1_INVLD_PA 0x148
104 #define REG_MMU0_INT_ID 0x150
105 #define REG_MMU1_INT_ID 0x154
106 #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7)
107 #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
108 #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7)
109 #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7)
110 /* Macro for 5 bits length port ID field (default) */
111 #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
112 #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
113 /* Macro for 6 bits length port ID field */
114 #define F_MMU_INT_ID_LARB_ID_WID_6(a) (((a) >> 8) & 0x7)
115 #define F_MMU_INT_ID_PORT_ID_WID_6(a) (((a) >> 2) & 0x3f)
117 #define MTK_PROTECT_PA_ALIGN 256
118 #define MTK_IOMMU_BANK_SZ 0x1000
120 #define PERICFG_IOMMU_1 0x714
122 #define HAS_4GB_MODE BIT(0)
123 /* HW will use the EMI clock if there isn't the "bclk". */
124 #define HAS_BCLK BIT(1)
125 #define HAS_VLD_PA_RNG BIT(2)
126 #define RESET_AXI BIT(3)
127 #define OUT_ORDER_WR_EN BIT(4)
128 #define HAS_SUB_COMM_2BITS BIT(5)
129 #define HAS_SUB_COMM_3BITS BIT(6)
130 #define WR_THROT_EN BIT(7)
131 #define HAS_LEGACY_IVRP_PADDR BIT(8)
132 #define IOVA_34_EN BIT(9)
133 #define SHARE_PGTABLE BIT(10) /* 2 HW share pgtable */
134 #define DCM_DISABLE BIT(11)
135 #define STD_AXI_MODE BIT(12) /* For non MM iommu */
136 /* 2 bits: iommu type */
137 #define MTK_IOMMU_TYPE_MM (0x0 << 13)
138 #define MTK_IOMMU_TYPE_INFRA (0x1 << 13)
139 #define MTK_IOMMU_TYPE_MASK (0x3 << 13)
140 /* PM and clock always on. e.g. infra iommu */
141 #define PM_CLK_AO BIT(15)
142 #define IFA_IOMMU_PCIE_SUPPORT BIT(16)
143 #define PGTABLE_PA_35_EN BIT(17)
144 #define TF_PORT_TO_ADDR_MT8173 BIT(18)
145 #define INT_ID_PORT_WIDTH_6 BIT(19)
147 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
148 ((((pdata)->flags) & (mask)) == (_x))
150 #define MTK_IOMMU_HAS_FLAG(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x)
151 #define MTK_IOMMU_IS_TYPE(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\
154 #define MTK_INVALID_LARBID MTK_LARB_NR_MAX
156 #define MTK_LARB_COM_MAX 8
157 #define MTK_LARB_SUBCOM_MAX 8
159 #define MTK_IOMMU_GROUP_MAX 8
160 #define MTK_IOMMU_BANK_MAX 5
162 enum mtk_iommu_plat {
175 struct mtk_iommu_iova_region {
176 dma_addr_t iova_base;
177 unsigned long long size;
180 struct mtk_iommu_suspend_reg {
187 u32 int_control[MTK_IOMMU_BANK_MAX];
188 u32 int_main_control[MTK_IOMMU_BANK_MAX];
189 u32 ivrp_paddr[MTK_IOMMU_BANK_MAX];
192 struct mtk_iommu_plat_data {
193 enum mtk_iommu_plat m4u_plat;
197 char *pericfg_comp_str;
198 struct list_head *hw_list;
201 * The IOMMU HW may support 16GB iova. In order to balance the IOVA ranges,
202 * different masters will be put in different iova ranges, for example vcodec
203 * is in 4G-8G and cam is in 8G-12G. Meanwhile, some masters may have the
204 * special IOVA range requirement, like CCU can only support the address
205 * 0x40000000-0x44000000.
206 * Here list the iova ranges this SoC supports and which larbs/ports are in
209 * 16GB iova all use one pgtable, but each a region is a iommu group.
212 unsigned int iova_region_nr;
213 const struct mtk_iommu_iova_region *iova_region;
215 * Indicate the correspondance between larbs, ports and regions.
217 * The index is the same as iova_region and larb port numbers are
218 * described as bit positions.
219 * For example, storing BIT(0) at index 2,1 means "larb 1, port0 is in region 2".
220 * [2] = { [1] = BIT(0) }
222 const u32 (*iova_region_larb_msk)[MTK_LARB_NR_MAX];
226 * The IOMMU HW may have 5 banks. Each bank has a independent pgtable.
227 * Here list how many banks this SoC supports/enables and which ports are in which bank.
231 bool banks_enable[MTK_IOMMU_BANK_MAX];
232 unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX];
235 unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
238 struct mtk_iommu_bank_data {
242 struct device *parent_dev;
243 struct mtk_iommu_data *parent_data;
244 spinlock_t tlb_lock; /* lock for tlb range flush */
245 struct mtk_iommu_domain *m4u_dom; /* Each bank has a domain */
248 struct mtk_iommu_data {
251 phys_addr_t protect_base; /* protect memory base */
252 struct mtk_iommu_suspend_reg reg;
253 struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX];
256 struct iommu_device iommu;
257 const struct mtk_iommu_plat_data *plat_data;
258 struct device *smicomm_dev;
260 struct mtk_iommu_bank_data *bank;
261 struct regmap *pericfg;
262 struct mutex mutex; /* Protect m4u_group/m4u_dom above */
265 * In the sharing pgtable case, list data->list to the global list like m4ulist.
266 * In the non-sharing pgtable case, list data->list to the itself hw_list_head.
268 struct list_head *hw_list;
269 struct list_head hw_list_head;
270 struct list_head list;
271 struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
274 struct mtk_iommu_domain {
275 struct io_pgtable_cfg cfg;
276 struct io_pgtable_ops *iop;
278 struct mtk_iommu_bank_data *bank;
279 struct iommu_domain domain;
281 struct mutex mutex; /* Protect "data" in this structure */
284 static int mtk_iommu_bind(struct device *dev)
286 struct mtk_iommu_data *data = dev_get_drvdata(dev);
288 return component_bind_all(dev, &data->larb_imu);
291 static void mtk_iommu_unbind(struct device *dev)
293 struct mtk_iommu_data *data = dev_get_drvdata(dev);
295 component_unbind_all(dev, &data->larb_imu);
298 static const struct iommu_ops mtk_iommu_ops;
300 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid);
302 #define MTK_IOMMU_TLB_ADDR(iova) ({ \
303 dma_addr_t _addr = iova; \
304 ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\
308 * In M4U 4GB mode, the physical address is remapped as below:
310 * CPU Physical address:
311 * ====================
314 * |---A---|---B---|---C---|---D---|---E---|
315 * +--I/O--+------------Memory-------------+
317 * IOMMU output physical address:
318 * =============================
321 * |---E---|---B---|---C---|---D---|
322 * +------------Memory-------------+
324 * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the
325 * bit32 of the CPU physical address always is needed to set, and for Region
326 * 'E', the CPU physical address keep as is.
327 * Additionally, The iommu consumers always use the CPU phyiscal address.
329 #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL
331 static LIST_HEAD(m4ulist); /* List all the M4U HWs */
333 #define for_each_m4u(data, head) list_for_each_entry(data, head, list)
335 #define MTK_IOMMU_IOVA_SZ_4G (SZ_4G - SZ_8M) /* 8M as gap */
337 static const struct mtk_iommu_iova_region single_domain[] = {
338 {.iova_base = 0, .size = MTK_IOMMU_IOVA_SZ_4G},
341 #define MT8192_MULTI_REGION_NR_MAX 6
343 #define MT8192_MULTI_REGION_NR (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) ? \
344 MT8192_MULTI_REGION_NR_MAX : 1)
346 static const struct mtk_iommu_iova_region mt8192_multi_dom[MT8192_MULTI_REGION_NR] = {
347 { .iova_base = 0x0, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 0 ~ 4G, */
348 #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
349 { .iova_base = SZ_4G, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 4G ~ 8G */
350 { .iova_base = SZ_4G * 2, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 8G ~ 12G */
351 { .iova_base = SZ_4G * 3, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 12G ~ 16G */
353 { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */
354 { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */
358 /* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/
359 static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist)
361 return list_first_entry(hwlist, struct mtk_iommu_data, list);
364 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
366 return container_of(dom, struct mtk_iommu_domain, domain);
369 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
371 /* Tlb flush all always is in bank0. */
372 struct mtk_iommu_bank_data *bank = &data->bank[0];
373 void __iomem *base = bank->base;
376 spin_lock_irqsave(&bank->tlb_lock, flags);
377 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg);
378 writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE);
379 wmb(); /* Make sure the tlb flush all done */
380 spin_unlock_irqrestore(&bank->tlb_lock, flags);
383 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
384 struct mtk_iommu_bank_data *bank)
386 struct list_head *head = bank->parent_data->hw_list;
387 struct mtk_iommu_bank_data *curbank;
388 struct mtk_iommu_data *data;
389 bool check_pm_status;
395 for_each_m4u(data, head) {
397 * To avoid resume the iommu device frequently when the iommu device
398 * is not active, it doesn't always call pm_runtime_get here, then tlb
399 * flush depends on the tlb flush all in the runtime resume.
401 * There are 2 special cases:
403 * Case1: The iommu dev doesn't have power domain but has bclk. This case
404 * should also avoid the tlb flush while the dev is not active to mute
405 * the tlb timeout log. like mt8173.
407 * Case2: The power/clock of infra iommu is always on, and it doesn't
408 * have the device link with the master devices. This case should avoid
409 * the PM status check.
411 check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO);
413 if (check_pm_status) {
414 if (pm_runtime_get_if_in_use(data->dev) <= 0)
418 curbank = &data->bank[bank->id];
419 base = curbank->base;
421 spin_lock_irqsave(&curbank->tlb_lock, flags);
422 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
423 base + data->plat_data->inv_sel_reg);
425 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A);
426 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),
427 base + REG_MMU_INVLD_END_A);
428 writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE);
431 ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE,
432 tmp, tmp != 0, 10, 1000);
434 /* Clear the CPE status */
435 writel_relaxed(0, base + REG_MMU_CPE_DONE);
436 spin_unlock_irqrestore(&curbank->tlb_lock, flags);
440 "Partial TLB flush timed out, falling back to full flush\n");
441 mtk_iommu_tlb_flush_all(data);
445 pm_runtime_put(data->dev);
449 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
451 struct mtk_iommu_bank_data *bank = dev_id;
452 struct mtk_iommu_data *data = bank->parent_data;
453 struct mtk_iommu_domain *dom = bank->m4u_dom;
454 unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0;
455 u32 int_state, regval, va34_32, pa34_32;
456 const struct mtk_iommu_plat_data *plat_data = data->plat_data;
457 void __iomem *base = bank->base;
458 u64 fault_iova, fault_pa;
461 /* Read error info from registers */
462 int_state = readl_relaxed(base + REG_MMU_FAULT_ST1);
463 if (int_state & F_REG_MMU0_FAULT_MASK) {
464 regval = readl_relaxed(base + REG_MMU0_INT_ID);
465 fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA);
466 fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA);
468 regval = readl_relaxed(base + REG_MMU1_INT_ID);
469 fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA);
470 fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA);
472 layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
473 write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
474 if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) {
475 va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
476 fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
477 fault_iova |= (u64)va34_32 << 32;
479 pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
480 fault_pa |= (u64)pa34_32 << 32;
482 if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) {
483 if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
484 fault_larb = F_MMU_INT_ID_COMM_ID(regval);
485 sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
486 fault_port = F_MMU_INT_ID_PORT_ID(regval);
487 } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) {
488 fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
489 sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
490 fault_port = F_MMU_INT_ID_PORT_ID(regval);
491 } else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) {
492 fault_port = F_MMU_INT_ID_PORT_ID_WID_6(regval);
493 fault_larb = F_MMU_INT_ID_LARB_ID_WID_6(regval);
495 fault_port = F_MMU_INT_ID_PORT_ID(regval);
496 fault_larb = F_MMU_INT_ID_LARB_ID(regval);
498 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
501 if (!dom || report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova,
502 write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
505 "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n",
506 int_state, fault_iova, fault_pa, regval, fault_larb, fault_port,
507 layer, write ? "write" : "read");
510 /* Interrupt clear */
511 regval = readl_relaxed(base + REG_MMU_INT_CONTROL0);
512 regval |= F_INT_CLR_BIT;
513 writel_relaxed(regval, base + REG_MMU_INT_CONTROL0);
515 mtk_iommu_tlb_flush_all(data);
520 static unsigned int mtk_iommu_get_bank_id(struct device *dev,
521 const struct mtk_iommu_plat_data *plat_data)
523 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
524 unsigned int i, portmsk = 0, bankid = 0;
526 if (plat_data->banks_num == 1)
529 for (i = 0; i < fwspec->num_ids; i++)
530 portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i]));
532 for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) {
533 if (!plat_data->banks_enable[i])
536 if (portmsk & plat_data->banks_portmsk[i]) {
541 return bankid; /* default is 0 */
544 static int mtk_iommu_get_iova_region_id(struct device *dev,
545 const struct mtk_iommu_plat_data *plat_data)
547 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
548 unsigned int portidmsk = 0, larbid;
549 const u32 *rgn_larb_msk;
552 if (plat_data->iova_region_nr == 1)
555 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
556 for (i = 0; i < fwspec->num_ids; i++)
557 portidmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i]));
559 for (i = 0; i < plat_data->iova_region_nr; i++) {
560 rgn_larb_msk = plat_data->iova_region_larb_msk[i];
564 if ((rgn_larb_msk[larbid] & portidmsk) == portidmsk)
568 dev_err(dev, "Can NOT find the region for larb(%d-%x).\n",
573 static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
574 bool enable, unsigned int regionid)
576 struct mtk_smi_larb_iommu *larb_mmu;
577 unsigned int larbid, portid;
578 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
579 const struct mtk_iommu_iova_region *region;
580 u32 peri_mmuen, peri_mmuen_msk;
583 for (i = 0; i < fwspec->num_ids; ++i) {
584 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
585 portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
587 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
588 larb_mmu = &data->larb_imu[larbid];
590 region = data->plat_data->iova_region + regionid;
591 larb_mmu->bank[portid] = upper_32_bits(region->iova_base);
593 dev_dbg(dev, "%s iommu for larb(%s) port %d region %d rgn-bank %d.\n",
594 enable ? "enable" : "disable", dev_name(larb_mmu->dev),
595 portid, regionid, larb_mmu->bank[portid]);
598 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
600 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
601 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
602 peri_mmuen_msk = BIT(portid);
603 /* PCI dev has only one output id, enable the next writing bit for PCIe */
605 peri_mmuen_msk |= BIT(portid + 1);
607 peri_mmuen = enable ? peri_mmuen_msk : 0;
608 ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,
609 peri_mmuen_msk, peri_mmuen);
611 dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n",
612 enable ? "enable" : "disable",
613 dev_name(data->dev), peri_mmuen_msk, ret);
619 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
620 struct mtk_iommu_data *data,
621 unsigned int region_id)
623 const struct mtk_iommu_iova_region *region;
624 struct mtk_iommu_domain *m4u_dom;
626 /* Always use bank0 in sharing pgtable case */
627 m4u_dom = data->bank[0].m4u_dom;
629 dom->iop = m4u_dom->iop;
630 dom->cfg = m4u_dom->cfg;
631 dom->domain.pgsize_bitmap = m4u_dom->cfg.pgsize_bitmap;
632 goto update_iova_region;
635 dom->cfg = (struct io_pgtable_cfg) {
636 .quirks = IO_PGTABLE_QUIRK_ARM_NS |
637 IO_PGTABLE_QUIRK_NO_PERMS |
638 IO_PGTABLE_QUIRK_ARM_MTK_EXT,
639 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
640 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32,
641 .iommu_dev = data->dev,
644 if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
645 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
647 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
648 dom->cfg.oas = data->enable_4GB ? 33 : 32;
652 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
654 dev_err(data->dev, "Failed to alloc io pgtable\n");
658 /* Update our support page sizes bitmap */
659 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
662 /* Update the iova region for this domain */
663 region = data->plat_data->iova_region + region_id;
664 dom->domain.geometry.aperture_start = region->iova_base;
665 dom->domain.geometry.aperture_end = region->iova_base + region->size - 1;
666 dom->domain.geometry.force_aperture = true;
670 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
672 struct mtk_iommu_domain *dom;
674 if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED)
677 dom = kzalloc(sizeof(*dom), GFP_KERNEL);
680 mutex_init(&dom->mutex);
685 static void mtk_iommu_domain_free(struct iommu_domain *domain)
687 kfree(to_mtk_domain(domain));
690 static int mtk_iommu_attach_device(struct iommu_domain *domain,
693 struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata;
694 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
695 struct list_head *hw_list = data->hw_list;
696 struct device *m4udev = data->dev;
697 struct mtk_iommu_bank_data *bank;
701 region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data);
705 bankid = mtk_iommu_get_bank_id(dev, data->plat_data);
706 mutex_lock(&dom->mutex);
708 /* Data is in the frstdata in sharing pgtable case. */
709 frstdata = mtk_iommu_get_frst_data(hw_list);
711 ret = mtk_iommu_domain_finalise(dom, frstdata, region_id);
713 mutex_unlock(&dom->mutex);
716 dom->bank = &data->bank[bankid];
718 mutex_unlock(&dom->mutex);
720 mutex_lock(&data->mutex);
721 bank = &data->bank[bankid];
722 if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */
723 ret = pm_runtime_resume_and_get(m4udev);
725 dev_err(m4udev, "pm get fail(%d) in attach.\n", ret);
729 ret = mtk_iommu_hw_init(data, bankid);
731 pm_runtime_put(m4udev);
735 writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR);
737 pm_runtime_put(m4udev);
739 mutex_unlock(&data->mutex);
742 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34));
744 dev_err(m4udev, "Failed to set dma_mask for %s(%d).\n", dev_name(dev), ret);
749 return mtk_iommu_config(data, dev, true, region_id);
752 mutex_unlock(&data->mutex);
756 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
757 phys_addr_t paddr, size_t pgsize, size_t pgcount,
758 int prot, gfp_t gfp, size_t *mapped)
760 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
762 /* The "4GB mode" M4U physically can not use the lower remap of Dram. */
763 if (dom->bank->parent_data->enable_4GB)
764 paddr |= BIT_ULL(32);
766 /* Synchronize with the tlb_lock */
767 return dom->iop->map_pages(dom->iop, iova, paddr, pgsize, pgcount, prot, gfp, mapped);
770 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
771 unsigned long iova, size_t pgsize, size_t pgcount,
772 struct iommu_iotlb_gather *gather)
774 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
776 iommu_iotlb_gather_add_range(gather, iova, pgsize * pgcount);
777 return dom->iop->unmap_pages(dom->iop, iova, pgsize, pgcount, gather);
780 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
782 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
784 mtk_iommu_tlb_flush_all(dom->bank->parent_data);
787 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
788 struct iommu_iotlb_gather *gather)
790 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
791 size_t length = gather->end - gather->start + 1;
793 mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank);
796 static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
799 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
801 mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank);
804 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
807 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
810 pa = dom->iop->iova_to_phys(dom->iop, iova);
811 if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
812 dom->bank->parent_data->enable_4GB &&
813 pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
819 static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
821 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
822 struct mtk_iommu_data *data;
823 struct device_link *link;
824 struct device *larbdev;
825 unsigned int larbid, larbidx, i;
827 if (!fwspec || fwspec->ops != &mtk_iommu_ops)
828 return ERR_PTR(-ENODEV); /* Not a iommu client device */
830 data = dev_iommu_priv_get(dev);
832 if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
836 * Link the consumer device with the smi-larb device(supplier).
837 * The device that connects with each a larb is a independent HW.
838 * All the ports in each a device should be in the same larbs.
840 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
841 if (larbid >= MTK_LARB_NR_MAX)
842 return ERR_PTR(-EINVAL);
844 for (i = 1; i < fwspec->num_ids; i++) {
845 larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]);
846 if (larbid != larbidx) {
847 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n",
849 return ERR_PTR(-EINVAL);
852 larbdev = data->larb_imu[larbid].dev;
854 return ERR_PTR(-EINVAL);
856 link = device_link_add(dev, larbdev,
857 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
859 dev_err(dev, "Unable to link %s\n", dev_name(larbdev));
863 static void mtk_iommu_release_device(struct device *dev)
865 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
866 struct mtk_iommu_data *data;
867 struct device *larbdev;
870 data = dev_iommu_priv_get(dev);
871 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
872 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
873 larbdev = data->larb_imu[larbid].dev;
874 device_link_remove(dev, larbdev);
878 static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data)
883 * If the bank function is enabled, each bank is a iommu group/domain.
884 * Otherwise, each iova region is a iommu group/domain.
886 bankid = mtk_iommu_get_bank_id(dev, plat_data);
890 return mtk_iommu_get_iova_region_id(dev, plat_data);
893 static struct iommu_group *mtk_iommu_device_group(struct device *dev)
895 struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data;
896 struct list_head *hw_list = c_data->hw_list;
897 struct iommu_group *group;
900 data = mtk_iommu_get_frst_data(hw_list);
902 return ERR_PTR(-ENODEV);
904 groupid = mtk_iommu_get_group_id(dev, data->plat_data);
906 return ERR_PTR(groupid);
908 mutex_lock(&data->mutex);
909 group = data->m4u_group[groupid];
911 group = iommu_group_alloc();
913 data->m4u_group[groupid] = group;
915 iommu_group_ref_get(group);
917 mutex_unlock(&data->mutex);
921 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
923 struct platform_device *m4updev;
925 if (args->args_count != 1) {
926 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
931 if (!dev_iommu_priv_get(dev)) {
932 /* Get the m4u device */
933 m4updev = of_find_device_by_node(args->np);
934 if (WARN_ON(!m4updev))
937 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
940 return iommu_fwspec_add_ids(dev, args->args, 1);
943 static void mtk_iommu_get_resv_regions(struct device *dev,
944 struct list_head *head)
946 struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
947 unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i;
948 const struct mtk_iommu_iova_region *resv, *curdom;
949 struct iommu_resv_region *region;
950 int prot = IOMMU_WRITE | IOMMU_READ;
952 if ((int)regionid < 0)
954 curdom = data->plat_data->iova_region + regionid;
955 for (i = 0; i < data->plat_data->iova_region_nr; i++) {
956 resv = data->plat_data->iova_region + i;
958 /* Only reserve when the region is inside the current domain */
959 if (resv->iova_base <= curdom->iova_base ||
960 resv->iova_base + resv->size >= curdom->iova_base + curdom->size)
963 region = iommu_alloc_resv_region(resv->iova_base, resv->size,
964 prot, IOMMU_RESV_RESERVED,
969 list_add_tail(®ion->list, head);
973 static const struct iommu_ops mtk_iommu_ops = {
974 .domain_alloc = mtk_iommu_domain_alloc,
975 .probe_device = mtk_iommu_probe_device,
976 .release_device = mtk_iommu_release_device,
977 .device_group = mtk_iommu_device_group,
978 .of_xlate = mtk_iommu_of_xlate,
979 .get_resv_regions = mtk_iommu_get_resv_regions,
980 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
981 .owner = THIS_MODULE,
982 .default_domain_ops = &(const struct iommu_domain_ops) {
983 .attach_dev = mtk_iommu_attach_device,
984 .map_pages = mtk_iommu_map,
985 .unmap_pages = mtk_iommu_unmap,
986 .flush_iotlb_all = mtk_iommu_flush_iotlb_all,
987 .iotlb_sync = mtk_iommu_iotlb_sync,
988 .iotlb_sync_map = mtk_iommu_sync_map,
989 .iova_to_phys = mtk_iommu_iova_to_phys,
990 .free = mtk_iommu_domain_free,
994 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid)
996 const struct mtk_iommu_bank_data *bankx = &data->bank[bankid];
997 const struct mtk_iommu_bank_data *bank0 = &data->bank[0];
1001 * Global control settings are in bank0. May re-init these global registers
1002 * since no sure if there is bank0 consumers.
1004 if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) {
1005 regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
1006 F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
1008 regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG);
1009 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
1011 writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG);
1013 if (data->enable_4GB &&
1014 MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
1016 * If 4GB mode is enabled, the validate PA range is from
1017 * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
1019 regval = F_MMU_VLD_PA_RNG(7, 4);
1020 writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG);
1022 if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE))
1023 writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS);
1025 writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS);
1027 if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) {
1028 /* write command throttling mode */
1029 regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL);
1030 regval &= ~F_MMU_WR_THROT_DIS_MASK;
1031 writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL);
1034 if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
1035 /* The register is called STANDARD_AXI_MODE in this case */
1038 regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL);
1039 if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE))
1040 regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
1041 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
1042 regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
1044 writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL);
1046 /* Independent settings for each bank */
1047 regval = F_L2_MULIT_HIT_EN |
1048 F_TABLE_WALK_FAULT_INT_EN |
1049 F_PREETCH_FIFO_OVERFLOW_INT_EN |
1050 F_MISS_FIFO_OVERFLOW_INT_EN |
1051 F_PREFETCH_FIFO_ERR_INT_EN |
1052 F_MISS_FIFO_ERR_INT_EN;
1053 writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0);
1055 regval = F_INT_TRANSLATION_FAULT |
1056 F_INT_MAIN_MULTI_HIT_FAULT |
1057 F_INT_INVALID_PA_FAULT |
1058 F_INT_ENTRY_REPLACEMENT_FAULT |
1059 F_INT_TLB_MISS_FAULT |
1060 F_INT_MISS_TRANSACTION_FIFO_FAULT |
1061 F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
1062 writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL);
1064 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
1065 regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
1067 regval = lower_32_bits(data->protect_base) |
1068 upper_32_bits(data->protect_base);
1069 writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR);
1071 if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0,
1072 dev_name(bankx->parent_dev), (void *)bankx)) {
1073 writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR);
1074 dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq);
1081 static const struct component_master_ops mtk_iommu_com_ops = {
1082 .bind = mtk_iommu_bind,
1083 .unbind = mtk_iommu_unbind,
1086 static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match,
1087 struct mtk_iommu_data *data)
1089 struct device_node *larbnode, *frst_avail_smicomm_node = NULL;
1090 struct platform_device *plarbdev, *pcommdev;
1091 struct device_link *link;
1092 int i, larb_nr, ret;
1094 larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL);
1097 if (larb_nr == 0 || larb_nr > MTK_LARB_NR_MAX)
1100 for (i = 0; i < larb_nr; i++) {
1101 struct device_node *smicomm_node, *smi_subcomm_node;
1104 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
1107 goto err_larbdev_put;
1110 if (!of_device_is_available(larbnode)) {
1111 of_node_put(larbnode);
1115 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
1116 if (ret)/* The id is consecutive if there is no this property */
1118 if (id >= MTK_LARB_NR_MAX) {
1119 of_node_put(larbnode);
1121 goto err_larbdev_put;
1124 plarbdev = of_find_device_by_node(larbnode);
1125 of_node_put(larbnode);
1128 goto err_larbdev_put;
1130 if (data->larb_imu[id].dev) {
1131 platform_device_put(plarbdev);
1133 goto err_larbdev_put;
1135 data->larb_imu[id].dev = &plarbdev->dev;
1137 if (!plarbdev->dev.driver) {
1138 ret = -EPROBE_DEFER;
1139 goto err_larbdev_put;
1142 /* Get smi-(sub)-common dev from the last larb. */
1143 smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0);
1144 if (!smi_subcomm_node) {
1146 goto err_larbdev_put;
1150 * It may have two level smi-common. the node is smi-sub-common if it
1151 * has a new mediatek,smi property. otherwise it is smi-commmon.
1153 smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0);
1155 of_node_put(smi_subcomm_node);
1157 smicomm_node = smi_subcomm_node;
1160 * All the larbs that connect to one IOMMU must connect with the same
1163 if (!frst_avail_smicomm_node) {
1164 frst_avail_smicomm_node = smicomm_node;
1165 } else if (frst_avail_smicomm_node != smicomm_node) {
1166 dev_err(dev, "mediatek,smi property is not right @larb%d.", id);
1167 of_node_put(smicomm_node);
1169 goto err_larbdev_put;
1171 of_node_put(smicomm_node);
1174 component_match_add(dev, match, component_compare_dev, &plarbdev->dev);
1175 platform_device_put(plarbdev);
1178 if (!frst_avail_smicomm_node)
1181 pcommdev = of_find_device_by_node(frst_avail_smicomm_node);
1182 of_node_put(frst_avail_smicomm_node);
1185 data->smicomm_dev = &pcommdev->dev;
1187 link = device_link_add(data->smicomm_dev, dev,
1188 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
1189 platform_device_put(pcommdev);
1191 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev));
1197 for (i = MTK_LARB_NR_MAX - 1; i >= 0; i--) {
1198 if (!data->larb_imu[i].dev)
1200 put_device(data->larb_imu[i].dev);
1205 static int mtk_iommu_probe(struct platform_device *pdev)
1207 struct mtk_iommu_data *data;
1208 struct device *dev = &pdev->dev;
1209 struct resource *res;
1210 resource_size_t ioaddr;
1211 struct component_match *match = NULL;
1212 struct regmap *infracfg;
1214 int ret, banks_num, i = 0;
1217 struct mtk_iommu_bank_data *bank;
1220 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1224 data->plat_data = of_device_get_match_data(dev);
1226 /* Protect memory. HW will access here while translation fault.*/
1227 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
1230 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
1232 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) {
1233 infracfg = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,infracfg");
1234 if (IS_ERR(infracfg)) {
1236 * Legacy devicetrees will not specify a phandle to
1237 * mediatek,infracfg: in that case, we use the older
1238 * way to retrieve a syscon to infra.
1240 * This is for retrocompatibility purposes only, hence
1241 * no more compatibles shall be added to this.
1243 switch (data->plat_data->m4u_plat) {
1245 p = "mediatek,mt2712-infracfg";
1248 p = "mediatek,mt8173-infracfg";
1254 infracfg = syscon_regmap_lookup_by_compatible(p);
1255 if (IS_ERR(infracfg))
1256 return PTR_ERR(infracfg);
1259 ret = regmap_read(infracfg, REG_INFRA_MISC, &val);
1262 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN);
1265 banks_num = data->plat_data->banks_num;
1266 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1269 if (resource_size(res) < banks_num * MTK_IOMMU_BANK_SZ) {
1270 dev_err(dev, "banknr %d. res %pR is not enough.\n", banks_num, res);
1273 base = devm_ioremap_resource(dev, res);
1275 return PTR_ERR(base);
1276 ioaddr = res->start;
1278 data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL);
1283 if (!data->plat_data->banks_enable[i])
1285 bank = &data->bank[i];
1287 bank->base = base + i * MTK_IOMMU_BANK_SZ;
1288 bank->m4u_dom = NULL;
1290 bank->irq = platform_get_irq(pdev, i);
1293 bank->parent_dev = dev;
1294 bank->parent_data = data;
1295 spin_lock_init(&bank->tlb_lock);
1296 } while (++i < banks_num);
1298 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {
1299 data->bclk = devm_clk_get(dev, "bclk");
1300 if (IS_ERR(data->bclk))
1301 return PTR_ERR(data->bclk);
1304 if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) {
1305 ret = dma_set_mask(dev, DMA_BIT_MASK(35));
1307 dev_err(dev, "Failed to set dma_mask 35.\n");
1312 pm_runtime_enable(dev);
1314 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1315 ret = mtk_iommu_mm_dts_parse(dev, &match, data);
1317 dev_err_probe(dev, ret, "mm dts parse fail\n");
1318 goto out_runtime_disable;
1320 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
1321 p = data->plat_data->pericfg_comp_str;
1322 data->pericfg = syscon_regmap_lookup_by_compatible(p);
1323 if (IS_ERR(data->pericfg)) {
1324 ret = PTR_ERR(data->pericfg);
1325 goto out_runtime_disable;
1329 platform_set_drvdata(pdev, data);
1330 mutex_init(&data->mutex);
1332 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,
1333 "mtk-iommu.%pa", &ioaddr);
1335 goto out_link_remove;
1337 ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev);
1339 goto out_sysfs_remove;
1341 if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) {
1342 list_add_tail(&data->list, data->plat_data->hw_list);
1343 data->hw_list = data->plat_data->hw_list;
1345 INIT_LIST_HEAD(&data->hw_list_head);
1346 list_add_tail(&data->list, &data->hw_list_head);
1347 data->hw_list = &data->hw_list_head;
1350 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1351 ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
1358 list_del(&data->list);
1359 iommu_device_unregister(&data->iommu);
1361 iommu_device_sysfs_remove(&data->iommu);
1363 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
1364 device_link_remove(data->smicomm_dev, dev);
1365 out_runtime_disable:
1366 pm_runtime_disable(dev);
1370 static void mtk_iommu_remove(struct platform_device *pdev)
1372 struct mtk_iommu_data *data = platform_get_drvdata(pdev);
1373 struct mtk_iommu_bank_data *bank;
1376 iommu_device_sysfs_remove(&data->iommu);
1377 iommu_device_unregister(&data->iommu);
1379 list_del(&data->list);
1381 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1382 device_link_remove(data->smicomm_dev, &pdev->dev);
1383 component_master_del(&pdev->dev, &mtk_iommu_com_ops);
1385 pm_runtime_disable(&pdev->dev);
1386 for (i = 0; i < data->plat_data->banks_num; i++) {
1387 bank = &data->bank[i];
1390 devm_free_irq(&pdev->dev, bank->irq, bank);
1394 static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev)
1396 struct mtk_iommu_data *data = dev_get_drvdata(dev);
1397 struct mtk_iommu_suspend_reg *reg = &data->reg;
1401 base = data->bank[i].base;
1402 reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
1403 reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
1404 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
1405 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
1406 reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
1408 if (!data->plat_data->banks_enable[i])
1410 base = data->bank[i].base;
1411 reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0);
1412 reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
1413 reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR);
1414 } while (++i < data->plat_data->banks_num);
1415 clk_disable_unprepare(data->bclk);
1419 static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
1421 struct mtk_iommu_data *data = dev_get_drvdata(dev);
1422 struct mtk_iommu_suspend_reg *reg = &data->reg;
1423 struct mtk_iommu_domain *m4u_dom;
1427 ret = clk_prepare_enable(data->bclk);
1429 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
1434 * Uppon first resume, only enable the clk and return, since the values of the
1435 * registers are not yet set.
1437 if (!reg->wr_len_ctrl)
1440 base = data->bank[i].base;
1441 writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
1442 writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
1443 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
1444 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
1445 writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
1447 m4u_dom = data->bank[i].m4u_dom;
1448 if (!data->plat_data->banks_enable[i] || !m4u_dom)
1450 base = data->bank[i].base;
1451 writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
1452 writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
1453 writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
1454 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR);
1455 } while (++i < data->plat_data->banks_num);
1458 * Users may allocate dma buffer before they call pm_runtime_get,
1459 * in which case it will lack the necessary tlb flush.
1460 * Thus, make sure to update the tlb after each PM resume.
1462 mtk_iommu_tlb_flush_all(data);
1466 static const struct dev_pm_ops mtk_iommu_pm_ops = {
1467 SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL)
1468 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1469 pm_runtime_force_resume)
1472 static const struct mtk_iommu_plat_data mt2712_data = {
1473 .m4u_plat = M4U_MT2712,
1474 .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE |
1476 .hw_list = &m4ulist,
1477 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1478 .iova_region = single_domain,
1480 .banks_enable = {true},
1481 .iova_region_nr = ARRAY_SIZE(single_domain),
1482 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
1485 static const struct mtk_iommu_plat_data mt6779_data = {
1486 .m4u_plat = M4U_MT6779,
1487 .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
1488 MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN,
1489 .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1491 .banks_enable = {true},
1492 .iova_region = single_domain,
1493 .iova_region_nr = ARRAY_SIZE(single_domain),
1494 .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
1497 static const struct mtk_iommu_plat_data mt6795_data = {
1498 .m4u_plat = M4U_MT6795,
1499 .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
1500 HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM |
1501 TF_PORT_TO_ADDR_MT8173,
1502 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1504 .banks_enable = {true},
1505 .iova_region = single_domain,
1506 .iova_region_nr = ARRAY_SIZE(single_domain),
1507 .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */
1510 static const struct mtk_iommu_plat_data mt8167_data = {
1511 .m4u_plat = M4U_MT8167,
1512 .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM,
1513 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1515 .banks_enable = {true},
1516 .iova_region = single_domain,
1517 .iova_region_nr = ARRAY_SIZE(single_domain),
1518 .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
1521 static const struct mtk_iommu_plat_data mt8173_data = {
1522 .m4u_plat = M4U_MT8173,
1523 .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
1524 HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM |
1525 TF_PORT_TO_ADDR_MT8173,
1526 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1528 .banks_enable = {true},
1529 .iova_region = single_domain,
1530 .iova_region_nr = ARRAY_SIZE(single_domain),
1531 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
1534 static const struct mtk_iommu_plat_data mt8183_data = {
1535 .m4u_plat = M4U_MT8183,
1536 .flags = RESET_AXI | MTK_IOMMU_TYPE_MM,
1537 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1539 .banks_enable = {true},
1540 .iova_region = single_domain,
1541 .iova_region_nr = ARRAY_SIZE(single_domain),
1542 .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
1545 static const unsigned int mt8186_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
1546 [0] = {~0, ~0, ~0}, /* Region0: all ports for larb0/1/2 */
1547 [1] = {0, 0, 0, 0, ~0, 0, 0, ~0}, /* Region1: larb4/7 */
1548 [2] = {0, 0, 0, 0, 0, 0, 0, 0, /* Region2: larb8/9/11/13/16/17/19/20 */
1549 ~0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), 0, 0,
1550 /* larb13: the other ports except port9/10 */
1553 [4] = {[13] = BIT(9) | BIT(10)}, /* larb13 port9/10 */
1554 [5] = {[14] = ~0}, /* larb14 */
1557 static const struct mtk_iommu_plat_data mt8186_data_mm = {
1558 .m4u_plat = M4U_MT8186,
1559 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1560 WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM,
1561 .larbid_remap = {{0}, {1, MTK_INVALID_LARBID, 8}, {4}, {7}, {2}, {9, 11, 19, 20},
1562 {MTK_INVALID_LARBID, 14, 16},
1563 {MTK_INVALID_LARBID, 13, MTK_INVALID_LARBID, 17}},
1564 .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1566 .banks_enable = {true},
1567 .iova_region = mt8192_multi_dom,
1568 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1569 .iova_region_larb_msk = mt8186_larb_region_msk,
1572 static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
1573 [0] = {~0, ~0}, /* Region0: larb0/1 */
1574 [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0}, /* Region1: larb4/5/7 */
1575 [2] = {0, 0, ~0, 0, 0, 0, 0, 0, /* Region2: larb2/9/11/13/14/16/17/18/19/20 */
1576 0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), ~(u32)(BIT(4) | BIT(5)), 0,
1577 ~0, ~0, ~0, ~0, ~0},
1579 [4] = {[13] = BIT(9) | BIT(10)}, /* larb13 port9/10 */
1580 [5] = {[14] = BIT(4) | BIT(5)}, /* larb14 port4/5 */
1583 static const struct mtk_iommu_plat_data mt8192_data = {
1584 .m4u_plat = M4U_MT8192,
1585 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1586 WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM,
1587 .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1589 .banks_enable = {true},
1590 .iova_region = mt8192_multi_dom,
1591 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1592 .iova_region_larb_msk = mt8192_larb_region_msk,
1593 .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
1594 {0, 14, 16}, {0, 13, 18, 17}},
1597 static const struct mtk_iommu_plat_data mt8195_data_infra = {
1598 .m4u_plat = M4U_MT8195,
1599 .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO |
1600 MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT,
1601 .pericfg_comp_str = "mediatek,mt8195-pericfg_ao",
1602 .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1604 .banks_enable = {true, false, false, false, true},
1605 .banks_portmsk = {[0] = GENMASK(19, 16), /* PCIe */
1606 [4] = GENMASK(31, 20), /* USB */
1608 .iova_region = single_domain,
1609 .iova_region_nr = ARRAY_SIZE(single_domain),
1612 static const unsigned int mt8195_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
1613 [0] = {~0, ~0, ~0, ~0}, /* Region0: all ports for larb0/1/2/3 */
1614 [1] = {0, 0, 0, 0, 0, 0, 0, 0,
1615 0, 0, 0, 0, 0, 0, 0, 0,
1616 0, 0, 0, ~0, ~0, ~0, ~0, ~0, /* Region1: larb19/20/21/22/23/24 */
1618 [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0, /* Region2: the other larbs. */
1619 ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0,
1620 ~0, ~0, 0, 0, 0, 0, 0, 0,
1623 [4] = {[18] = BIT(0) | BIT(1)}, /* Only larb18 port0/1 */
1624 [5] = {[18] = BIT(2) | BIT(3)}, /* Only larb18 port2/3 */
1627 static const struct mtk_iommu_plat_data mt8195_data_vdo = {
1628 .m4u_plat = M4U_MT8195,
1629 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1630 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
1631 .hw_list = &m4ulist,
1632 .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1634 .banks_enable = {true},
1635 .iova_region = mt8192_multi_dom,
1636 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1637 .iova_region_larb_msk = mt8195_larb_region_msk,
1638 .larbid_remap = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11},
1639 {13, 17, 15/* 17b */, 25}, {5}},
1642 static const struct mtk_iommu_plat_data mt8195_data_vpp = {
1643 .m4u_plat = M4U_MT8195,
1644 .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
1645 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
1646 .hw_list = &m4ulist,
1647 .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1649 .banks_enable = {true},
1650 .iova_region = mt8192_multi_dom,
1651 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1652 .iova_region_larb_msk = mt8195_larb_region_msk,
1653 .larbid_remap = {{1}, {3},
1654 {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23},
1656 /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */
1657 {14, 16, 29, 26, 30, 31, 18},
1658 {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}},
1661 static const struct mtk_iommu_plat_data mt8365_data = {
1662 .m4u_plat = M4U_MT8365,
1663 .flags = RESET_AXI | INT_ID_PORT_WIDTH_6,
1664 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1666 .banks_enable = {true},
1667 .iova_region = single_domain,
1668 .iova_region_nr = ARRAY_SIZE(single_domain),
1669 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
1672 static const struct of_device_id mtk_iommu_of_ids[] = {
1673 { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
1674 { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
1675 { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data},
1676 { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
1677 { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
1678 { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
1679 { .compatible = "mediatek,mt8186-iommu-mm", .data = &mt8186_data_mm}, /* mm: m4u */
1680 { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
1681 { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
1682 { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo},
1683 { .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp},
1684 { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data},
1688 static struct platform_driver mtk_iommu_driver = {
1689 .probe = mtk_iommu_probe,
1690 .remove_new = mtk_iommu_remove,
1692 .name = "mtk-iommu",
1693 .of_match_table = mtk_iommu_of_ids,
1694 .pm = &mtk_iommu_pm_ops,
1697 module_platform_driver(mtk_iommu_driver);
1699 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations");
1700 MODULE_LICENSE("GPL v2");