drivers/iommu/mtk_iommu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015-2016 MediaTek Inc.
   4  * Author: Yong Wu <yong.wu@mediatek.com>
   5  */
   6 #include <linux/arm-smccc.h>
   7 #include <linux/bitfield.h>
   8 #include <linux/bug.h>
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/device.h>
  12 #include <linux/err.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/iommu.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/io-pgtable.h>
  18 #include <linux/list.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/module.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/pci.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/regmap.h>
  28 #include <linux/slab.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/soc/mediatek/infracfg.h>
  31 #include <linux/soc/mediatek/mtk_sip_svc.h>
  32 #include <asm/barrier.h>
  33 #include <soc/mediatek/smi.h>
  34
  35 #include <dt-bindings/memory/mtk-memory-port.h>
  36
  37 #define REG_MMU_PT_BASE_ADDR                    0x000
  38
  39 #define REG_MMU_INVALIDATE                      0x020
  40 #define F_ALL_INVLD                             0x2
  41 #define F_MMU_INV_RANGE                         0x1
  42
  43 #define REG_MMU_INVLD_START_A                   0x024
  44 #define REG_MMU_INVLD_END_A                     0x028
  45
  46 #define REG_MMU_INV_SEL_GEN2                    0x02c
  47 #define REG_MMU_INV_SEL_GEN1                    0x038
  48 #define F_INVLD_EN0                             BIT(0)
  49 #define F_INVLD_EN1                             BIT(1)
  50
  51 #define REG_MMU_MISC_CTRL                       0x048
  52 #define F_MMU_IN_ORDER_WR_EN_MASK               (BIT(1) | BIT(17))
  53 #define F_MMU_STANDARD_AXI_MODE_MASK            (BIT(3) | BIT(19))
  54
  55 #define REG_MMU_DCM_DIS                         0x050
  56 #define F_MMU_DCM                               BIT(8)
  57
  58 #define REG_MMU_WR_LEN_CTRL                     0x054
  59 #define F_MMU_WR_THROT_DIS_MASK                 (BIT(5) | BIT(21))
  60
  61 #define REG_MMU_CTRL_REG                        0x110
  62 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR           (2 << 4)
  63 #define F_MMU_PREFETCH_RT_REPLACE_MOD           BIT(4)
  64 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173    (2 << 5)
  65
  66 #define REG_MMU_IVRP_PADDR                      0x114
  67
  68 #define REG_MMU_VLD_PA_RNG                      0x118
  69 #define F_MMU_VLD_PA_RNG(EA, SA)                (((EA) << 8) | (SA))
  70
  71 #define REG_MMU_INT_CONTROL0                    0x120
  72 #define F_L2_MULIT_HIT_EN                       BIT(0)
  73 #define F_TABLE_WALK_FAULT_INT_EN               BIT(1)
  74 #define F_PREETCH_FIFO_OVERFLOW_INT_EN          BIT(2)
  75 #define F_MISS_FIFO_OVERFLOW_INT_EN             BIT(3)
  76 #define F_PREFETCH_FIFO_ERR_INT_EN              BIT(5)
  77 #define F_MISS_FIFO_ERR_INT_EN                  BIT(6)
  78 #define F_INT_CLR_BIT                           BIT(12)
  79
  80 #define REG_MMU_INT_MAIN_CONTROL                0x124
  81                                                 /* mmu0 | mmu1 */
  82 #define F_INT_TRANSLATION_FAULT                 (BIT(0) | BIT(7))
  83 #define F_INT_MAIN_MULTI_HIT_FAULT              (BIT(1) | BIT(8))
  84 #define F_INT_INVALID_PA_FAULT                  (BIT(2) | BIT(9))
  85 #define F_INT_ENTRY_REPLACEMENT_FAULT           (BIT(3) | BIT(10))
  86 #define F_INT_TLB_MISS_FAULT                    (BIT(4) | BIT(11))
  87 #define F_INT_MISS_TRANSACTION_FIFO_FAULT       (BIT(5) | BIT(12))
  88 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT    (BIT(6) | BIT(13))
  89
  90 #define REG_MMU_CPE_DONE                        0x12C
  91
  92 #define REG_MMU_FAULT_ST1                       0x134
  93 #define F_REG_MMU0_FAULT_MASK                   GENMASK(6, 0)
  94 #define F_REG_MMU1_FAULT_MASK                   GENMASK(13, 7)
  95
  96 #define REG_MMU0_FAULT_VA                       0x13c
  97 #define F_MMU_INVAL_VA_31_12_MASK               GENMASK(31, 12)
  98 #define F_MMU_INVAL_VA_34_32_MASK               GENMASK(11, 9)
  99 #define F_MMU_INVAL_PA_34_32_MASK               GENMASK(8, 6)
 100 #define F_MMU_FAULT_VA_WRITE_BIT                BIT(1)
 101 #define F_MMU_FAULT_VA_LAYER_BIT                BIT(0)
 102
 103 #define REG_MMU0_INVLD_PA                       0x140
 104 #define REG_MMU1_FAULT_VA                       0x144
 105 #define REG_MMU1_INVLD_PA                       0x148
 106 #define REG_MMU0_INT_ID                         0x150
 107 #define REG_MMU1_INT_ID                         0x154
 108 #define F_MMU_INT_ID_COMM_ID(a)                 (((a) >> 9) & 0x7)
 109 #define F_MMU_INT_ID_SUB_COMM_ID(a)             (((a) >> 7) & 0x3)
 110 #define F_MMU_INT_ID_COMM_ID_EXT(a)             (((a) >> 10) & 0x7)
 111 #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a)         (((a) >> 7) & 0x7)
 112 /* Macro for 5 bits length port ID field (default) */
 113 #define F_MMU_INT_ID_LARB_ID(a)                 (((a) >> 7) & 0x7)
 114 #define F_MMU_INT_ID_PORT_ID(a)                 (((a) >> 2) & 0x1f)
 115 /* Macro for 6 bits length port ID field */
 116 #define F_MMU_INT_ID_LARB_ID_WID_6(a)           (((a) >> 8) & 0x7)
 117 #define F_MMU_INT_ID_PORT_ID_WID_6(a)           (((a) >> 2) & 0x3f)
 118
 119 #define MTK_PROTECT_PA_ALIGN                    256
 120 #define MTK_IOMMU_BANK_SZ                       0x1000
 121
 122 #define PERICFG_IOMMU_1                         0x714
 123
 124 #define HAS_4GB_MODE                    BIT(0)
 125 /* HW will use the EMI clock if there isn't the "bclk". */
 126 #define HAS_BCLK                        BIT(1)
 127 #define HAS_VLD_PA_RNG                  BIT(2)
 128 #define RESET_AXI                       BIT(3)
 129 #define OUT_ORDER_WR_EN                 BIT(4)
 130 #define HAS_SUB_COMM_2BITS              BIT(5)
 131 #define HAS_SUB_COMM_3BITS              BIT(6)
 132 #define WR_THROT_EN                     BIT(7)
 133 #define HAS_LEGACY_IVRP_PADDR           BIT(8)
 134 #define IOVA_34_EN                      BIT(9)
 135 #define SHARE_PGTABLE                   BIT(10) /* 2 HW share pgtable */
 136 #define DCM_DISABLE                     BIT(11)
 137 #define STD_AXI_MODE                    BIT(12) /* For non MM iommu */
 138 /* 2 bits: iommu type */
 139 #define MTK_IOMMU_TYPE_MM               (0x0 << 13)
 140 #define MTK_IOMMU_TYPE_INFRA            (0x1 << 13)
 141 #define MTK_IOMMU_TYPE_MASK             (0x3 << 13)
 142 /* PM and clock always on. e.g. infra iommu */
 143 #define PM_CLK_AO                       BIT(15)
 144 #define IFA_IOMMU_PCIE_SUPPORT          BIT(16)
 145 #define PGTABLE_PA_35_EN                BIT(17)
 146 #define TF_PORT_TO_ADDR_MT8173          BIT(18)
 147 #define INT_ID_PORT_WIDTH_6             BIT(19)
 148 #define CFG_IFA_MASTER_IN_ATF           BIT(20)
 149
 150 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask)        \
 151                                 ((((pdata)->flags) & (mask)) == (_x))
 152
 153 #define MTK_IOMMU_HAS_FLAG(pdata, _x)   MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x)
 154 #define MTK_IOMMU_IS_TYPE(pdata, _x)    MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\
 155                                                         MTK_IOMMU_TYPE_MASK)
 156
 157 #define MTK_INVALID_LARBID              MTK_LARB_NR_MAX
 158
 159 #define MTK_LARB_COM_MAX        8
 160 #define MTK_LARB_SUBCOM_MAX     8
 161
 162 #define MTK_IOMMU_GROUP_MAX     8
 163 #define MTK_IOMMU_BANK_MAX      5
 164
 165 enum mtk_iommu_plat {
 166         M4U_MT2712,
 167         M4U_MT6779,
 168         M4U_MT6795,
 169         M4U_MT8167,
 170         M4U_MT8173,
 171         M4U_MT8183,
 172         M4U_MT8186,
 173         M4U_MT8188,
 174         M4U_MT8192,
 175         M4U_MT8195,
 176         M4U_MT8365,
 177 };
 178
 179 struct mtk_iommu_iova_region {
 180         dma_addr_t              iova_base;
 181         unsigned long long      size;
 182 };
 183
 184 struct mtk_iommu_suspend_reg {
 185         u32                     misc_ctrl;
 186         u32                     dcm_dis;
 187         u32                     ctrl_reg;
 188         u32                     vld_pa_rng;
 189         u32                     wr_len_ctrl;
 190
 191         u32                     int_control[MTK_IOMMU_BANK_MAX];
 192         u32                     int_main_control[MTK_IOMMU_BANK_MAX];
 193         u32                     ivrp_paddr[MTK_IOMMU_BANK_MAX];
 194 };
 195
 196 struct mtk_iommu_plat_data {
 197         enum mtk_iommu_plat     m4u_plat;
 198         u32                     flags;
 199         u32                     inv_sel_reg;
 200
 201         char                    *pericfg_comp_str;
 202         struct list_head        *hw_list;
 203
 204         /*
 205          * The IOMMU HW may support 16GB iova. In order to balance the IOVA ranges,
 206          * different masters will be put in different iova ranges, for example vcodec
 207          * is in 4G-8G and cam is in 8G-12G. Meanwhile, some masters may have the
 208          * special IOVA range requirement, like CCU can only support the address
 209          * 0x40000000-0x44000000.
 210          * Here list the iova ranges this SoC supports and which larbs/ports are in
 211          * which region.
 212          *
 213          * 16GB iova all use one pgtable, but each a region is a iommu group.
 214          */
 215         struct {
 216                 unsigned int    iova_region_nr;
 217                 const struct mtk_iommu_iova_region      *iova_region;
 218                 /*
 219                  * Indicate the correspondance between larbs, ports and regions.
 220                  *
 221                  * The index is the same as iova_region and larb port numbers are
 222                  * described as bit positions.
 223                  * For example, storing BIT(0) at index 2,1 means "larb 1, port0 is in region 2".
 224                  *              [2] = { [1] = BIT(0) }
 225                  */
 226                 const u32       (*iova_region_larb_msk)[MTK_LARB_NR_MAX];
 227         };
 228
 229         /*
 230          * The IOMMU HW may have 5 banks. Each bank has a independent pgtable.
 231          * Here list how many banks this SoC supports/enables and which ports are in which bank.
 232          */
 233         struct {
 234                 u8              banks_num;
 235                 bool            banks_enable[MTK_IOMMU_BANK_MAX];
 236                 unsigned int    banks_portmsk[MTK_IOMMU_BANK_MAX];
 237         };
 238
 239         unsigned char       larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
 240 };
 241
 242 struct mtk_iommu_bank_data {
 243         void __iomem                    *base;
 244         int                             irq;
 245         u8                              id;
 246         struct device                   *parent_dev;
 247         struct mtk_iommu_data           *parent_data;
 248         spinlock_t                      tlb_lock; /* lock for tlb range flush */
 249         struct mtk_iommu_domain         *m4u_dom; /* Each bank has a domain */
 250 };
 251
 252 struct mtk_iommu_data {
 253         struct device                   *dev;
 254         struct clk                      *bclk;
 255         phys_addr_t                     protect_base; /* protect memory base */
 256         struct mtk_iommu_suspend_reg    reg;
 257         struct iommu_group              *m4u_group[MTK_IOMMU_GROUP_MAX];
 258         bool                            enable_4GB;
 259
 260         struct iommu_device             iommu;
 261         const struct mtk_iommu_plat_data *plat_data;
 262         struct device                   *smicomm_dev;
 263
 264         struct mtk_iommu_bank_data      *bank;
 265         struct mtk_iommu_domain         *share_dom; /* For 2 HWs share pgtable */
 266
 267         struct regmap                   *pericfg;
 268         struct mutex                    mutex; /* Protect m4u_group/m4u_dom above */
 269
 270         /*
 271          * In the sharing pgtable case, list data->list to the global list like m4ulist.
 272          * In the non-sharing pgtable case, list data->list to the itself hw_list_head.
 273          */
 274         struct list_head                *hw_list;
 275         struct list_head                hw_list_head;
 276         struct list_head                list;
 277         struct mtk_smi_larb_iommu       larb_imu[MTK_LARB_NR_MAX];
 278 };
 279
 280 struct mtk_iommu_domain {
 281         struct io_pgtable_cfg           cfg;
 282         struct io_pgtable_ops           *iop;
 283
 284         struct mtk_iommu_bank_data      *bank;
 285         struct iommu_domain             domain;
 286
 287         struct mutex                    mutex; /* Protect "data" in this structure */
 288 };
 289
 290 static int mtk_iommu_bind(struct device *dev)
 291 {
 292         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 293
 294         return component_bind_all(dev, &data->larb_imu);
 295 }
 296
 297 static void mtk_iommu_unbind(struct device *dev)
 298 {
 299         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 300
 301         component_unbind_all(dev, &data->larb_imu);
 302 }
 303
 304 static const struct iommu_ops mtk_iommu_ops;
 305
 306 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid);
 307
 308 #define MTK_IOMMU_TLB_ADDR(iova) ({                                     \
 309         dma_addr_t _addr = iova;                                        \
 310         ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\
 311 })
 312
 313 /*
 314  * In M4U 4GB mode, the physical address is remapped as below:
 315  *
 316  * CPU Physical address:
 317  * ====================
 318  *
 319  * 0      1G       2G     3G       4G     5G
 320  * |---A---|---B---|---C---|---D---|---E---|
 321  * +--I/O--+------------Memory-------------+
 322  *
 323  * IOMMU output physical address:
 324  *  =============================
 325  *
 326  *                                 4G      5G     6G      7G      8G
 327  *                                 |---E---|---B---|---C---|---D---|
 328  *                                 +------------Memory-------------+
 329  *
 330  * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the
 331  * bit32 of the CPU physical address always is needed to set, and for Region
 332  * 'E', the CPU physical address keep as is.
 333  * Additionally, The iommu consumers always use the CPU phyiscal address.
 334  */
 335 #define MTK_IOMMU_4GB_MODE_REMAP_BASE    0x140000000UL
 336
 337 static LIST_HEAD(m4ulist);      /* List all the M4U HWs */
 338
 339 #define for_each_m4u(data, head)  list_for_each_entry(data, head, list)
 340
 341 #define MTK_IOMMU_IOVA_SZ_4G            (SZ_4G - SZ_8M) /* 8M as gap */
 342
 343 static const struct mtk_iommu_iova_region single_domain[] = {
 344         {.iova_base = 0,                .size = MTK_IOMMU_IOVA_SZ_4G},
 345 };
 346
 347 #define MT8192_MULTI_REGION_NR_MAX      6
 348
 349 #define MT8192_MULTI_REGION_NR  (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) ? \
 350                                  MT8192_MULTI_REGION_NR_MAX : 1)
 351
 352 static const struct mtk_iommu_iova_region mt8192_multi_dom[MT8192_MULTI_REGION_NR] = {
 353         { .iova_base = 0x0,             .size = MTK_IOMMU_IOVA_SZ_4G},  /* 0 ~ 4G,  */
 354         #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
 355         { .iova_base = SZ_4G,           .size = MTK_IOMMU_IOVA_SZ_4G},  /* 4G ~ 8G */
 356         { .iova_base = SZ_4G * 2,       .size = MTK_IOMMU_IOVA_SZ_4G},  /* 8G ~ 12G */
 357         { .iova_base = SZ_4G * 3,       .size = MTK_IOMMU_IOVA_SZ_4G},  /* 12G ~ 16G */
 358
 359         { .iova_base = 0x240000000ULL,  .size = 0x4000000},     /* CCU0 */
 360         { .iova_base = 0x244000000ULL,  .size = 0x4000000},     /* CCU1 */
 361         #endif
 362 };
 363
 364 /* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/
 365 static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist)
 366 {
 367         return list_first_entry(hwlist, struct mtk_iommu_data, list);
 368 }
 369
 370 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
 371 {
 372         return container_of(dom, struct mtk_iommu_domain, domain);
 373 }
 374
 375 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
 376 {
 377         /* Tlb flush all always is in bank0. */
 378         struct mtk_iommu_bank_data *bank = &data->bank[0];
 379         void __iomem *base = bank->base;
 380         unsigned long flags;
 381
 382         spin_lock_irqsave(&bank->tlb_lock, flags);
 383         writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg);
 384         writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE);
 385         wmb(); /* Make sure the tlb flush all done */
 386         spin_unlock_irqrestore(&bank->tlb_lock, flags);
 387 }
 388
 389 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
 390                                            struct mtk_iommu_bank_data *bank)
 391 {
 392         struct list_head *head = bank->parent_data->hw_list;
 393         struct mtk_iommu_bank_data *curbank;
 394         struct mtk_iommu_data *data;
 395         bool check_pm_status;
 396         unsigned long flags;
 397         void __iomem *base;
 398         int ret;
 399         u32 tmp;
 400
 401         for_each_m4u(data, head) {
 402                 /*
 403                  * To avoid resume the iommu device frequently when the iommu device
 404                  * is not active, it doesn't always call pm_runtime_get here, then tlb
 405                  * flush depends on the tlb flush all in the runtime resume.
 406                  *
 407                  * There are 2 special cases:
 408                  *
 409                  * Case1: The iommu dev doesn't have power domain but has bclk. This case
 410                  * should also avoid the tlb flush while the dev is not active to mute
 411                  * the tlb timeout log. like mt8173.
 412                  *
 413                  * Case2: The power/clock of infra iommu is always on, and it doesn't
 414                  * have the device link with the master devices. This case should avoid
 415                  * the PM status check.
 416                  */
 417                 check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO);
 418
 419                 if (check_pm_status) {
 420                         if (pm_runtime_get_if_in_use(data->dev) <= 0)
 421                                 continue;
 422                 }
 423
 424                 curbank = &data->bank[bank->id];
 425                 base = curbank->base;
 426
 427                 spin_lock_irqsave(&curbank->tlb_lock, flags);
 428                 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 429                                base + data->plat_data->inv_sel_reg);
 430
 431                 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A);
 432                 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),
 433                                base + REG_MMU_INVLD_END_A);
 434                 writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE);
 435
 436                 /* tlb sync */
 437                 ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE,
 438                                                 tmp, tmp != 0, 10, 1000);
 439
 440                 /* Clear the CPE status */
 441                 writel_relaxed(0, base + REG_MMU_CPE_DONE);
 442                 spin_unlock_irqrestore(&curbank->tlb_lock, flags);
 443
 444                 if (ret) {
 445                         dev_warn(data->dev,
 446                                  "Partial TLB flush timed out, falling back to full flush\n");
 447                         mtk_iommu_tlb_flush_all(data);
 448                 }
 449
 450                 if (check_pm_status)
 451                         pm_runtime_put(data->dev);
 452         }
 453 }
 454
 455 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
 456 {
 457         struct mtk_iommu_bank_data *bank = dev_id;
 458         struct mtk_iommu_data *data = bank->parent_data;
 459         struct mtk_iommu_domain *dom = bank->m4u_dom;
 460         unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0;
 461         u32 int_state, regval, va34_32, pa34_32;
 462         const struct mtk_iommu_plat_data *plat_data = data->plat_data;
 463         void __iomem *base = bank->base;
 464         u64 fault_iova, fault_pa;
 465         bool layer, write;
 466
 467         /* Read error info from registers */
 468         int_state = readl_relaxed(base + REG_MMU_FAULT_ST1);
 469         if (int_state & F_REG_MMU0_FAULT_MASK) {
 470                 regval = readl_relaxed(base + REG_MMU0_INT_ID);
 471                 fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA);
 472                 fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA);
 473         } else {
 474                 regval = readl_relaxed(base + REG_MMU1_INT_ID);
 475                 fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA);
 476                 fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA);
 477         }
 478         layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
 479         write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
 480         if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) {
 481                 va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
 482                 fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
 483                 fault_iova |= (u64)va34_32 << 32;
 484         }
 485         pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
 486         fault_pa |= (u64)pa34_32 << 32;
 487
 488         if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) {
 489                 if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
 490                         fault_larb = F_MMU_INT_ID_COMM_ID(regval);
 491                         sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
 492                         fault_port = F_MMU_INT_ID_PORT_ID(regval);
 493                 } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) {
 494                         fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
 495                         sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
 496                         fault_port = F_MMU_INT_ID_PORT_ID(regval);
 497                 } else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) {
 498                         fault_port = F_MMU_INT_ID_PORT_ID_WID_6(regval);
 499                         fault_larb = F_MMU_INT_ID_LARB_ID_WID_6(regval);
 500                 } else {
 501                         fault_port = F_MMU_INT_ID_PORT_ID(regval);
 502                         fault_larb = F_MMU_INT_ID_LARB_ID(regval);
 503                 }
 504                 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
 505         }
 506
 507         if (!dom || report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova,
 508                                write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
 509                 dev_err_ratelimited(
 510                         bank->parent_dev,
 511                         "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n",
 512                         int_state, fault_iova, fault_pa, regval, fault_larb, fault_port,
 513                         layer, write ? "write" : "read");
 514         }
 515
 516         /* Interrupt clear */
 517         regval = readl_relaxed(base + REG_MMU_INT_CONTROL0);
 518         regval |= F_INT_CLR_BIT;
 519         writel_relaxed(regval, base + REG_MMU_INT_CONTROL0);
 520
 521         mtk_iommu_tlb_flush_all(data);
 522
 523         return IRQ_HANDLED;
 524 }
 525
 526 static unsigned int mtk_iommu_get_bank_id(struct device *dev,
 527                                           const struct mtk_iommu_plat_data *plat_data)
 528 {
 529         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 530         unsigned int i, portmsk = 0, bankid = 0;
 531
 532         if (plat_data->banks_num == 1)
 533                 return bankid;
 534
 535         for (i = 0; i < fwspec->num_ids; i++)
 536                 portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i]));
 537
 538         for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) {
 539                 if (!plat_data->banks_enable[i])
 540                         continue;
 541
 542                 if (portmsk & plat_data->banks_portmsk[i]) {
 543                         bankid = i;
 544                         break;
 545                 }
 546         }
 547         return bankid; /* default is 0 */
 548 }
 549
 550 static int mtk_iommu_get_iova_region_id(struct device *dev,
 551                                         const struct mtk_iommu_plat_data *plat_data)
 552 {
 553         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 554         unsigned int portidmsk = 0, larbid;
 555         const u32 *rgn_larb_msk;
 556         int i;
 557
 558         if (plat_data->iova_region_nr == 1)
 559                 return 0;
 560
 561         larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
 562         for (i = 0; i < fwspec->num_ids; i++)
 563                 portidmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i]));
 564
 565         for (i = 0; i < plat_data->iova_region_nr; i++) {
 566                 rgn_larb_msk = plat_data->iova_region_larb_msk[i];
 567                 if (!rgn_larb_msk)
 568                         continue;
 569
 570                 if ((rgn_larb_msk[larbid] & portidmsk) == portidmsk)
 571                         return i;
 572         }
 573
 574         dev_err(dev, "Can NOT find the region for larb(%d-%x).\n",
 575                 larbid, portidmsk);
 576         return -EINVAL;
 577 }
 578
 579 static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
 580                             bool enable, unsigned int regionid)
 581 {
 582         struct mtk_smi_larb_iommu    *larb_mmu;
 583         unsigned int                 larbid, portid;
 584         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 585         const struct mtk_iommu_iova_region *region;
 586         unsigned long portid_msk = 0;
 587         struct arm_smccc_res res;
 588         int i, ret = 0;
 589
 590         for (i = 0; i < fwspec->num_ids; ++i) {
 591                 portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
 592                 portid_msk |= BIT(portid);
 593         }
 594
 595         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
 596                 /* All ports should be in the same larb. just use 0 here */
 597                 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
 598                 larb_mmu = &data->larb_imu[larbid];
 599                 region = data->plat_data->iova_region + regionid;
 600
 601                 for_each_set_bit(portid, &portid_msk, 32)
 602                         larb_mmu->bank[portid] = upper_32_bits(region->iova_base);
 603
 604                 dev_dbg(dev, "%s iommu for larb(%s) port 0x%lx region %d rgn-bank %d.\n",
 605                         enable ? "enable" : "disable", dev_name(larb_mmu->dev),
 606                         portid_msk, regionid, upper_32_bits(region->iova_base));
 607
 608                 if (enable)
 609                         larb_mmu->mmu |= portid_msk;
 610                 else
 611                         larb_mmu->mmu &= ~portid_msk;
 612         } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
 613                 if (MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) {
 614                         arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL,
 615                                       IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU,
 616                                       portid_msk, enable, 0, 0, 0, 0, &res);
 617                         ret = res.a0;
 618                 } else {
 619                         /* PCI dev has only one output id, enable the next writing bit for PCIe */
 620                         if (dev_is_pci(dev)) {
 621                                 if (fwspec->num_ids != 1) {
 622                                         dev_err(dev, "PCI dev can only have one port.\n");
 623                                         return -ENODEV;
 624                                 }
 625                                 portid_msk |= BIT(portid + 1);
 626                         }
 627
 628                         ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,
 629                                                  (u32)portid_msk, enable ? (u32)portid_msk : 0);
 630                 }
 631                 if (ret)
 632                         dev_err(dev, "%s iommu(%s) inframaster 0x%lx fail(%d).\n",
 633                                 enable ? "enable" : "disable",
 634                                 dev_name(data->dev), portid_msk, ret);
 635         }
 636         return ret;
 637 }
 638
 639 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
 640                                      struct mtk_iommu_data *data,
 641                                      unsigned int region_id)
 642 {
 643         struct mtk_iommu_domain *share_dom = data->share_dom;
 644         const struct mtk_iommu_iova_region *region;
 645
 646         /* Always use share domain in sharing pgtable case */
 647         if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE) && share_dom) {
 648                 dom->iop = share_dom->iop;
 649                 dom->cfg = share_dom->cfg;
 650                 dom->domain.pgsize_bitmap = share_dom->cfg.pgsize_bitmap;
 651                 goto update_iova_region;
 652         }
 653
 654         dom->cfg = (struct io_pgtable_cfg) {
 655                 .quirks = IO_PGTABLE_QUIRK_ARM_NS |
 656                         IO_PGTABLE_QUIRK_NO_PERMS |
 657                         IO_PGTABLE_QUIRK_ARM_MTK_EXT,
 658                 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
 659                 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32,
 660                 .iommu_dev = data->dev,
 661         };
 662
 663         if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
 664                 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
 665
 666         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
 667                 dom->cfg.oas = data->enable_4GB ? 33 : 32;
 668         else
 669                 dom->cfg.oas = 35;
 670
 671         dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
 672         if (!dom->iop) {
 673                 dev_err(data->dev, "Failed to alloc io pgtable\n");
 674                 return -ENOMEM;
 675         }
 676
 677         /* Update our support page sizes bitmap */
 678         dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
 679
 680         if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE))
 681                 data->share_dom = dom;
 682
 683 update_iova_region:
 684         /* Update the iova region for this domain */
 685         region = data->plat_data->iova_region + region_id;
 686         dom->domain.geometry.aperture_start = region->iova_base;
 687         dom->domain.geometry.aperture_end = region->iova_base + region->size - 1;
 688         dom->domain.geometry.force_aperture = true;
 689         return 0;
 690 }
 691
 692 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
 693 {
 694         struct mtk_iommu_domain *dom;
 695
 696         if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED)
 697                 return NULL;
 698
 699         dom = kzalloc(sizeof(*dom), GFP_KERNEL);
 700         if (!dom)
 701                 return NULL;
 702         mutex_init(&dom->mutex);
 703
 704         return &dom->domain;
 705 }
 706
 707 static void mtk_iommu_domain_free(struct iommu_domain *domain)
 708 {
 709         kfree(to_mtk_domain(domain));
 710 }
 711
 712 static int mtk_iommu_attach_device(struct iommu_domain *domain,
 713                                    struct device *dev)
 714 {
 715         struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata;
 716         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 717         struct list_head *hw_list = data->hw_list;
 718         struct device *m4udev = data->dev;
 719         struct mtk_iommu_bank_data *bank;
 720         unsigned int bankid;
 721         int ret, region_id;
 722
 723         region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data);
 724         if (region_id < 0)
 725                 return region_id;
 726
 727         bankid = mtk_iommu_get_bank_id(dev, data->plat_data);
 728         mutex_lock(&dom->mutex);
 729         if (!dom->bank) {
 730                 /* Data is in the frstdata in sharing pgtable case. */
 731                 frstdata = mtk_iommu_get_frst_data(hw_list);
 732
 733                 mutex_lock(&frstdata->mutex);
 734                 ret = mtk_iommu_domain_finalise(dom, frstdata, region_id);
 735                 mutex_unlock(&frstdata->mutex);
 736                 if (ret) {
 737                         mutex_unlock(&dom->mutex);
 738                         return ret;
 739                 }
 740                 dom->bank = &data->bank[bankid];
 741         }
 742         mutex_unlock(&dom->mutex);
 743
 744         mutex_lock(&data->mutex);
 745         bank = &data->bank[bankid];
 746         if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */
 747                 ret = pm_runtime_resume_and_get(m4udev);
 748                 if (ret < 0) {
 749                         dev_err(m4udev, "pm get fail(%d) in attach.\n", ret);
 750                         goto err_unlock;
 751                 }
 752
 753                 ret = mtk_iommu_hw_init(data, bankid);
 754                 if (ret) {
 755                         pm_runtime_put(m4udev);
 756                         goto err_unlock;
 757                 }
 758                 bank->m4u_dom = dom;
 759                 writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR);
 760
 761                 pm_runtime_put(m4udev);
 762         }
 763         mutex_unlock(&data->mutex);
 764
 765         if (region_id > 0) {
 766                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34));
 767                 if (ret) {
 768                         dev_err(m4udev, "Failed to set dma_mask for %s(%d).\n", dev_name(dev), ret);
 769                         return ret;
 770                 }
 771         }
 772
 773         return mtk_iommu_config(data, dev, true, region_id);
 774
 775 err_unlock:
 776         mutex_unlock(&data->mutex);
 777         return ret;
 778 }
 779
 780 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
 781                          phys_addr_t paddr, size_t pgsize, size_t pgcount,
 782                          int prot, gfp_t gfp, size_t *mapped)
 783 {
 784         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 785
 786         /* The "4GB mode" M4U physically can not use the lower remap of Dram. */
 787         if (dom->bank->parent_data->enable_4GB)
 788                 paddr |= BIT_ULL(32);
 789
 790         /* Synchronize with the tlb_lock */
 791         return dom->iop->map_pages(dom->iop, iova, paddr, pgsize, pgcount, prot, gfp, mapped);
 792 }
 793
 794 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
 795                               unsigned long iova, size_t pgsize, size_t pgcount,
 796                               struct iommu_iotlb_gather *gather)
 797 {
 798         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 799
 800         iommu_iotlb_gather_add_range(gather, iova, pgsize * pgcount);
 801         return dom->iop->unmap_pages(dom->iop, iova, pgsize, pgcount, gather);
 802 }
 803
 804 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
 805 {
 806         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 807
 808         if (dom->bank)
 809                 mtk_iommu_tlb_flush_all(dom->bank->parent_data);
 810 }
 811
 812 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
 813                                  struct iommu_iotlb_gather *gather)
 814 {
 815         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 816         size_t length = gather->end - gather->start + 1;
 817
 818         mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank);
 819 }
 820
 821 static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
 822                                size_t size)
 823 {
 824         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 825
 826         mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank);
 827 }
 828
 829 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
 830                                           dma_addr_t iova)
 831 {
 832         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 833         phys_addr_t pa;
 834
 835         pa = dom->iop->iova_to_phys(dom->iop, iova);
 836         if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
 837             dom->bank->parent_data->enable_4GB &&
 838             pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
 839                 pa &= ~BIT_ULL(32);
 840
 841         return pa;
 842 }
 843
 844 static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
 845 {
 846         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 847         struct mtk_iommu_data *data;
 848         struct device_link *link;
 849         struct device *larbdev;
 850         unsigned int larbid, larbidx, i;
 851
 852         if (!fwspec || fwspec->ops != &mtk_iommu_ops)
 853                 return ERR_PTR(-ENODEV); /* Not a iommu client device */
 854
 855         data = dev_iommu_priv_get(dev);
 856
 857         if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
 858                 return &data->iommu;
 859
 860         /*
 861          * Link the consumer device with the smi-larb device(supplier).
 862          * The device that connects with each a larb is a independent HW.
 863          * All the ports in each a device should be in the same larbs.
 864          */
 865         larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
 866         if (larbid >= MTK_LARB_NR_MAX)
 867                 return ERR_PTR(-EINVAL);
 868
 869         for (i = 1; i < fwspec->num_ids; i++) {
 870                 larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]);
 871                 if (larbid != larbidx) {
 872                         dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n",
 873                                 larbid, larbidx);
 874                         return ERR_PTR(-EINVAL);
 875                 }
 876         }
 877         larbdev = data->larb_imu[larbid].dev;
 878         if (!larbdev)
 879                 return ERR_PTR(-EINVAL);
 880
 881         link = device_link_add(dev, larbdev,
 882                                DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
 883         if (!link)
 884                 dev_err(dev, "Unable to link %s\n", dev_name(larbdev));
 885         return &data->iommu;
 886 }
 887
 888 static void mtk_iommu_release_device(struct device *dev)
 889 {
 890         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 891         struct mtk_iommu_data *data;
 892         struct device *larbdev;
 893         unsigned int larbid;
 894
 895         data = dev_iommu_priv_get(dev);
 896         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
 897                 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
 898                 larbdev = data->larb_imu[larbid].dev;
 899                 device_link_remove(dev, larbdev);
 900         }
 901 }
 902
 903 static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data)
 904 {
 905         unsigned int bankid;
 906
 907         /*
 908          * If the bank function is enabled, each bank is a iommu group/domain.
 909          * Otherwise, each iova region is a iommu group/domain.
 910          */
 911         bankid = mtk_iommu_get_bank_id(dev, plat_data);
 912         if (bankid)
 913                 return bankid;
 914
 915         return mtk_iommu_get_iova_region_id(dev, plat_data);
 916 }
 917
 918 static struct iommu_group *mtk_iommu_device_group(struct device *dev)
 919 {
 920         struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data;
 921         struct list_head *hw_list = c_data->hw_list;
 922         struct iommu_group *group;
 923         int groupid;
 924
 925         data = mtk_iommu_get_frst_data(hw_list);
 926         if (!data)
 927                 return ERR_PTR(-ENODEV);
 928
 929         groupid = mtk_iommu_get_group_id(dev, data->plat_data);
 930         if (groupid < 0)
 931                 return ERR_PTR(groupid);
 932
 933         mutex_lock(&data->mutex);
 934         group = data->m4u_group[groupid];
 935         if (!group) {
 936                 group = iommu_group_alloc();
 937                 if (!IS_ERR(group))
 938                         data->m4u_group[groupid] = group;
 939         } else {
 940                 iommu_group_ref_get(group);
 941         }
 942         mutex_unlock(&data->mutex);
 943         return group;
 944 }
 945
 946 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
 947 {
 948         struct platform_device *m4updev;
 949
 950         if (args->args_count != 1) {
 951                 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
 952                         args->args_count);
 953                 return -EINVAL;
 954         }
 955
 956         if (!dev_iommu_priv_get(dev)) {
 957                 /* Get the m4u device */
 958                 m4updev = of_find_device_by_node(args->np);
 959                 if (WARN_ON(!m4updev))
 960                         return -EINVAL;
 961
 962                 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
 963         }
 964
 965         return iommu_fwspec_add_ids(dev, args->args, 1);
 966 }
 967
 968 static void mtk_iommu_get_resv_regions(struct device *dev,
 969                                        struct list_head *head)
 970 {
 971         struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
 972         unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i;
 973         const struct mtk_iommu_iova_region *resv, *curdom;
 974         struct iommu_resv_region *region;
 975         int prot = IOMMU_WRITE | IOMMU_READ;
 976
 977         if ((int)regionid < 0)
 978                 return;
 979         curdom = data->plat_data->iova_region + regionid;
 980         for (i = 0; i < data->plat_data->iova_region_nr; i++) {
 981                 resv = data->plat_data->iova_region + i;
 982
 983                 /* Only reserve when the region is inside the current domain */
 984                 if (resv->iova_base <= curdom->iova_base ||
 985                     resv->iova_base + resv->size >= curdom->iova_base + curdom->size)
 986                         continue;
 987
 988                 region = iommu_alloc_resv_region(resv->iova_base, resv->size,
 989                                                  prot, IOMMU_RESV_RESERVED,
 990                                                  GFP_KERNEL);
 991                 if (!region)
 992                         return;
 993
 994                 list_add_tail(&region->list, head);
 995         }
 996 }
 997
 998 static const struct iommu_ops mtk_iommu_ops = {
 999         .domain_alloc   = mtk_iommu_domain_alloc,
1000         .probe_device   = mtk_iommu_probe_device,
1001         .release_device = mtk_iommu_release_device,
1002         .device_group   = mtk_iommu_device_group,
1003         .of_xlate       = mtk_iommu_of_xlate,
1004         .get_resv_regions = mtk_iommu_get_resv_regions,
1005         .pgsize_bitmap  = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
1006         .owner          = THIS_MODULE,
1007         .default_domain_ops = &(const struct iommu_domain_ops) {
1008                 .attach_dev     = mtk_iommu_attach_device,
1009                 .map_pages      = mtk_iommu_map,
1010                 .unmap_pages    = mtk_iommu_unmap,
1011                 .flush_iotlb_all = mtk_iommu_flush_iotlb_all,
1012                 .iotlb_sync     = mtk_iommu_iotlb_sync,
1013                 .iotlb_sync_map = mtk_iommu_sync_map,
1014                 .iova_to_phys   = mtk_iommu_iova_to_phys,
1015                 .free           = mtk_iommu_domain_free,
1016         }
1017 };
1018
1019 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid)
1020 {
1021         const struct mtk_iommu_bank_data *bankx = &data->bank[bankid];
1022         const struct mtk_iommu_bank_data *bank0 = &data->bank[0];
1023         u32 regval;
1024
1025         /*
1026          * Global control settings are in bank0. May re-init these global registers
1027          * since no sure if there is bank0 consumers.
1028          */
1029         if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) {
1030                 regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
1031                          F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
1032         } else {
1033                 regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG);
1034                 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
1035         }
1036         writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG);
1037
1038         if (data->enable_4GB &&
1039             MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
1040                 /*
1041                  * If 4GB mode is enabled, the validate PA range is from
1042                  * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
1043                  */
1044                 regval = F_MMU_VLD_PA_RNG(7, 4);
1045                 writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG);
1046         }
1047         if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE))
1048                 writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS);
1049         else
1050                 writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS);
1051
1052         if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) {
1053                 /* write command throttling mode */
1054                 regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL);
1055                 regval &= ~F_MMU_WR_THROT_DIS_MASK;
1056                 writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL);
1057         }
1058
1059         if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
1060                 /* The register is called STANDARD_AXI_MODE in this case */
1061                 regval = 0;
1062         } else {
1063                 regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL);
1064                 if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE))
1065                         regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
1066                 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
1067                         regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
1068         }
1069         writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL);
1070
1071         /* Independent settings for each bank */
1072         regval = F_L2_MULIT_HIT_EN |
1073                 F_TABLE_WALK_FAULT_INT_EN |
1074                 F_PREETCH_FIFO_OVERFLOW_INT_EN |
1075                 F_MISS_FIFO_OVERFLOW_INT_EN |
1076                 F_PREFETCH_FIFO_ERR_INT_EN |
1077                 F_MISS_FIFO_ERR_INT_EN;
1078         writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0);
1079
1080         regval = F_INT_TRANSLATION_FAULT |
1081                 F_INT_MAIN_MULTI_HIT_FAULT |
1082                 F_INT_INVALID_PA_FAULT |
1083                 F_INT_ENTRY_REPLACEMENT_FAULT |
1084                 F_INT_TLB_MISS_FAULT |
1085                 F_INT_MISS_TRANSACTION_FIFO_FAULT |
1086                 F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
1087         writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL);
1088
1089         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
1090                 regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
1091         else
1092                 regval = lower_32_bits(data->protect_base) |
1093                          upper_32_bits(data->protect_base);
1094         writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR);
1095
1096         if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0,
1097                              dev_name(bankx->parent_dev), (void *)bankx)) {
1098                 writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR);
1099                 dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq);
1100                 return -ENODEV;
1101         }
1102
1103         return 0;
1104 }
1105
1106 static const struct component_master_ops mtk_iommu_com_ops = {
1107         .bind           = mtk_iommu_bind,
1108         .unbind         = mtk_iommu_unbind,
1109 };
1110
1111 static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match,
1112                                   struct mtk_iommu_data *data)
1113 {
1114         struct device_node *larbnode, *frst_avail_smicomm_node = NULL;
1115         struct platform_device *plarbdev, *pcommdev;
1116         struct device_link *link;
1117         int i, larb_nr, ret;
1118
1119         larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL);
1120         if (larb_nr < 0)
1121                 return larb_nr;
1122         if (larb_nr == 0 || larb_nr > MTK_LARB_NR_MAX)
1123                 return -EINVAL;
1124
1125         for (i = 0; i < larb_nr; i++) {
1126                 struct device_node *smicomm_node, *smi_subcomm_node;
1127                 u32 id;
1128
1129                 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
1130                 if (!larbnode) {
1131                         ret = -EINVAL;
1132                         goto err_larbdev_put;
1133                 }
1134
1135                 if (!of_device_is_available(larbnode)) {
1136                         of_node_put(larbnode);
1137                         continue;
1138                 }
1139
1140                 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
1141                 if (ret)/* The id is consecutive if there is no this property */
1142                         id = i;
1143                 if (id >= MTK_LARB_NR_MAX) {
1144                         of_node_put(larbnode);
1145                         ret = -EINVAL;
1146                         goto err_larbdev_put;
1147                 }
1148
1149                 plarbdev = of_find_device_by_node(larbnode);
1150                 of_node_put(larbnode);
1151                 if (!plarbdev) {
1152                         ret = -ENODEV;
1153                         goto err_larbdev_put;
1154                 }
1155                 if (data->larb_imu[id].dev) {
1156                         platform_device_put(plarbdev);
1157                         ret = -EEXIST;
1158                         goto err_larbdev_put;
1159                 }
1160                 data->larb_imu[id].dev = &plarbdev->dev;
1161
1162                 if (!plarbdev->dev.driver) {
1163                         ret = -EPROBE_DEFER;
1164                         goto err_larbdev_put;
1165                 }
1166
1167                 /* Get smi-(sub)-common dev from the last larb. */
1168                 smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0);
1169                 if (!smi_subcomm_node) {
1170                         ret = -EINVAL;
1171                         goto err_larbdev_put;
1172                 }
1173
1174                 /*
1175                  * It may have two level smi-common. the node is smi-sub-common if it
1176                  * has a new mediatek,smi property. otherwise it is smi-commmon.
1177                  */
1178                 smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0);
1179                 if (smicomm_node)
1180                         of_node_put(smi_subcomm_node);
1181                 else
1182                         smicomm_node = smi_subcomm_node;
1183
1184                 /*
1185                  * All the larbs that connect to one IOMMU must connect with the same
1186                  * smi-common.
1187                  */
1188                 if (!frst_avail_smicomm_node) {
1189                         frst_avail_smicomm_node = smicomm_node;
1190                 } else if (frst_avail_smicomm_node != smicomm_node) {
1191                         dev_err(dev, "mediatek,smi property is not right @larb%d.", id);
1192                         of_node_put(smicomm_node);
1193                         ret = -EINVAL;
1194                         goto err_larbdev_put;
1195                 } else {
1196                         of_node_put(smicomm_node);
1197                 }
1198
1199                 component_match_add(dev, match, component_compare_dev, &plarbdev->dev);
1200                 platform_device_put(plarbdev);
1201         }
1202
1203         if (!frst_avail_smicomm_node)
1204                 return -EINVAL;
1205
1206         pcommdev = of_find_device_by_node(frst_avail_smicomm_node);
1207         of_node_put(frst_avail_smicomm_node);
1208         if (!pcommdev)
1209                 return -ENODEV;
1210         data->smicomm_dev = &pcommdev->dev;
1211
1212         link = device_link_add(data->smicomm_dev, dev,
1213                                DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
1214         platform_device_put(pcommdev);
1215         if (!link) {
1216                 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev));
1217                 return -EINVAL;
1218         }
1219         return 0;
1220
1221 err_larbdev_put:
1222         for (i = MTK_LARB_NR_MAX - 1; i >= 0; i--) {
1223                 if (!data->larb_imu[i].dev)
1224                         continue;
1225                 put_device(data->larb_imu[i].dev);
1226         }
1227         return ret;
1228 }
1229
1230 static int mtk_iommu_probe(struct platform_device *pdev)
1231 {
1232         struct mtk_iommu_data   *data;
1233         struct device           *dev = &pdev->dev;
1234         struct resource         *res;
1235         resource_size_t         ioaddr;
1236         struct component_match  *match = NULL;
1237         struct regmap           *infracfg;
1238         void                    *protect;
1239         int                     ret, banks_num, i = 0;
1240         u32                     val;
1241         char                    *p;
1242         struct mtk_iommu_bank_data *bank;
1243         void __iomem            *base;
1244
1245         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1246         if (!data)
1247                 return -ENOMEM;
1248         data->dev = dev;
1249         data->plat_data = of_device_get_match_data(dev);
1250
1251         /* Protect memory. HW will access here while translation fault.*/
1252         protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
1253         if (!protect)
1254                 return -ENOMEM;
1255         data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
1256
1257         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) {
1258                 infracfg = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,infracfg");
1259                 if (IS_ERR(infracfg)) {
1260                         /*
1261                          * Legacy devicetrees will not specify a phandle to
1262                          * mediatek,infracfg: in that case, we use the older
1263                          * way to retrieve a syscon to infra.
1264                          *
1265                          * This is for retrocompatibility purposes only, hence
1266                          * no more compatibles shall be added to this.
1267                          */
1268                         switch (data->plat_data->m4u_plat) {
1269                         case M4U_MT2712:
1270                                 p = "mediatek,mt2712-infracfg";
1271                                 break;
1272                         case M4U_MT8173:
1273                                 p = "mediatek,mt8173-infracfg";
1274                                 break;
1275                         default:
1276                                 p = NULL;
1277                         }
1278
1279                         infracfg = syscon_regmap_lookup_by_compatible(p);
1280                         if (IS_ERR(infracfg))
1281                                 return PTR_ERR(infracfg);
1282                 }
1283
1284                 ret = regmap_read(infracfg, REG_INFRA_MISC, &val);
1285                 if (ret)
1286                         return ret;
1287                 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN);
1288         }
1289
1290         banks_num = data->plat_data->banks_num;
1291         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1292         if (!res)
1293                 return -EINVAL;
1294         if (resource_size(res) < banks_num * MTK_IOMMU_BANK_SZ) {
1295                 dev_err(dev, "banknr %d. res %pR is not enough.\n", banks_num, res);
1296                 return -EINVAL;
1297         }
1298         base = devm_ioremap_resource(dev, res);
1299         if (IS_ERR(base))
1300                 return PTR_ERR(base);
1301         ioaddr = res->start;
1302
1303         data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL);
1304         if (!data->bank)
1305                 return -ENOMEM;
1306
1307         do {
1308                 if (!data->plat_data->banks_enable[i])
1309                         continue;
1310                 bank = &data->bank[i];
1311                 bank->id = i;
1312                 bank->base = base + i * MTK_IOMMU_BANK_SZ;
1313                 bank->m4u_dom = NULL;
1314
1315                 bank->irq = platform_get_irq(pdev, i);
1316                 if (bank->irq < 0)
1317                         return bank->irq;
1318                 bank->parent_dev = dev;
1319                 bank->parent_data = data;
1320                 spin_lock_init(&bank->tlb_lock);
1321         } while (++i < banks_num);
1322
1323         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {
1324                 data->bclk = devm_clk_get(dev, "bclk");
1325                 if (IS_ERR(data->bclk))
1326                         return PTR_ERR(data->bclk);
1327         }
1328
1329         if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) {
1330                 ret = dma_set_mask(dev, DMA_BIT_MASK(35));
1331                 if (ret) {
1332                         dev_err(dev, "Failed to set dma_mask 35.\n");
1333                         return ret;
1334                 }
1335         }
1336
1337         pm_runtime_enable(dev);
1338
1339         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1340                 ret = mtk_iommu_mm_dts_parse(dev, &match, data);
1341                 if (ret) {
1342                         dev_err_probe(dev, ret, "mm dts parse fail\n");
1343                         goto out_runtime_disable;
1344                 }
1345         } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) &&
1346                    !MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) {
1347                 p = data->plat_data->pericfg_comp_str;
1348                 data->pericfg = syscon_regmap_lookup_by_compatible(p);
1349                 if (IS_ERR(data->pericfg)) {
1350                         ret = PTR_ERR(data->pericfg);
1351                         goto out_runtime_disable;
1352                 }
1353         }
1354
1355         platform_set_drvdata(pdev, data);
1356         mutex_init(&data->mutex);
1357
1358         ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,
1359                                      "mtk-iommu.%pa", &ioaddr);
1360         if (ret)
1361                 goto out_link_remove;
1362
1363         ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev);
1364         if (ret)
1365                 goto out_sysfs_remove;
1366
1367         if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) {
1368                 list_add_tail(&data->list, data->plat_data->hw_list);
1369                 data->hw_list = data->plat_data->hw_list;
1370         } else {
1371                 INIT_LIST_HEAD(&data->hw_list_head);
1372                 list_add_tail(&data->list, &data->hw_list_head);
1373                 data->hw_list = &data->hw_list_head;
1374         }
1375
1376         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1377                 ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
1378                 if (ret)
1379                         goto out_list_del;
1380         }
1381         return ret;
1382
1383 out_list_del:
1384         list_del(&data->list);
1385         iommu_device_unregister(&data->iommu);
1386 out_sysfs_remove:
1387         iommu_device_sysfs_remove(&data->iommu);
1388 out_link_remove:
1389         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
1390                 device_link_remove(data->smicomm_dev, dev);
1391 out_runtime_disable:
1392         pm_runtime_disable(dev);
1393         return ret;
1394 }
1395
1396 static void mtk_iommu_remove(struct platform_device *pdev)
1397 {
1398         struct mtk_iommu_data *data = platform_get_drvdata(pdev);
1399         struct mtk_iommu_bank_data *bank;
1400         int i;
1401
1402         iommu_device_sysfs_remove(&data->iommu);
1403         iommu_device_unregister(&data->iommu);
1404
1405         list_del(&data->list);
1406
1407         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1408                 device_link_remove(data->smicomm_dev, &pdev->dev);
1409                 component_master_del(&pdev->dev, &mtk_iommu_com_ops);
1410         }
1411         pm_runtime_disable(&pdev->dev);
1412         for (i = 0; i < data->plat_data->banks_num; i++) {
1413                 bank = &data->bank[i];
1414                 if (!bank->m4u_dom)
1415                         continue;
1416                 devm_free_irq(&pdev->dev, bank->irq, bank);
1417         }
1418 }
1419
1420 static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev)
1421 {
1422         struct mtk_iommu_data *data = dev_get_drvdata(dev);
1423         struct mtk_iommu_suspend_reg *reg = &data->reg;
1424         void __iomem *base;
1425         int i = 0;
1426
1427         base = data->bank[i].base;
1428         reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
1429         reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
1430         reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
1431         reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
1432         reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
1433         do {
1434                 if (!data->plat_data->banks_enable[i])
1435                         continue;
1436                 base = data->bank[i].base;
1437                 reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0);
1438                 reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
1439                 reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR);
1440         } while (++i < data->plat_data->banks_num);
1441         clk_disable_unprepare(data->bclk);
1442         return 0;
1443 }
1444
1445 static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
1446 {
1447         struct mtk_iommu_data *data = dev_get_drvdata(dev);
1448         struct mtk_iommu_suspend_reg *reg = &data->reg;
1449         struct mtk_iommu_domain *m4u_dom;
1450         void __iomem *base;
1451         int ret, i = 0;
1452
1453         ret = clk_prepare_enable(data->bclk);
1454         if (ret) {
1455                 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
1456                 return ret;
1457         }
1458
1459         /*
1460          * Uppon first resume, only enable the clk and return, since the values of the
1461          * registers are not yet set.
1462          */
1463         if (!reg->wr_len_ctrl)
1464                 return 0;
1465
1466         base = data->bank[i].base;
1467         writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
1468         writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
1469         writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
1470         writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
1471         writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
1472         do {
1473                 m4u_dom = data->bank[i].m4u_dom;
1474                 if (!data->plat_data->banks_enable[i] || !m4u_dom)
1475                         continue;
1476                 base = data->bank[i].base;
1477                 writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
1478                 writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
1479                 writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
1480                 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR);
1481         } while (++i < data->plat_data->banks_num);
1482
1483         /*
1484          * Users may allocate dma buffer before they call pm_runtime_get,
1485          * in which case it will lack the necessary tlb flush.
1486          * Thus, make sure to update the tlb after each PM resume.
1487          */
1488         mtk_iommu_tlb_flush_all(data);
1489         return 0;
1490 }
1491
1492 static const struct dev_pm_ops mtk_iommu_pm_ops = {
1493         SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL)
1494         SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1495                                      pm_runtime_force_resume)
1496 };
1497
1498 static const struct mtk_iommu_plat_data mt2712_data = {
1499         .m4u_plat     = M4U_MT2712,
1500         .flags        = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE |
1501                         MTK_IOMMU_TYPE_MM,
1502         .hw_list      = &m4ulist,
1503         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1504         .iova_region  = single_domain,
1505         .banks_num    = 1,
1506         .banks_enable = {true},
1507         .iova_region_nr = ARRAY_SIZE(single_domain),
1508         .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
1509 };
1510
1511 static const struct mtk_iommu_plat_data mt6779_data = {
1512         .m4u_plat      = M4U_MT6779,
1513         .flags         = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
1514                          MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN,
1515         .inv_sel_reg   = REG_MMU_INV_SEL_GEN2,
1516         .banks_num    = 1,
1517         .banks_enable = {true},
1518         .iova_region   = single_domain,
1519         .iova_region_nr = ARRAY_SIZE(single_domain),
1520         .larbid_remap  = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
1521 };
1522
1523 static const struct mtk_iommu_plat_data mt6795_data = {
1524         .m4u_plat     = M4U_MT6795,
1525         .flags        = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
1526                         HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM |
1527                         TF_PORT_TO_ADDR_MT8173,
1528         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1529         .banks_num    = 1,
1530         .banks_enable = {true},
1531         .iova_region  = single_domain,
1532         .iova_region_nr = ARRAY_SIZE(single_domain),
1533         .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */
1534 };
1535
1536 static const struct mtk_iommu_plat_data mt8167_data = {
1537         .m4u_plat     = M4U_MT8167,
1538         .flags        = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM,
1539         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1540         .banks_num    = 1,
1541         .banks_enable = {true},
1542         .iova_region  = single_domain,
1543         .iova_region_nr = ARRAY_SIZE(single_domain),
1544         .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
1545 };
1546
1547 static const struct mtk_iommu_plat_data mt8173_data = {
1548         .m4u_plat     = M4U_MT8173,
1549         .flags        = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
1550                         HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM |
1551                         TF_PORT_TO_ADDR_MT8173,
1552         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1553         .banks_num    = 1,
1554         .banks_enable = {true},
1555         .iova_region  = single_domain,
1556         .iova_region_nr = ARRAY_SIZE(single_domain),
1557         .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
1558 };
1559
1560 static const struct mtk_iommu_plat_data mt8183_data = {
1561         .m4u_plat     = M4U_MT8183,
1562         .flags        = RESET_AXI | MTK_IOMMU_TYPE_MM,
1563         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1564         .banks_num    = 1,
1565         .banks_enable = {true},
1566         .iova_region  = single_domain,
1567         .iova_region_nr = ARRAY_SIZE(single_domain),
1568         .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
1569 };
1570
1571 static const unsigned int mt8186_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
1572         [0] = {~0, ~0, ~0},                     /* Region0: all ports for larb0/1/2 */
1573         [1] = {0, 0, 0, 0, ~0, 0, 0, ~0},       /* Region1: larb4/7 */
1574         [2] = {0, 0, 0, 0, 0, 0, 0, 0,          /* Region2: larb8/9/11/13/16/17/19/20 */
1575                ~0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), 0, 0,
1576                                                 /* larb13: the other ports except port9/10 */
1577                ~0, ~0, 0, ~0, ~0},
1578         [3] = {0},
1579         [4] = {[13] = BIT(9) | BIT(10)},        /* larb13 port9/10 */
1580         [5] = {[14] = ~0},                      /* larb14 */
1581 };
1582
1583 static const struct mtk_iommu_plat_data mt8186_data_mm = {
1584         .m4u_plat       = M4U_MT8186,
1585         .flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1586                           WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM,
1587         .larbid_remap   = {{0}, {1, MTK_INVALID_LARBID, 8}, {4}, {7}, {2}, {9, 11, 19, 20},
1588                            {MTK_INVALID_LARBID, 14, 16},
1589                            {MTK_INVALID_LARBID, 13, MTK_INVALID_LARBID, 17}},
1590         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1591         .banks_num      = 1,
1592         .banks_enable   = {true},
1593         .iova_region    = mt8192_multi_dom,
1594         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1595         .iova_region_larb_msk = mt8186_larb_region_msk,
1596 };
1597
1598 static const struct mtk_iommu_plat_data mt8188_data_infra = {
1599         .m4u_plat         = M4U_MT8188,
1600         .flags            = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO |
1601                             MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT |
1602                             PGTABLE_PA_35_EN | CFG_IFA_MASTER_IN_ATF,
1603         .inv_sel_reg      = REG_MMU_INV_SEL_GEN2,
1604         .banks_num        = 1,
1605         .banks_enable     = {true},
1606         .iova_region      = single_domain,
1607         .iova_region_nr   = ARRAY_SIZE(single_domain),
1608 };
1609
1610 static const u32 mt8188_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
1611         [0] = {~0, ~0, ~0, ~0},               /* Region0: all ports for larb0/1/2/3 */
1612         [1] = {0, 0, 0, 0, 0, 0, 0, 0,
1613                0, 0, 0, 0, 0, 0, 0, 0,
1614                0, 0, 0, 0, 0, ~0, ~0, ~0},    /* Region1: larb19(21)/21(22)/23 */
1615         [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0,    /* Region2: the other larbs. */
1616                ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0,
1617                ~0, ~0, ~0, ~0, ~0, 0, 0, 0,
1618                0, ~0},
1619         [3] = {0},
1620         [4] = {[24] = BIT(0) | BIT(1)},       /* Only larb27(24) port0/1 */
1621         [5] = {[24] = BIT(2) | BIT(3)},       /* Only larb27(24) port2/3 */
1622 };
1623
1624 static const struct mtk_iommu_plat_data mt8188_data_vdo = {
1625         .m4u_plat       = M4U_MT8188,
1626         .flags          = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
1627                           WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE |
1628                           PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
1629         .hw_list        = &m4ulist,
1630         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1631         .banks_num      = 1,
1632         .banks_enable   = {true},
1633         .iova_region    = mt8192_multi_dom,
1634         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1635         .iova_region_larb_msk = mt8188_larb_region_msk,
1636         .larbid_remap   = {{2}, {0}, {21}, {0}, {19}, {9, 10,
1637                            11 /* 11a */, 25 /* 11c */},
1638                            {13, 0, 29 /* 16b */, 30 /* 17b */, 0}, {5}},
1639 };
1640
1641 static const struct mtk_iommu_plat_data mt8188_data_vpp = {
1642         .m4u_plat       = M4U_MT8188,
1643         .flags          = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
1644                           WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE |
1645                           PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
1646         .hw_list        = &m4ulist,
1647         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1648         .banks_num      = 1,
1649         .banks_enable   = {true},
1650         .iova_region    = mt8192_multi_dom,
1651         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1652         .iova_region_larb_msk = mt8188_larb_region_msk,
1653         .larbid_remap   = {{1}, {3}, {23}, {7}, {MTK_INVALID_LARBID},
1654                            {12, 15, 24 /* 11b */}, {14, MTK_INVALID_LARBID,
1655                            16 /* 16a */, 17 /* 17a */, MTK_INVALID_LARBID,
1656                            27, 28 /* ccu0 */, MTK_INVALID_LARBID}, {4, 6}},
1657 };
1658
1659 static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
1660         [0] = {~0, ~0},                         /* Region0: larb0/1 */
1661         [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0},      /* Region1: larb4/5/7 */
1662         [2] = {0, 0, ~0, 0, 0, 0, 0, 0,         /* Region2: larb2/9/11/13/14/16/17/18/19/20 */
1663                0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), ~(u32)(BIT(4) | BIT(5)), 0,
1664                ~0, ~0, ~0, ~0, ~0},
1665         [3] = {0},
1666         [4] = {[13] = BIT(9) | BIT(10)},        /* larb13 port9/10 */
1667         [5] = {[14] = BIT(4) | BIT(5)},         /* larb14 port4/5 */
1668 };
1669
1670 static const struct mtk_iommu_plat_data mt8192_data = {
1671         .m4u_plat       = M4U_MT8192,
1672         .flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1673                           WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM,
1674         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1675         .banks_num      = 1,
1676         .banks_enable   = {true},
1677         .iova_region    = mt8192_multi_dom,
1678         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1679         .iova_region_larb_msk = mt8192_larb_region_msk,
1680         .larbid_remap   = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
1681                            {0, 14, 16}, {0, 13, 18, 17}},
1682 };
1683
1684 static const struct mtk_iommu_plat_data mt8195_data_infra = {
1685         .m4u_plat         = M4U_MT8195,
1686         .flags            = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO |
1687                             MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT,
1688         .pericfg_comp_str = "mediatek,mt8195-pericfg_ao",
1689         .inv_sel_reg      = REG_MMU_INV_SEL_GEN2,
1690         .banks_num        = 5,
1691         .banks_enable     = {true, false, false, false, true},
1692         .banks_portmsk    = {[0] = GENMASK(19, 16),     /* PCIe */
1693                              [4] = GENMASK(31, 20),     /* USB */
1694                             },
1695         .iova_region      = single_domain,
1696         .iova_region_nr   = ARRAY_SIZE(single_domain),
1697 };
1698
1699 static const unsigned int mt8195_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
1700         [0] = {~0, ~0, ~0, ~0},               /* Region0: all ports for larb0/1/2/3 */
1701         [1] = {0, 0, 0, 0, 0, 0, 0, 0,
1702                0, 0, 0, 0, 0, 0, 0, 0,
1703                0, 0, 0, ~0, ~0, ~0, ~0, ~0,   /* Region1: larb19/20/21/22/23/24 */
1704                ~0},
1705         [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0,    /* Region2: the other larbs. */
1706                ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0,
1707                ~0, ~0, 0, 0, 0, 0, 0, 0,
1708                0, ~0, ~0, ~0, ~0},
1709         [3] = {0},
1710         [4] = {[18] = BIT(0) | BIT(1)},       /* Only larb18 port0/1 */
1711         [5] = {[18] = BIT(2) | BIT(3)},       /* Only larb18 port2/3 */
1712 };
1713
1714 static const struct mtk_iommu_plat_data mt8195_data_vdo = {
1715         .m4u_plat       = M4U_MT8195,
1716         .flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1717                           WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
1718         .hw_list        = &m4ulist,
1719         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1720         .banks_num      = 1,
1721         .banks_enable   = {true},
1722         .iova_region    = mt8192_multi_dom,
1723         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1724         .iova_region_larb_msk = mt8195_larb_region_msk,
1725         .larbid_remap   = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11},
1726                            {13, 17, 15/* 17b */, 25}, {5}},
1727 };
1728
1729 static const struct mtk_iommu_plat_data mt8195_data_vpp = {
1730         .m4u_plat       = M4U_MT8195,
1731         .flags          = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
1732                           WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
1733         .hw_list        = &m4ulist,
1734         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1735         .banks_num      = 1,
1736         .banks_enable   = {true},
1737         .iova_region    = mt8192_multi_dom,
1738         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1739         .iova_region_larb_msk = mt8195_larb_region_msk,
1740         .larbid_remap   = {{1}, {3},
1741                            {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23},
1742                            {8}, {20}, {12},
1743                            /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */
1744                            {14, 16, 29, 26, 30, 31, 18},
1745                            {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}},
1746 };
1747
1748 static const struct mtk_iommu_plat_data mt8365_data = {
1749         .m4u_plat       = M4U_MT8365,
1750         .flags          = RESET_AXI | INT_ID_PORT_WIDTH_6,
1751         .inv_sel_reg    = REG_MMU_INV_SEL_GEN1,
1752         .banks_num      = 1,
1753         .banks_enable   = {true},
1754         .iova_region    = single_domain,
1755         .iova_region_nr = ARRAY_SIZE(single_domain),
1756         .larbid_remap   = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
1757 };
1758
1759 static const struct of_device_id mtk_iommu_of_ids[] = {
1760         { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
1761         { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
1762         { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data},
1763         { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
1764         { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
1765         { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
1766         { .compatible = "mediatek,mt8186-iommu-mm",    .data = &mt8186_data_mm}, /* mm: m4u */
1767         { .compatible = "mediatek,mt8188-iommu-infra", .data = &mt8188_data_infra},
1768         { .compatible = "mediatek,mt8188-iommu-vdo",   .data = &mt8188_data_vdo},
1769         { .compatible = "mediatek,mt8188-iommu-vpp",   .data = &mt8188_data_vpp},
1770         { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
1771         { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
1772         { .compatible = "mediatek,mt8195-iommu-vdo",   .data = &mt8195_data_vdo},
1773         { .compatible = "mediatek,mt8195-iommu-vpp",   .data = &mt8195_data_vpp},
1774         { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data},
1775         {}
1776 };
1777
1778 static struct platform_driver mtk_iommu_driver = {
1779         .probe  = mtk_iommu_probe,
1780         .remove_new = mtk_iommu_remove,
1781         .driver = {
1782                 .name = "mtk-iommu",
1783                 .of_match_table = mtk_iommu_of_ids,
1784                 .pm = &mtk_iommu_pm_ops,
1785         }
1786 };
1787 module_platform_driver(mtk_iommu_driver);
1788
1789 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations");
1790 MODULE_LICENSE("GPL v2");