1 // SPDX-License-Identifier: GPL-2.0-only
3 * CPU-agnostic ARM page table allocator.
5 * Copyright (C) 2014 ARM Limited
7 * Author: Will Deacon <will.deacon@arm.com>
10 #define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt
12 #include <linux/atomic.h>
13 #include <linux/bitops.h>
14 #include <linux/io-pgtable.h>
15 #include <linux/kernel.h>
16 #include <linux/sizes.h>
17 #include <linux/slab.h>
18 #include <linux/types.h>
19 #include <linux/dma-mapping.h>
21 #include <asm/barrier.h>
23 #include "io-pgtable-arm.h"
25 #define ARM_LPAE_MAX_ADDR_BITS 52
26 #define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
27 #define ARM_LPAE_MAX_LEVELS 4
29 /* Struct accessors */
30 #define io_pgtable_to_data(x) \
31 container_of((x), struct arm_lpae_io_pgtable, iop)
33 #define io_pgtable_ops_to_data(x) \
34 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
37 * Calculate the right shift amount to get to the portion describing level l
38 * in a virtual address mapped by the pagetable in d.
40 #define ARM_LPAE_LVL_SHIFT(l,d) \
41 (((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level) + \
42 ilog2(sizeof(arm_lpae_iopte)))
44 #define ARM_LPAE_GRANULE(d) \
45 (sizeof(arm_lpae_iopte) << (d)->bits_per_level)
46 #define ARM_LPAE_PGD_SIZE(d) \
47 (sizeof(arm_lpae_iopte) << (d)->pgd_bits)
49 #define ARM_LPAE_PTES_PER_TABLE(d) \
50 (ARM_LPAE_GRANULE(d) >> ilog2(sizeof(arm_lpae_iopte)))
53 * Calculate the index at level l used to map virtual address a using the
56 #define ARM_LPAE_PGD_IDX(l,d) \
57 ((l) == (d)->start_level ? (d)->pgd_bits - (d)->bits_per_level : 0)
59 #define ARM_LPAE_LVL_IDX(a,l,d) \
60 (((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \
61 ((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1))
63 /* Calculate the block/page mapping size at level l for pagetable in d. */
64 #define ARM_LPAE_BLOCK_SIZE(l,d) (1ULL << ARM_LPAE_LVL_SHIFT(l,d))
67 #define ARM_LPAE_PTE_TYPE_SHIFT 0
68 #define ARM_LPAE_PTE_TYPE_MASK 0x3
70 #define ARM_LPAE_PTE_TYPE_BLOCK 1
71 #define ARM_LPAE_PTE_TYPE_TABLE 3
72 #define ARM_LPAE_PTE_TYPE_PAGE 3
74 #define ARM_LPAE_PTE_ADDR_MASK GENMASK_ULL(47,12)
76 #define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63)
77 #define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53)
78 #define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10)
79 #define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8)
80 #define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8)
81 #define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8)
82 #define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5)
83 #define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0)
85 #define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2)
86 /* Ignore the contiguous bit for block splitting */
87 #define ARM_LPAE_PTE_ATTR_HI_MASK (((arm_lpae_iopte)6) << 52)
88 #define ARM_LPAE_PTE_ATTR_MASK (ARM_LPAE_PTE_ATTR_LO_MASK | \
89 ARM_LPAE_PTE_ATTR_HI_MASK)
90 /* Software bit for solving coherency races */
91 #define ARM_LPAE_PTE_SW_SYNC (((arm_lpae_iopte)1) << 55)
94 #define ARM_LPAE_PTE_AP_UNPRIV (((arm_lpae_iopte)1) << 6)
95 #define ARM_LPAE_PTE_AP_RDONLY (((arm_lpae_iopte)2) << 6)
96 #define ARM_LPAE_PTE_ATTRINDX_SHIFT 2
97 #define ARM_LPAE_PTE_nG (((arm_lpae_iopte)1) << 11)
100 #define ARM_LPAE_PTE_HAP_FAULT (((arm_lpae_iopte)0) << 6)
101 #define ARM_LPAE_PTE_HAP_READ (((arm_lpae_iopte)1) << 6)
102 #define ARM_LPAE_PTE_HAP_WRITE (((arm_lpae_iopte)2) << 6)
103 #define ARM_LPAE_PTE_MEMATTR_OIWB (((arm_lpae_iopte)0xf) << 2)
104 #define ARM_LPAE_PTE_MEMATTR_NC (((arm_lpae_iopte)0x5) << 2)
105 #define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2)
108 #define ARM_LPAE_VTCR_SL0_MASK 0x3
110 #define ARM_LPAE_TCR_T0SZ_SHIFT 0
112 #define ARM_LPAE_VTCR_PS_SHIFT 16
113 #define ARM_LPAE_VTCR_PS_MASK 0x7
115 #define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
116 #define ARM_LPAE_MAIR_ATTR_MASK 0xff
117 #define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
118 #define ARM_LPAE_MAIR_ATTR_NC 0x44
119 #define ARM_LPAE_MAIR_ATTR_INC_OWBRWA 0xf4
120 #define ARM_LPAE_MAIR_ATTR_WBRWA 0xff
121 #define ARM_LPAE_MAIR_ATTR_IDX_NC 0
122 #define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1
123 #define ARM_LPAE_MAIR_ATTR_IDX_DEV 2
124 #define ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE 3
126 #define ARM_MALI_LPAE_TTBR_ADRMODE_TABLE (3u << 0)
127 #define ARM_MALI_LPAE_TTBR_READ_INNER BIT(2)
128 #define ARM_MALI_LPAE_TTBR_SHARE_OUTER BIT(4)
130 #define ARM_MALI_LPAE_MEMATTR_IMP_DEF 0x88ULL
131 #define ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC 0x8DULL
133 /* IOPTE accessors */
134 #define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d))
136 #define iopte_type(pte) \
137 (((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK)
139 #define iopte_prot(pte) ((pte) & ARM_LPAE_PTE_ATTR_MASK)
141 struct arm_lpae_io_pgtable {
142 struct io_pgtable iop;
151 typedef u64 arm_lpae_iopte;
153 static inline bool iopte_leaf(arm_lpae_iopte pte, int lvl,
154 enum io_pgtable_fmt fmt)
156 if (lvl == (ARM_LPAE_MAX_LEVELS - 1) && fmt != ARM_MALI_LPAE)
157 return iopte_type(pte) == ARM_LPAE_PTE_TYPE_PAGE;
159 return iopte_type(pte) == ARM_LPAE_PTE_TYPE_BLOCK;
162 static arm_lpae_iopte paddr_to_iopte(phys_addr_t paddr,
163 struct arm_lpae_io_pgtable *data)
165 arm_lpae_iopte pte = paddr;
167 /* Of the bits which overlap, either 51:48 or 15:12 are always RES0 */
168 return (pte | (pte >> (48 - 12))) & ARM_LPAE_PTE_ADDR_MASK;
171 static phys_addr_t iopte_to_paddr(arm_lpae_iopte pte,
172 struct arm_lpae_io_pgtable *data)
174 u64 paddr = pte & ARM_LPAE_PTE_ADDR_MASK;
176 if (ARM_LPAE_GRANULE(data) < SZ_64K)
179 /* Rotate the packed high-order bits back to the top */
180 return (paddr | (paddr << (48 - 12))) & (ARM_LPAE_PTE_ADDR_MASK << 4);
183 static bool selftest_running = false;
185 static dma_addr_t __arm_lpae_dma_addr(void *pages)
187 return (dma_addr_t)virt_to_phys(pages);
190 static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp,
191 struct io_pgtable_cfg *cfg)
193 struct device *dev = cfg->iommu_dev;
194 int order = get_order(size);
199 VM_BUG_ON((gfp & __GFP_HIGHMEM));
200 p = alloc_pages_node(dev_to_node(dev), gfp | __GFP_ZERO, order);
204 pages = page_address(p);
205 if (!cfg->coherent_walk) {
206 dma = dma_map_single(dev, pages, size, DMA_TO_DEVICE);
207 if (dma_mapping_error(dev, dma))
210 * We depend on the IOMMU being able to work with any physical
211 * address directly, so if the DMA layer suggests otherwise by
212 * translating or truncating them, that bodes very badly...
214 if (dma != virt_to_phys(pages))
221 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
222 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
224 __free_pages(p, order);
228 static void __arm_lpae_free_pages(void *pages, size_t size,
229 struct io_pgtable_cfg *cfg)
231 if (!cfg->coherent_walk)
232 dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages),
233 size, DMA_TO_DEVICE);
234 free_pages((unsigned long)pages, get_order(size));
237 static void __arm_lpae_sync_pte(arm_lpae_iopte *ptep, int num_entries,
238 struct io_pgtable_cfg *cfg)
240 dma_sync_single_for_device(cfg->iommu_dev, __arm_lpae_dma_addr(ptep),
241 sizeof(*ptep) * num_entries, DMA_TO_DEVICE);
244 static void __arm_lpae_clear_pte(arm_lpae_iopte *ptep, struct io_pgtable_cfg *cfg)
249 if (!cfg->coherent_walk)
250 __arm_lpae_sync_pte(ptep, 1, cfg);
253 static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
254 struct iommu_iotlb_gather *gather,
255 unsigned long iova, size_t size, size_t pgcount,
256 int lvl, arm_lpae_iopte *ptep);
258 static void __arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
259 phys_addr_t paddr, arm_lpae_iopte prot,
260 int lvl, int num_entries, arm_lpae_iopte *ptep)
262 arm_lpae_iopte pte = prot;
263 struct io_pgtable_cfg *cfg = &data->iop.cfg;
264 size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
267 if (data->iop.fmt != ARM_MALI_LPAE && lvl == ARM_LPAE_MAX_LEVELS - 1)
268 pte |= ARM_LPAE_PTE_TYPE_PAGE;
270 pte |= ARM_LPAE_PTE_TYPE_BLOCK;
272 for (i = 0; i < num_entries; i++)
273 ptep[i] = pte | paddr_to_iopte(paddr + i * sz, data);
275 if (!cfg->coherent_walk)
276 __arm_lpae_sync_pte(ptep, num_entries, cfg);
279 static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
280 unsigned long iova, phys_addr_t paddr,
281 arm_lpae_iopte prot, int lvl, int num_entries,
282 arm_lpae_iopte *ptep)
286 for (i = 0; i < num_entries; i++)
287 if (iopte_leaf(ptep[i], lvl, data->iop.fmt)) {
288 /* We require an unmap first */
289 WARN_ON(!selftest_running);
291 } else if (iopte_type(ptep[i]) == ARM_LPAE_PTE_TYPE_TABLE) {
293 * We need to unmap and free the old table before
294 * overwriting it with a block entry.
296 arm_lpae_iopte *tblp;
297 size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
299 tblp = ptep - ARM_LPAE_LVL_IDX(iova, lvl, data);
300 if (__arm_lpae_unmap(data, NULL, iova + i * sz, sz, 1,
307 __arm_lpae_init_pte(data, paddr, prot, lvl, num_entries, ptep);
311 static arm_lpae_iopte arm_lpae_install_table(arm_lpae_iopte *table,
312 arm_lpae_iopte *ptep,
314 struct arm_lpae_io_pgtable *data)
316 arm_lpae_iopte old, new;
317 struct io_pgtable_cfg *cfg = &data->iop.cfg;
319 new = paddr_to_iopte(__pa(table), data) | ARM_LPAE_PTE_TYPE_TABLE;
320 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
321 new |= ARM_LPAE_PTE_NSTABLE;
324 * Ensure the table itself is visible before its PTE can be.
325 * Whilst we could get away with cmpxchg64_release below, this
326 * doesn't have any ordering semantics when !CONFIG_SMP.
330 old = cmpxchg64_relaxed(ptep, curr, new);
332 if (cfg->coherent_walk || (old & ARM_LPAE_PTE_SW_SYNC))
335 /* Even if it's not ours, there's no point waiting; just kick it */
336 __arm_lpae_sync_pte(ptep, 1, cfg);
338 WRITE_ONCE(*ptep, new | ARM_LPAE_PTE_SW_SYNC);
343 static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,
344 phys_addr_t paddr, size_t size, size_t pgcount,
345 arm_lpae_iopte prot, int lvl, arm_lpae_iopte *ptep,
346 gfp_t gfp, size_t *mapped)
348 arm_lpae_iopte *cptep, pte;
349 size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data);
350 size_t tblsz = ARM_LPAE_GRANULE(data);
351 struct io_pgtable_cfg *cfg = &data->iop.cfg;
352 int ret = 0, num_entries, max_entries, map_idx_start;
354 /* Find our entry at the current level */
355 map_idx_start = ARM_LPAE_LVL_IDX(iova, lvl, data);
356 ptep += map_idx_start;
358 /* If we can install a leaf entry at this level, then do so */
359 if (size == block_size) {
360 max_entries = ARM_LPAE_PTES_PER_TABLE(data) - map_idx_start;
361 num_entries = min_t(int, pgcount, max_entries);
362 ret = arm_lpae_init_pte(data, iova, paddr, prot, lvl, num_entries, ptep);
364 *mapped += num_entries * size;
369 /* We can't allocate tables at the final level */
370 if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1))
373 /* Grab a pointer to the next level */
374 pte = READ_ONCE(*ptep);
376 cptep = __arm_lpae_alloc_pages(tblsz, gfp, cfg);
380 pte = arm_lpae_install_table(cptep, ptep, 0, data);
382 __arm_lpae_free_pages(cptep, tblsz, cfg);
383 } else if (!cfg->coherent_walk && !(pte & ARM_LPAE_PTE_SW_SYNC)) {
384 __arm_lpae_sync_pte(ptep, 1, cfg);
387 if (pte && !iopte_leaf(pte, lvl, data->iop.fmt)) {
388 cptep = iopte_deref(pte, data);
390 /* We require an unmap first */
391 WARN_ON(!selftest_running);
396 return __arm_lpae_map(data, iova, paddr, size, pgcount, prot, lvl + 1,
400 static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
405 if (data->iop.fmt == ARM_64_LPAE_S1 ||
406 data->iop.fmt == ARM_32_LPAE_S1) {
407 pte = ARM_LPAE_PTE_nG;
408 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
409 pte |= ARM_LPAE_PTE_AP_RDONLY;
410 if (!(prot & IOMMU_PRIV))
411 pte |= ARM_LPAE_PTE_AP_UNPRIV;
413 pte = ARM_LPAE_PTE_HAP_FAULT;
414 if (prot & IOMMU_READ)
415 pte |= ARM_LPAE_PTE_HAP_READ;
416 if (prot & IOMMU_WRITE)
417 pte |= ARM_LPAE_PTE_HAP_WRITE;
421 * Note that this logic is structured to accommodate Mali LPAE
422 * having stage-1-like attributes but stage-2-like permissions.
424 if (data->iop.fmt == ARM_64_LPAE_S2 ||
425 data->iop.fmt == ARM_32_LPAE_S2) {
426 if (prot & IOMMU_MMIO)
427 pte |= ARM_LPAE_PTE_MEMATTR_DEV;
428 else if (prot & IOMMU_CACHE)
429 pte |= ARM_LPAE_PTE_MEMATTR_OIWB;
431 pte |= ARM_LPAE_PTE_MEMATTR_NC;
433 if (prot & IOMMU_MMIO)
434 pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV
435 << ARM_LPAE_PTE_ATTRINDX_SHIFT);
436 else if (prot & IOMMU_CACHE)
437 pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
438 << ARM_LPAE_PTE_ATTRINDX_SHIFT);
442 * Also Mali has its own notions of shareability wherein its Inner
443 * domain covers the cores within the GPU, and its Outer domain is
444 * "outside the GPU" (i.e. either the Inner or System domain in CPU
445 * terms, depending on coherency).
447 if (prot & IOMMU_CACHE && data->iop.fmt != ARM_MALI_LPAE)
448 pte |= ARM_LPAE_PTE_SH_IS;
450 pte |= ARM_LPAE_PTE_SH_OS;
452 if (prot & IOMMU_NOEXEC)
453 pte |= ARM_LPAE_PTE_XN;
455 if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_NS)
456 pte |= ARM_LPAE_PTE_NS;
458 if (data->iop.fmt != ARM_MALI_LPAE)
459 pte |= ARM_LPAE_PTE_AF;
464 static int arm_lpae_map_pages(struct io_pgtable_ops *ops, unsigned long iova,
465 phys_addr_t paddr, size_t pgsize, size_t pgcount,
466 int iommu_prot, gfp_t gfp, size_t *mapped)
468 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
469 struct io_pgtable_cfg *cfg = &data->iop.cfg;
470 arm_lpae_iopte *ptep = data->pgd;
471 int ret, lvl = data->start_level;
473 long iaext = (s64)iova >> cfg->ias;
475 if (WARN_ON(!pgsize || (pgsize & cfg->pgsize_bitmap) != pgsize))
478 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1)
480 if (WARN_ON(iaext || paddr >> cfg->oas))
483 /* If no access, then nothing to do */
484 if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
487 prot = arm_lpae_prot_to_pte(data, iommu_prot);
488 ret = __arm_lpae_map(data, iova, paddr, pgsize, pgcount, prot, lvl,
491 * Synchronise all PTE updates for the new mapping before there's
492 * a chance for anything to kick off a table walk for the new iova.
499 static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova,
500 phys_addr_t paddr, size_t size, int iommu_prot, gfp_t gfp)
502 return arm_lpae_map_pages(ops, iova, paddr, size, 1, iommu_prot, gfp,
506 static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,
507 arm_lpae_iopte *ptep)
509 arm_lpae_iopte *start, *end;
510 unsigned long table_size;
512 if (lvl == data->start_level)
513 table_size = ARM_LPAE_PGD_SIZE(data);
515 table_size = ARM_LPAE_GRANULE(data);
519 /* Only leaf entries at the last level */
520 if (lvl == ARM_LPAE_MAX_LEVELS - 1)
523 end = (void *)ptep + table_size;
525 while (ptep != end) {
526 arm_lpae_iopte pte = *ptep++;
528 if (!pte || iopte_leaf(pte, lvl, data->iop.fmt))
531 __arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
534 __arm_lpae_free_pages(start, table_size, &data->iop.cfg);
537 static void arm_lpae_free_pgtable(struct io_pgtable *iop)
539 struct arm_lpae_io_pgtable *data = io_pgtable_to_data(iop);
541 __arm_lpae_free_pgtable(data, data->start_level, data->pgd);
545 static size_t arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data,
546 struct iommu_iotlb_gather *gather,
547 unsigned long iova, size_t size,
548 arm_lpae_iopte blk_pte, int lvl,
549 arm_lpae_iopte *ptep, size_t pgcount)
551 struct io_pgtable_cfg *cfg = &data->iop.cfg;
552 arm_lpae_iopte pte, *tablep;
553 phys_addr_t blk_paddr;
554 size_t tablesz = ARM_LPAE_GRANULE(data);
555 size_t split_sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
556 int ptes_per_table = ARM_LPAE_PTES_PER_TABLE(data);
557 int i, unmap_idx_start = -1, num_entries = 0, max_entries;
559 if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
562 tablep = __arm_lpae_alloc_pages(tablesz, GFP_ATOMIC, cfg);
564 return 0; /* Bytes unmapped */
566 if (size == split_sz) {
567 unmap_idx_start = ARM_LPAE_LVL_IDX(iova, lvl, data);
568 max_entries = ptes_per_table - unmap_idx_start;
569 num_entries = min_t(int, pgcount, max_entries);
572 blk_paddr = iopte_to_paddr(blk_pte, data);
573 pte = iopte_prot(blk_pte);
575 for (i = 0; i < ptes_per_table; i++, blk_paddr += split_sz) {
577 if (i >= unmap_idx_start && i < (unmap_idx_start + num_entries))
580 __arm_lpae_init_pte(data, blk_paddr, pte, lvl, 1, &tablep[i]);
583 pte = arm_lpae_install_table(tablep, ptep, blk_pte, data);
584 if (pte != blk_pte) {
585 __arm_lpae_free_pages(tablep, tablesz, cfg);
587 * We may race against someone unmapping another part of this
588 * block, but anything else is invalid. We can't misinterpret
589 * a page entry here since we're never at the last level.
591 if (iopte_type(pte) != ARM_LPAE_PTE_TYPE_TABLE)
594 tablep = iopte_deref(pte, data);
595 } else if (unmap_idx_start >= 0) {
596 for (i = 0; i < num_entries; i++)
597 io_pgtable_tlb_add_page(&data->iop, gather, iova + i * size, size);
599 return num_entries * size;
602 return __arm_lpae_unmap(data, gather, iova, size, pgcount, lvl, tablep);
605 static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
606 struct iommu_iotlb_gather *gather,
607 unsigned long iova, size_t size, size_t pgcount,
608 int lvl, arm_lpae_iopte *ptep)
611 struct io_pgtable *iop = &data->iop;
612 int i = 0, num_entries, max_entries, unmap_idx_start;
614 /* Something went horribly wrong and we ran out of page table */
615 if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
618 unmap_idx_start = ARM_LPAE_LVL_IDX(iova, lvl, data);
619 ptep += unmap_idx_start;
620 pte = READ_ONCE(*ptep);
624 /* If the size matches this level, we're in the right place */
625 if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) {
626 max_entries = ARM_LPAE_PTES_PER_TABLE(data) - unmap_idx_start;
627 num_entries = min_t(int, pgcount, max_entries);
629 while (i < num_entries) {
630 pte = READ_ONCE(*ptep);
634 __arm_lpae_clear_pte(ptep, &iop->cfg);
636 if (!iopte_leaf(pte, lvl, iop->fmt)) {
637 /* Also flush any partial walks */
638 io_pgtable_tlb_flush_walk(iop, iova + i * size, size,
639 ARM_LPAE_GRANULE(data));
640 __arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
641 } else if (!iommu_iotlb_gather_queued(gather)) {
642 io_pgtable_tlb_add_page(iop, gather, iova + i * size, size);
650 } else if (iopte_leaf(pte, lvl, iop->fmt)) {
652 * Insert a table at the next level to map the old region,
653 * minus the part we want to unmap
655 return arm_lpae_split_blk_unmap(data, gather, iova, size, pte,
656 lvl + 1, ptep, pgcount);
659 /* Keep on walkin' */
660 ptep = iopte_deref(pte, data);
661 return __arm_lpae_unmap(data, gather, iova, size, pgcount, lvl + 1, ptep);
664 static size_t arm_lpae_unmap_pages(struct io_pgtable_ops *ops, unsigned long iova,
665 size_t pgsize, size_t pgcount,
666 struct iommu_iotlb_gather *gather)
668 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
669 struct io_pgtable_cfg *cfg = &data->iop.cfg;
670 arm_lpae_iopte *ptep = data->pgd;
671 long iaext = (s64)iova >> cfg->ias;
673 if (WARN_ON(!pgsize || (pgsize & cfg->pgsize_bitmap) != pgsize || !pgcount))
676 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1)
681 return __arm_lpae_unmap(data, gather, iova, pgsize, pgcount,
682 data->start_level, ptep);
685 static size_t arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova,
686 size_t size, struct iommu_iotlb_gather *gather)
688 return arm_lpae_unmap_pages(ops, iova, size, 1, gather);
691 static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
694 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
695 arm_lpae_iopte pte, *ptep = data->pgd;
696 int lvl = data->start_level;
699 /* Valid IOPTE pointer? */
703 /* Grab the IOPTE we're interested in */
704 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
705 pte = READ_ONCE(*ptep);
712 if (iopte_leaf(pte, lvl, data->iop.fmt))
713 goto found_translation;
715 /* Take it to the next level */
716 ptep = iopte_deref(pte, data);
717 } while (++lvl < ARM_LPAE_MAX_LEVELS);
719 /* Ran out of page tables to walk */
723 iova &= (ARM_LPAE_BLOCK_SIZE(lvl, data) - 1);
724 return iopte_to_paddr(pte, data) | iova;
727 static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg)
729 unsigned long granule, page_sizes;
730 unsigned int max_addr_bits = 48;
733 * We need to restrict the supported page sizes to match the
734 * translation regime for a particular granule. Aim to match
735 * the CPU page size if possible, otherwise prefer smaller sizes.
736 * While we're at it, restrict the block sizes to match the
739 if (cfg->pgsize_bitmap & PAGE_SIZE)
741 else if (cfg->pgsize_bitmap & ~PAGE_MASK)
742 granule = 1UL << __fls(cfg->pgsize_bitmap & ~PAGE_MASK);
743 else if (cfg->pgsize_bitmap & PAGE_MASK)
744 granule = 1UL << __ffs(cfg->pgsize_bitmap & PAGE_MASK);
750 page_sizes = (SZ_4K | SZ_2M | SZ_1G);
753 page_sizes = (SZ_16K | SZ_32M);
757 page_sizes = (SZ_64K | SZ_512M);
759 page_sizes |= 1ULL << 42; /* 4TB */
765 cfg->pgsize_bitmap &= page_sizes;
766 cfg->ias = min(cfg->ias, max_addr_bits);
767 cfg->oas = min(cfg->oas, max_addr_bits);
770 static struct arm_lpae_io_pgtable *
771 arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg)
773 struct arm_lpae_io_pgtable *data;
774 int levels, va_bits, pg_shift;
776 arm_lpae_restrict_pgsizes(cfg);
778 if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K)))
781 if (cfg->ias > ARM_LPAE_MAX_ADDR_BITS)
784 if (cfg->oas > ARM_LPAE_MAX_ADDR_BITS)
787 data = kmalloc(sizeof(*data), GFP_KERNEL);
791 pg_shift = __ffs(cfg->pgsize_bitmap);
792 data->bits_per_level = pg_shift - ilog2(sizeof(arm_lpae_iopte));
794 va_bits = cfg->ias - pg_shift;
795 levels = DIV_ROUND_UP(va_bits, data->bits_per_level);
796 data->start_level = ARM_LPAE_MAX_LEVELS - levels;
798 /* Calculate the actual size of our pgd (without concatenation) */
799 data->pgd_bits = va_bits - (data->bits_per_level * (levels - 1));
801 data->iop.ops = (struct io_pgtable_ops) {
803 .map_pages = arm_lpae_map_pages,
804 .unmap = arm_lpae_unmap,
805 .unmap_pages = arm_lpae_unmap_pages,
806 .iova_to_phys = arm_lpae_iova_to_phys,
812 static struct io_pgtable *
813 arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
816 struct arm_lpae_io_pgtable *data;
817 typeof(&cfg->arm_lpae_s1_cfg.tcr) tcr = &cfg->arm_lpae_s1_cfg.tcr;
820 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
821 IO_PGTABLE_QUIRK_ARM_TTBR1 |
822 IO_PGTABLE_QUIRK_ARM_OUTER_WBWA))
825 data = arm_lpae_alloc_pgtable(cfg);
830 if (cfg->coherent_walk) {
831 tcr->sh = ARM_LPAE_TCR_SH_IS;
832 tcr->irgn = ARM_LPAE_TCR_RGN_WBWA;
833 tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;
834 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_OUTER_WBWA)
837 tcr->sh = ARM_LPAE_TCR_SH_OS;
838 tcr->irgn = ARM_LPAE_TCR_RGN_NC;
839 if (!(cfg->quirks & IO_PGTABLE_QUIRK_ARM_OUTER_WBWA))
840 tcr->orgn = ARM_LPAE_TCR_RGN_NC;
842 tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;
845 tg1 = cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1;
846 switch (ARM_LPAE_GRANULE(data)) {
848 tcr->tg = tg1 ? ARM_LPAE_TCR_TG1_4K : ARM_LPAE_TCR_TG0_4K;
851 tcr->tg = tg1 ? ARM_LPAE_TCR_TG1_16K : ARM_LPAE_TCR_TG0_16K;
854 tcr->tg = tg1 ? ARM_LPAE_TCR_TG1_64K : ARM_LPAE_TCR_TG0_64K;
860 tcr->ips = ARM_LPAE_TCR_PS_32_BIT;
863 tcr->ips = ARM_LPAE_TCR_PS_36_BIT;
866 tcr->ips = ARM_LPAE_TCR_PS_40_BIT;
869 tcr->ips = ARM_LPAE_TCR_PS_42_BIT;
872 tcr->ips = ARM_LPAE_TCR_PS_44_BIT;
875 tcr->ips = ARM_LPAE_TCR_PS_48_BIT;
878 tcr->ips = ARM_LPAE_TCR_PS_52_BIT;
884 tcr->tsz = 64ULL - cfg->ias;
887 reg = (ARM_LPAE_MAIR_ATTR_NC
888 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |
889 (ARM_LPAE_MAIR_ATTR_WBRWA
890 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |
891 (ARM_LPAE_MAIR_ATTR_DEVICE
892 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV)) |
893 (ARM_LPAE_MAIR_ATTR_INC_OWBRWA
894 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE));
896 cfg->arm_lpae_s1_cfg.mair = reg;
898 /* Looking good; allocate a pgd */
899 data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data),
904 /* Ensure the empty pgd is visible before any actual TTBR write */
908 cfg->arm_lpae_s1_cfg.ttbr = virt_to_phys(data->pgd);
916 static struct io_pgtable *
917 arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
920 struct arm_lpae_io_pgtable *data;
921 typeof(&cfg->arm_lpae_s2_cfg.vtcr) vtcr = &cfg->arm_lpae_s2_cfg.vtcr;
923 /* The NS quirk doesn't apply at stage 2 */
927 data = arm_lpae_alloc_pgtable(cfg);
932 * Concatenate PGDs at level 1 if possible in order to reduce
933 * the depth of the stage-2 walk.
935 if (data->start_level == 0) {
936 unsigned long pgd_pages;
938 pgd_pages = ARM_LPAE_PGD_SIZE(data) / sizeof(arm_lpae_iopte);
939 if (pgd_pages <= ARM_LPAE_S2_MAX_CONCAT_PAGES) {
940 data->pgd_bits += data->bits_per_level;
946 if (cfg->coherent_walk) {
947 vtcr->sh = ARM_LPAE_TCR_SH_IS;
948 vtcr->irgn = ARM_LPAE_TCR_RGN_WBWA;
949 vtcr->orgn = ARM_LPAE_TCR_RGN_WBWA;
951 vtcr->sh = ARM_LPAE_TCR_SH_OS;
952 vtcr->irgn = ARM_LPAE_TCR_RGN_NC;
953 vtcr->orgn = ARM_LPAE_TCR_RGN_NC;
956 sl = data->start_level;
958 switch (ARM_LPAE_GRANULE(data)) {
960 vtcr->tg = ARM_LPAE_TCR_TG0_4K;
961 sl++; /* SL0 format is different for 4K granule size */
964 vtcr->tg = ARM_LPAE_TCR_TG0_16K;
967 vtcr->tg = ARM_LPAE_TCR_TG0_64K;
973 vtcr->ps = ARM_LPAE_TCR_PS_32_BIT;
976 vtcr->ps = ARM_LPAE_TCR_PS_36_BIT;
979 vtcr->ps = ARM_LPAE_TCR_PS_40_BIT;
982 vtcr->ps = ARM_LPAE_TCR_PS_42_BIT;
985 vtcr->ps = ARM_LPAE_TCR_PS_44_BIT;
988 vtcr->ps = ARM_LPAE_TCR_PS_48_BIT;
991 vtcr->ps = ARM_LPAE_TCR_PS_52_BIT;
997 vtcr->tsz = 64ULL - cfg->ias;
998 vtcr->sl = ~sl & ARM_LPAE_VTCR_SL0_MASK;
1000 /* Allocate pgd pages */
1001 data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data),
1006 /* Ensure the empty pgd is visible before any actual TTBR write */
1010 cfg->arm_lpae_s2_cfg.vttbr = virt_to_phys(data->pgd);
1018 static struct io_pgtable *
1019 arm_32_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
1021 if (cfg->ias > 32 || cfg->oas > 40)
1024 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
1025 return arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
1028 static struct io_pgtable *
1029 arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
1031 if (cfg->ias > 40 || cfg->oas > 40)
1034 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
1035 return arm_64_lpae_alloc_pgtable_s2(cfg, cookie);
1038 static struct io_pgtable *
1039 arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
1041 struct arm_lpae_io_pgtable *data;
1043 /* No quirks for Mali (hopefully) */
1047 if (cfg->ias > 48 || cfg->oas > 40)
1050 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
1052 data = arm_lpae_alloc_pgtable(cfg);
1056 /* Mali seems to need a full 4-level table regardless of IAS */
1057 if (data->start_level > 0) {
1058 data->start_level = 0;
1062 * MEMATTR: Mali has no actual notion of a non-cacheable type, so the
1063 * best we can do is mimic the out-of-tree driver and hope that the
1064 * "implementation-defined caching policy" is good enough. Similarly,
1065 * we'll use it for the sake of a valid attribute for our 'device'
1066 * index, although callers should never request that in practice.
1068 cfg->arm_mali_lpae_cfg.memattr =
1069 (ARM_MALI_LPAE_MEMATTR_IMP_DEF
1070 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |
1071 (ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC
1072 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |
1073 (ARM_MALI_LPAE_MEMATTR_IMP_DEF
1074 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));
1076 data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data), GFP_KERNEL,
1081 /* Ensure the empty pgd is visible before TRANSTAB can be written */
1084 cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) |
1085 ARM_MALI_LPAE_TTBR_READ_INNER |
1086 ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
1087 if (cfg->coherent_walk)
1088 cfg->arm_mali_lpae_cfg.transtab |= ARM_MALI_LPAE_TTBR_SHARE_OUTER;
1097 struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = {
1098 .alloc = arm_64_lpae_alloc_pgtable_s1,
1099 .free = arm_lpae_free_pgtable,
1102 struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns = {
1103 .alloc = arm_64_lpae_alloc_pgtable_s2,
1104 .free = arm_lpae_free_pgtable,
1107 struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns = {
1108 .alloc = arm_32_lpae_alloc_pgtable_s1,
1109 .free = arm_lpae_free_pgtable,
1112 struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns = {
1113 .alloc = arm_32_lpae_alloc_pgtable_s2,
1114 .free = arm_lpae_free_pgtable,
1117 struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns = {
1118 .alloc = arm_mali_lpae_alloc_pgtable,
1119 .free = arm_lpae_free_pgtable,
1122 #ifdef CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST
1124 static struct io_pgtable_cfg *cfg_cookie __initdata;
1126 static void __init dummy_tlb_flush_all(void *cookie)
1128 WARN_ON(cookie != cfg_cookie);
1131 static void __init dummy_tlb_flush(unsigned long iova, size_t size,
1132 size_t granule, void *cookie)
1134 WARN_ON(cookie != cfg_cookie);
1135 WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
1138 static void __init dummy_tlb_add_page(struct iommu_iotlb_gather *gather,
1139 unsigned long iova, size_t granule,
1142 dummy_tlb_flush(iova, granule, granule, cookie);
1145 static const struct iommu_flush_ops dummy_tlb_ops __initconst = {
1146 .tlb_flush_all = dummy_tlb_flush_all,
1147 .tlb_flush_walk = dummy_tlb_flush,
1148 .tlb_add_page = dummy_tlb_add_page,
1151 static void __init arm_lpae_dump_ops(struct io_pgtable_ops *ops)
1153 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
1154 struct io_pgtable_cfg *cfg = &data->iop.cfg;
1156 pr_err("cfg: pgsize_bitmap 0x%lx, ias %u-bit\n",
1157 cfg->pgsize_bitmap, cfg->ias);
1158 pr_err("data: %d levels, 0x%zx pgd_size, %u pg_shift, %u bits_per_level, pgd @ %p\n",
1159 ARM_LPAE_MAX_LEVELS - data->start_level, ARM_LPAE_PGD_SIZE(data),
1160 ilog2(ARM_LPAE_GRANULE(data)), data->bits_per_level, data->pgd);
1163 #define __FAIL(ops, i) ({ \
1164 WARN(1, "selftest: test failed for fmt idx %d\n", (i)); \
1165 arm_lpae_dump_ops(ops); \
1166 selftest_running = false; \
1170 static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg)
1172 static const enum io_pgtable_fmt fmts[] __initconst = {
1180 struct io_pgtable_ops *ops;
1182 selftest_running = true;
1184 for (i = 0; i < ARRAY_SIZE(fmts); ++i) {
1186 ops = alloc_io_pgtable_ops(fmts[i], cfg, cfg);
1188 pr_err("selftest: failed to allocate io pgtable ops\n");
1193 * Initial sanity checks.
1194 * Empty page tables shouldn't provide any translations.
1196 if (ops->iova_to_phys(ops, 42))
1197 return __FAIL(ops, i);
1199 if (ops->iova_to_phys(ops, SZ_1G + 42))
1200 return __FAIL(ops, i);
1202 if (ops->iova_to_phys(ops, SZ_2G + 42))
1203 return __FAIL(ops, i);
1206 * Distinct mappings of different granule sizes.
1209 for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) {
1212 if (ops->map(ops, iova, iova, size, IOMMU_READ |
1215 IOMMU_CACHE, GFP_KERNEL))
1216 return __FAIL(ops, i);
1218 /* Overlapping mappings */
1219 if (!ops->map(ops, iova, iova + size, size,
1220 IOMMU_READ | IOMMU_NOEXEC, GFP_KERNEL))
1221 return __FAIL(ops, i);
1223 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
1224 return __FAIL(ops, i);
1230 size = 1UL << __ffs(cfg->pgsize_bitmap);
1231 if (ops->unmap(ops, SZ_1G + size, size, NULL) != size)
1232 return __FAIL(ops, i);
1234 /* Remap of partial unmap */
1235 if (ops->map(ops, SZ_1G + size, size, size, IOMMU_READ, GFP_KERNEL))
1236 return __FAIL(ops, i);
1238 if (ops->iova_to_phys(ops, SZ_1G + size + 42) != (size + 42))
1239 return __FAIL(ops, i);
1243 for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) {
1246 if (ops->unmap(ops, iova, size, NULL) != size)
1247 return __FAIL(ops, i);
1249 if (ops->iova_to_phys(ops, iova + 42))
1250 return __FAIL(ops, i);
1252 /* Remap full block */
1253 if (ops->map(ops, iova, iova, size, IOMMU_WRITE, GFP_KERNEL))
1254 return __FAIL(ops, i);
1256 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
1257 return __FAIL(ops, i);
1262 free_io_pgtable_ops(ops);
1265 selftest_running = false;
1269 static int __init arm_lpae_do_selftests(void)
1271 static const unsigned long pgsize[] __initconst = {
1272 SZ_4K | SZ_2M | SZ_1G,
1277 static const unsigned int ias[] __initconst = {
1278 32, 36, 40, 42, 44, 48,
1281 int i, j, pass = 0, fail = 0;
1283 struct io_pgtable_cfg cfg = {
1284 .tlb = &dummy_tlb_ops,
1286 .coherent_walk = true,
1290 /* __arm_lpae_alloc_pages() merely needs dev_to_node() to work */
1291 set_dev_node(&dev, NUMA_NO_NODE);
1293 for (i = 0; i < ARRAY_SIZE(pgsize); ++i) {
1294 for (j = 0; j < ARRAY_SIZE(ias); ++j) {
1295 cfg.pgsize_bitmap = pgsize[i];
1297 pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u\n",
1299 if (arm_lpae_run_tests(&cfg))
1306 pr_info("selftest: completed with %d PASS %d FAIL\n", pass, fail);
1307 return fail ? -EFAULT : 0;
1309 subsys_initcall(arm_lpae_do_selftests);