2 * CPU-agnostic ARM page table allocator.
4 * ARMv7 Short-descriptor format, supporting
5 * - Basic memory attributes
6 * - Simplified access permissions (AP[2:1] model)
7 * - Backwards-compatible TEX remap
8 * - Large pages/supersections (if indicated by the caller)
11 * - Legacy access permissions (AP[2:0] model)
13 * Almost certainly never supporting:
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program. If not, see <http://www.gnu.org/licenses/>.
29 * Copyright (C) 2014-2015 ARM Limited
30 * Copyright (c) 2014-2015 MediaTek Inc.
33 #define pr_fmt(fmt) "arm-v7s io-pgtable: " fmt
35 #include <linux/atomic.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/gfp.h>
38 #include <linux/iommu.h>
39 #include <linux/kernel.h>
40 #include <linux/kmemleak.h>
41 #include <linux/sizes.h>
42 #include <linux/slab.h>
43 #include <linux/spinlock.h>
44 #include <linux/types.h>
46 #include <asm/barrier.h>
48 #include "io-pgtable.h"
50 /* Struct accessors */
51 #define io_pgtable_to_data(x) \
52 container_of((x), struct arm_v7s_io_pgtable, iop)
54 #define io_pgtable_ops_to_data(x) \
55 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
58 * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2,
59 * and 12 bits in a page. With some carefully-chosen coefficients we can
60 * hide the ugly inconsistencies behind these macros and at least let the
61 * rest of the code pretend to be somewhat sane.
63 #define ARM_V7S_ADDR_BITS 32
64 #define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
65 #define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
66 #define ARM_V7S_TABLE_SHIFT 10
68 #define ARM_V7S_PTES_PER_LVL(lvl) (1 << _ARM_V7S_LVL_BITS(lvl))
69 #define ARM_V7S_TABLE_SIZE(lvl) \
70 (ARM_V7S_PTES_PER_LVL(lvl) * sizeof(arm_v7s_iopte))
72 #define ARM_V7S_BLOCK_SIZE(lvl) (1UL << ARM_V7S_LVL_SHIFT(lvl))
73 #define ARM_V7S_LVL_MASK(lvl) ((u32)(~0U << ARM_V7S_LVL_SHIFT(lvl)))
74 #define ARM_V7S_TABLE_MASK ((u32)(~0U << ARM_V7S_TABLE_SHIFT))
75 #define _ARM_V7S_IDX_MASK(lvl) (ARM_V7S_PTES_PER_LVL(lvl) - 1)
76 #define ARM_V7S_LVL_IDX(addr, lvl) ({ \
78 ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l); \
82 * Large page/supersection entries are effectively a block of 16 page/section
83 * entries, along the lines of the LPAE contiguous hint, but all with the
84 * same output address. For want of a better common name we'll call them
85 * "contiguous" versions of their respective page/section entries here, but
86 * noting the distinction (WRT to TLB maintenance) that they represent *one*
87 * entry repeated 16 times, not 16 separate entries (as in the LPAE case).
89 #define ARM_V7S_CONT_PAGES 16
91 /* PTE type bits: these are all mixed up with XN/PXN bits in most cases */
92 #define ARM_V7S_PTE_TYPE_TABLE 0x1
93 #define ARM_V7S_PTE_TYPE_PAGE 0x2
94 #define ARM_V7S_PTE_TYPE_CONT_PAGE 0x1
96 #define ARM_V7S_PTE_IS_VALID(pte) (((pte) & 0x3) != 0)
97 #define ARM_V7S_PTE_IS_TABLE(pte, lvl) \
98 ((lvl) == 1 && (((pte) & 0x3) == ARM_V7S_PTE_TYPE_TABLE))
100 /* Page table bits */
101 #define ARM_V7S_ATTR_XN(lvl) BIT(4 * (2 - (lvl)))
102 #define ARM_V7S_ATTR_B BIT(2)
103 #define ARM_V7S_ATTR_C BIT(3)
104 #define ARM_V7S_ATTR_NS_TABLE BIT(3)
105 #define ARM_V7S_ATTR_NS_SECTION BIT(19)
107 #define ARM_V7S_CONT_SECTION BIT(18)
108 #define ARM_V7S_CONT_PAGE_XN_SHIFT 15
111 * The attribute bits are consistently ordered*, but occupy bits [17:10] of
112 * a level 1 PTE vs. bits [11:4] at level 2. Thus we define the individual
113 * fields relative to that 8-bit block, plus a total shift relative to the PTE.
115 #define ARM_V7S_ATTR_SHIFT(lvl) (16 - (lvl) * 6)
117 #define ARM_V7S_ATTR_MASK 0xff
118 #define ARM_V7S_ATTR_AP0 BIT(0)
119 #define ARM_V7S_ATTR_AP1 BIT(1)
120 #define ARM_V7S_ATTR_AP2 BIT(5)
121 #define ARM_V7S_ATTR_S BIT(6)
122 #define ARM_V7S_ATTR_NG BIT(7)
123 #define ARM_V7S_TEX_SHIFT 2
124 #define ARM_V7S_TEX_MASK 0x7
125 #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
127 #define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
129 /* *well, except for TEX on level 2 large pages, of course :( */
130 #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
131 #define ARM_V7S_CONT_PAGE_TEX_MASK (ARM_V7S_TEX_MASK << ARM_V7S_CONT_PAGE_TEX_SHIFT)
133 /* Simplified access permissions */
134 #define ARM_V7S_PTE_AF ARM_V7S_ATTR_AP0
135 #define ARM_V7S_PTE_AP_UNPRIV ARM_V7S_ATTR_AP1
136 #define ARM_V7S_PTE_AP_RDONLY ARM_V7S_ATTR_AP2
139 #define ARM_V7S_RGN_NC 0
140 #define ARM_V7S_RGN_WBWA 1
141 #define ARM_V7S_RGN_WT 2
142 #define ARM_V7S_RGN_WB 3
144 #define ARM_V7S_PRRR_TYPE_DEVICE 1
145 #define ARM_V7S_PRRR_TYPE_NORMAL 2
146 #define ARM_V7S_PRRR_TR(n, type) (((type) & 0x3) << ((n) * 2))
147 #define ARM_V7S_PRRR_DS0 BIT(16)
148 #define ARM_V7S_PRRR_DS1 BIT(17)
149 #define ARM_V7S_PRRR_NS0 BIT(18)
150 #define ARM_V7S_PRRR_NS1 BIT(19)
151 #define ARM_V7S_PRRR_NOS(n) BIT((n) + 24)
153 #define ARM_V7S_NMRR_IR(n, attr) (((attr) & 0x3) << ((n) * 2))
154 #define ARM_V7S_NMRR_OR(n, attr) (((attr) & 0x3) << ((n) * 2 + 16))
156 #define ARM_V7S_TTBR_S BIT(1)
157 #define ARM_V7S_TTBR_NOS BIT(5)
158 #define ARM_V7S_TTBR_ORGN_ATTR(attr) (((attr) & 0x3) << 3)
159 #define ARM_V7S_TTBR_IRGN_ATTR(attr) \
160 ((((attr) & 0x1) << 6) | (((attr) & 0x2) >> 1))
162 #define ARM_V7S_TCR_PD1 BIT(5)
164 typedef u32 arm_v7s_iopte;
166 static bool selftest_running;
168 struct arm_v7s_io_pgtable {
169 struct io_pgtable iop;
172 struct kmem_cache *l2_tables;
173 spinlock_t split_lock;
176 static dma_addr_t __arm_v7s_dma_addr(void *pages)
178 return (dma_addr_t)virt_to_phys(pages);
181 static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl)
183 if (ARM_V7S_PTE_IS_TABLE(pte, lvl))
184 pte &= ARM_V7S_TABLE_MASK;
186 pte &= ARM_V7S_LVL_MASK(lvl);
187 return phys_to_virt(pte);
190 static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
191 struct arm_v7s_io_pgtable *data)
193 struct io_pgtable_cfg *cfg = &data->iop.cfg;
194 struct device *dev = cfg->iommu_dev;
196 size_t size = ARM_V7S_TABLE_SIZE(lvl);
200 table = (void *)__get_dma_pages(__GFP_ZERO, get_order(size));
202 table = kmem_cache_zalloc(data->l2_tables, gfp | GFP_DMA);
203 if (table && !(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA)) {
204 dma = dma_map_single(dev, table, size, DMA_TO_DEVICE);
205 if (dma_mapping_error(dev, dma))
208 * We depend on the IOMMU being able to work with any physical
209 * address directly, so if the DMA layer suggests otherwise by
210 * translating or truncating them, that bodes very badly...
212 if (dma != virt_to_phys(table))
215 kmemleak_ignore(table);
219 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
220 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
223 free_pages((unsigned long)table, get_order(size));
225 kmem_cache_free(data->l2_tables, table);
229 static void __arm_v7s_free_table(void *table, int lvl,
230 struct arm_v7s_io_pgtable *data)
232 struct io_pgtable_cfg *cfg = &data->iop.cfg;
233 struct device *dev = cfg->iommu_dev;
234 size_t size = ARM_V7S_TABLE_SIZE(lvl);
236 if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA))
237 dma_unmap_single(dev, __arm_v7s_dma_addr(table), size,
240 free_pages((unsigned long)table, get_order(size));
242 kmem_cache_free(data->l2_tables, table);
245 static void __arm_v7s_pte_sync(arm_v7s_iopte *ptep, int num_entries,
246 struct io_pgtable_cfg *cfg)
248 if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA))
251 dma_sync_single_for_device(cfg->iommu_dev, __arm_v7s_dma_addr(ptep),
252 num_entries * sizeof(*ptep), DMA_TO_DEVICE);
254 static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
255 int num_entries, struct io_pgtable_cfg *cfg)
259 for (i = 0; i < num_entries; i++)
262 __arm_v7s_pte_sync(ptep, num_entries, cfg);
265 static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
266 struct io_pgtable_cfg *cfg)
268 bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
269 arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
271 if (!(prot & IOMMU_MMIO))
272 pte |= ARM_V7S_ATTR_TEX(1);
274 pte |= ARM_V7S_PTE_AF;
275 if (!(prot & IOMMU_PRIV))
276 pte |= ARM_V7S_PTE_AP_UNPRIV;
277 if (!(prot & IOMMU_WRITE))
278 pte |= ARM_V7S_PTE_AP_RDONLY;
280 pte <<= ARM_V7S_ATTR_SHIFT(lvl);
282 if ((prot & IOMMU_NOEXEC) && ap)
283 pte |= ARM_V7S_ATTR_XN(lvl);
284 if (prot & IOMMU_MMIO)
285 pte |= ARM_V7S_ATTR_B;
286 else if (prot & IOMMU_CACHE)
287 pte |= ARM_V7S_ATTR_B | ARM_V7S_ATTR_C;
289 pte |= ARM_V7S_PTE_TYPE_PAGE;
290 if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
291 pte |= ARM_V7S_ATTR_NS_SECTION;
293 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
294 pte |= ARM_V7S_ATTR_MTK_4GB;
299 static int arm_v7s_pte_to_prot(arm_v7s_iopte pte, int lvl)
301 int prot = IOMMU_READ;
302 arm_v7s_iopte attr = pte >> ARM_V7S_ATTR_SHIFT(lvl);
304 if (!(attr & ARM_V7S_PTE_AP_RDONLY))
306 if (!(attr & ARM_V7S_PTE_AP_UNPRIV))
308 if ((attr & (ARM_V7S_TEX_MASK << ARM_V7S_TEX_SHIFT)) == 0)
310 else if (pte & ARM_V7S_ATTR_C)
312 if (pte & ARM_V7S_ATTR_XN(lvl))
313 prot |= IOMMU_NOEXEC;
318 static arm_v7s_iopte arm_v7s_pte_to_cont(arm_v7s_iopte pte, int lvl)
321 pte |= ARM_V7S_CONT_SECTION;
322 } else if (lvl == 2) {
323 arm_v7s_iopte xn = pte & ARM_V7S_ATTR_XN(lvl);
324 arm_v7s_iopte tex = pte & ARM_V7S_CONT_PAGE_TEX_MASK;
326 pte ^= xn | tex | ARM_V7S_PTE_TYPE_PAGE;
327 pte |= (xn << ARM_V7S_CONT_PAGE_XN_SHIFT) |
328 (tex << ARM_V7S_CONT_PAGE_TEX_SHIFT) |
329 ARM_V7S_PTE_TYPE_CONT_PAGE;
334 static arm_v7s_iopte arm_v7s_cont_to_pte(arm_v7s_iopte pte, int lvl)
337 pte &= ~ARM_V7S_CONT_SECTION;
338 } else if (lvl == 2) {
339 arm_v7s_iopte xn = pte & BIT(ARM_V7S_CONT_PAGE_XN_SHIFT);
340 arm_v7s_iopte tex = pte & (ARM_V7S_CONT_PAGE_TEX_MASK <<
341 ARM_V7S_CONT_PAGE_TEX_SHIFT);
343 pte ^= xn | tex | ARM_V7S_PTE_TYPE_CONT_PAGE;
344 pte |= (xn >> ARM_V7S_CONT_PAGE_XN_SHIFT) |
345 (tex >> ARM_V7S_CONT_PAGE_TEX_SHIFT) |
346 ARM_V7S_PTE_TYPE_PAGE;
351 static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl)
353 if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte, lvl))
354 return pte & ARM_V7S_CONT_SECTION;
356 return !(pte & ARM_V7S_PTE_TYPE_PAGE);
360 static int __arm_v7s_unmap(struct arm_v7s_io_pgtable *, unsigned long,
361 size_t, int, arm_v7s_iopte *);
363 static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
364 unsigned long iova, phys_addr_t paddr, int prot,
365 int lvl, int num_entries, arm_v7s_iopte *ptep)
367 struct io_pgtable_cfg *cfg = &data->iop.cfg;
371 for (i = 0; i < num_entries; i++)
372 if (ARM_V7S_PTE_IS_TABLE(ptep[i], lvl)) {
374 * We need to unmap and free the old table before
375 * overwriting it with a block entry.
378 size_t sz = ARM_V7S_BLOCK_SIZE(lvl);
380 tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl);
381 if (WARN_ON(__arm_v7s_unmap(data, iova + i * sz,
382 sz, lvl, tblp) != sz))
384 } else if (ptep[i]) {
385 /* We require an unmap first */
386 WARN_ON(!selftest_running);
390 pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
392 pte = arm_v7s_pte_to_cont(pte, lvl);
394 pte |= paddr & ARM_V7S_LVL_MASK(lvl);
396 __arm_v7s_set_pte(ptep, pte, num_entries, cfg);
400 static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table,
403 struct io_pgtable_cfg *cfg)
405 arm_v7s_iopte old, new;
407 new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE;
408 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
409 new |= ARM_V7S_ATTR_NS_TABLE;
412 * Ensure the table itself is visible before its PTE can be.
413 * Whilst we could get away with cmpxchg64_release below, this
414 * doesn't have any ordering semantics when !CONFIG_SMP.
418 old = cmpxchg_relaxed(ptep, curr, new);
419 __arm_v7s_pte_sync(ptep, 1, cfg);
424 static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova,
425 phys_addr_t paddr, size_t size, int prot,
426 int lvl, arm_v7s_iopte *ptep)
428 struct io_pgtable_cfg *cfg = &data->iop.cfg;
429 arm_v7s_iopte pte, *cptep;
430 int num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
432 /* Find our entry at the current level */
433 ptep += ARM_V7S_LVL_IDX(iova, lvl);
435 /* If we can install a leaf entry at this level, then do so */
437 return arm_v7s_init_pte(data, iova, paddr, prot,
438 lvl, num_entries, ptep);
440 /* We can't allocate tables at the final level */
441 if (WARN_ON(lvl == 2))
444 /* Grab a pointer to the next level */
445 pte = READ_ONCE(*ptep);
447 cptep = __arm_v7s_alloc_table(lvl + 1, GFP_ATOMIC, data);
451 pte = arm_v7s_install_table(cptep, ptep, 0, cfg);
453 __arm_v7s_free_table(cptep, lvl + 1, data);
455 /* We've no easy way of knowing if it's synced yet, so... */
456 __arm_v7s_pte_sync(ptep, 1, cfg);
459 if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) {
460 cptep = iopte_deref(pte, lvl);
462 /* We require an unmap first */
463 WARN_ON(!selftest_running);
468 return __arm_v7s_map(data, iova, paddr, size, prot, lvl + 1, cptep);
471 static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
472 phys_addr_t paddr, size_t size, int prot)
474 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
475 struct io_pgtable *iop = &data->iop;
478 /* If no access, then nothing to do */
479 if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
482 if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
485 ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
487 * Synchronise all PTE updates for the new mapping before there's
488 * a chance for anything to kick off a table walk for the new iova.
490 if (iop->cfg.quirks & IO_PGTABLE_QUIRK_TLBI_ON_MAP) {
491 io_pgtable_tlb_add_flush(iop, iova, size,
492 ARM_V7S_BLOCK_SIZE(2), false);
493 io_pgtable_tlb_sync(iop);
501 static void arm_v7s_free_pgtable(struct io_pgtable *iop)
503 struct arm_v7s_io_pgtable *data = io_pgtable_to_data(iop);
506 for (i = 0; i < ARM_V7S_PTES_PER_LVL(1); i++) {
507 arm_v7s_iopte pte = data->pgd[i];
509 if (ARM_V7S_PTE_IS_TABLE(pte, 1))
510 __arm_v7s_free_table(iopte_deref(pte, 1), 2, data);
512 __arm_v7s_free_table(data->pgd, 1, data);
513 kmem_cache_destroy(data->l2_tables);
517 static arm_v7s_iopte arm_v7s_split_cont(struct arm_v7s_io_pgtable *data,
518 unsigned long iova, int idx, int lvl,
521 struct io_pgtable *iop = &data->iop;
523 size_t size = ARM_V7S_BLOCK_SIZE(lvl);
526 /* Check that we didn't lose a race to get the lock */
528 if (!arm_v7s_pte_is_cont(pte, lvl))
531 ptep -= idx & (ARM_V7S_CONT_PAGES - 1);
532 pte = arm_v7s_cont_to_pte(pte, lvl);
533 for (i = 0; i < ARM_V7S_CONT_PAGES; i++)
534 ptep[i] = pte + i * size;
536 __arm_v7s_pte_sync(ptep, ARM_V7S_CONT_PAGES, &iop->cfg);
538 size *= ARM_V7S_CONT_PAGES;
539 io_pgtable_tlb_add_flush(iop, iova, size, size, true);
540 io_pgtable_tlb_sync(iop);
544 static int arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
545 unsigned long iova, size_t size,
546 arm_v7s_iopte blk_pte, arm_v7s_iopte *ptep)
548 struct io_pgtable_cfg *cfg = &data->iop.cfg;
549 arm_v7s_iopte pte, *tablep;
550 int i, unmap_idx, num_entries, num_ptes;
552 tablep = __arm_v7s_alloc_table(2, GFP_ATOMIC, data);
554 return 0; /* Bytes unmapped */
556 num_ptes = ARM_V7S_PTES_PER_LVL(2);
557 num_entries = size >> ARM_V7S_LVL_SHIFT(2);
558 unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
560 pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
562 pte = arm_v7s_pte_to_cont(pte, 2);
564 for (i = 0; i < num_ptes; i += num_entries, pte += size) {
569 __arm_v7s_set_pte(&tablep[i], pte, num_entries, cfg);
572 pte = arm_v7s_install_table(tablep, ptep, blk_pte, cfg);
573 if (pte != blk_pte) {
574 __arm_v7s_free_table(tablep, 2, data);
576 if (!ARM_V7S_PTE_IS_TABLE(pte, 1))
579 tablep = iopte_deref(pte, 1);
580 return __arm_v7s_unmap(data, iova, size, 2, tablep);
583 io_pgtable_tlb_add_flush(&data->iop, iova, size, size, true);
587 static int __arm_v7s_unmap(struct arm_v7s_io_pgtable *data,
588 unsigned long iova, size_t size, int lvl,
591 arm_v7s_iopte pte[ARM_V7S_CONT_PAGES];
592 struct io_pgtable *iop = &data->iop;
593 int idx, i = 0, num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
595 /* Something went horribly wrong and we ran out of page table */
596 if (WARN_ON(lvl > 2))
599 idx = ARM_V7S_LVL_IDX(iova, lvl);
602 pte[i] = READ_ONCE(ptep[i]);
603 if (WARN_ON(!ARM_V7S_PTE_IS_VALID(pte[i])))
605 } while (++i < num_entries);
608 * If we've hit a contiguous 'large page' entry at this level, it
609 * needs splitting first, unless we're unmapping the whole lot.
611 * For splitting, we can't rewrite 16 PTEs atomically, and since we
612 * can't necessarily assume TEX remap we don't have a software bit to
613 * mark live entries being split. In practice (i.e. DMA API code), we
614 * will never be splitting large pages anyway, so just wrap this edge
615 * case in a lock for the sake of correctness and be done with it.
617 if (num_entries <= 1 && arm_v7s_pte_is_cont(pte[0], lvl)) {
620 spin_lock_irqsave(&data->split_lock, flags);
621 pte[0] = arm_v7s_split_cont(data, iova, idx, lvl, ptep);
622 spin_unlock_irqrestore(&data->split_lock, flags);
625 /* If the size matches this level, we're in the right place */
627 size_t blk_size = ARM_V7S_BLOCK_SIZE(lvl);
629 __arm_v7s_set_pte(ptep, 0, num_entries, &iop->cfg);
631 for (i = 0; i < num_entries; i++) {
632 if (ARM_V7S_PTE_IS_TABLE(pte[i], lvl)) {
633 /* Also flush any partial walks */
634 io_pgtable_tlb_add_flush(iop, iova, blk_size,
635 ARM_V7S_BLOCK_SIZE(lvl + 1), false);
636 io_pgtable_tlb_sync(iop);
637 ptep = iopte_deref(pte[i], lvl);
638 __arm_v7s_free_table(ptep, lvl + 1, data);
640 io_pgtable_tlb_add_flush(iop, iova, blk_size,
646 } else if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte[0], lvl)) {
648 * Insert a table at the next level to map the old region,
649 * minus the part we want to unmap
651 return arm_v7s_split_blk_unmap(data, iova, size, pte[0], ptep);
654 /* Keep on walkin' */
655 ptep = iopte_deref(pte[0], lvl);
656 return __arm_v7s_unmap(data, iova, size, lvl + 1, ptep);
659 static int arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova,
662 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
664 if (WARN_ON(upper_32_bits(iova)))
667 return __arm_v7s_unmap(data, iova, size, 1, data->pgd);
670 static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
673 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
674 arm_v7s_iopte *ptep = data->pgd, pte;
679 ptep += ARM_V7S_LVL_IDX(iova, ++lvl);
680 pte = READ_ONCE(*ptep);
681 ptep = iopte_deref(pte, lvl);
682 } while (ARM_V7S_PTE_IS_TABLE(pte, lvl));
684 if (!ARM_V7S_PTE_IS_VALID(pte))
687 mask = ARM_V7S_LVL_MASK(lvl);
688 if (arm_v7s_pte_is_cont(pte, lvl))
689 mask *= ARM_V7S_CONT_PAGES;
690 return (pte & mask) | (iova & ~mask);
693 static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
696 struct arm_v7s_io_pgtable *data;
699 if (upper_32_bits(PHYS_OFFSET))
702 if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS)
705 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
706 IO_PGTABLE_QUIRK_NO_PERMS |
707 IO_PGTABLE_QUIRK_TLBI_ON_MAP |
708 IO_PGTABLE_QUIRK_ARM_MTK_4GB |
709 IO_PGTABLE_QUIRK_NO_DMA))
712 /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
713 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB &&
714 !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS))
717 data = kmalloc(sizeof(*data), GFP_KERNEL);
721 spin_lock_init(&data->split_lock);
722 data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
723 ARM_V7S_TABLE_SIZE(2),
724 ARM_V7S_TABLE_SIZE(2),
725 SLAB_CACHE_DMA, NULL);
726 if (!data->l2_tables)
729 data->iop.ops = (struct io_pgtable_ops) {
731 .unmap = arm_v7s_unmap,
732 .iova_to_phys = arm_v7s_iova_to_phys,
735 /* We have to do this early for __arm_v7s_alloc_table to work... */
736 data->iop.cfg = *cfg;
739 * Unless the IOMMU driver indicates supersection support by
740 * having SZ_16M set in the initial bitmap, they won't be used.
742 cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M;
744 /* TCR: T0SZ=0, disable TTBR1 */
745 cfg->arm_v7s_cfg.tcr = ARM_V7S_TCR_PD1;
748 * TEX remap: the indices used map to the closest equivalent types
749 * under the non-TEX-remap interpretation of those attribute bits,
750 * excepting various implementation-defined aspects of shareability.
752 cfg->arm_v7s_cfg.prrr = ARM_V7S_PRRR_TR(1, ARM_V7S_PRRR_TYPE_DEVICE) |
753 ARM_V7S_PRRR_TR(4, ARM_V7S_PRRR_TYPE_NORMAL) |
754 ARM_V7S_PRRR_TR(7, ARM_V7S_PRRR_TYPE_NORMAL) |
755 ARM_V7S_PRRR_DS0 | ARM_V7S_PRRR_DS1 |
756 ARM_V7S_PRRR_NS1 | ARM_V7S_PRRR_NOS(7);
757 cfg->arm_v7s_cfg.nmrr = ARM_V7S_NMRR_IR(7, ARM_V7S_RGN_WBWA) |
758 ARM_V7S_NMRR_OR(7, ARM_V7S_RGN_WBWA);
760 /* Looking good; allocate a pgd */
761 data->pgd = __arm_v7s_alloc_table(1, GFP_KERNEL, data);
765 /* Ensure the empty pgd is visible before any actual TTBR write */
769 cfg->arm_v7s_cfg.ttbr[0] = virt_to_phys(data->pgd) |
770 ARM_V7S_TTBR_S | ARM_V7S_TTBR_NOS |
771 ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
772 ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA);
773 cfg->arm_v7s_cfg.ttbr[1] = 0;
777 kmem_cache_destroy(data->l2_tables);
782 struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns = {
783 .alloc = arm_v7s_alloc_pgtable,
784 .free = arm_v7s_free_pgtable,
787 #ifdef CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST
789 static struct io_pgtable_cfg *cfg_cookie;
791 static void dummy_tlb_flush_all(void *cookie)
793 WARN_ON(cookie != cfg_cookie);
796 static void dummy_tlb_add_flush(unsigned long iova, size_t size,
797 size_t granule, bool leaf, void *cookie)
799 WARN_ON(cookie != cfg_cookie);
800 WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
803 static void dummy_tlb_sync(void *cookie)
805 WARN_ON(cookie != cfg_cookie);
808 static const struct iommu_gather_ops dummy_tlb_ops = {
809 .tlb_flush_all = dummy_tlb_flush_all,
810 .tlb_add_flush = dummy_tlb_add_flush,
811 .tlb_sync = dummy_tlb_sync,
814 #define __FAIL(ops) ({ \
815 WARN(1, "selftest: test failed\n"); \
816 selftest_running = false; \
820 static int __init arm_v7s_do_selftests(void)
822 struct io_pgtable_ops *ops;
823 struct io_pgtable_cfg cfg = {
824 .tlb = &dummy_tlb_ops,
827 .quirks = IO_PGTABLE_QUIRK_ARM_NS | IO_PGTABLE_QUIRK_NO_DMA,
828 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
830 unsigned int iova, size, iova_start;
831 unsigned int i, loopnr = 0;
833 selftest_running = true;
837 ops = alloc_io_pgtable_ops(ARM_V7S, &cfg, &cfg);
839 pr_err("selftest: failed to allocate io pgtable ops\n");
844 * Initial sanity checks.
845 * Empty page tables shouldn't provide any translations.
847 if (ops->iova_to_phys(ops, 42))
850 if (ops->iova_to_phys(ops, SZ_1G + 42))
853 if (ops->iova_to_phys(ops, SZ_2G + 42))
857 * Distinct mappings of different granule sizes.
860 for_each_set_bit(i, &cfg.pgsize_bitmap, BITS_PER_LONG) {
862 if (ops->map(ops, iova, iova, size, IOMMU_READ |
868 /* Overlapping mappings */
869 if (!ops->map(ops, iova, iova + size, size,
870 IOMMU_READ | IOMMU_NOEXEC))
873 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
882 size = 1UL << __ffs(cfg.pgsize_bitmap);
884 iova_start = i * SZ_16M;
885 if (ops->unmap(ops, iova_start + size, size) != size)
888 /* Remap of partial unmap */
889 if (ops->map(ops, iova_start + size, size, size, IOMMU_READ))
892 if (ops->iova_to_phys(ops, iova_start + size + 42)
900 i = find_first_bit(&cfg.pgsize_bitmap, BITS_PER_LONG);
901 while (i != BITS_PER_LONG) {
904 if (ops->unmap(ops, iova, size) != size)
907 if (ops->iova_to_phys(ops, iova + 42))
910 /* Remap full block */
911 if (ops->map(ops, iova, iova, size, IOMMU_WRITE))
914 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
919 i = find_next_bit(&cfg.pgsize_bitmap, BITS_PER_LONG, i);
922 free_io_pgtable_ops(ops);
924 selftest_running = false;
926 pr_info("self test ok\n");
929 subsys_initcall(arm_v7s_do_selftests);