1 #include <linux/interrupt.h>
2 #include <linux/dmar.h>
3 #include <linux/spinlock.h>
4 #include <linux/slab.h>
5 #include <linux/jiffies.h>
6 #include <linux/hpet.h>
9 #include <linux/intel-iommu.h>
10 #include <linux/acpi.h>
11 #include <asm/io_apic.h>
14 #include <asm/irq_remapping.h>
15 #include <asm/pci-direct.h>
16 #include <asm/msidef.h>
18 #include "irq_remapping.h"
21 struct intel_iommu *iommu;
23 unsigned int bus; /* PCI bus number */
24 unsigned int devfn; /* PCI devfn number */
28 struct intel_iommu *iommu;
34 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
35 #define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8)
37 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
38 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
39 static int ir_ioapic_num, ir_hpet_num;
41 static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
43 static int __init parse_ioapics_under_ir(void);
45 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
47 struct irq_cfg *cfg = irq_get_chip_data(irq);
48 return cfg ? &cfg->irq_2_iommu : NULL;
51 static int get_irte(int irq, struct irte *entry)
53 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
57 if (!entry || !irq_iommu)
60 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
62 index = irq_iommu->irte_index + irq_iommu->sub_handle;
63 *entry = *(irq_iommu->iommu->ir_table->base + index);
65 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
69 static int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
71 struct ir_table *table = iommu->ir_table;
72 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
73 struct irq_cfg *cfg = irq_get_chip_data(irq);
74 unsigned int mask = 0;
78 if (!count || !irq_iommu)
82 count = __roundup_pow_of_two(count);
86 if (mask > ecap_max_handle_mask(iommu->ecap)) {
88 "Requested mask %x exceeds the max invalidation handle"
89 " mask value %Lx\n", mask,
90 ecap_max_handle_mask(iommu->ecap));
94 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
95 index = bitmap_find_free_region(table->bitmap,
96 INTR_REMAP_TABLE_ENTRIES, mask);
98 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
101 irq_iommu->iommu = iommu;
102 irq_iommu->irte_index = index;
103 irq_iommu->sub_handle = 0;
104 irq_iommu->irte_mask = mask;
106 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
111 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
115 desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
119 return qi_submit_sync(&desc, iommu);
122 static int map_irq_to_irte_handle(int irq, u16 *sub_handle)
124 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
131 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
132 *sub_handle = irq_iommu->sub_handle;
133 index = irq_iommu->irte_index;
134 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
138 static int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
140 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
141 struct irq_cfg *cfg = irq_get_chip_data(irq);
147 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
150 irq_iommu->iommu = iommu;
151 irq_iommu->irte_index = index;
152 irq_iommu->sub_handle = subhandle;
153 irq_iommu->irte_mask = 0;
155 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
160 static int modify_irte(int irq, struct irte *irte_modified)
162 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
163 struct intel_iommu *iommu;
171 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
173 iommu = irq_iommu->iommu;
175 index = irq_iommu->irte_index + irq_iommu->sub_handle;
176 irte = &iommu->ir_table->base[index];
178 set_64bit(&irte->low, irte_modified->low);
179 set_64bit(&irte->high, irte_modified->high);
180 __iommu_flush_cache(iommu, irte, sizeof(*irte));
182 rc = qi_flush_iec(iommu, index, 0);
183 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
188 static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
192 for (i = 0; i < MAX_HPET_TBS; i++)
193 if (ir_hpet[i].id == hpet_id)
194 return ir_hpet[i].iommu;
198 static struct intel_iommu *map_ioapic_to_ir(int apic)
202 for (i = 0; i < MAX_IO_APICS; i++)
203 if (ir_ioapic[i].id == apic)
204 return ir_ioapic[i].iommu;
208 static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
210 struct dmar_drhd_unit *drhd;
212 drhd = dmar_find_matched_drhd_unit(dev);
219 static int clear_entries(struct irq_2_iommu *irq_iommu)
221 struct irte *start, *entry, *end;
222 struct intel_iommu *iommu;
225 if (irq_iommu->sub_handle)
228 iommu = irq_iommu->iommu;
229 index = irq_iommu->irte_index + irq_iommu->sub_handle;
231 start = iommu->ir_table->base + index;
232 end = start + (1 << irq_iommu->irte_mask);
234 for (entry = start; entry < end; entry++) {
235 set_64bit(&entry->low, 0);
236 set_64bit(&entry->high, 0);
238 bitmap_release_region(iommu->ir_table->bitmap, index,
239 irq_iommu->irte_mask);
241 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
244 static int free_irte(int irq)
246 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
253 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
255 rc = clear_entries(irq_iommu);
257 irq_iommu->iommu = NULL;
258 irq_iommu->irte_index = 0;
259 irq_iommu->sub_handle = 0;
260 irq_iommu->irte_mask = 0;
262 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
268 * source validation type
270 #define SVT_NO_VERIFY 0x0 /* no verification is required */
271 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
272 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
275 * source-id qualifier
277 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
278 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
279 * the third least significant bit
281 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
282 * the second and third least significant bits
284 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
285 * the least three significant bits
289 * set SVT, SQ and SID fields of irte to verify
290 * source ids of interrupt requests
292 static void set_irte_sid(struct irte *irte, unsigned int svt,
293 unsigned int sq, unsigned int sid)
295 if (disable_sourceid_checking)
302 static int set_ioapic_sid(struct irte *irte, int apic)
310 for (i = 0; i < MAX_IO_APICS; i++) {
311 if (ir_ioapic[i].id == apic) {
312 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
318 pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic);
322 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
327 static int set_hpet_sid(struct irte *irte, u8 id)
335 for (i = 0; i < MAX_HPET_TBS; i++) {
336 if (ir_hpet[i].id == id) {
337 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
343 pr_warning("Failed to set source-id of HPET block (%d)\n", id);
348 * Should really use SQ_ALL_16. Some platforms are broken.
349 * While we figure out the right quirks for these broken platforms, use
350 * SQ_13_IGNORE_3 for now.
352 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
357 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
359 struct pci_dev *bridge;
364 /* PCIe device or Root Complex integrated PCI device */
365 if (pci_is_pcie(dev) || !dev->bus->parent) {
366 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
367 (dev->bus->number << 8) | dev->devfn);
371 bridge = pci_find_upstream_pcie_bridge(dev);
373 if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */
374 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
375 (bridge->bus->number << 8) | dev->bus->number);
376 else /* this is a legacy PCI bridge */
377 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
378 (bridge->bus->number << 8) | bridge->devfn);
384 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
390 addr = virt_to_phys((void *)iommu->ir_table->base);
392 raw_spin_lock_irqsave(&iommu->register_lock, flags);
394 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
395 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
397 /* Set interrupt-remapping table pointer */
398 iommu->gcmd |= DMA_GCMD_SIRTP;
399 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
401 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
402 readl, (sts & DMA_GSTS_IRTPS), sts);
403 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
406 * global invalidation of interrupt entry cache before enabling
407 * interrupt-remapping.
409 qi_global_iec(iommu);
411 raw_spin_lock_irqsave(&iommu->register_lock, flags);
413 /* Enable interrupt-remapping */
414 iommu->gcmd |= DMA_GCMD_IRE;
415 iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */
416 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
418 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
419 readl, (sts & DMA_GSTS_IRES), sts);
422 * With CFI clear in the Global Command register, we should be
423 * protected from dangerous (i.e. compatibility) interrupts
424 * regardless of x2apic status. Check just to be sure.
426 if (sts & DMA_GSTS_CFIS)
428 "Compatibility-format IRQs enabled despite intr remapping;\n"
429 "you are vulnerable to IRQ injection.\n");
431 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
435 static int intel_setup_irq_remapping(struct intel_iommu *iommu, int mode)
437 struct ir_table *ir_table;
439 unsigned long *bitmap;
441 ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
444 if (!iommu->ir_table)
447 pages = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO,
448 INTR_REMAP_PAGE_ORDER);
451 pr_err("IR%d: failed to allocate pages of order %d\n",
452 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
453 kfree(iommu->ir_table);
457 bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
458 sizeof(long), GFP_ATOMIC);
459 if (bitmap == NULL) {
460 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
461 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
466 ir_table->base = page_address(pages);
467 ir_table->bitmap = bitmap;
469 iommu_set_irq_remapping(iommu, mode);
474 * Disable Interrupt Remapping.
476 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
481 if (!ecap_ir_support(iommu->ecap))
485 * global invalidation of interrupt entry cache before disabling
486 * interrupt-remapping.
488 qi_global_iec(iommu);
490 raw_spin_lock_irqsave(&iommu->register_lock, flags);
492 sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
493 if (!(sts & DMA_GSTS_IRES))
496 iommu->gcmd &= ~DMA_GCMD_IRE;
497 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
499 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
500 readl, !(sts & DMA_GSTS_IRES), sts);
503 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
506 static int __init dmar_x2apic_optout(void)
508 struct acpi_table_dmar *dmar;
509 dmar = (struct acpi_table_dmar *)dmar_tbl;
510 if (!dmar || no_x2apic_optout)
512 return dmar->flags & DMAR_X2APIC_OPT_OUT;
515 static int __init intel_irq_remapping_supported(void)
517 struct dmar_drhd_unit *drhd;
518 struct intel_iommu *iommu;
520 if (disable_irq_remap)
522 if (irq_remap_broken) {
524 "This system BIOS has enabled interrupt remapping\n"
525 "on a chipset that contains an erratum making that\n"
526 "feature unstable. To maintain system stability\n"
527 "interrupt remapping is being disabled. Please\n"
528 "contact your BIOS vendor for an update\n");
529 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
530 disable_irq_remap = 1;
534 if (!dmar_ir_support())
537 for_each_iommu(iommu, drhd)
538 if (!ecap_ir_support(iommu->ecap))
544 static int __init intel_enable_irq_remapping(void)
546 struct dmar_drhd_unit *drhd;
547 struct intel_iommu *iommu;
552 x2apic_present = x2apic_supported();
554 if (parse_ioapics_under_ir() != 1) {
555 printk(KERN_INFO "Not enable interrupt remapping\n");
559 if (x2apic_present) {
560 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
562 eim = !dmar_x2apic_optout();
565 "Your BIOS is broken and requested that x2apic be disabled.\n"
566 "This will slightly decrease performance.\n"
567 "Use 'intremap=no_x2apic_optout' to override BIOS request.\n");
570 for_each_iommu(iommu, drhd) {
572 * If the queued invalidation is already initialized,
573 * shouldn't disable it.
579 * Clear previous faults.
581 dmar_fault(-1, iommu);
584 * Disable intr remapping and queued invalidation, if already
585 * enabled prior to OS handover.
587 iommu_disable_irq_remapping(iommu);
589 dmar_disable_qi(iommu);
593 * check for the Interrupt-remapping support
595 for_each_iommu(iommu, drhd) {
596 if (!ecap_ir_support(iommu->ecap))
599 if (eim && !ecap_eim_support(iommu->ecap)) {
600 printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
601 " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
607 * Enable queued invalidation for all the DRHD's.
609 for_each_iommu(iommu, drhd) {
610 int ret = dmar_enable_qi(iommu);
613 printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
614 " invalidation, ecap %Lx, ret %d\n",
615 drhd->reg_base_addr, iommu->ecap, ret);
621 * Setup Interrupt-remapping for all the DRHD's now.
623 for_each_iommu(iommu, drhd) {
624 if (!ecap_ir_support(iommu->ecap))
627 if (intel_setup_irq_remapping(iommu, eim))
636 irq_remapping_enabled = 1;
639 * VT-d has a different layout for IO-APIC entries when
640 * interrupt remapping is enabled. So it needs a special routine
641 * to print IO-APIC entries for debugging purposes too.
643 x86_io_apic_ops.print_entries = intel_ir_io_apic_print_entries;
645 pr_info("Enabled IRQ remapping in %s mode\n", eim ? "x2apic" : "xapic");
647 return eim ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
651 * handle error condition gracefully here!
655 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
660 static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
661 struct intel_iommu *iommu)
663 struct acpi_dmar_pci_path *path;
668 path = (struct acpi_dmar_pci_path *)(scope + 1);
669 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
670 / sizeof(struct acpi_dmar_pci_path);
672 while (--count > 0) {
674 * Access PCI directly due to the PCI
675 * subsystem isn't initialized yet.
677 bus = read_pci_config_byte(bus, path->device, path->function,
681 ir_hpet[ir_hpet_num].bus = bus;
682 ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->device, path->function);
683 ir_hpet[ir_hpet_num].iommu = iommu;
684 ir_hpet[ir_hpet_num].id = scope->enumeration_id;
688 static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
689 struct intel_iommu *iommu)
691 struct acpi_dmar_pci_path *path;
696 path = (struct acpi_dmar_pci_path *)(scope + 1);
697 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
698 / sizeof(struct acpi_dmar_pci_path);
700 while (--count > 0) {
702 * Access PCI directly due to the PCI
703 * subsystem isn't initialized yet.
705 bus = read_pci_config_byte(bus, path->device, path->function,
710 ir_ioapic[ir_ioapic_num].bus = bus;
711 ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->device, path->function);
712 ir_ioapic[ir_ioapic_num].iommu = iommu;
713 ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
717 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
718 struct intel_iommu *iommu)
720 struct acpi_dmar_hardware_unit *drhd;
721 struct acpi_dmar_device_scope *scope;
724 drhd = (struct acpi_dmar_hardware_unit *)header;
726 start = (void *)(drhd + 1);
727 end = ((void *)drhd) + header->length;
729 while (start < end) {
731 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
732 if (ir_ioapic_num == MAX_IO_APICS) {
733 printk(KERN_WARNING "Exceeded Max IO APICS\n");
737 printk(KERN_INFO "IOAPIC id %d under DRHD base "
738 " 0x%Lx IOMMU %d\n", scope->enumeration_id,
739 drhd->address, iommu->seq_id);
741 ir_parse_one_ioapic_scope(scope, iommu);
742 } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) {
743 if (ir_hpet_num == MAX_HPET_TBS) {
744 printk(KERN_WARNING "Exceeded Max HPET blocks\n");
748 printk(KERN_INFO "HPET id %d under DRHD base"
749 " 0x%Lx\n", scope->enumeration_id,
752 ir_parse_one_hpet_scope(scope, iommu);
754 start += scope->length;
761 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
764 static int __init parse_ioapics_under_ir(void)
766 struct dmar_drhd_unit *drhd;
767 struct intel_iommu *iommu;
768 int ir_supported = 0;
771 for_each_iommu(iommu, drhd)
772 if (ecap_ir_support(iommu->ecap)) {
773 if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
782 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
783 int ioapic_id = mpc_ioapic_id(ioapic_idx);
784 if (!map_ioapic_to_ir(ioapic_id)) {
785 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
786 "interrupt remapping will be disabled\n",
795 static int __init ir_dev_scope_init(void)
797 if (!irq_remapping_enabled)
800 return dmar_dev_scope_init();
802 rootfs_initcall(ir_dev_scope_init);
804 static void disable_irq_remapping(void)
806 struct dmar_drhd_unit *drhd;
807 struct intel_iommu *iommu = NULL;
810 * Disable Interrupt-remapping for all the DRHD's now.
812 for_each_iommu(iommu, drhd) {
813 if (!ecap_ir_support(iommu->ecap))
816 iommu_disable_irq_remapping(iommu);
820 static int reenable_irq_remapping(int eim)
822 struct dmar_drhd_unit *drhd;
824 struct intel_iommu *iommu = NULL;
826 for_each_iommu(iommu, drhd)
828 dmar_reenable_qi(iommu);
831 * Setup Interrupt-remapping for all the DRHD's now.
833 for_each_iommu(iommu, drhd) {
834 if (!ecap_ir_support(iommu->ecap))
837 /* Set up interrupt remapping for iommu.*/
838 iommu_set_irq_remapping(iommu, eim);
849 * handle error condition gracefully here!
854 static void prepare_irte(struct irte *irte, int vector,
857 memset(irte, 0, sizeof(*irte));
860 irte->dst_mode = apic->irq_dest_mode;
862 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
863 * actual level or edge trigger will be setup in the IO-APIC
864 * RTE. This will help simplify level triggered irq migration.
865 * For more details, see the comments (in io_apic.c) explainig IO-APIC
866 * irq migration in the presence of interrupt-remapping.
868 irte->trigger_mode = 0;
869 irte->dlvry_mode = apic->irq_delivery_mode;
870 irte->vector = vector;
871 irte->dest_id = IRTE_DEST(dest);
872 irte->redir_hint = 1;
875 static int intel_setup_ioapic_entry(int irq,
876 struct IO_APIC_route_entry *route_entry,
877 unsigned int destination, int vector,
878 struct io_apic_irq_attr *attr)
880 int ioapic_id = mpc_ioapic_id(attr->ioapic);
881 struct intel_iommu *iommu = map_ioapic_to_ir(ioapic_id);
882 struct IR_IO_APIC_route_entry *entry;
887 pr_warn("No mapping iommu for ioapic %d\n", ioapic_id);
891 entry = (struct IR_IO_APIC_route_entry *)route_entry;
893 index = alloc_irte(iommu, irq, 1);
895 pr_warn("Failed to allocate IRTE for ioapic %d\n", ioapic_id);
899 prepare_irte(&irte, vector, destination);
901 /* Set source-id of interrupt request */
902 set_ioapic_sid(&irte, ioapic_id);
904 modify_irte(irq, &irte);
906 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
907 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
908 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
909 "Avail:%X Vector:%02X Dest:%08X "
910 "SID:%04X SQ:%X SVT:%X)\n",
911 attr->ioapic, irte.present, irte.fpd, irte.dst_mode,
912 irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
913 irte.avail, irte.vector, irte.dest_id,
914 irte.sid, irte.sq, irte.svt);
916 memset(entry, 0, sizeof(*entry));
918 entry->index2 = (index >> 15) & 0x1;
921 entry->index = (index & 0x7fff);
923 * IO-APIC RTE will be configured with virtual vector.
924 * irq handler will do the explicit EOI to the io-apic.
926 entry->vector = attr->ioapic_pin;
927 entry->mask = 0; /* enable IRQ */
928 entry->trigger = attr->trigger;
929 entry->polarity = attr->polarity;
931 /* Mask level triggered irqs.
932 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
941 * Migrate the IO-APIC irq in the presence of intr-remapping.
943 * For both level and edge triggered, irq migration is a simple atomic
944 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
946 * For level triggered, we eliminate the io-apic RTE modification (with the
947 * updated vector information), by using a virtual vector (io-apic pin number).
948 * Real vector that is used for interrupting cpu will be coming from
949 * the interrupt-remapping table entry.
951 * As the migration is a simple atomic update of IRTE, the same mechanism
952 * is used to migrate MSI irq's in the presence of interrupt-remapping.
955 intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
958 struct irq_cfg *cfg = data->chip_data;
959 unsigned int dest, irq = data->irq;
963 if (!config_enabled(CONFIG_SMP))
966 if (!cpumask_intersects(mask, cpu_online_mask))
969 if (get_irte(irq, &irte))
972 err = assign_irq_vector(irq, cfg, mask);
976 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
978 if (assign_irq_vector(irq, cfg, data->affinity))
979 pr_err("Failed to recover vector for irq %d\n", irq);
983 irte.vector = cfg->vector;
984 irte.dest_id = IRTE_DEST(dest);
987 * Atomically updates the IRTE with the new destination, vector
988 * and flushes the interrupt entry cache.
990 modify_irte(irq, &irte);
993 * After this point, all the interrupts will start arriving
994 * at the new destination. So, time to cleanup the previous
997 if (cfg->move_in_progress)
998 send_cleanup_vector(cfg);
1000 cpumask_copy(data->affinity, mask);
1004 static void intel_compose_msi_msg(struct pci_dev *pdev,
1005 unsigned int irq, unsigned int dest,
1006 struct msi_msg *msg, u8 hpet_id)
1008 struct irq_cfg *cfg;
1013 cfg = irq_get_chip_data(irq);
1015 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
1016 BUG_ON(ir_index == -1);
1018 prepare_irte(&irte, cfg->vector, dest);
1020 /* Set source-id of interrupt request */
1022 set_msi_sid(&irte, pdev);
1024 set_hpet_sid(&irte, hpet_id);
1026 modify_irte(irq, &irte);
1028 msg->address_hi = MSI_ADDR_BASE_HI;
1029 msg->data = sub_handle;
1030 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1032 MSI_ADDR_IR_INDEX1(ir_index) |
1033 MSI_ADDR_IR_INDEX2(ir_index);
1037 * Map the PCI dev to the corresponding remapping hardware unit
1038 * and allocate 'nvec' consecutive interrupt-remapping table entries
1041 static int intel_msi_alloc_irq(struct pci_dev *dev, int irq, int nvec)
1043 struct intel_iommu *iommu;
1046 iommu = map_dev_to_ir(dev);
1049 "Unable to map PCI %s to iommu\n", pci_name(dev));
1053 index = alloc_irte(iommu, irq, nvec);
1056 "Unable to allocate %d IRTE for PCI %s\n", nvec,
1063 static int intel_msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
1064 int index, int sub_handle)
1066 struct intel_iommu *iommu;
1068 iommu = map_dev_to_ir(pdev);
1072 * setup the mapping between the irq and the IRTE
1073 * base index, the sub_handle pointing to the
1074 * appropriate interrupt remap table entry.
1076 set_irte_irq(irq, iommu, index, sub_handle);
1081 static int intel_setup_hpet_msi(unsigned int irq, unsigned int id)
1083 struct intel_iommu *iommu = map_hpet_to_ir(id);
1089 index = alloc_irte(iommu, irq, 1);
1096 struct irq_remap_ops intel_irq_remap_ops = {
1097 .supported = intel_irq_remapping_supported,
1098 .prepare = dmar_table_init,
1099 .enable = intel_enable_irq_remapping,
1100 .disable = disable_irq_remapping,
1101 .reenable = reenable_irq_remapping,
1102 .enable_faulting = enable_drhd_fault_handling,
1103 .setup_ioapic_entry = intel_setup_ioapic_entry,
1104 .set_affinity = intel_ioapic_set_affinity,
1105 .free_irq = free_irte,
1106 .compose_msi_msg = intel_compose_msi_msg,
1107 .msi_alloc_irq = intel_msi_alloc_irq,
1108 .msi_setup_irq = intel_msi_setup_irq,
1109 .setup_hpet_msi = intel_setup_hpet_msi,