2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <linux/amd-iommu.h>
28 #include <linux/export.h>
29 #include <linux/acpi.h>
30 #include <acpi/acpi.h>
31 #include <asm/pci-direct.h>
32 #include <asm/iommu.h>
34 #include <asm/x86_init.h>
35 #include <asm/iommu_table.h>
36 #include <asm/io_apic.h>
38 #include "amd_iommu_proto.h"
39 #include "amd_iommu_types.h"
40 #include "irq_remapping.h"
43 * definitions for the ACPI scanning code
45 #define IVRS_HEADER_LENGTH 48
47 #define ACPI_IVHD_TYPE 0x10
48 #define ACPI_IVMD_TYPE_ALL 0x20
49 #define ACPI_IVMD_TYPE 0x21
50 #define ACPI_IVMD_TYPE_RANGE 0x22
52 #define IVHD_DEV_ALL 0x01
53 #define IVHD_DEV_SELECT 0x02
54 #define IVHD_DEV_SELECT_RANGE_START 0x03
55 #define IVHD_DEV_RANGE_END 0x04
56 #define IVHD_DEV_ALIAS 0x42
57 #define IVHD_DEV_ALIAS_RANGE 0x43
58 #define IVHD_DEV_EXT_SELECT 0x46
59 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
60 #define IVHD_DEV_SPECIAL 0x48
62 #define IVHD_SPECIAL_IOAPIC 1
63 #define IVHD_SPECIAL_HPET 2
65 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
66 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
67 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
68 #define IVHD_FLAG_ISOC_EN_MASK 0x08
70 #define IVMD_FLAG_EXCL_RANGE 0x08
71 #define IVMD_FLAG_UNITY_MAP 0x01
73 #define ACPI_DEVFLAG_INITPASS 0x01
74 #define ACPI_DEVFLAG_EXTINT 0x02
75 #define ACPI_DEVFLAG_NMI 0x04
76 #define ACPI_DEVFLAG_SYSMGT1 0x10
77 #define ACPI_DEVFLAG_SYSMGT2 0x20
78 #define ACPI_DEVFLAG_LINT0 0x40
79 #define ACPI_DEVFLAG_LINT1 0x80
80 #define ACPI_DEVFLAG_ATSDIS 0x10000000
83 * ACPI table definitions
85 * These data structures are laid over the table to parse the important values
90 * structure describing one IOMMU in the ACPI table. Typically followed by one
91 * or more ivhd_entrys.
103 } __attribute__((packed));
106 * A device entry describing which devices a specific IOMMU translates and
107 * which requestor ids they use.
114 } __attribute__((packed));
117 * An AMD IOMMU memory definition structure. It defines things like exclusion
118 * ranges for devices and regions that should be unity mapped.
129 } __attribute__((packed));
132 bool amd_iommu_irq_remap __read_mostly;
134 static bool amd_iommu_detected;
135 static bool __initdata amd_iommu_disabled;
137 u16 amd_iommu_last_bdf; /* largest PCI device id we have
139 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
141 u32 amd_iommu_unmap_flush; /* if true, flush on every unmap */
143 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
146 /* Array to assign indices to IOMMUs*/
147 struct amd_iommu *amd_iommus[MAX_IOMMUS];
148 int amd_iommus_present;
150 /* IOMMUs have a non-present cache? */
151 bool amd_iommu_np_cache __read_mostly;
152 bool amd_iommu_iotlb_sup __read_mostly = true;
154 u32 amd_iommu_max_pasids __read_mostly = ~0;
156 bool amd_iommu_v2_present __read_mostly;
158 bool amd_iommu_force_isolation __read_mostly;
161 * List of protection domains - used during resume
163 LIST_HEAD(amd_iommu_pd_list);
164 spinlock_t amd_iommu_pd_lock;
167 * Pointer to the device table which is shared by all AMD IOMMUs
168 * it is indexed by the PCI device id or the HT unit id and contains
169 * information about the domain the device belongs to as well as the
170 * page table root pointer.
172 struct dev_table_entry *amd_iommu_dev_table;
175 * The alias table is a driver specific data structure which contains the
176 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
177 * More than one device can share the same requestor id.
179 u16 *amd_iommu_alias_table;
182 * The rlookup table is used to find the IOMMU which is responsible
183 * for a specific device. It is also indexed by the PCI device id.
185 struct amd_iommu **amd_iommu_rlookup_table;
188 * This table is used to find the irq remapping table for a given device id
191 struct irq_remap_table **irq_lookup_table;
194 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
195 * to know which ones are already in use.
197 unsigned long *amd_iommu_pd_alloc_bitmap;
199 static u32 dev_table_size; /* size of the device table */
200 static u32 alias_table_size; /* size of the alias table */
201 static u32 rlookup_table_size; /* size if the rlookup table */
203 enum iommu_init_state {
216 static enum iommu_init_state init_state = IOMMU_START_STATE;
218 static int amd_iommu_enable_interrupts(void);
219 static int __init iommu_go_to_state(enum iommu_init_state state);
221 static inline void update_last_devid(u16 devid)
223 if (devid > amd_iommu_last_bdf)
224 amd_iommu_last_bdf = devid;
227 static inline unsigned long tbl_size(int entry_size)
229 unsigned shift = PAGE_SHIFT +
230 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
235 /* Access to l1 and l2 indexed register spaces */
237 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
241 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
242 pci_read_config_dword(iommu->dev, 0xfc, &val);
246 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
248 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
249 pci_write_config_dword(iommu->dev, 0xfc, val);
250 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
253 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
257 pci_write_config_dword(iommu->dev, 0xf0, address);
258 pci_read_config_dword(iommu->dev, 0xf4, &val);
262 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
264 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
265 pci_write_config_dword(iommu->dev, 0xf4, val);
268 /****************************************************************************
270 * AMD IOMMU MMIO register space handling functions
272 * These functions are used to program the IOMMU device registers in
273 * MMIO space required for that driver.
275 ****************************************************************************/
278 * This function set the exclusion range in the IOMMU. DMA accesses to the
279 * exclusion range are passed through untranslated
281 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
283 u64 start = iommu->exclusion_start & PAGE_MASK;
284 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
287 if (!iommu->exclusion_start)
290 entry = start | MMIO_EXCL_ENABLE_MASK;
291 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
292 &entry, sizeof(entry));
295 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
296 &entry, sizeof(entry));
299 /* Programs the physical address of the device table into the IOMMU hardware */
300 static void iommu_set_device_table(struct amd_iommu *iommu)
304 BUG_ON(iommu->mmio_base == NULL);
306 entry = virt_to_phys(amd_iommu_dev_table);
307 entry |= (dev_table_size >> 12) - 1;
308 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
309 &entry, sizeof(entry));
312 /* Generic functions to enable/disable certain features of the IOMMU. */
313 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
317 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
319 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
322 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
326 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
328 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
331 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
335 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
336 ctrl &= ~CTRL_INV_TO_MASK;
337 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
338 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
341 /* Function to enable the hardware */
342 static void iommu_enable(struct amd_iommu *iommu)
344 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
347 static void iommu_disable(struct amd_iommu *iommu)
349 /* Disable command buffer */
350 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
352 /* Disable event logging and event interrupts */
353 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
354 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
356 /* Disable IOMMU hardware itself */
357 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
361 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
362 * the system has one.
364 static u8 __iomem * __init iommu_map_mmio_space(u64 address)
366 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
367 pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
369 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
373 return (u8 __iomem *)ioremap_nocache(address, MMIO_REGION_LENGTH);
376 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
378 if (iommu->mmio_base)
379 iounmap(iommu->mmio_base);
380 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
383 /****************************************************************************
385 * The functions below belong to the first pass of AMD IOMMU ACPI table
386 * parsing. In this pass we try to find out the highest device id this
387 * code has to handle. Upon this information the size of the shared data
388 * structures is determined later.
390 ****************************************************************************/
393 * This function calculates the length of a given IVHD entry
395 static inline int ivhd_entry_length(u8 *ivhd)
397 return 0x04 << (*ivhd >> 6);
401 * This function reads the last device id the IOMMU has to handle from the PCI
402 * capability header for this IOMMU
404 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
408 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
409 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
415 * After reading the highest device id from the IOMMU PCI capability header
416 * this function looks if there is a higher device id defined in the ACPI table
418 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
420 u8 *p = (void *)h, *end = (void *)h;
421 struct ivhd_entry *dev;
426 find_last_devid_on_pci(PCI_BUS(h->devid),
432 dev = (struct ivhd_entry *)p;
434 case IVHD_DEV_SELECT:
435 case IVHD_DEV_RANGE_END:
437 case IVHD_DEV_EXT_SELECT:
438 /* all the above subfield types refer to device ids */
439 update_last_devid(dev->devid);
444 p += ivhd_entry_length(p);
453 * Iterate over all IVHD entries in the ACPI table and find the highest device
454 * id which we need to handle. This is the first of three functions which parse
455 * the ACPI table. So we check the checksum here.
457 static int __init find_last_devid_acpi(struct acpi_table_header *table)
460 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
461 struct ivhd_header *h;
464 * Validate checksum here so we don't need to do it when
465 * we actually parse the table
467 for (i = 0; i < table->length; ++i)
470 /* ACPI table corrupt */
473 p += IVRS_HEADER_LENGTH;
475 end += table->length;
477 h = (struct ivhd_header *)p;
480 find_last_devid_from_ivhd(h);
492 /****************************************************************************
494 * The following functions belong the the code path which parses the ACPI table
495 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
496 * data structures, initialize the device/alias/rlookup table and also
497 * basically initialize the hardware.
499 ****************************************************************************/
502 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
503 * write commands to that buffer later and the IOMMU will execute them
506 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
508 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
509 get_order(CMD_BUFFER_SIZE));
514 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
520 * This function resets the command buffer if the IOMMU stopped fetching
523 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
525 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
527 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
528 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
530 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
534 * This function writes the command buffer address to the hardware and
537 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
541 BUG_ON(iommu->cmd_buf == NULL);
543 entry = (u64)virt_to_phys(iommu->cmd_buf);
544 entry |= MMIO_CMD_SIZE_512;
546 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
547 &entry, sizeof(entry));
549 amd_iommu_reset_cmd_buffer(iommu);
550 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
553 static void __init free_command_buffer(struct amd_iommu *iommu)
555 free_pages((unsigned long)iommu->cmd_buf,
556 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
559 /* allocates the memory where the IOMMU will log its events to */
560 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
562 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
563 get_order(EVT_BUFFER_SIZE));
565 if (iommu->evt_buf == NULL)
568 iommu->evt_buf_size = EVT_BUFFER_SIZE;
570 return iommu->evt_buf;
573 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
577 BUG_ON(iommu->evt_buf == NULL);
579 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
581 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
582 &entry, sizeof(entry));
584 /* set head and tail to zero manually */
585 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
586 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
588 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
591 static void __init free_event_buffer(struct amd_iommu *iommu)
593 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
596 /* allocates the memory where the IOMMU will log its events to */
597 static u8 * __init alloc_ppr_log(struct amd_iommu *iommu)
599 iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
600 get_order(PPR_LOG_SIZE));
602 if (iommu->ppr_log == NULL)
605 return iommu->ppr_log;
608 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
612 if (iommu->ppr_log == NULL)
615 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
617 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
618 &entry, sizeof(entry));
620 /* set head and tail to zero manually */
621 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
622 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
624 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
625 iommu_feature_enable(iommu, CONTROL_PPR_EN);
628 static void __init free_ppr_log(struct amd_iommu *iommu)
630 if (iommu->ppr_log == NULL)
633 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
636 static void iommu_enable_gt(struct amd_iommu *iommu)
638 if (!iommu_feature(iommu, FEATURE_GT))
641 iommu_feature_enable(iommu, CONTROL_GT_EN);
644 /* sets a specific bit in the device table entry. */
645 static void set_dev_entry_bit(u16 devid, u8 bit)
647 int i = (bit >> 6) & 0x03;
648 int _bit = bit & 0x3f;
650 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
653 static int get_dev_entry_bit(u16 devid, u8 bit)
655 int i = (bit >> 6) & 0x03;
656 int _bit = bit & 0x3f;
658 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
662 void amd_iommu_apply_erratum_63(u16 devid)
666 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
667 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
670 set_dev_entry_bit(devid, DEV_ENTRY_IW);
673 /* Writes the specific IOMMU for a device into the rlookup table */
674 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
676 amd_iommu_rlookup_table[devid] = iommu;
680 * This function takes the device specific flags read from the ACPI
681 * table and sets up the device table entry with that information
683 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
684 u16 devid, u32 flags, u32 ext_flags)
686 if (flags & ACPI_DEVFLAG_INITPASS)
687 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
688 if (flags & ACPI_DEVFLAG_EXTINT)
689 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
690 if (flags & ACPI_DEVFLAG_NMI)
691 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
692 if (flags & ACPI_DEVFLAG_SYSMGT1)
693 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
694 if (flags & ACPI_DEVFLAG_SYSMGT2)
695 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
696 if (flags & ACPI_DEVFLAG_LINT0)
697 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
698 if (flags & ACPI_DEVFLAG_LINT1)
699 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
701 amd_iommu_apply_erratum_63(devid);
703 set_iommu_for_device(iommu, devid);
706 static int add_special_device(u8 type, u8 id, u16 devid)
708 struct devid_map *entry;
709 struct list_head *list;
711 if (type != IVHD_SPECIAL_IOAPIC && type != IVHD_SPECIAL_HPET)
714 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
719 entry->devid = devid;
721 if (type == IVHD_SPECIAL_IOAPIC)
726 list_add_tail(&entry->list, list);
732 * Reads the device exclusion range from ACPI and initialize IOMMU with
735 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
737 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
739 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
744 * We only can configure exclusion ranges per IOMMU, not
745 * per device. But we can enable the exclusion range per
746 * device. This is done here
748 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
749 iommu->exclusion_start = m->range_start;
750 iommu->exclusion_length = m->range_length;
755 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
756 * initializes the hardware and our data structures with it.
758 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
759 struct ivhd_header *h)
762 u8 *end = p, flags = 0;
763 u16 devid = 0, devid_start = 0, devid_to = 0;
764 u32 dev_i, ext_flags = 0;
766 struct ivhd_entry *e;
769 * First save the recommended feature enable bits from ACPI
771 iommu->acpi_flags = h->flags;
774 * Done. Now parse the device entries
776 p += sizeof(struct ivhd_header);
781 e = (struct ivhd_entry *)p;
785 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
786 " last device %02x:%02x.%x flags: %02x\n",
787 PCI_BUS(iommu->first_device),
788 PCI_SLOT(iommu->first_device),
789 PCI_FUNC(iommu->first_device),
790 PCI_BUS(iommu->last_device),
791 PCI_SLOT(iommu->last_device),
792 PCI_FUNC(iommu->last_device),
795 for (dev_i = iommu->first_device;
796 dev_i <= iommu->last_device; ++dev_i)
797 set_dev_entry_from_acpi(iommu, dev_i,
800 case IVHD_DEV_SELECT:
802 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
810 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
812 case IVHD_DEV_SELECT_RANGE_START:
814 DUMP_printk(" DEV_SELECT_RANGE_START\t "
815 "devid: %02x:%02x.%x flags: %02x\n",
821 devid_start = e->devid;
828 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
829 "flags: %02x devid_to: %02x:%02x.%x\n",
834 PCI_BUS(e->ext >> 8),
835 PCI_SLOT(e->ext >> 8),
836 PCI_FUNC(e->ext >> 8));
839 devid_to = e->ext >> 8;
840 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
841 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
842 amd_iommu_alias_table[devid] = devid_to;
844 case IVHD_DEV_ALIAS_RANGE:
846 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
847 "devid: %02x:%02x.%x flags: %02x "
848 "devid_to: %02x:%02x.%x\n",
853 PCI_BUS(e->ext >> 8),
854 PCI_SLOT(e->ext >> 8),
855 PCI_FUNC(e->ext >> 8));
857 devid_start = e->devid;
859 devid_to = e->ext >> 8;
863 case IVHD_DEV_EXT_SELECT:
865 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
866 "flags: %02x ext: %08x\n",
873 set_dev_entry_from_acpi(iommu, devid, e->flags,
876 case IVHD_DEV_EXT_SELECT_RANGE:
878 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
879 "%02x:%02x.%x flags: %02x ext: %08x\n",
885 devid_start = e->devid;
890 case IVHD_DEV_RANGE_END:
892 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
898 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
900 amd_iommu_alias_table[dev_i] = devid_to;
901 set_dev_entry_from_acpi(iommu,
902 devid_to, flags, ext_flags);
904 set_dev_entry_from_acpi(iommu, dev_i,
908 case IVHD_DEV_SPECIAL: {
914 handle = e->ext & 0xff;
915 devid = (e->ext >> 8) & 0xffff;
916 type = (e->ext >> 24) & 0xff;
918 if (type == IVHD_SPECIAL_IOAPIC)
920 else if (type == IVHD_SPECIAL_HPET)
925 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
931 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
932 ret = add_special_device(type, handle, devid);
941 p += ivhd_entry_length(p);
947 /* Initializes the device->iommu mapping for the driver */
948 static int __init init_iommu_devices(struct amd_iommu *iommu)
952 for (i = iommu->first_device; i <= iommu->last_device; ++i)
953 set_iommu_for_device(iommu, i);
958 static void __init free_iommu_one(struct amd_iommu *iommu)
960 free_command_buffer(iommu);
961 free_event_buffer(iommu);
963 iommu_unmap_mmio_space(iommu);
966 static void __init free_iommu_all(void)
968 struct amd_iommu *iommu, *next;
970 for_each_iommu_safe(iommu, next) {
971 list_del(&iommu->list);
972 free_iommu_one(iommu);
978 * This function clues the initialization function for one IOMMU
979 * together and also allocates the command buffer and programs the
980 * hardware. It does NOT enable the IOMMU. This is done afterwards.
982 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
986 spin_lock_init(&iommu->lock);
988 /* Add IOMMU to internal data structures */
989 list_add_tail(&iommu->list, &amd_iommu_list);
990 iommu->index = amd_iommus_present++;
992 if (unlikely(iommu->index >= MAX_IOMMUS)) {
993 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
997 /* Index is fine - add IOMMU to the array */
998 amd_iommus[iommu->index] = iommu;
1001 * Copy data from ACPI table entry to the iommu struct
1003 iommu->devid = h->devid;
1004 iommu->cap_ptr = h->cap_ptr;
1005 iommu->pci_seg = h->pci_seg;
1006 iommu->mmio_phys = h->mmio_phys;
1007 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
1008 if (!iommu->mmio_base)
1011 iommu->cmd_buf = alloc_command_buffer(iommu);
1012 if (!iommu->cmd_buf)
1015 iommu->evt_buf = alloc_event_buffer(iommu);
1016 if (!iommu->evt_buf)
1019 iommu->int_enabled = false;
1021 ret = init_iommu_from_acpi(iommu, h);
1024 init_iommu_devices(iommu);
1030 * Iterates over all IOMMU entries in the ACPI table, allocates the
1031 * IOMMU structure and initializes it with init_iommu_one()
1033 static int __init init_iommu_all(struct acpi_table_header *table)
1035 u8 *p = (u8 *)table, *end = (u8 *)table;
1036 struct ivhd_header *h;
1037 struct amd_iommu *iommu;
1040 end += table->length;
1041 p += IVRS_HEADER_LENGTH;
1044 h = (struct ivhd_header *)p;
1046 case ACPI_IVHD_TYPE:
1048 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1049 "seg: %d flags: %01x info %04x\n",
1050 PCI_BUS(h->devid), PCI_SLOT(h->devid),
1051 PCI_FUNC(h->devid), h->cap_ptr,
1052 h->pci_seg, h->flags, h->info);
1053 DUMP_printk(" mmio-addr: %016llx\n",
1056 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1060 ret = init_iommu_one(iommu, h);
1075 static int iommu_init_pci(struct amd_iommu *iommu)
1077 int cap_ptr = iommu->cap_ptr;
1078 u32 range, misc, low, high;
1080 iommu->dev = pci_get_bus_and_slot(PCI_BUS(iommu->devid),
1081 iommu->devid & 0xff);
1085 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1087 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1089 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1092 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
1093 MMIO_GET_FD(range));
1094 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
1095 MMIO_GET_LD(range));
1097 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1098 amd_iommu_iotlb_sup = false;
1100 /* read extended feature bits */
1101 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1102 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1104 iommu->features = ((u64)high << 32) | low;
1106 if (iommu_feature(iommu, FEATURE_GT)) {
1111 shift = iommu->features & FEATURE_PASID_MASK;
1112 shift >>= FEATURE_PASID_SHIFT;
1113 pasids = (1 << shift);
1115 amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids);
1117 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1118 glxval >>= FEATURE_GLXVAL_SHIFT;
1120 if (amd_iommu_max_glx_val == -1)
1121 amd_iommu_max_glx_val = glxval;
1123 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1126 if (iommu_feature(iommu, FEATURE_GT) &&
1127 iommu_feature(iommu, FEATURE_PPR)) {
1128 iommu->is_iommu_v2 = true;
1129 amd_iommu_v2_present = true;
1132 if (iommu_feature(iommu, FEATURE_PPR)) {
1133 iommu->ppr_log = alloc_ppr_log(iommu);
1134 if (!iommu->ppr_log)
1138 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1139 amd_iommu_np_cache = true;
1141 if (is_rd890_iommu(iommu->dev)) {
1144 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1148 * Some rd890 systems may not be fully reconfigured by the
1149 * BIOS, so it's necessary for us to store this information so
1150 * it can be reprogrammed on resume
1152 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1153 &iommu->stored_addr_lo);
1154 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1155 &iommu->stored_addr_hi);
1157 /* Low bit locks writes to configuration space */
1158 iommu->stored_addr_lo &= ~1;
1160 for (i = 0; i < 6; i++)
1161 for (j = 0; j < 0x12; j++)
1162 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1164 for (i = 0; i < 0x83; i++)
1165 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1168 return pci_enable_device(iommu->dev);
1171 static void print_iommu_info(void)
1173 static const char * const feat_str[] = {
1174 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1175 "IA", "GA", "HE", "PC"
1177 struct amd_iommu *iommu;
1179 for_each_iommu(iommu) {
1182 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1183 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1185 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1186 pr_info("AMD-Vi: Extended features: ");
1187 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1188 if (iommu_feature(iommu, (1ULL << i)))
1189 pr_cont(" %s", feat_str[i]);
1196 static int __init amd_iommu_init_pci(void)
1198 struct amd_iommu *iommu;
1201 for_each_iommu(iommu) {
1202 ret = iommu_init_pci(iommu);
1207 ret = amd_iommu_init_devices();
1214 /****************************************************************************
1216 * The following functions initialize the MSI interrupts for all IOMMUs
1217 * in the system. Its a bit challenging because there could be multiple
1218 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1221 ****************************************************************************/
1223 static int iommu_setup_msi(struct amd_iommu *iommu)
1227 r = pci_enable_msi(iommu->dev);
1231 r = request_threaded_irq(iommu->dev->irq,
1232 amd_iommu_int_handler,
1233 amd_iommu_int_thread,
1238 pci_disable_msi(iommu->dev);
1242 iommu->int_enabled = true;
1247 static int iommu_init_msi(struct amd_iommu *iommu)
1251 if (iommu->int_enabled)
1254 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
1255 ret = iommu_setup_msi(iommu);
1263 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1265 if (iommu->ppr_log != NULL)
1266 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1271 /****************************************************************************
1273 * The next functions belong to the third pass of parsing the ACPI
1274 * table. In this last pass the memory mapping requirements are
1275 * gathered (like exclusion and unity mapping reanges).
1277 ****************************************************************************/
1279 static void __init free_unity_maps(void)
1281 struct unity_map_entry *entry, *next;
1283 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1284 list_del(&entry->list);
1289 /* called when we find an exclusion range definition in ACPI */
1290 static int __init init_exclusion_range(struct ivmd_header *m)
1295 case ACPI_IVMD_TYPE:
1296 set_device_exclusion_range(m->devid, m);
1298 case ACPI_IVMD_TYPE_ALL:
1299 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1300 set_device_exclusion_range(i, m);
1302 case ACPI_IVMD_TYPE_RANGE:
1303 for (i = m->devid; i <= m->aux; ++i)
1304 set_device_exclusion_range(i, m);
1313 /* called for unity map ACPI definition */
1314 static int __init init_unity_map_range(struct ivmd_header *m)
1316 struct unity_map_entry *e = NULL;
1319 e = kzalloc(sizeof(*e), GFP_KERNEL);
1327 case ACPI_IVMD_TYPE:
1328 s = "IVMD_TYPEi\t\t\t";
1329 e->devid_start = e->devid_end = m->devid;
1331 case ACPI_IVMD_TYPE_ALL:
1332 s = "IVMD_TYPE_ALL\t\t";
1334 e->devid_end = amd_iommu_last_bdf;
1336 case ACPI_IVMD_TYPE_RANGE:
1337 s = "IVMD_TYPE_RANGE\t\t";
1338 e->devid_start = m->devid;
1339 e->devid_end = m->aux;
1342 e->address_start = PAGE_ALIGN(m->range_start);
1343 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1344 e->prot = m->flags >> 1;
1346 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1347 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1348 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1349 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1350 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1351 e->address_start, e->address_end, m->flags);
1353 list_add_tail(&e->list, &amd_iommu_unity_map);
1358 /* iterates over all memory definitions we find in the ACPI table */
1359 static int __init init_memory_definitions(struct acpi_table_header *table)
1361 u8 *p = (u8 *)table, *end = (u8 *)table;
1362 struct ivmd_header *m;
1364 end += table->length;
1365 p += IVRS_HEADER_LENGTH;
1368 m = (struct ivmd_header *)p;
1369 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1370 init_exclusion_range(m);
1371 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1372 init_unity_map_range(m);
1381 * Init the device table to not allow DMA access for devices and
1382 * suppress all page faults
1384 static void init_device_table(void)
1388 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1389 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1390 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1394 static void iommu_init_flags(struct amd_iommu *iommu)
1396 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1397 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1398 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1400 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1401 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1402 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1404 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1405 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1406 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1408 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1409 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1410 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1413 * make IOMMU memory accesses cache coherent
1415 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1417 /* Set IOTLB invalidation timeout to 1s */
1418 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1421 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1424 u32 ioc_feature_control;
1425 struct pci_dev *pdev = iommu->root_pdev;
1427 /* RD890 BIOSes may not have completely reconfigured the iommu */
1428 if (!is_rd890_iommu(iommu->dev) || !pdev)
1432 * First, we need to ensure that the iommu is enabled. This is
1433 * controlled by a register in the northbridge
1436 /* Select Northbridge indirect register 0x75 and enable writing */
1437 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1438 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1440 /* Enable the iommu */
1441 if (!(ioc_feature_control & 0x1))
1442 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1444 /* Restore the iommu BAR */
1445 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1446 iommu->stored_addr_lo);
1447 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1448 iommu->stored_addr_hi);
1450 /* Restore the l1 indirect regs for each of the 6 l1s */
1451 for (i = 0; i < 6; i++)
1452 for (j = 0; j < 0x12; j++)
1453 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1455 /* Restore the l2 indirect regs */
1456 for (i = 0; i < 0x83; i++)
1457 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1459 /* Lock PCI setup registers */
1460 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1461 iommu->stored_addr_lo | 1);
1465 * This function finally enables all IOMMUs found in the system after
1466 * they have been initialized
1468 static void early_enable_iommus(void)
1470 struct amd_iommu *iommu;
1472 for_each_iommu(iommu) {
1473 iommu_disable(iommu);
1474 iommu_init_flags(iommu);
1475 iommu_set_device_table(iommu);
1476 iommu_enable_command_buffer(iommu);
1477 iommu_enable_event_buffer(iommu);
1478 iommu_set_exclusion_range(iommu);
1479 iommu_enable(iommu);
1480 iommu_flush_all_caches(iommu);
1484 static void enable_iommus_v2(void)
1486 struct amd_iommu *iommu;
1488 for_each_iommu(iommu) {
1489 iommu_enable_ppr_log(iommu);
1490 iommu_enable_gt(iommu);
1494 static void enable_iommus(void)
1496 early_enable_iommus();
1501 static void disable_iommus(void)
1503 struct amd_iommu *iommu;
1505 for_each_iommu(iommu)
1506 iommu_disable(iommu);
1510 * Suspend/Resume support
1511 * disable suspend until real resume implemented
1514 static void amd_iommu_resume(void)
1516 struct amd_iommu *iommu;
1518 for_each_iommu(iommu)
1519 iommu_apply_resume_quirks(iommu);
1521 /* re-load the hardware */
1524 amd_iommu_enable_interrupts();
1527 static int amd_iommu_suspend(void)
1529 /* disable IOMMUs to go out of the way for BIOS */
1535 static struct syscore_ops amd_iommu_syscore_ops = {
1536 .suspend = amd_iommu_suspend,
1537 .resume = amd_iommu_resume,
1540 static void __init free_on_init_error(void)
1542 free_pages((unsigned long)irq_lookup_table,
1543 get_order(rlookup_table_size));
1545 if (amd_iommu_irq_cache) {
1546 kmem_cache_destroy(amd_iommu_irq_cache);
1547 amd_iommu_irq_cache = NULL;
1551 amd_iommu_uninit_devices();
1553 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1554 get_order(MAX_DOMAIN_ID/8));
1556 free_pages((unsigned long)amd_iommu_rlookup_table,
1557 get_order(rlookup_table_size));
1559 free_pages((unsigned long)amd_iommu_alias_table,
1560 get_order(alias_table_size));
1562 free_pages((unsigned long)amd_iommu_dev_table,
1563 get_order(dev_table_size));
1569 #ifdef CONFIG_GART_IOMMU
1571 * We failed to initialize the AMD IOMMU - try fallback to GART
1579 static bool __init check_ioapic_information(void)
1583 for (idx = 0; idx < nr_ioapics; idx++) {
1584 int id = mpc_ioapic_id(idx);
1586 if (get_ioapic_devid(id) < 0) {
1587 pr_err(FW_BUG "AMD-Vi: IO-APIC[%d] not in IVRS table\n", id);
1588 pr_err("AMD-Vi: Disabling interrupt remapping due to BIOS Bug\n");
1597 * This is the hardware init function for AMD IOMMU in the system.
1598 * This function is called either from amd_iommu_init or from the interrupt
1599 * remapping setup code.
1601 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1604 * 1 pass) Find the highest PCI device id the driver has to handle.
1605 * Upon this information the size of the data structures is
1606 * determined that needs to be allocated.
1608 * 2 pass) Initialize the data structures just allocated with the
1609 * information in the ACPI table about available AMD IOMMUs
1610 * in the system. It also maps the PCI devices in the
1611 * system to specific IOMMUs
1613 * 3 pass) After the basic data structures are allocated and
1614 * initialized we update them with information about memory
1615 * remapping requirements parsed out of the ACPI table in
1618 * After everything is set up the IOMMUs are enabled and the necessary
1619 * hotplug and suspend notifiers are registered.
1621 static int __init early_amd_iommu_init(void)
1623 struct acpi_table_header *ivrs_base;
1624 acpi_size ivrs_size;
1628 if (!amd_iommu_detected)
1631 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1632 if (status == AE_NOT_FOUND)
1634 else if (ACPI_FAILURE(status)) {
1635 const char *err = acpi_format_exception(status);
1636 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1641 * First parse ACPI tables to find the largest Bus/Dev/Func
1642 * we need to handle. Upon this information the shared data
1643 * structures for the IOMMUs in the system will be allocated
1645 ret = find_last_devid_acpi(ivrs_base);
1649 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1650 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1651 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1653 /* Device table - directly used by all IOMMUs */
1655 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1656 get_order(dev_table_size));
1657 if (amd_iommu_dev_table == NULL)
1661 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1662 * IOMMU see for that device
1664 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1665 get_order(alias_table_size));
1666 if (amd_iommu_alias_table == NULL)
1669 /* IOMMU rlookup table - find the IOMMU for a specific device */
1670 amd_iommu_rlookup_table = (void *)__get_free_pages(
1671 GFP_KERNEL | __GFP_ZERO,
1672 get_order(rlookup_table_size));
1673 if (amd_iommu_rlookup_table == NULL)
1676 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1677 GFP_KERNEL | __GFP_ZERO,
1678 get_order(MAX_DOMAIN_ID/8));
1679 if (amd_iommu_pd_alloc_bitmap == NULL)
1683 * let all alias entries point to itself
1685 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1686 amd_iommu_alias_table[i] = i;
1689 * never allocate domain 0 because its used as the non-allocated and
1690 * error value placeholder
1692 amd_iommu_pd_alloc_bitmap[0] = 1;
1694 spin_lock_init(&amd_iommu_pd_lock);
1697 * now the data structures are allocated and basically initialized
1698 * start the real acpi table scan
1700 ret = init_iommu_all(ivrs_base);
1704 if (amd_iommu_irq_remap)
1705 amd_iommu_irq_remap = check_ioapic_information();
1707 if (amd_iommu_irq_remap) {
1709 * Interrupt remapping enabled, create kmem_cache for the
1712 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
1713 MAX_IRQS_PER_TABLE * sizeof(u32),
1714 IRQ_TABLE_ALIGNMENT,
1716 if (!amd_iommu_irq_cache)
1719 irq_lookup_table = (void *)__get_free_pages(
1720 GFP_KERNEL | __GFP_ZERO,
1721 get_order(rlookup_table_size));
1722 if (!irq_lookup_table)
1726 ret = init_memory_definitions(ivrs_base);
1730 /* init the device table */
1731 init_device_table();
1734 /* Don't leak any ACPI memory */
1735 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1741 static int amd_iommu_enable_interrupts(void)
1743 struct amd_iommu *iommu;
1746 for_each_iommu(iommu) {
1747 ret = iommu_init_msi(iommu);
1756 static bool detect_ivrs(void)
1758 struct acpi_table_header *ivrs_base;
1759 acpi_size ivrs_size;
1762 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1763 if (status == AE_NOT_FOUND)
1765 else if (ACPI_FAILURE(status)) {
1766 const char *err = acpi_format_exception(status);
1767 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1771 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1773 /* Make sure ACS will be enabled during PCI probe */
1776 if (!disable_irq_remap)
1777 amd_iommu_irq_remap = true;
1782 static int amd_iommu_init_dma(void)
1786 if (iommu_pass_through)
1787 ret = amd_iommu_init_passthrough();
1789 ret = amd_iommu_init_dma_ops();
1794 amd_iommu_init_api();
1796 amd_iommu_init_notifier();
1801 /****************************************************************************
1803 * AMD IOMMU Initialization State Machine
1805 ****************************************************************************/
1807 static int __init state_next(void)
1811 switch (init_state) {
1812 case IOMMU_START_STATE:
1813 if (!detect_ivrs()) {
1814 init_state = IOMMU_NOT_FOUND;
1817 init_state = IOMMU_IVRS_DETECTED;
1820 case IOMMU_IVRS_DETECTED:
1821 ret = early_amd_iommu_init();
1822 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
1824 case IOMMU_ACPI_FINISHED:
1825 early_enable_iommus();
1826 register_syscore_ops(&amd_iommu_syscore_ops);
1827 x86_platform.iommu_shutdown = disable_iommus;
1828 init_state = IOMMU_ENABLED;
1831 ret = amd_iommu_init_pci();
1832 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
1835 case IOMMU_PCI_INIT:
1836 ret = amd_iommu_enable_interrupts();
1837 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
1839 case IOMMU_INTERRUPTS_EN:
1840 ret = amd_iommu_init_dma();
1841 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
1844 init_state = IOMMU_INITIALIZED;
1846 case IOMMU_INITIALIZED:
1849 case IOMMU_NOT_FOUND:
1850 case IOMMU_INIT_ERROR:
1851 /* Error states => do nothing */
1862 static int __init iommu_go_to_state(enum iommu_init_state state)
1866 while (init_state != state) {
1868 if (init_state == IOMMU_NOT_FOUND ||
1869 init_state == IOMMU_INIT_ERROR)
1879 * This is the core init function for AMD IOMMU hardware in the system.
1880 * This function is called from the generic x86 DMA layer initialization
1883 static int __init amd_iommu_init(void)
1887 ret = iommu_go_to_state(IOMMU_INITIALIZED);
1890 free_on_init_error();
1896 /****************************************************************************
1898 * Early detect code. This code runs at IOMMU detection time in the DMA
1899 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1902 ****************************************************************************/
1903 int __init amd_iommu_detect(void)
1907 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
1910 if (amd_iommu_disabled)
1913 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
1917 amd_iommu_detected = true;
1919 x86_init.iommu.iommu_init = amd_iommu_init;
1924 /****************************************************************************
1926 * Parsing functions for the AMD IOMMU specific kernel command line
1929 ****************************************************************************/
1931 static int __init parse_amd_iommu_dump(char *str)
1933 amd_iommu_dump = true;
1938 static int __init parse_amd_iommu_options(char *str)
1940 for (; *str; ++str) {
1941 if (strncmp(str, "fullflush", 9) == 0)
1942 amd_iommu_unmap_flush = true;
1943 if (strncmp(str, "off", 3) == 0)
1944 amd_iommu_disabled = true;
1945 if (strncmp(str, "force_isolation", 15) == 0)
1946 amd_iommu_force_isolation = true;
1952 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1953 __setup("amd_iommu=", parse_amd_iommu_options);
1955 IOMMU_INIT_FINISH(amd_iommu_detect,
1956 gart_iommu_hole_init,
1960 bool amd_iommu_v2_supported(void)
1962 return amd_iommu_v2_present;
1964 EXPORT_SYMBOL(amd_iommu_v2_supported);