2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <linux/amd-iommu.h>
28 #include <linux/export.h>
29 #include <linux/acpi.h>
30 #include <acpi/acpi.h>
31 #include <asm/pci-direct.h>
32 #include <asm/iommu.h>
34 #include <asm/x86_init.h>
35 #include <asm/iommu_table.h>
37 #include "amd_iommu_proto.h"
38 #include "amd_iommu_types.h"
41 * definitions for the ACPI scanning code
43 #define IVRS_HEADER_LENGTH 48
45 #define ACPI_IVHD_TYPE 0x10
46 #define ACPI_IVMD_TYPE_ALL 0x20
47 #define ACPI_IVMD_TYPE 0x21
48 #define ACPI_IVMD_TYPE_RANGE 0x22
50 #define IVHD_DEV_ALL 0x01
51 #define IVHD_DEV_SELECT 0x02
52 #define IVHD_DEV_SELECT_RANGE_START 0x03
53 #define IVHD_DEV_RANGE_END 0x04
54 #define IVHD_DEV_ALIAS 0x42
55 #define IVHD_DEV_ALIAS_RANGE 0x43
56 #define IVHD_DEV_EXT_SELECT 0x46
57 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
59 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
60 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
61 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
62 #define IVHD_FLAG_ISOC_EN_MASK 0x08
64 #define IVMD_FLAG_EXCL_RANGE 0x08
65 #define IVMD_FLAG_UNITY_MAP 0x01
67 #define ACPI_DEVFLAG_INITPASS 0x01
68 #define ACPI_DEVFLAG_EXTINT 0x02
69 #define ACPI_DEVFLAG_NMI 0x04
70 #define ACPI_DEVFLAG_SYSMGT1 0x10
71 #define ACPI_DEVFLAG_SYSMGT2 0x20
72 #define ACPI_DEVFLAG_LINT0 0x40
73 #define ACPI_DEVFLAG_LINT1 0x80
74 #define ACPI_DEVFLAG_ATSDIS 0x10000000
77 * ACPI table definitions
79 * These data structures are laid over the table to parse the important values
84 * structure describing one IOMMU in the ACPI table. Typically followed by one
85 * or more ivhd_entrys.
97 } __attribute__((packed));
100 * A device entry describing which devices a specific IOMMU translates and
101 * which requestor ids they use.
108 } __attribute__((packed));
111 * An AMD IOMMU memory definition structure. It defines things like exclusion
112 * ranges for devices and regions that should be unity mapped.
123 } __attribute__((packed));
127 static bool amd_iommu_detected;
128 static bool __initdata amd_iommu_disabled;
130 u16 amd_iommu_last_bdf; /* largest PCI device id we have
132 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
134 u32 amd_iommu_unmap_flush; /* if true, flush on every unmap */
136 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
139 /* Array to assign indices to IOMMUs*/
140 struct amd_iommu *amd_iommus[MAX_IOMMUS];
141 int amd_iommus_present;
143 /* IOMMUs have a non-present cache? */
144 bool amd_iommu_np_cache __read_mostly;
145 bool amd_iommu_iotlb_sup __read_mostly = true;
147 u32 amd_iommu_max_pasids __read_mostly = ~0;
149 bool amd_iommu_v2_present __read_mostly;
151 bool amd_iommu_force_isolation __read_mostly;
154 * List of protection domains - used during resume
156 LIST_HEAD(amd_iommu_pd_list);
157 spinlock_t amd_iommu_pd_lock;
160 * Pointer to the device table which is shared by all AMD IOMMUs
161 * it is indexed by the PCI device id or the HT unit id and contains
162 * information about the domain the device belongs to as well as the
163 * page table root pointer.
165 struct dev_table_entry *amd_iommu_dev_table;
168 * The alias table is a driver specific data structure which contains the
169 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
170 * More than one device can share the same requestor id.
172 u16 *amd_iommu_alias_table;
175 * The rlookup table is used to find the IOMMU which is responsible
176 * for a specific device. It is also indexed by the PCI device id.
178 struct amd_iommu **amd_iommu_rlookup_table;
181 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
182 * to know which ones are already in use.
184 unsigned long *amd_iommu_pd_alloc_bitmap;
186 static u32 dev_table_size; /* size of the device table */
187 static u32 alias_table_size; /* size of the alias table */
188 static u32 rlookup_table_size; /* size if the rlookup table */
190 static int amd_iommu_enable_interrupts(void);
192 static inline void update_last_devid(u16 devid)
194 if (devid > amd_iommu_last_bdf)
195 amd_iommu_last_bdf = devid;
198 static inline unsigned long tbl_size(int entry_size)
200 unsigned shift = PAGE_SHIFT +
201 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
206 /* Access to l1 and l2 indexed register spaces */
208 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
212 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
213 pci_read_config_dword(iommu->dev, 0xfc, &val);
217 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
219 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
220 pci_write_config_dword(iommu->dev, 0xfc, val);
221 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
224 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
228 pci_write_config_dword(iommu->dev, 0xf0, address);
229 pci_read_config_dword(iommu->dev, 0xf4, &val);
233 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
235 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
236 pci_write_config_dword(iommu->dev, 0xf4, val);
239 /****************************************************************************
241 * AMD IOMMU MMIO register space handling functions
243 * These functions are used to program the IOMMU device registers in
244 * MMIO space required for that driver.
246 ****************************************************************************/
249 * This function set the exclusion range in the IOMMU. DMA accesses to the
250 * exclusion range are passed through untranslated
252 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
254 u64 start = iommu->exclusion_start & PAGE_MASK;
255 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
258 if (!iommu->exclusion_start)
261 entry = start | MMIO_EXCL_ENABLE_MASK;
262 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
263 &entry, sizeof(entry));
266 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
267 &entry, sizeof(entry));
270 /* Programs the physical address of the device table into the IOMMU hardware */
271 static void iommu_set_device_table(struct amd_iommu *iommu)
275 BUG_ON(iommu->mmio_base == NULL);
277 entry = virt_to_phys(amd_iommu_dev_table);
278 entry |= (dev_table_size >> 12) - 1;
279 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
280 &entry, sizeof(entry));
283 /* Generic functions to enable/disable certain features of the IOMMU. */
284 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
288 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
290 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
293 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
297 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
299 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
302 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
306 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
307 ctrl &= ~CTRL_INV_TO_MASK;
308 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
309 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
312 /* Function to enable the hardware */
313 static void iommu_enable(struct amd_iommu *iommu)
315 static const char * const feat_str[] = {
316 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
317 "IA", "GA", "HE", "PC", NULL
321 printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx",
322 dev_name(&iommu->dev->dev), iommu->cap_ptr);
324 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
325 printk(KERN_CONT " extended features: ");
326 for (i = 0; feat_str[i]; ++i)
327 if (iommu_feature(iommu, (1ULL << i)))
328 printk(KERN_CONT " %s", feat_str[i]);
330 printk(KERN_CONT "\n");
332 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
335 static void iommu_disable(struct amd_iommu *iommu)
337 /* Disable command buffer */
338 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
340 /* Disable event logging and event interrupts */
341 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
342 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
344 /* Disable IOMMU hardware itself */
345 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
349 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
350 * the system has one.
352 static u8 __iomem * __init iommu_map_mmio_space(u64 address)
354 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
355 pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
357 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
361 return (u8 __iomem *)ioremap_nocache(address, MMIO_REGION_LENGTH);
364 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
366 if (iommu->mmio_base)
367 iounmap(iommu->mmio_base);
368 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
371 /****************************************************************************
373 * The functions below belong to the first pass of AMD IOMMU ACPI table
374 * parsing. In this pass we try to find out the highest device id this
375 * code has to handle. Upon this information the size of the shared data
376 * structures is determined later.
378 ****************************************************************************/
381 * This function calculates the length of a given IVHD entry
383 static inline int ivhd_entry_length(u8 *ivhd)
385 return 0x04 << (*ivhd >> 6);
389 * This function reads the last device id the IOMMU has to handle from the PCI
390 * capability header for this IOMMU
392 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
396 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
397 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
403 * After reading the highest device id from the IOMMU PCI capability header
404 * this function looks if there is a higher device id defined in the ACPI table
406 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
408 u8 *p = (void *)h, *end = (void *)h;
409 struct ivhd_entry *dev;
414 find_last_devid_on_pci(PCI_BUS(h->devid),
420 dev = (struct ivhd_entry *)p;
422 case IVHD_DEV_SELECT:
423 case IVHD_DEV_RANGE_END:
425 case IVHD_DEV_EXT_SELECT:
426 /* all the above subfield types refer to device ids */
427 update_last_devid(dev->devid);
432 p += ivhd_entry_length(p);
441 * Iterate over all IVHD entries in the ACPI table and find the highest device
442 * id which we need to handle. This is the first of three functions which parse
443 * the ACPI table. So we check the checksum here.
445 static int __init find_last_devid_acpi(struct acpi_table_header *table)
448 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
449 struct ivhd_header *h;
452 * Validate checksum here so we don't need to do it when
453 * we actually parse the table
455 for (i = 0; i < table->length; ++i)
458 /* ACPI table corrupt */
461 p += IVRS_HEADER_LENGTH;
463 end += table->length;
465 h = (struct ivhd_header *)p;
468 find_last_devid_from_ivhd(h);
480 /****************************************************************************
482 * The following functions belong the the code path which parses the ACPI table
483 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
484 * data structures, initialize the device/alias/rlookup table and also
485 * basically initialize the hardware.
487 ****************************************************************************/
490 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
491 * write commands to that buffer later and the IOMMU will execute them
494 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
496 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
497 get_order(CMD_BUFFER_SIZE));
502 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
508 * This function resets the command buffer if the IOMMU stopped fetching
511 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
513 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
515 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
516 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
518 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
522 * This function writes the command buffer address to the hardware and
525 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
529 BUG_ON(iommu->cmd_buf == NULL);
531 entry = (u64)virt_to_phys(iommu->cmd_buf);
532 entry |= MMIO_CMD_SIZE_512;
534 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
535 &entry, sizeof(entry));
537 amd_iommu_reset_cmd_buffer(iommu);
538 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
541 static void __init free_command_buffer(struct amd_iommu *iommu)
543 free_pages((unsigned long)iommu->cmd_buf,
544 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
547 /* allocates the memory where the IOMMU will log its events to */
548 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
550 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
551 get_order(EVT_BUFFER_SIZE));
553 if (iommu->evt_buf == NULL)
556 iommu->evt_buf_size = EVT_BUFFER_SIZE;
558 return iommu->evt_buf;
561 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
565 BUG_ON(iommu->evt_buf == NULL);
567 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
569 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
570 &entry, sizeof(entry));
572 /* set head and tail to zero manually */
573 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
574 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
576 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
579 static void __init free_event_buffer(struct amd_iommu *iommu)
581 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
584 /* allocates the memory where the IOMMU will log its events to */
585 static u8 * __init alloc_ppr_log(struct amd_iommu *iommu)
587 iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
588 get_order(PPR_LOG_SIZE));
590 if (iommu->ppr_log == NULL)
593 return iommu->ppr_log;
596 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
600 if (iommu->ppr_log == NULL)
603 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
605 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
606 &entry, sizeof(entry));
608 /* set head and tail to zero manually */
609 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
610 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
612 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
613 iommu_feature_enable(iommu, CONTROL_PPR_EN);
616 static void __init free_ppr_log(struct amd_iommu *iommu)
618 if (iommu->ppr_log == NULL)
621 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
624 static void iommu_enable_gt(struct amd_iommu *iommu)
626 if (!iommu_feature(iommu, FEATURE_GT))
629 iommu_feature_enable(iommu, CONTROL_GT_EN);
632 /* sets a specific bit in the device table entry. */
633 static void set_dev_entry_bit(u16 devid, u8 bit)
635 int i = (bit >> 6) & 0x03;
636 int _bit = bit & 0x3f;
638 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
641 static int get_dev_entry_bit(u16 devid, u8 bit)
643 int i = (bit >> 6) & 0x03;
644 int _bit = bit & 0x3f;
646 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
650 void amd_iommu_apply_erratum_63(u16 devid)
654 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
655 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
658 set_dev_entry_bit(devid, DEV_ENTRY_IW);
661 /* Writes the specific IOMMU for a device into the rlookup table */
662 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
664 amd_iommu_rlookup_table[devid] = iommu;
668 * This function takes the device specific flags read from the ACPI
669 * table and sets up the device table entry with that information
671 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
672 u16 devid, u32 flags, u32 ext_flags)
674 if (flags & ACPI_DEVFLAG_INITPASS)
675 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
676 if (flags & ACPI_DEVFLAG_EXTINT)
677 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
678 if (flags & ACPI_DEVFLAG_NMI)
679 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
680 if (flags & ACPI_DEVFLAG_SYSMGT1)
681 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
682 if (flags & ACPI_DEVFLAG_SYSMGT2)
683 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
684 if (flags & ACPI_DEVFLAG_LINT0)
685 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
686 if (flags & ACPI_DEVFLAG_LINT1)
687 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
689 amd_iommu_apply_erratum_63(devid);
691 set_iommu_for_device(iommu, devid);
695 * Reads the device exclusion range from ACPI and initialize IOMMU with
698 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
700 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
702 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
707 * We only can configure exclusion ranges per IOMMU, not
708 * per device. But we can enable the exclusion range per
709 * device. This is done here
711 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
712 iommu->exclusion_start = m->range_start;
713 iommu->exclusion_length = m->range_length;
718 * This function reads some important data from the IOMMU PCI space and
719 * initializes the driver data structure with it. It reads the hardware
720 * capabilities and the first/last device entries
722 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
724 int cap_ptr = iommu->cap_ptr;
725 u32 range, misc, low, high;
728 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
730 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
732 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
735 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
737 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
739 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
741 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
742 amd_iommu_iotlb_sup = false;
744 /* read extended feature bits */
745 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
746 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
748 iommu->features = ((u64)high << 32) | low;
750 if (iommu_feature(iommu, FEATURE_GT)) {
755 shift = iommu->features & FEATURE_PASID_MASK;
756 shift >>= FEATURE_PASID_SHIFT;
757 pasids = (1 << shift);
759 amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids);
761 glxval = iommu->features & FEATURE_GLXVAL_MASK;
762 glxval >>= FEATURE_GLXVAL_SHIFT;
764 if (amd_iommu_max_glx_val == -1)
765 amd_iommu_max_glx_val = glxval;
767 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
770 if (iommu_feature(iommu, FEATURE_GT) &&
771 iommu_feature(iommu, FEATURE_PPR)) {
772 iommu->is_iommu_v2 = true;
773 amd_iommu_v2_present = true;
776 if (!is_rd890_iommu(iommu->dev))
780 * Some rd890 systems may not be fully reconfigured by the BIOS, so
781 * it's necessary for us to store this information so it can be
782 * reprogrammed on resume
785 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
786 &iommu->stored_addr_lo);
787 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
788 &iommu->stored_addr_hi);
790 /* Low bit locks writes to configuration space */
791 iommu->stored_addr_lo &= ~1;
793 for (i = 0; i < 6; i++)
794 for (j = 0; j < 0x12; j++)
795 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
797 for (i = 0; i < 0x83; i++)
798 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
802 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
803 * initializes the hardware and our data structures with it.
805 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
806 struct ivhd_header *h)
809 u8 *end = p, flags = 0;
810 u16 devid = 0, devid_start = 0, devid_to = 0;
811 u32 dev_i, ext_flags = 0;
813 struct ivhd_entry *e;
816 * First save the recommended feature enable bits from ACPI
818 iommu->acpi_flags = h->flags;
821 * Done. Now parse the device entries
823 p += sizeof(struct ivhd_header);
828 e = (struct ivhd_entry *)p;
832 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
833 " last device %02x:%02x.%x flags: %02x\n",
834 PCI_BUS(iommu->first_device),
835 PCI_SLOT(iommu->first_device),
836 PCI_FUNC(iommu->first_device),
837 PCI_BUS(iommu->last_device),
838 PCI_SLOT(iommu->last_device),
839 PCI_FUNC(iommu->last_device),
842 for (dev_i = iommu->first_device;
843 dev_i <= iommu->last_device; ++dev_i)
844 set_dev_entry_from_acpi(iommu, dev_i,
847 case IVHD_DEV_SELECT:
849 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
857 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
859 case IVHD_DEV_SELECT_RANGE_START:
861 DUMP_printk(" DEV_SELECT_RANGE_START\t "
862 "devid: %02x:%02x.%x flags: %02x\n",
868 devid_start = e->devid;
875 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
876 "flags: %02x devid_to: %02x:%02x.%x\n",
881 PCI_BUS(e->ext >> 8),
882 PCI_SLOT(e->ext >> 8),
883 PCI_FUNC(e->ext >> 8));
886 devid_to = e->ext >> 8;
887 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
888 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
889 amd_iommu_alias_table[devid] = devid_to;
891 case IVHD_DEV_ALIAS_RANGE:
893 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
894 "devid: %02x:%02x.%x flags: %02x "
895 "devid_to: %02x:%02x.%x\n",
900 PCI_BUS(e->ext >> 8),
901 PCI_SLOT(e->ext >> 8),
902 PCI_FUNC(e->ext >> 8));
904 devid_start = e->devid;
906 devid_to = e->ext >> 8;
910 case IVHD_DEV_EXT_SELECT:
912 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
913 "flags: %02x ext: %08x\n",
920 set_dev_entry_from_acpi(iommu, devid, e->flags,
923 case IVHD_DEV_EXT_SELECT_RANGE:
925 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
926 "%02x:%02x.%x flags: %02x ext: %08x\n",
932 devid_start = e->devid;
937 case IVHD_DEV_RANGE_END:
939 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
945 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
947 amd_iommu_alias_table[dev_i] = devid_to;
948 set_dev_entry_from_acpi(iommu,
949 devid_to, flags, ext_flags);
951 set_dev_entry_from_acpi(iommu, dev_i,
959 p += ivhd_entry_length(p);
963 /* Initializes the device->iommu mapping for the driver */
964 static int __init init_iommu_devices(struct amd_iommu *iommu)
968 for (i = iommu->first_device; i <= iommu->last_device; ++i)
969 set_iommu_for_device(iommu, i);
974 static void __init free_iommu_one(struct amd_iommu *iommu)
976 free_command_buffer(iommu);
977 free_event_buffer(iommu);
979 iommu_unmap_mmio_space(iommu);
982 static void __init free_iommu_all(void)
984 struct amd_iommu *iommu, *next;
986 for_each_iommu_safe(iommu, next) {
987 list_del(&iommu->list);
988 free_iommu_one(iommu);
994 * This function clues the initialization function for one IOMMU
995 * together and also allocates the command buffer and programs the
996 * hardware. It does NOT enable the IOMMU. This is done afterwards.
998 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1000 spin_lock_init(&iommu->lock);
1002 /* Add IOMMU to internal data structures */
1003 list_add_tail(&iommu->list, &amd_iommu_list);
1004 iommu->index = amd_iommus_present++;
1006 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1007 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1011 /* Index is fine - add IOMMU to the array */
1012 amd_iommus[iommu->index] = iommu;
1015 * Copy data from ACPI table entry to the iommu struct
1017 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
1021 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1024 iommu->cap_ptr = h->cap_ptr;
1025 iommu->pci_seg = h->pci_seg;
1026 iommu->mmio_phys = h->mmio_phys;
1027 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
1028 if (!iommu->mmio_base)
1031 iommu->cmd_buf = alloc_command_buffer(iommu);
1032 if (!iommu->cmd_buf)
1035 iommu->evt_buf = alloc_event_buffer(iommu);
1036 if (!iommu->evt_buf)
1039 iommu->int_enabled = false;
1041 init_iommu_from_pci(iommu);
1042 init_iommu_from_acpi(iommu, h);
1043 init_iommu_devices(iommu);
1045 if (iommu_feature(iommu, FEATURE_PPR)) {
1046 iommu->ppr_log = alloc_ppr_log(iommu);
1047 if (!iommu->ppr_log)
1051 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1052 amd_iommu_np_cache = true;
1054 return pci_enable_device(iommu->dev);
1058 * Iterates over all IOMMU entries in the ACPI table, allocates the
1059 * IOMMU structure and initializes it with init_iommu_one()
1061 static int __init init_iommu_all(struct acpi_table_header *table)
1063 u8 *p = (u8 *)table, *end = (u8 *)table;
1064 struct ivhd_header *h;
1065 struct amd_iommu *iommu;
1068 end += table->length;
1069 p += IVRS_HEADER_LENGTH;
1072 h = (struct ivhd_header *)p;
1074 case ACPI_IVHD_TYPE:
1076 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1077 "seg: %d flags: %01x info %04x\n",
1078 PCI_BUS(h->devid), PCI_SLOT(h->devid),
1079 PCI_FUNC(h->devid), h->cap_ptr,
1080 h->pci_seg, h->flags, h->info);
1081 DUMP_printk(" mmio-addr: %016llx\n",
1084 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1088 ret = init_iommu_one(iommu, h);
1103 /****************************************************************************
1105 * The following functions initialize the MSI interrupts for all IOMMUs
1106 * in the system. Its a bit challenging because there could be multiple
1107 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1110 ****************************************************************************/
1112 static int iommu_setup_msi(struct amd_iommu *iommu)
1116 r = pci_enable_msi(iommu->dev);
1120 r = request_threaded_irq(iommu->dev->irq,
1121 amd_iommu_int_handler,
1122 amd_iommu_int_thread,
1127 pci_disable_msi(iommu->dev);
1131 iommu->int_enabled = true;
1136 static int iommu_init_msi(struct amd_iommu *iommu)
1140 if (iommu->int_enabled)
1143 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
1144 ret = iommu_setup_msi(iommu);
1152 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1154 if (iommu->ppr_log != NULL)
1155 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1160 /****************************************************************************
1162 * The next functions belong to the third pass of parsing the ACPI
1163 * table. In this last pass the memory mapping requirements are
1164 * gathered (like exclusion and unity mapping reanges).
1166 ****************************************************************************/
1168 static void __init free_unity_maps(void)
1170 struct unity_map_entry *entry, *next;
1172 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1173 list_del(&entry->list);
1178 /* called when we find an exclusion range definition in ACPI */
1179 static int __init init_exclusion_range(struct ivmd_header *m)
1184 case ACPI_IVMD_TYPE:
1185 set_device_exclusion_range(m->devid, m);
1187 case ACPI_IVMD_TYPE_ALL:
1188 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1189 set_device_exclusion_range(i, m);
1191 case ACPI_IVMD_TYPE_RANGE:
1192 for (i = m->devid; i <= m->aux; ++i)
1193 set_device_exclusion_range(i, m);
1202 /* called for unity map ACPI definition */
1203 static int __init init_unity_map_range(struct ivmd_header *m)
1205 struct unity_map_entry *e = NULL;
1208 e = kzalloc(sizeof(*e), GFP_KERNEL);
1216 case ACPI_IVMD_TYPE:
1217 s = "IVMD_TYPEi\t\t\t";
1218 e->devid_start = e->devid_end = m->devid;
1220 case ACPI_IVMD_TYPE_ALL:
1221 s = "IVMD_TYPE_ALL\t\t";
1223 e->devid_end = amd_iommu_last_bdf;
1225 case ACPI_IVMD_TYPE_RANGE:
1226 s = "IVMD_TYPE_RANGE\t\t";
1227 e->devid_start = m->devid;
1228 e->devid_end = m->aux;
1231 e->address_start = PAGE_ALIGN(m->range_start);
1232 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1233 e->prot = m->flags >> 1;
1235 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1236 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1237 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1238 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1239 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1240 e->address_start, e->address_end, m->flags);
1242 list_add_tail(&e->list, &amd_iommu_unity_map);
1247 /* iterates over all memory definitions we find in the ACPI table */
1248 static int __init init_memory_definitions(struct acpi_table_header *table)
1250 u8 *p = (u8 *)table, *end = (u8 *)table;
1251 struct ivmd_header *m;
1253 end += table->length;
1254 p += IVRS_HEADER_LENGTH;
1257 m = (struct ivmd_header *)p;
1258 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1259 init_exclusion_range(m);
1260 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1261 init_unity_map_range(m);
1270 * Init the device table to not allow DMA access for devices and
1271 * suppress all page faults
1273 static void init_device_table(void)
1277 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1278 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1279 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1283 static void iommu_init_flags(struct amd_iommu *iommu)
1285 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1286 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1287 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1289 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1290 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1291 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1293 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1294 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1295 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1297 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1298 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1299 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1302 * make IOMMU memory accesses cache coherent
1304 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1306 /* Set IOTLB invalidation timeout to 1s */
1307 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1310 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1313 u32 ioc_feature_control;
1314 struct pci_dev *pdev = iommu->root_pdev;
1316 /* RD890 BIOSes may not have completely reconfigured the iommu */
1317 if (!is_rd890_iommu(iommu->dev) || !pdev)
1321 * First, we need to ensure that the iommu is enabled. This is
1322 * controlled by a register in the northbridge
1325 /* Select Northbridge indirect register 0x75 and enable writing */
1326 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1327 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1329 /* Enable the iommu */
1330 if (!(ioc_feature_control & 0x1))
1331 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1333 /* Restore the iommu BAR */
1334 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1335 iommu->stored_addr_lo);
1336 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1337 iommu->stored_addr_hi);
1339 /* Restore the l1 indirect regs for each of the 6 l1s */
1340 for (i = 0; i < 6; i++)
1341 for (j = 0; j < 0x12; j++)
1342 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1344 /* Restore the l2 indirect regs */
1345 for (i = 0; i < 0x83; i++)
1346 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1348 /* Lock PCI setup registers */
1349 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1350 iommu->stored_addr_lo | 1);
1354 * This function finally enables all IOMMUs found in the system after
1355 * they have been initialized
1357 static void enable_iommus(void)
1359 struct amd_iommu *iommu;
1361 for_each_iommu(iommu) {
1362 iommu_disable(iommu);
1363 iommu_init_flags(iommu);
1364 iommu_set_device_table(iommu);
1365 iommu_enable_command_buffer(iommu);
1366 iommu_enable_event_buffer(iommu);
1367 iommu_enable_ppr_log(iommu);
1368 iommu_enable_gt(iommu);
1369 iommu_set_exclusion_range(iommu);
1370 iommu_enable(iommu);
1371 iommu_flush_all_caches(iommu);
1375 static void disable_iommus(void)
1377 struct amd_iommu *iommu;
1379 for_each_iommu(iommu)
1380 iommu_disable(iommu);
1384 * Suspend/Resume support
1385 * disable suspend until real resume implemented
1388 static void amd_iommu_resume(void)
1390 struct amd_iommu *iommu;
1392 for_each_iommu(iommu)
1393 iommu_apply_resume_quirks(iommu);
1395 /* re-load the hardware */
1398 amd_iommu_enable_interrupts();
1401 static int amd_iommu_suspend(void)
1403 /* disable IOMMUs to go out of the way for BIOS */
1409 static struct syscore_ops amd_iommu_syscore_ops = {
1410 .suspend = amd_iommu_suspend,
1411 .resume = amd_iommu_resume,
1414 static void __init free_on_init_error(void)
1416 amd_iommu_uninit_devices();
1418 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1419 get_order(MAX_DOMAIN_ID/8));
1421 free_pages((unsigned long)amd_iommu_rlookup_table,
1422 get_order(rlookup_table_size));
1424 free_pages((unsigned long)amd_iommu_alias_table,
1425 get_order(alias_table_size));
1427 free_pages((unsigned long)amd_iommu_dev_table,
1428 get_order(dev_table_size));
1434 #ifdef CONFIG_GART_IOMMU
1436 * We failed to initialize the AMD IOMMU - try fallback to GART
1445 * This is the hardware init function for AMD IOMMU in the system.
1446 * This function is called either from amd_iommu_init or from the interrupt
1447 * remapping setup code.
1449 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1452 * 1 pass) Find the highest PCI device id the driver has to handle.
1453 * Upon this information the size of the data structures is
1454 * determined that needs to be allocated.
1456 * 2 pass) Initialize the data structures just allocated with the
1457 * information in the ACPI table about available AMD IOMMUs
1458 * in the system. It also maps the PCI devices in the
1459 * system to specific IOMMUs
1461 * 3 pass) After the basic data structures are allocated and
1462 * initialized we update them with information about memory
1463 * remapping requirements parsed out of the ACPI table in
1466 * After everything is set up the IOMMUs are enabled and the necessary
1467 * hotplug and suspend notifiers are registered.
1469 int __init amd_iommu_init_hardware(void)
1471 struct acpi_table_header *ivrs_base;
1472 acpi_size ivrs_size;
1476 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
1479 if (amd_iommu_disabled || !amd_iommu_detected)
1482 if (amd_iommu_dev_table != NULL) {
1483 /* Hardware already initialized */
1487 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1488 if (status == AE_NOT_FOUND)
1490 else if (ACPI_FAILURE(status)) {
1491 const char *err = acpi_format_exception(status);
1492 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1497 * First parse ACPI tables to find the largest Bus/Dev/Func
1498 * we need to handle. Upon this information the shared data
1499 * structures for the IOMMUs in the system will be allocated
1501 if (find_last_devid_acpi(ivrs_base))
1504 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1505 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1506 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1508 /* Device table - directly used by all IOMMUs */
1510 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1511 get_order(dev_table_size));
1512 if (amd_iommu_dev_table == NULL)
1516 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1517 * IOMMU see for that device
1519 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1520 get_order(alias_table_size));
1521 if (amd_iommu_alias_table == NULL)
1524 /* IOMMU rlookup table - find the IOMMU for a specific device */
1525 amd_iommu_rlookup_table = (void *)__get_free_pages(
1526 GFP_KERNEL | __GFP_ZERO,
1527 get_order(rlookup_table_size));
1528 if (amd_iommu_rlookup_table == NULL)
1531 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1532 GFP_KERNEL | __GFP_ZERO,
1533 get_order(MAX_DOMAIN_ID/8));
1534 if (amd_iommu_pd_alloc_bitmap == NULL)
1537 /* init the device table */
1538 init_device_table();
1541 * let all alias entries point to itself
1543 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1544 amd_iommu_alias_table[i] = i;
1547 * never allocate domain 0 because its used as the non-allocated and
1548 * error value placeholder
1550 amd_iommu_pd_alloc_bitmap[0] = 1;
1552 spin_lock_init(&amd_iommu_pd_lock);
1555 * now the data structures are allocated and basically initialized
1556 * start the real acpi table scan
1558 ret = init_iommu_all(ivrs_base);
1562 ret = init_memory_definitions(ivrs_base);
1566 ret = amd_iommu_init_devices();
1572 amd_iommu_init_notifier();
1574 register_syscore_ops(&amd_iommu_syscore_ops);
1577 /* Don't leak any ACPI memory */
1578 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1584 free_on_init_error();
1589 static int amd_iommu_enable_interrupts(void)
1591 struct amd_iommu *iommu;
1594 for_each_iommu(iommu) {
1595 ret = iommu_init_msi(iommu);
1604 static bool detect_ivrs(void)
1606 struct acpi_table_header *ivrs_base;
1607 acpi_size ivrs_size;
1610 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1611 if (status == AE_NOT_FOUND)
1613 else if (ACPI_FAILURE(status)) {
1614 const char *err = acpi_format_exception(status);
1615 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1619 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1625 * This is the core init function for AMD IOMMU hardware in the system.
1626 * This function is called from the generic x86 DMA layer initialization
1629 * The function calls amd_iommu_init_hardware() to setup and enable the
1630 * IOMMU hardware if this has not happened yet. After that the driver
1631 * registers for the DMA-API and for the IOMMU-API as necessary.
1633 static int __init amd_iommu_init(void)
1637 ret = amd_iommu_init_hardware();
1641 ret = amd_iommu_enable_interrupts();
1645 if (iommu_pass_through)
1646 ret = amd_iommu_init_passthrough();
1648 ret = amd_iommu_init_dma_ops();
1653 amd_iommu_init_api();
1655 x86_platform.iommu_shutdown = disable_iommus;
1657 if (iommu_pass_through)
1660 if (amd_iommu_unmap_flush)
1661 printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
1663 printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
1671 free_on_init_error();
1676 /****************************************************************************
1678 * Early detect code. This code runs at IOMMU detection time in the DMA
1679 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1682 ****************************************************************************/
1683 int __init amd_iommu_detect(void)
1686 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
1689 if (amd_iommu_disabled)
1695 amd_iommu_detected = true;
1697 x86_init.iommu.iommu_init = amd_iommu_init;
1699 /* Make sure ACS will be enabled */
1705 /****************************************************************************
1707 * Parsing functions for the AMD IOMMU specific kernel command line
1710 ****************************************************************************/
1712 static int __init parse_amd_iommu_dump(char *str)
1714 amd_iommu_dump = true;
1719 static int __init parse_amd_iommu_options(char *str)
1721 for (; *str; ++str) {
1722 if (strncmp(str, "fullflush", 9) == 0)
1723 amd_iommu_unmap_flush = true;
1724 if (strncmp(str, "off", 3) == 0)
1725 amd_iommu_disabled = true;
1726 if (strncmp(str, "force_isolation", 15) == 0)
1727 amd_iommu_force_isolation = true;
1733 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1734 __setup("amd_iommu=", parse_amd_iommu_options);
1736 IOMMU_INIT_FINISH(amd_iommu_detect,
1737 gart_iommu_hole_init,
1741 bool amd_iommu_v2_supported(void)
1743 return amd_iommu_v2_present;
1745 EXPORT_SYMBOL(amd_iommu_v2_supported);