2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <linux/amd-iommu.h>
28 #include <linux/export.h>
29 #include <asm/pci-direct.h>
30 #include <asm/iommu.h>
32 #include <asm/x86_init.h>
33 #include <asm/iommu_table.h>
35 #include "amd_iommu_proto.h"
36 #include "amd_iommu_types.h"
39 * definitions for the ACPI scanning code
41 #define IVRS_HEADER_LENGTH 48
43 #define ACPI_IVHD_TYPE 0x10
44 #define ACPI_IVMD_TYPE_ALL 0x20
45 #define ACPI_IVMD_TYPE 0x21
46 #define ACPI_IVMD_TYPE_RANGE 0x22
48 #define IVHD_DEV_ALL 0x01
49 #define IVHD_DEV_SELECT 0x02
50 #define IVHD_DEV_SELECT_RANGE_START 0x03
51 #define IVHD_DEV_RANGE_END 0x04
52 #define IVHD_DEV_ALIAS 0x42
53 #define IVHD_DEV_ALIAS_RANGE 0x43
54 #define IVHD_DEV_EXT_SELECT 0x46
55 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
57 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
58 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
59 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
60 #define IVHD_FLAG_ISOC_EN_MASK 0x08
62 #define IVMD_FLAG_EXCL_RANGE 0x08
63 #define IVMD_FLAG_UNITY_MAP 0x01
65 #define ACPI_DEVFLAG_INITPASS 0x01
66 #define ACPI_DEVFLAG_EXTINT 0x02
67 #define ACPI_DEVFLAG_NMI 0x04
68 #define ACPI_DEVFLAG_SYSMGT1 0x10
69 #define ACPI_DEVFLAG_SYSMGT2 0x20
70 #define ACPI_DEVFLAG_LINT0 0x40
71 #define ACPI_DEVFLAG_LINT1 0x80
72 #define ACPI_DEVFLAG_ATSDIS 0x10000000
75 * ACPI table definitions
77 * These data structures are laid over the table to parse the important values
82 * structure describing one IOMMU in the ACPI table. Typically followed by one
83 * or more ivhd_entrys.
95 } __attribute__((packed));
98 * A device entry describing which devices a specific IOMMU translates and
99 * which requestor ids they use.
106 } __attribute__((packed));
109 * An AMD IOMMU memory definition structure. It defines things like exclusion
110 * ranges for devices and regions that should be unity mapped.
121 } __attribute__((packed));
125 static int __initdata amd_iommu_detected;
126 static bool __initdata amd_iommu_disabled;
128 u16 amd_iommu_last_bdf; /* largest PCI device id we have
130 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
132 u32 amd_iommu_unmap_flush; /* if true, flush on every unmap */
134 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
137 /* Array to assign indices to IOMMUs*/
138 struct amd_iommu *amd_iommus[MAX_IOMMUS];
139 int amd_iommus_present;
141 /* IOMMUs have a non-present cache? */
142 bool amd_iommu_np_cache __read_mostly;
143 bool amd_iommu_iotlb_sup __read_mostly = true;
145 u32 amd_iommu_max_pasids __read_mostly = ~0;
147 bool amd_iommu_v2_present __read_mostly;
149 bool amd_iommu_force_isolation __read_mostly;
152 * The ACPI table parsing functions set this variable on an error
154 static int __initdata amd_iommu_init_err;
157 * List of protection domains - used during resume
159 LIST_HEAD(amd_iommu_pd_list);
160 spinlock_t amd_iommu_pd_lock;
163 * Pointer to the device table which is shared by all AMD IOMMUs
164 * it is indexed by the PCI device id or the HT unit id and contains
165 * information about the domain the device belongs to as well as the
166 * page table root pointer.
168 struct dev_table_entry *amd_iommu_dev_table;
171 * The alias table is a driver specific data structure which contains the
172 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
173 * More than one device can share the same requestor id.
175 u16 *amd_iommu_alias_table;
178 * The rlookup table is used to find the IOMMU which is responsible
179 * for a specific device. It is also indexed by the PCI device id.
181 struct amd_iommu **amd_iommu_rlookup_table;
184 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
185 * to know which ones are already in use.
187 unsigned long *amd_iommu_pd_alloc_bitmap;
189 static u32 dev_table_size; /* size of the device table */
190 static u32 alias_table_size; /* size of the alias table */
191 static u32 rlookup_table_size; /* size if the rlookup table */
193 static int amd_iommu_enable_interrupts(void);
195 static inline void update_last_devid(u16 devid)
197 if (devid > amd_iommu_last_bdf)
198 amd_iommu_last_bdf = devid;
201 static inline unsigned long tbl_size(int entry_size)
203 unsigned shift = PAGE_SHIFT +
204 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
209 /* Access to l1 and l2 indexed register spaces */
211 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
215 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
216 pci_read_config_dword(iommu->dev, 0xfc, &val);
220 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
222 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
223 pci_write_config_dword(iommu->dev, 0xfc, val);
224 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
227 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
231 pci_write_config_dword(iommu->dev, 0xf0, address);
232 pci_read_config_dword(iommu->dev, 0xf4, &val);
236 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
238 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
239 pci_write_config_dword(iommu->dev, 0xf4, val);
242 /****************************************************************************
244 * AMD IOMMU MMIO register space handling functions
246 * These functions are used to program the IOMMU device registers in
247 * MMIO space required for that driver.
249 ****************************************************************************/
252 * This function set the exclusion range in the IOMMU. DMA accesses to the
253 * exclusion range are passed through untranslated
255 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
257 u64 start = iommu->exclusion_start & PAGE_MASK;
258 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
261 if (!iommu->exclusion_start)
264 entry = start | MMIO_EXCL_ENABLE_MASK;
265 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
266 &entry, sizeof(entry));
269 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
270 &entry, sizeof(entry));
273 /* Programs the physical address of the device table into the IOMMU hardware */
274 static void iommu_set_device_table(struct amd_iommu *iommu)
278 BUG_ON(iommu->mmio_base == NULL);
280 entry = virt_to_phys(amd_iommu_dev_table);
281 entry |= (dev_table_size >> 12) - 1;
282 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
283 &entry, sizeof(entry));
286 /* Generic functions to enable/disable certain features of the IOMMU. */
287 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
291 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
293 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
296 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
300 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
302 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
305 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
309 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
310 ctrl &= ~CTRL_INV_TO_MASK;
311 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
312 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
315 /* Function to enable the hardware */
316 static void iommu_enable(struct amd_iommu *iommu)
318 static const char * const feat_str[] = {
319 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
320 "IA", "GA", "HE", "PC", NULL
324 printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx",
325 dev_name(&iommu->dev->dev), iommu->cap_ptr);
327 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
328 printk(KERN_CONT " extended features: ");
329 for (i = 0; feat_str[i]; ++i)
330 if (iommu_feature(iommu, (1ULL << i)))
331 printk(KERN_CONT " %s", feat_str[i]);
333 printk(KERN_CONT "\n");
335 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
338 static void iommu_disable(struct amd_iommu *iommu)
340 /* Disable command buffer */
341 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
343 /* Disable event logging and event interrupts */
344 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
345 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
347 /* Disable IOMMU hardware itself */
348 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
352 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
353 * the system has one.
355 static u8 __iomem * __init iommu_map_mmio_space(u64 address)
357 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
358 pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
360 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
364 return (u8 __iomem *)ioremap_nocache(address, MMIO_REGION_LENGTH);
367 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
369 if (iommu->mmio_base)
370 iounmap(iommu->mmio_base);
371 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
374 /****************************************************************************
376 * The functions below belong to the first pass of AMD IOMMU ACPI table
377 * parsing. In this pass we try to find out the highest device id this
378 * code has to handle. Upon this information the size of the shared data
379 * structures is determined later.
381 ****************************************************************************/
384 * This function calculates the length of a given IVHD entry
386 static inline int ivhd_entry_length(u8 *ivhd)
388 return 0x04 << (*ivhd >> 6);
392 * This function reads the last device id the IOMMU has to handle from the PCI
393 * capability header for this IOMMU
395 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
399 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
400 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
406 * After reading the highest device id from the IOMMU PCI capability header
407 * this function looks if there is a higher device id defined in the ACPI table
409 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
411 u8 *p = (void *)h, *end = (void *)h;
412 struct ivhd_entry *dev;
417 find_last_devid_on_pci(PCI_BUS(h->devid),
423 dev = (struct ivhd_entry *)p;
425 case IVHD_DEV_SELECT:
426 case IVHD_DEV_RANGE_END:
428 case IVHD_DEV_EXT_SELECT:
429 /* all the above subfield types refer to device ids */
430 update_last_devid(dev->devid);
435 p += ivhd_entry_length(p);
444 * Iterate over all IVHD entries in the ACPI table and find the highest device
445 * id which we need to handle. This is the first of three functions which parse
446 * the ACPI table. So we check the checksum here.
448 static int __init find_last_devid_acpi(struct acpi_table_header *table)
451 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
452 struct ivhd_header *h;
455 * Validate checksum here so we don't need to do it when
456 * we actually parse the table
458 for (i = 0; i < table->length; ++i)
461 /* ACPI table corrupt */
462 amd_iommu_init_err = -ENODEV;
466 p += IVRS_HEADER_LENGTH;
468 end += table->length;
470 h = (struct ivhd_header *)p;
473 find_last_devid_from_ivhd(h);
485 /****************************************************************************
487 * The following functions belong the the code path which parses the ACPI table
488 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
489 * data structures, initialize the device/alias/rlookup table and also
490 * basically initialize the hardware.
492 ****************************************************************************/
495 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
496 * write commands to that buffer later and the IOMMU will execute them
499 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
501 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
502 get_order(CMD_BUFFER_SIZE));
507 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
513 * This function resets the command buffer if the IOMMU stopped fetching
516 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
518 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
520 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
521 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
523 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
527 * This function writes the command buffer address to the hardware and
530 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
534 BUG_ON(iommu->cmd_buf == NULL);
536 entry = (u64)virt_to_phys(iommu->cmd_buf);
537 entry |= MMIO_CMD_SIZE_512;
539 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
540 &entry, sizeof(entry));
542 amd_iommu_reset_cmd_buffer(iommu);
543 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
546 static void __init free_command_buffer(struct amd_iommu *iommu)
548 free_pages((unsigned long)iommu->cmd_buf,
549 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
552 /* allocates the memory where the IOMMU will log its events to */
553 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
555 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
556 get_order(EVT_BUFFER_SIZE));
558 if (iommu->evt_buf == NULL)
561 iommu->evt_buf_size = EVT_BUFFER_SIZE;
563 return iommu->evt_buf;
566 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
570 BUG_ON(iommu->evt_buf == NULL);
572 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
574 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
575 &entry, sizeof(entry));
577 /* set head and tail to zero manually */
578 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
579 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
581 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
584 static void __init free_event_buffer(struct amd_iommu *iommu)
586 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
589 /* allocates the memory where the IOMMU will log its events to */
590 static u8 * __init alloc_ppr_log(struct amd_iommu *iommu)
592 iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
593 get_order(PPR_LOG_SIZE));
595 if (iommu->ppr_log == NULL)
598 return iommu->ppr_log;
601 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
605 if (iommu->ppr_log == NULL)
608 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
610 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
611 &entry, sizeof(entry));
613 /* set head and tail to zero manually */
614 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
615 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
617 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
618 iommu_feature_enable(iommu, CONTROL_PPR_EN);
621 static void __init free_ppr_log(struct amd_iommu *iommu)
623 if (iommu->ppr_log == NULL)
626 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
629 static void iommu_enable_gt(struct amd_iommu *iommu)
631 if (!iommu_feature(iommu, FEATURE_GT))
634 iommu_feature_enable(iommu, CONTROL_GT_EN);
637 /* sets a specific bit in the device table entry. */
638 static void set_dev_entry_bit(u16 devid, u8 bit)
640 int i = (bit >> 6) & 0x03;
641 int _bit = bit & 0x3f;
643 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
646 static int get_dev_entry_bit(u16 devid, u8 bit)
648 int i = (bit >> 6) & 0x03;
649 int _bit = bit & 0x3f;
651 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
655 void amd_iommu_apply_erratum_63(u16 devid)
659 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
660 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
663 set_dev_entry_bit(devid, DEV_ENTRY_IW);
666 /* Writes the specific IOMMU for a device into the rlookup table */
667 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
669 amd_iommu_rlookup_table[devid] = iommu;
673 * This function takes the device specific flags read from the ACPI
674 * table and sets up the device table entry with that information
676 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
677 u16 devid, u32 flags, u32 ext_flags)
679 if (flags & ACPI_DEVFLAG_INITPASS)
680 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
681 if (flags & ACPI_DEVFLAG_EXTINT)
682 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
683 if (flags & ACPI_DEVFLAG_NMI)
684 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
685 if (flags & ACPI_DEVFLAG_SYSMGT1)
686 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
687 if (flags & ACPI_DEVFLAG_SYSMGT2)
688 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
689 if (flags & ACPI_DEVFLAG_LINT0)
690 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
691 if (flags & ACPI_DEVFLAG_LINT1)
692 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
694 amd_iommu_apply_erratum_63(devid);
696 set_iommu_for_device(iommu, devid);
700 * Reads the device exclusion range from ACPI and initialize IOMMU with
703 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
705 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
707 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
712 * We only can configure exclusion ranges per IOMMU, not
713 * per device. But we can enable the exclusion range per
714 * device. This is done here
716 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
717 iommu->exclusion_start = m->range_start;
718 iommu->exclusion_length = m->range_length;
723 * This function reads some important data from the IOMMU PCI space and
724 * initializes the driver data structure with it. It reads the hardware
725 * capabilities and the first/last device entries
727 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
729 int cap_ptr = iommu->cap_ptr;
730 u32 range, misc, low, high;
733 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
735 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
737 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
740 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
742 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
744 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
746 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
747 amd_iommu_iotlb_sup = false;
749 /* read extended feature bits */
750 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
751 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
753 iommu->features = ((u64)high << 32) | low;
755 if (iommu_feature(iommu, FEATURE_GT)) {
760 shift = iommu->features & FEATURE_PASID_MASK;
761 shift >>= FEATURE_PASID_SHIFT;
762 pasids = (1 << shift);
764 amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids);
766 glxval = iommu->features & FEATURE_GLXVAL_MASK;
767 glxval >>= FEATURE_GLXVAL_SHIFT;
769 if (amd_iommu_max_glx_val == -1)
770 amd_iommu_max_glx_val = glxval;
772 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
775 if (iommu_feature(iommu, FEATURE_GT) &&
776 iommu_feature(iommu, FEATURE_PPR)) {
777 iommu->is_iommu_v2 = true;
778 amd_iommu_v2_present = true;
781 if (!is_rd890_iommu(iommu->dev))
785 * Some rd890 systems may not be fully reconfigured by the BIOS, so
786 * it's necessary for us to store this information so it can be
787 * reprogrammed on resume
790 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
791 &iommu->stored_addr_lo);
792 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
793 &iommu->stored_addr_hi);
795 /* Low bit locks writes to configuration space */
796 iommu->stored_addr_lo &= ~1;
798 for (i = 0; i < 6; i++)
799 for (j = 0; j < 0x12; j++)
800 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
802 for (i = 0; i < 0x83; i++)
803 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
807 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
808 * initializes the hardware and our data structures with it.
810 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
811 struct ivhd_header *h)
814 u8 *end = p, flags = 0;
815 u16 devid = 0, devid_start = 0, devid_to = 0;
816 u32 dev_i, ext_flags = 0;
818 struct ivhd_entry *e;
821 * First save the recommended feature enable bits from ACPI
823 iommu->acpi_flags = h->flags;
826 * Done. Now parse the device entries
828 p += sizeof(struct ivhd_header);
833 e = (struct ivhd_entry *)p;
837 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
838 " last device %02x:%02x.%x flags: %02x\n",
839 PCI_BUS(iommu->first_device),
840 PCI_SLOT(iommu->first_device),
841 PCI_FUNC(iommu->first_device),
842 PCI_BUS(iommu->last_device),
843 PCI_SLOT(iommu->last_device),
844 PCI_FUNC(iommu->last_device),
847 for (dev_i = iommu->first_device;
848 dev_i <= iommu->last_device; ++dev_i)
849 set_dev_entry_from_acpi(iommu, dev_i,
852 case IVHD_DEV_SELECT:
854 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
862 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
864 case IVHD_DEV_SELECT_RANGE_START:
866 DUMP_printk(" DEV_SELECT_RANGE_START\t "
867 "devid: %02x:%02x.%x flags: %02x\n",
873 devid_start = e->devid;
880 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
881 "flags: %02x devid_to: %02x:%02x.%x\n",
886 PCI_BUS(e->ext >> 8),
887 PCI_SLOT(e->ext >> 8),
888 PCI_FUNC(e->ext >> 8));
891 devid_to = e->ext >> 8;
892 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
893 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
894 amd_iommu_alias_table[devid] = devid_to;
896 case IVHD_DEV_ALIAS_RANGE:
898 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
899 "devid: %02x:%02x.%x flags: %02x "
900 "devid_to: %02x:%02x.%x\n",
905 PCI_BUS(e->ext >> 8),
906 PCI_SLOT(e->ext >> 8),
907 PCI_FUNC(e->ext >> 8));
909 devid_start = e->devid;
911 devid_to = e->ext >> 8;
915 case IVHD_DEV_EXT_SELECT:
917 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
918 "flags: %02x ext: %08x\n",
925 set_dev_entry_from_acpi(iommu, devid, e->flags,
928 case IVHD_DEV_EXT_SELECT_RANGE:
930 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
931 "%02x:%02x.%x flags: %02x ext: %08x\n",
937 devid_start = e->devid;
942 case IVHD_DEV_RANGE_END:
944 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
950 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
952 amd_iommu_alias_table[dev_i] = devid_to;
953 set_dev_entry_from_acpi(iommu,
954 devid_to, flags, ext_flags);
956 set_dev_entry_from_acpi(iommu, dev_i,
964 p += ivhd_entry_length(p);
968 /* Initializes the device->iommu mapping for the driver */
969 static int __init init_iommu_devices(struct amd_iommu *iommu)
973 for (i = iommu->first_device; i <= iommu->last_device; ++i)
974 set_iommu_for_device(iommu, i);
979 static void __init free_iommu_one(struct amd_iommu *iommu)
981 free_command_buffer(iommu);
982 free_event_buffer(iommu);
984 iommu_unmap_mmio_space(iommu);
987 static void __init free_iommu_all(void)
989 struct amd_iommu *iommu, *next;
991 for_each_iommu_safe(iommu, next) {
992 list_del(&iommu->list);
993 free_iommu_one(iommu);
999 * This function clues the initialization function for one IOMMU
1000 * together and also allocates the command buffer and programs the
1001 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1003 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1005 spin_lock_init(&iommu->lock);
1007 /* Add IOMMU to internal data structures */
1008 list_add_tail(&iommu->list, &amd_iommu_list);
1009 iommu->index = amd_iommus_present++;
1011 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1012 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1016 /* Index is fine - add IOMMU to the array */
1017 amd_iommus[iommu->index] = iommu;
1020 * Copy data from ACPI table entry to the iommu struct
1022 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
1026 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1029 iommu->cap_ptr = h->cap_ptr;
1030 iommu->pci_seg = h->pci_seg;
1031 iommu->mmio_phys = h->mmio_phys;
1032 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
1033 if (!iommu->mmio_base)
1036 iommu->cmd_buf = alloc_command_buffer(iommu);
1037 if (!iommu->cmd_buf)
1040 iommu->evt_buf = alloc_event_buffer(iommu);
1041 if (!iommu->evt_buf)
1044 iommu->int_enabled = false;
1046 init_iommu_from_pci(iommu);
1047 init_iommu_from_acpi(iommu, h);
1048 init_iommu_devices(iommu);
1050 if (iommu_feature(iommu, FEATURE_PPR)) {
1051 iommu->ppr_log = alloc_ppr_log(iommu);
1052 if (!iommu->ppr_log)
1056 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1057 amd_iommu_np_cache = true;
1059 return pci_enable_device(iommu->dev);
1063 * Iterates over all IOMMU entries in the ACPI table, allocates the
1064 * IOMMU structure and initializes it with init_iommu_one()
1066 static int __init init_iommu_all(struct acpi_table_header *table)
1068 u8 *p = (u8 *)table, *end = (u8 *)table;
1069 struct ivhd_header *h;
1070 struct amd_iommu *iommu;
1073 end += table->length;
1074 p += IVRS_HEADER_LENGTH;
1077 h = (struct ivhd_header *)p;
1079 case ACPI_IVHD_TYPE:
1081 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1082 "seg: %d flags: %01x info %04x\n",
1083 PCI_BUS(h->devid), PCI_SLOT(h->devid),
1084 PCI_FUNC(h->devid), h->cap_ptr,
1085 h->pci_seg, h->flags, h->info);
1086 DUMP_printk(" mmio-addr: %016llx\n",
1089 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1090 if (iommu == NULL) {
1091 amd_iommu_init_err = -ENOMEM;
1095 ret = init_iommu_one(iommu, h);
1097 amd_iommu_init_err = ret;
1112 /****************************************************************************
1114 * The following functions initialize the MSI interrupts for all IOMMUs
1115 * in the system. Its a bit challenging because there could be multiple
1116 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1119 ****************************************************************************/
1121 static int iommu_setup_msi(struct amd_iommu *iommu)
1125 r = pci_enable_msi(iommu->dev);
1129 r = request_threaded_irq(iommu->dev->irq,
1130 amd_iommu_int_handler,
1131 amd_iommu_int_thread,
1136 pci_disable_msi(iommu->dev);
1140 iommu->int_enabled = true;
1145 static int iommu_init_msi(struct amd_iommu *iommu)
1149 if (iommu->int_enabled)
1152 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
1153 ret = iommu_setup_msi(iommu);
1161 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1163 if (iommu->ppr_log != NULL)
1164 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1169 /****************************************************************************
1171 * The next functions belong to the third pass of parsing the ACPI
1172 * table. In this last pass the memory mapping requirements are
1173 * gathered (like exclusion and unity mapping reanges).
1175 ****************************************************************************/
1177 static void __init free_unity_maps(void)
1179 struct unity_map_entry *entry, *next;
1181 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1182 list_del(&entry->list);
1187 /* called when we find an exclusion range definition in ACPI */
1188 static int __init init_exclusion_range(struct ivmd_header *m)
1193 case ACPI_IVMD_TYPE:
1194 set_device_exclusion_range(m->devid, m);
1196 case ACPI_IVMD_TYPE_ALL:
1197 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1198 set_device_exclusion_range(i, m);
1200 case ACPI_IVMD_TYPE_RANGE:
1201 for (i = m->devid; i <= m->aux; ++i)
1202 set_device_exclusion_range(i, m);
1211 /* called for unity map ACPI definition */
1212 static int __init init_unity_map_range(struct ivmd_header *m)
1214 struct unity_map_entry *e = NULL;
1217 e = kzalloc(sizeof(*e), GFP_KERNEL);
1225 case ACPI_IVMD_TYPE:
1226 s = "IVMD_TYPEi\t\t\t";
1227 e->devid_start = e->devid_end = m->devid;
1229 case ACPI_IVMD_TYPE_ALL:
1230 s = "IVMD_TYPE_ALL\t\t";
1232 e->devid_end = amd_iommu_last_bdf;
1234 case ACPI_IVMD_TYPE_RANGE:
1235 s = "IVMD_TYPE_RANGE\t\t";
1236 e->devid_start = m->devid;
1237 e->devid_end = m->aux;
1240 e->address_start = PAGE_ALIGN(m->range_start);
1241 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1242 e->prot = m->flags >> 1;
1244 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1245 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1246 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1247 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1248 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1249 e->address_start, e->address_end, m->flags);
1251 list_add_tail(&e->list, &amd_iommu_unity_map);
1256 /* iterates over all memory definitions we find in the ACPI table */
1257 static int __init init_memory_definitions(struct acpi_table_header *table)
1259 u8 *p = (u8 *)table, *end = (u8 *)table;
1260 struct ivmd_header *m;
1262 end += table->length;
1263 p += IVRS_HEADER_LENGTH;
1266 m = (struct ivmd_header *)p;
1267 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1268 init_exclusion_range(m);
1269 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1270 init_unity_map_range(m);
1279 * Init the device table to not allow DMA access for devices and
1280 * suppress all page faults
1282 static void init_device_table(void)
1286 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1287 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1288 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1292 static void iommu_init_flags(struct amd_iommu *iommu)
1294 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1295 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1296 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1298 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1299 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1300 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1302 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1303 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1304 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1306 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1307 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1308 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1311 * make IOMMU memory accesses cache coherent
1313 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1315 /* Set IOTLB invalidation timeout to 1s */
1316 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1319 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1322 u32 ioc_feature_control;
1323 struct pci_dev *pdev = iommu->root_pdev;
1325 /* RD890 BIOSes may not have completely reconfigured the iommu */
1326 if (!is_rd890_iommu(iommu->dev) || !pdev)
1330 * First, we need to ensure that the iommu is enabled. This is
1331 * controlled by a register in the northbridge
1334 /* Select Northbridge indirect register 0x75 and enable writing */
1335 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1336 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1338 /* Enable the iommu */
1339 if (!(ioc_feature_control & 0x1))
1340 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1342 /* Restore the iommu BAR */
1343 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1344 iommu->stored_addr_lo);
1345 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1346 iommu->stored_addr_hi);
1348 /* Restore the l1 indirect regs for each of the 6 l1s */
1349 for (i = 0; i < 6; i++)
1350 for (j = 0; j < 0x12; j++)
1351 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1353 /* Restore the l2 indirect regs */
1354 for (i = 0; i < 0x83; i++)
1355 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1357 /* Lock PCI setup registers */
1358 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1359 iommu->stored_addr_lo | 1);
1363 * This function finally enables all IOMMUs found in the system after
1364 * they have been initialized
1366 static void enable_iommus(void)
1368 struct amd_iommu *iommu;
1370 for_each_iommu(iommu) {
1371 iommu_disable(iommu);
1372 iommu_init_flags(iommu);
1373 iommu_set_device_table(iommu);
1374 iommu_enable_command_buffer(iommu);
1375 iommu_enable_event_buffer(iommu);
1376 iommu_enable_ppr_log(iommu);
1377 iommu_enable_gt(iommu);
1378 iommu_set_exclusion_range(iommu);
1379 iommu_enable(iommu);
1380 iommu_flush_all_caches(iommu);
1384 static void disable_iommus(void)
1386 struct amd_iommu *iommu;
1388 for_each_iommu(iommu)
1389 iommu_disable(iommu);
1393 * Suspend/Resume support
1394 * disable suspend until real resume implemented
1397 static void amd_iommu_resume(void)
1399 struct amd_iommu *iommu;
1401 for_each_iommu(iommu)
1402 iommu_apply_resume_quirks(iommu);
1404 /* re-load the hardware */
1407 amd_iommu_enable_interrupts();
1410 static int amd_iommu_suspend(void)
1412 /* disable IOMMUs to go out of the way for BIOS */
1418 static struct syscore_ops amd_iommu_syscore_ops = {
1419 .suspend = amd_iommu_suspend,
1420 .resume = amd_iommu_resume,
1423 static void __init free_on_init_error(void)
1425 amd_iommu_uninit_devices();
1427 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1428 get_order(MAX_DOMAIN_ID/8));
1430 free_pages((unsigned long)amd_iommu_rlookup_table,
1431 get_order(rlookup_table_size));
1433 free_pages((unsigned long)amd_iommu_alias_table,
1434 get_order(alias_table_size));
1436 free_pages((unsigned long)amd_iommu_dev_table,
1437 get_order(dev_table_size));
1443 #ifdef CONFIG_GART_IOMMU
1445 * We failed to initialize the AMD IOMMU - try fallback to GART
1454 * This is the hardware init function for AMD IOMMU in the system.
1455 * This function is called either from amd_iommu_init or from the interrupt
1456 * remapping setup code.
1458 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1461 * 1 pass) Find the highest PCI device id the driver has to handle.
1462 * Upon this information the size of the data structures is
1463 * determined that needs to be allocated.
1465 * 2 pass) Initialize the data structures just allocated with the
1466 * information in the ACPI table about available AMD IOMMUs
1467 * in the system. It also maps the PCI devices in the
1468 * system to specific IOMMUs
1470 * 3 pass) After the basic data structures are allocated and
1471 * initialized we update them with information about memory
1472 * remapping requirements parsed out of the ACPI table in
1475 * After everything is set up the IOMMUs are enabled and the necessary
1476 * hotplug and suspend notifiers are registered.
1478 int __init amd_iommu_init_hardware(void)
1482 if (!amd_iommu_detected)
1485 if (amd_iommu_dev_table != NULL) {
1486 /* Hardware already initialized */
1491 * First parse ACPI tables to find the largest Bus/Dev/Func
1492 * we need to handle. Upon this information the shared data
1493 * structures for the IOMMUs in the system will be allocated
1495 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1498 ret = amd_iommu_init_err;
1502 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1503 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1504 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1506 /* Device table - directly used by all IOMMUs */
1508 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1509 get_order(dev_table_size));
1510 if (amd_iommu_dev_table == NULL)
1514 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1515 * IOMMU see for that device
1517 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1518 get_order(alias_table_size));
1519 if (amd_iommu_alias_table == NULL)
1522 /* IOMMU rlookup table - find the IOMMU for a specific device */
1523 amd_iommu_rlookup_table = (void *)__get_free_pages(
1524 GFP_KERNEL | __GFP_ZERO,
1525 get_order(rlookup_table_size));
1526 if (amd_iommu_rlookup_table == NULL)
1529 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1530 GFP_KERNEL | __GFP_ZERO,
1531 get_order(MAX_DOMAIN_ID/8));
1532 if (amd_iommu_pd_alloc_bitmap == NULL)
1535 /* init the device table */
1536 init_device_table();
1539 * let all alias entries point to itself
1541 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1542 amd_iommu_alias_table[i] = i;
1545 * never allocate domain 0 because its used as the non-allocated and
1546 * error value placeholder
1548 amd_iommu_pd_alloc_bitmap[0] = 1;
1550 spin_lock_init(&amd_iommu_pd_lock);
1553 * now the data structures are allocated and basically initialized
1554 * start the real acpi table scan
1557 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1560 if (amd_iommu_init_err) {
1561 ret = amd_iommu_init_err;
1565 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1568 if (amd_iommu_init_err) {
1569 ret = amd_iommu_init_err;
1573 ret = amd_iommu_init_devices();
1579 amd_iommu_init_notifier();
1581 register_syscore_ops(&amd_iommu_syscore_ops);
1587 free_on_init_error();
1592 static int amd_iommu_enable_interrupts(void)
1594 struct amd_iommu *iommu;
1597 for_each_iommu(iommu) {
1598 ret = iommu_init_msi(iommu);
1608 * This is the core init function for AMD IOMMU hardware in the system.
1609 * This function is called from the generic x86 DMA layer initialization
1612 * The function calls amd_iommu_init_hardware() to setup and enable the
1613 * IOMMU hardware if this has not happened yet. After that the driver
1614 * registers for the DMA-API and for the IOMMU-API as necessary.
1616 static int __init amd_iommu_init(void)
1620 ret = amd_iommu_init_hardware();
1624 ret = amd_iommu_enable_interrupts();
1628 if (iommu_pass_through)
1629 ret = amd_iommu_init_passthrough();
1631 ret = amd_iommu_init_dma_ops();
1636 amd_iommu_init_api();
1638 x86_platform.iommu_shutdown = disable_iommus;
1640 if (iommu_pass_through)
1643 if (amd_iommu_unmap_flush)
1644 printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
1646 printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
1654 free_on_init_error();
1659 /****************************************************************************
1661 * Early detect code. This code runs at IOMMU detection time in the DMA
1662 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1665 ****************************************************************************/
1666 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1671 int __init amd_iommu_detect(void)
1673 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
1676 if (amd_iommu_disabled)
1679 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1681 amd_iommu_detected = 1;
1682 x86_init.iommu.iommu_init = amd_iommu_init;
1684 /* Make sure ACS will be enabled */
1691 /****************************************************************************
1693 * Parsing functions for the AMD IOMMU specific kernel command line
1696 ****************************************************************************/
1698 static int __init parse_amd_iommu_dump(char *str)
1700 amd_iommu_dump = true;
1705 static int __init parse_amd_iommu_options(char *str)
1707 for (; *str; ++str) {
1708 if (strncmp(str, "fullflush", 9) == 0)
1709 amd_iommu_unmap_flush = true;
1710 if (strncmp(str, "off", 3) == 0)
1711 amd_iommu_disabled = true;
1712 if (strncmp(str, "force_isolation", 15) == 0)
1713 amd_iommu_force_isolation = true;
1719 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1720 __setup("amd_iommu=", parse_amd_iommu_options);
1722 IOMMU_INIT_FINISH(amd_iommu_detect,
1723 gart_iommu_hole_init,
1727 bool amd_iommu_v2_supported(void)
1729 return amd_iommu_v2_present;
1731 EXPORT_SYMBOL(amd_iommu_v2_supported);