2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <linux/amd-iommu.h>
28 #include <linux/export.h>
29 #include <linux/acpi.h>
30 #include <acpi/acpi.h>
31 #include <asm/pci-direct.h>
32 #include <asm/iommu.h>
34 #include <asm/x86_init.h>
35 #include <asm/iommu_table.h>
37 #include "amd_iommu_proto.h"
38 #include "amd_iommu_types.h"
39 #include "irq_remapping.h"
42 * definitions for the ACPI scanning code
44 #define IVRS_HEADER_LENGTH 48
46 #define ACPI_IVHD_TYPE 0x10
47 #define ACPI_IVMD_TYPE_ALL 0x20
48 #define ACPI_IVMD_TYPE 0x21
49 #define ACPI_IVMD_TYPE_RANGE 0x22
51 #define IVHD_DEV_ALL 0x01
52 #define IVHD_DEV_SELECT 0x02
53 #define IVHD_DEV_SELECT_RANGE_START 0x03
54 #define IVHD_DEV_RANGE_END 0x04
55 #define IVHD_DEV_ALIAS 0x42
56 #define IVHD_DEV_ALIAS_RANGE 0x43
57 #define IVHD_DEV_EXT_SELECT 0x46
58 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
59 #define IVHD_DEV_SPECIAL 0x48
61 #define IVHD_SPECIAL_IOAPIC 1
62 #define IVHD_SPECIAL_HPET 2
64 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
65 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
66 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
67 #define IVHD_FLAG_ISOC_EN_MASK 0x08
69 #define IVMD_FLAG_EXCL_RANGE 0x08
70 #define IVMD_FLAG_UNITY_MAP 0x01
72 #define ACPI_DEVFLAG_INITPASS 0x01
73 #define ACPI_DEVFLAG_EXTINT 0x02
74 #define ACPI_DEVFLAG_NMI 0x04
75 #define ACPI_DEVFLAG_SYSMGT1 0x10
76 #define ACPI_DEVFLAG_SYSMGT2 0x20
77 #define ACPI_DEVFLAG_LINT0 0x40
78 #define ACPI_DEVFLAG_LINT1 0x80
79 #define ACPI_DEVFLAG_ATSDIS 0x10000000
82 * ACPI table definitions
84 * These data structures are laid over the table to parse the important values
89 * structure describing one IOMMU in the ACPI table. Typically followed by one
90 * or more ivhd_entrys.
102 } __attribute__((packed));
105 * A device entry describing which devices a specific IOMMU translates and
106 * which requestor ids they use.
113 } __attribute__((packed));
116 * An AMD IOMMU memory definition structure. It defines things like exclusion
117 * ranges for devices and regions that should be unity mapped.
128 } __attribute__((packed));
131 bool amd_iommu_irq_remap __read_mostly;
133 static bool amd_iommu_detected;
134 static bool __initdata amd_iommu_disabled;
136 u16 amd_iommu_last_bdf; /* largest PCI device id we have
138 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
140 u32 amd_iommu_unmap_flush; /* if true, flush on every unmap */
142 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
145 /* Array to assign indices to IOMMUs*/
146 struct amd_iommu *amd_iommus[MAX_IOMMUS];
147 int amd_iommus_present;
149 /* IOMMUs have a non-present cache? */
150 bool amd_iommu_np_cache __read_mostly;
151 bool amd_iommu_iotlb_sup __read_mostly = true;
153 u32 amd_iommu_max_pasids __read_mostly = ~0;
155 bool amd_iommu_v2_present __read_mostly;
157 bool amd_iommu_force_isolation __read_mostly;
160 * List of protection domains - used during resume
162 LIST_HEAD(amd_iommu_pd_list);
163 spinlock_t amd_iommu_pd_lock;
166 * Pointer to the device table which is shared by all AMD IOMMUs
167 * it is indexed by the PCI device id or the HT unit id and contains
168 * information about the domain the device belongs to as well as the
169 * page table root pointer.
171 struct dev_table_entry *amd_iommu_dev_table;
174 * The alias table is a driver specific data structure which contains the
175 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
176 * More than one device can share the same requestor id.
178 u16 *amd_iommu_alias_table;
181 * The rlookup table is used to find the IOMMU which is responsible
182 * for a specific device. It is also indexed by the PCI device id.
184 struct amd_iommu **amd_iommu_rlookup_table;
187 * This table is used to find the irq remapping table for a given device id
190 struct irq_remap_table **irq_lookup_table;
193 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
194 * to know which ones are already in use.
196 unsigned long *amd_iommu_pd_alloc_bitmap;
198 static u32 dev_table_size; /* size of the device table */
199 static u32 alias_table_size; /* size of the alias table */
200 static u32 rlookup_table_size; /* size if the rlookup table */
202 enum iommu_init_state {
215 static enum iommu_init_state init_state = IOMMU_START_STATE;
217 static int amd_iommu_enable_interrupts(void);
218 static int __init iommu_go_to_state(enum iommu_init_state state);
220 static inline void update_last_devid(u16 devid)
222 if (devid > amd_iommu_last_bdf)
223 amd_iommu_last_bdf = devid;
226 static inline unsigned long tbl_size(int entry_size)
228 unsigned shift = PAGE_SHIFT +
229 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
234 /* Access to l1 and l2 indexed register spaces */
236 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
240 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
241 pci_read_config_dword(iommu->dev, 0xfc, &val);
245 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
247 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
248 pci_write_config_dword(iommu->dev, 0xfc, val);
249 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
252 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
256 pci_write_config_dword(iommu->dev, 0xf0, address);
257 pci_read_config_dword(iommu->dev, 0xf4, &val);
261 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
263 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
264 pci_write_config_dword(iommu->dev, 0xf4, val);
267 /****************************************************************************
269 * AMD IOMMU MMIO register space handling functions
271 * These functions are used to program the IOMMU device registers in
272 * MMIO space required for that driver.
274 ****************************************************************************/
277 * This function set the exclusion range in the IOMMU. DMA accesses to the
278 * exclusion range are passed through untranslated
280 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
282 u64 start = iommu->exclusion_start & PAGE_MASK;
283 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
286 if (!iommu->exclusion_start)
289 entry = start | MMIO_EXCL_ENABLE_MASK;
290 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
291 &entry, sizeof(entry));
294 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
295 &entry, sizeof(entry));
298 /* Programs the physical address of the device table into the IOMMU hardware */
299 static void iommu_set_device_table(struct amd_iommu *iommu)
303 BUG_ON(iommu->mmio_base == NULL);
305 entry = virt_to_phys(amd_iommu_dev_table);
306 entry |= (dev_table_size >> 12) - 1;
307 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
308 &entry, sizeof(entry));
311 /* Generic functions to enable/disable certain features of the IOMMU. */
312 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
316 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
318 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
321 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
325 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
327 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
330 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
334 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
335 ctrl &= ~CTRL_INV_TO_MASK;
336 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
337 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
340 /* Function to enable the hardware */
341 static void iommu_enable(struct amd_iommu *iommu)
343 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
346 static void iommu_disable(struct amd_iommu *iommu)
348 /* Disable command buffer */
349 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
351 /* Disable event logging and event interrupts */
352 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
353 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
355 /* Disable IOMMU hardware itself */
356 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
360 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
361 * the system has one.
363 static u8 __iomem * __init iommu_map_mmio_space(u64 address)
365 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
366 pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
368 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
372 return (u8 __iomem *)ioremap_nocache(address, MMIO_REGION_LENGTH);
375 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
377 if (iommu->mmio_base)
378 iounmap(iommu->mmio_base);
379 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
382 /****************************************************************************
384 * The functions below belong to the first pass of AMD IOMMU ACPI table
385 * parsing. In this pass we try to find out the highest device id this
386 * code has to handle. Upon this information the size of the shared data
387 * structures is determined later.
389 ****************************************************************************/
392 * This function calculates the length of a given IVHD entry
394 static inline int ivhd_entry_length(u8 *ivhd)
396 return 0x04 << (*ivhd >> 6);
400 * This function reads the last device id the IOMMU has to handle from the PCI
401 * capability header for this IOMMU
403 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
407 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
408 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
414 * After reading the highest device id from the IOMMU PCI capability header
415 * this function looks if there is a higher device id defined in the ACPI table
417 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
419 u8 *p = (void *)h, *end = (void *)h;
420 struct ivhd_entry *dev;
425 find_last_devid_on_pci(PCI_BUS(h->devid),
431 dev = (struct ivhd_entry *)p;
433 case IVHD_DEV_SELECT:
434 case IVHD_DEV_RANGE_END:
436 case IVHD_DEV_EXT_SELECT:
437 /* all the above subfield types refer to device ids */
438 update_last_devid(dev->devid);
443 p += ivhd_entry_length(p);
452 * Iterate over all IVHD entries in the ACPI table and find the highest device
453 * id which we need to handle. This is the first of three functions which parse
454 * the ACPI table. So we check the checksum here.
456 static int __init find_last_devid_acpi(struct acpi_table_header *table)
459 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
460 struct ivhd_header *h;
463 * Validate checksum here so we don't need to do it when
464 * we actually parse the table
466 for (i = 0; i < table->length; ++i)
469 /* ACPI table corrupt */
472 p += IVRS_HEADER_LENGTH;
474 end += table->length;
476 h = (struct ivhd_header *)p;
479 find_last_devid_from_ivhd(h);
491 /****************************************************************************
493 * The following functions belong the the code path which parses the ACPI table
494 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
495 * data structures, initialize the device/alias/rlookup table and also
496 * basically initialize the hardware.
498 ****************************************************************************/
501 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
502 * write commands to that buffer later and the IOMMU will execute them
505 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
507 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
508 get_order(CMD_BUFFER_SIZE));
513 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
519 * This function resets the command buffer if the IOMMU stopped fetching
522 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
524 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
526 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
527 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
529 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
533 * This function writes the command buffer address to the hardware and
536 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
540 BUG_ON(iommu->cmd_buf == NULL);
542 entry = (u64)virt_to_phys(iommu->cmd_buf);
543 entry |= MMIO_CMD_SIZE_512;
545 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
546 &entry, sizeof(entry));
548 amd_iommu_reset_cmd_buffer(iommu);
549 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
552 static void __init free_command_buffer(struct amd_iommu *iommu)
554 free_pages((unsigned long)iommu->cmd_buf,
555 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
558 /* allocates the memory where the IOMMU will log its events to */
559 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
561 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
562 get_order(EVT_BUFFER_SIZE));
564 if (iommu->evt_buf == NULL)
567 iommu->evt_buf_size = EVT_BUFFER_SIZE;
569 return iommu->evt_buf;
572 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
576 BUG_ON(iommu->evt_buf == NULL);
578 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
580 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
581 &entry, sizeof(entry));
583 /* set head and tail to zero manually */
584 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
585 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
587 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
590 static void __init free_event_buffer(struct amd_iommu *iommu)
592 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
595 /* allocates the memory where the IOMMU will log its events to */
596 static u8 * __init alloc_ppr_log(struct amd_iommu *iommu)
598 iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
599 get_order(PPR_LOG_SIZE));
601 if (iommu->ppr_log == NULL)
604 return iommu->ppr_log;
607 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
611 if (iommu->ppr_log == NULL)
614 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
616 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
617 &entry, sizeof(entry));
619 /* set head and tail to zero manually */
620 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
621 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
623 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
624 iommu_feature_enable(iommu, CONTROL_PPR_EN);
627 static void __init free_ppr_log(struct amd_iommu *iommu)
629 if (iommu->ppr_log == NULL)
632 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
635 static void iommu_enable_gt(struct amd_iommu *iommu)
637 if (!iommu_feature(iommu, FEATURE_GT))
640 iommu_feature_enable(iommu, CONTROL_GT_EN);
643 /* sets a specific bit in the device table entry. */
644 static void set_dev_entry_bit(u16 devid, u8 bit)
646 int i = (bit >> 6) & 0x03;
647 int _bit = bit & 0x3f;
649 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
652 static int get_dev_entry_bit(u16 devid, u8 bit)
654 int i = (bit >> 6) & 0x03;
655 int _bit = bit & 0x3f;
657 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
661 void amd_iommu_apply_erratum_63(u16 devid)
665 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
666 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
669 set_dev_entry_bit(devid, DEV_ENTRY_IW);
672 /* Writes the specific IOMMU for a device into the rlookup table */
673 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
675 amd_iommu_rlookup_table[devid] = iommu;
679 * This function takes the device specific flags read from the ACPI
680 * table and sets up the device table entry with that information
682 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
683 u16 devid, u32 flags, u32 ext_flags)
685 if (flags & ACPI_DEVFLAG_INITPASS)
686 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
687 if (flags & ACPI_DEVFLAG_EXTINT)
688 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
689 if (flags & ACPI_DEVFLAG_NMI)
690 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
691 if (flags & ACPI_DEVFLAG_SYSMGT1)
692 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
693 if (flags & ACPI_DEVFLAG_SYSMGT2)
694 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
695 if (flags & ACPI_DEVFLAG_LINT0)
696 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
697 if (flags & ACPI_DEVFLAG_LINT1)
698 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
700 amd_iommu_apply_erratum_63(devid);
702 set_iommu_for_device(iommu, devid);
705 static int add_special_device(u8 type, u8 id, u16 devid)
707 struct devid_map *entry;
708 struct list_head *list;
710 if (type != IVHD_SPECIAL_IOAPIC && type != IVHD_SPECIAL_HPET)
713 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
718 entry->devid = devid;
720 if (type == IVHD_SPECIAL_IOAPIC)
725 list_add_tail(&entry->list, list);
731 * Reads the device exclusion range from ACPI and initialize IOMMU with
734 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
736 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
738 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
743 * We only can configure exclusion ranges per IOMMU, not
744 * per device. But we can enable the exclusion range per
745 * device. This is done here
747 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
748 iommu->exclusion_start = m->range_start;
749 iommu->exclusion_length = m->range_length;
754 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
755 * initializes the hardware and our data structures with it.
757 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
758 struct ivhd_header *h)
761 u8 *end = p, flags = 0;
762 u16 devid = 0, devid_start = 0, devid_to = 0;
763 u32 dev_i, ext_flags = 0;
765 struct ivhd_entry *e;
768 * First save the recommended feature enable bits from ACPI
770 iommu->acpi_flags = h->flags;
773 * Done. Now parse the device entries
775 p += sizeof(struct ivhd_header);
780 e = (struct ivhd_entry *)p;
784 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
785 " last device %02x:%02x.%x flags: %02x\n",
786 PCI_BUS(iommu->first_device),
787 PCI_SLOT(iommu->first_device),
788 PCI_FUNC(iommu->first_device),
789 PCI_BUS(iommu->last_device),
790 PCI_SLOT(iommu->last_device),
791 PCI_FUNC(iommu->last_device),
794 for (dev_i = iommu->first_device;
795 dev_i <= iommu->last_device; ++dev_i)
796 set_dev_entry_from_acpi(iommu, dev_i,
799 case IVHD_DEV_SELECT:
801 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
809 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
811 case IVHD_DEV_SELECT_RANGE_START:
813 DUMP_printk(" DEV_SELECT_RANGE_START\t "
814 "devid: %02x:%02x.%x flags: %02x\n",
820 devid_start = e->devid;
827 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
828 "flags: %02x devid_to: %02x:%02x.%x\n",
833 PCI_BUS(e->ext >> 8),
834 PCI_SLOT(e->ext >> 8),
835 PCI_FUNC(e->ext >> 8));
838 devid_to = e->ext >> 8;
839 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
840 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
841 amd_iommu_alias_table[devid] = devid_to;
843 case IVHD_DEV_ALIAS_RANGE:
845 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
846 "devid: %02x:%02x.%x flags: %02x "
847 "devid_to: %02x:%02x.%x\n",
852 PCI_BUS(e->ext >> 8),
853 PCI_SLOT(e->ext >> 8),
854 PCI_FUNC(e->ext >> 8));
856 devid_start = e->devid;
858 devid_to = e->ext >> 8;
862 case IVHD_DEV_EXT_SELECT:
864 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
865 "flags: %02x ext: %08x\n",
872 set_dev_entry_from_acpi(iommu, devid, e->flags,
875 case IVHD_DEV_EXT_SELECT_RANGE:
877 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
878 "%02x:%02x.%x flags: %02x ext: %08x\n",
884 devid_start = e->devid;
889 case IVHD_DEV_RANGE_END:
891 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
897 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
899 amd_iommu_alias_table[dev_i] = devid_to;
900 set_dev_entry_from_acpi(iommu,
901 devid_to, flags, ext_flags);
903 set_dev_entry_from_acpi(iommu, dev_i,
907 case IVHD_DEV_SPECIAL: {
913 handle = e->ext & 0xff;
914 devid = (e->ext >> 8) & 0xffff;
915 type = (e->ext >> 24) & 0xff;
917 if (type == IVHD_SPECIAL_IOAPIC)
919 else if (type == IVHD_SPECIAL_HPET)
924 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
930 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
931 ret = add_special_device(type, handle, devid);
940 p += ivhd_entry_length(p);
946 /* Initializes the device->iommu mapping for the driver */
947 static int __init init_iommu_devices(struct amd_iommu *iommu)
951 for (i = iommu->first_device; i <= iommu->last_device; ++i)
952 set_iommu_for_device(iommu, i);
957 static void __init free_iommu_one(struct amd_iommu *iommu)
959 free_command_buffer(iommu);
960 free_event_buffer(iommu);
962 iommu_unmap_mmio_space(iommu);
965 static void __init free_iommu_all(void)
967 struct amd_iommu *iommu, *next;
969 for_each_iommu_safe(iommu, next) {
970 list_del(&iommu->list);
971 free_iommu_one(iommu);
977 * This function clues the initialization function for one IOMMU
978 * together and also allocates the command buffer and programs the
979 * hardware. It does NOT enable the IOMMU. This is done afterwards.
981 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
985 spin_lock_init(&iommu->lock);
987 /* Add IOMMU to internal data structures */
988 list_add_tail(&iommu->list, &amd_iommu_list);
989 iommu->index = amd_iommus_present++;
991 if (unlikely(iommu->index >= MAX_IOMMUS)) {
992 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
996 /* Index is fine - add IOMMU to the array */
997 amd_iommus[iommu->index] = iommu;
1000 * Copy data from ACPI table entry to the iommu struct
1002 iommu->devid = h->devid;
1003 iommu->cap_ptr = h->cap_ptr;
1004 iommu->pci_seg = h->pci_seg;
1005 iommu->mmio_phys = h->mmio_phys;
1006 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
1007 if (!iommu->mmio_base)
1010 iommu->cmd_buf = alloc_command_buffer(iommu);
1011 if (!iommu->cmd_buf)
1014 iommu->evt_buf = alloc_event_buffer(iommu);
1015 if (!iommu->evt_buf)
1018 iommu->int_enabled = false;
1020 ret = init_iommu_from_acpi(iommu, h);
1023 init_iommu_devices(iommu);
1029 * Iterates over all IOMMU entries in the ACPI table, allocates the
1030 * IOMMU structure and initializes it with init_iommu_one()
1032 static int __init init_iommu_all(struct acpi_table_header *table)
1034 u8 *p = (u8 *)table, *end = (u8 *)table;
1035 struct ivhd_header *h;
1036 struct amd_iommu *iommu;
1039 end += table->length;
1040 p += IVRS_HEADER_LENGTH;
1043 h = (struct ivhd_header *)p;
1045 case ACPI_IVHD_TYPE:
1047 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1048 "seg: %d flags: %01x info %04x\n",
1049 PCI_BUS(h->devid), PCI_SLOT(h->devid),
1050 PCI_FUNC(h->devid), h->cap_ptr,
1051 h->pci_seg, h->flags, h->info);
1052 DUMP_printk(" mmio-addr: %016llx\n",
1055 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1059 ret = init_iommu_one(iommu, h);
1074 static int iommu_init_pci(struct amd_iommu *iommu)
1076 int cap_ptr = iommu->cap_ptr;
1077 u32 range, misc, low, high;
1079 iommu->dev = pci_get_bus_and_slot(PCI_BUS(iommu->devid),
1080 iommu->devid & 0xff);
1084 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1086 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1088 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1091 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
1092 MMIO_GET_FD(range));
1093 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
1094 MMIO_GET_LD(range));
1096 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1097 amd_iommu_iotlb_sup = false;
1099 /* read extended feature bits */
1100 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1101 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1103 iommu->features = ((u64)high << 32) | low;
1105 if (iommu_feature(iommu, FEATURE_GT)) {
1110 shift = iommu->features & FEATURE_PASID_MASK;
1111 shift >>= FEATURE_PASID_SHIFT;
1112 pasids = (1 << shift);
1114 amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids);
1116 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1117 glxval >>= FEATURE_GLXVAL_SHIFT;
1119 if (amd_iommu_max_glx_val == -1)
1120 amd_iommu_max_glx_val = glxval;
1122 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1125 if (iommu_feature(iommu, FEATURE_GT) &&
1126 iommu_feature(iommu, FEATURE_PPR)) {
1127 iommu->is_iommu_v2 = true;
1128 amd_iommu_v2_present = true;
1131 if (iommu_feature(iommu, FEATURE_PPR)) {
1132 iommu->ppr_log = alloc_ppr_log(iommu);
1133 if (!iommu->ppr_log)
1137 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1138 amd_iommu_np_cache = true;
1140 if (is_rd890_iommu(iommu->dev)) {
1143 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1147 * Some rd890 systems may not be fully reconfigured by the
1148 * BIOS, so it's necessary for us to store this information so
1149 * it can be reprogrammed on resume
1151 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1152 &iommu->stored_addr_lo);
1153 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1154 &iommu->stored_addr_hi);
1156 /* Low bit locks writes to configuration space */
1157 iommu->stored_addr_lo &= ~1;
1159 for (i = 0; i < 6; i++)
1160 for (j = 0; j < 0x12; j++)
1161 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1163 for (i = 0; i < 0x83; i++)
1164 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1167 return pci_enable_device(iommu->dev);
1170 static void print_iommu_info(void)
1172 static const char * const feat_str[] = {
1173 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1174 "IA", "GA", "HE", "PC"
1176 struct amd_iommu *iommu;
1178 for_each_iommu(iommu) {
1181 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1182 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1184 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1185 pr_info("AMD-Vi: Extended features: ");
1186 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1187 if (iommu_feature(iommu, (1ULL << i)))
1188 pr_cont(" %s", feat_str[i]);
1195 static int __init amd_iommu_init_pci(void)
1197 struct amd_iommu *iommu;
1200 for_each_iommu(iommu) {
1201 ret = iommu_init_pci(iommu);
1206 ret = amd_iommu_init_devices();
1213 /****************************************************************************
1215 * The following functions initialize the MSI interrupts for all IOMMUs
1216 * in the system. Its a bit challenging because there could be multiple
1217 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1220 ****************************************************************************/
1222 static int iommu_setup_msi(struct amd_iommu *iommu)
1226 r = pci_enable_msi(iommu->dev);
1230 r = request_threaded_irq(iommu->dev->irq,
1231 amd_iommu_int_handler,
1232 amd_iommu_int_thread,
1237 pci_disable_msi(iommu->dev);
1241 iommu->int_enabled = true;
1246 static int iommu_init_msi(struct amd_iommu *iommu)
1250 if (iommu->int_enabled)
1253 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
1254 ret = iommu_setup_msi(iommu);
1262 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1264 if (iommu->ppr_log != NULL)
1265 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1270 /****************************************************************************
1272 * The next functions belong to the third pass of parsing the ACPI
1273 * table. In this last pass the memory mapping requirements are
1274 * gathered (like exclusion and unity mapping reanges).
1276 ****************************************************************************/
1278 static void __init free_unity_maps(void)
1280 struct unity_map_entry *entry, *next;
1282 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1283 list_del(&entry->list);
1288 /* called when we find an exclusion range definition in ACPI */
1289 static int __init init_exclusion_range(struct ivmd_header *m)
1294 case ACPI_IVMD_TYPE:
1295 set_device_exclusion_range(m->devid, m);
1297 case ACPI_IVMD_TYPE_ALL:
1298 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1299 set_device_exclusion_range(i, m);
1301 case ACPI_IVMD_TYPE_RANGE:
1302 for (i = m->devid; i <= m->aux; ++i)
1303 set_device_exclusion_range(i, m);
1312 /* called for unity map ACPI definition */
1313 static int __init init_unity_map_range(struct ivmd_header *m)
1315 struct unity_map_entry *e = NULL;
1318 e = kzalloc(sizeof(*e), GFP_KERNEL);
1326 case ACPI_IVMD_TYPE:
1327 s = "IVMD_TYPEi\t\t\t";
1328 e->devid_start = e->devid_end = m->devid;
1330 case ACPI_IVMD_TYPE_ALL:
1331 s = "IVMD_TYPE_ALL\t\t";
1333 e->devid_end = amd_iommu_last_bdf;
1335 case ACPI_IVMD_TYPE_RANGE:
1336 s = "IVMD_TYPE_RANGE\t\t";
1337 e->devid_start = m->devid;
1338 e->devid_end = m->aux;
1341 e->address_start = PAGE_ALIGN(m->range_start);
1342 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1343 e->prot = m->flags >> 1;
1345 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1346 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1347 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1348 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1349 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1350 e->address_start, e->address_end, m->flags);
1352 list_add_tail(&e->list, &amd_iommu_unity_map);
1357 /* iterates over all memory definitions we find in the ACPI table */
1358 static int __init init_memory_definitions(struct acpi_table_header *table)
1360 u8 *p = (u8 *)table, *end = (u8 *)table;
1361 struct ivmd_header *m;
1363 end += table->length;
1364 p += IVRS_HEADER_LENGTH;
1367 m = (struct ivmd_header *)p;
1368 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1369 init_exclusion_range(m);
1370 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1371 init_unity_map_range(m);
1380 * Init the device table to not allow DMA access for devices and
1381 * suppress all page faults
1383 static void init_device_table(void)
1387 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1388 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1389 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1393 static void iommu_init_flags(struct amd_iommu *iommu)
1395 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1396 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1397 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1399 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1400 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1401 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1403 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1404 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1405 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1407 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1408 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1409 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1412 * make IOMMU memory accesses cache coherent
1414 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1416 /* Set IOTLB invalidation timeout to 1s */
1417 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1420 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1423 u32 ioc_feature_control;
1424 struct pci_dev *pdev = iommu->root_pdev;
1426 /* RD890 BIOSes may not have completely reconfigured the iommu */
1427 if (!is_rd890_iommu(iommu->dev) || !pdev)
1431 * First, we need to ensure that the iommu is enabled. This is
1432 * controlled by a register in the northbridge
1435 /* Select Northbridge indirect register 0x75 and enable writing */
1436 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1437 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1439 /* Enable the iommu */
1440 if (!(ioc_feature_control & 0x1))
1441 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1443 /* Restore the iommu BAR */
1444 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1445 iommu->stored_addr_lo);
1446 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1447 iommu->stored_addr_hi);
1449 /* Restore the l1 indirect regs for each of the 6 l1s */
1450 for (i = 0; i < 6; i++)
1451 for (j = 0; j < 0x12; j++)
1452 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1454 /* Restore the l2 indirect regs */
1455 for (i = 0; i < 0x83; i++)
1456 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1458 /* Lock PCI setup registers */
1459 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1460 iommu->stored_addr_lo | 1);
1464 * This function finally enables all IOMMUs found in the system after
1465 * they have been initialized
1467 static void early_enable_iommus(void)
1469 struct amd_iommu *iommu;
1471 for_each_iommu(iommu) {
1472 iommu_disable(iommu);
1473 iommu_init_flags(iommu);
1474 iommu_set_device_table(iommu);
1475 iommu_enable_command_buffer(iommu);
1476 iommu_enable_event_buffer(iommu);
1477 iommu_set_exclusion_range(iommu);
1478 iommu_enable(iommu);
1479 iommu_flush_all_caches(iommu);
1483 static void enable_iommus_v2(void)
1485 struct amd_iommu *iommu;
1487 for_each_iommu(iommu) {
1488 iommu_enable_ppr_log(iommu);
1489 iommu_enable_gt(iommu);
1493 static void enable_iommus(void)
1495 early_enable_iommus();
1500 static void disable_iommus(void)
1502 struct amd_iommu *iommu;
1504 for_each_iommu(iommu)
1505 iommu_disable(iommu);
1509 * Suspend/Resume support
1510 * disable suspend until real resume implemented
1513 static void amd_iommu_resume(void)
1515 struct amd_iommu *iommu;
1517 for_each_iommu(iommu)
1518 iommu_apply_resume_quirks(iommu);
1520 /* re-load the hardware */
1523 amd_iommu_enable_interrupts();
1526 static int amd_iommu_suspend(void)
1528 /* disable IOMMUs to go out of the way for BIOS */
1534 static struct syscore_ops amd_iommu_syscore_ops = {
1535 .suspend = amd_iommu_suspend,
1536 .resume = amd_iommu_resume,
1539 static void __init free_on_init_error(void)
1541 free_pages((unsigned long)irq_lookup_table,
1542 get_order(rlookup_table_size));
1544 if (amd_iommu_irq_cache) {
1545 kmem_cache_destroy(amd_iommu_irq_cache);
1546 amd_iommu_irq_cache = NULL;
1550 amd_iommu_uninit_devices();
1552 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1553 get_order(MAX_DOMAIN_ID/8));
1555 free_pages((unsigned long)amd_iommu_rlookup_table,
1556 get_order(rlookup_table_size));
1558 free_pages((unsigned long)amd_iommu_alias_table,
1559 get_order(alias_table_size));
1561 free_pages((unsigned long)amd_iommu_dev_table,
1562 get_order(dev_table_size));
1568 #ifdef CONFIG_GART_IOMMU
1570 * We failed to initialize the AMD IOMMU - try fallback to GART
1579 * This is the hardware init function for AMD IOMMU in the system.
1580 * This function is called either from amd_iommu_init or from the interrupt
1581 * remapping setup code.
1583 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1586 * 1 pass) Find the highest PCI device id the driver has to handle.
1587 * Upon this information the size of the data structures is
1588 * determined that needs to be allocated.
1590 * 2 pass) Initialize the data structures just allocated with the
1591 * information in the ACPI table about available AMD IOMMUs
1592 * in the system. It also maps the PCI devices in the
1593 * system to specific IOMMUs
1595 * 3 pass) After the basic data structures are allocated and
1596 * initialized we update them with information about memory
1597 * remapping requirements parsed out of the ACPI table in
1600 * After everything is set up the IOMMUs are enabled and the necessary
1601 * hotplug and suspend notifiers are registered.
1603 static int __init early_amd_iommu_init(void)
1605 struct acpi_table_header *ivrs_base;
1606 acpi_size ivrs_size;
1610 if (!amd_iommu_detected)
1613 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1614 if (status == AE_NOT_FOUND)
1616 else if (ACPI_FAILURE(status)) {
1617 const char *err = acpi_format_exception(status);
1618 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1623 * First parse ACPI tables to find the largest Bus/Dev/Func
1624 * we need to handle. Upon this information the shared data
1625 * structures for the IOMMUs in the system will be allocated
1627 ret = find_last_devid_acpi(ivrs_base);
1631 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1632 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1633 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1635 /* Device table - directly used by all IOMMUs */
1637 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1638 get_order(dev_table_size));
1639 if (amd_iommu_dev_table == NULL)
1643 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1644 * IOMMU see for that device
1646 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1647 get_order(alias_table_size));
1648 if (amd_iommu_alias_table == NULL)
1651 /* IOMMU rlookup table - find the IOMMU for a specific device */
1652 amd_iommu_rlookup_table = (void *)__get_free_pages(
1653 GFP_KERNEL | __GFP_ZERO,
1654 get_order(rlookup_table_size));
1655 if (amd_iommu_rlookup_table == NULL)
1658 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1659 GFP_KERNEL | __GFP_ZERO,
1660 get_order(MAX_DOMAIN_ID/8));
1661 if (amd_iommu_pd_alloc_bitmap == NULL)
1664 /* init the device table */
1665 init_device_table();
1668 * let all alias entries point to itself
1670 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1671 amd_iommu_alias_table[i] = i;
1674 * never allocate domain 0 because its used as the non-allocated and
1675 * error value placeholder
1677 amd_iommu_pd_alloc_bitmap[0] = 1;
1679 spin_lock_init(&amd_iommu_pd_lock);
1682 * now the data structures are allocated and basically initialized
1683 * start the real acpi table scan
1685 ret = init_iommu_all(ivrs_base);
1689 if (amd_iommu_irq_remap) {
1691 * Interrupt remapping enabled, create kmem_cache for the
1694 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
1695 MAX_IRQS_PER_TABLE * sizeof(u32),
1696 IRQ_TABLE_ALIGNMENT,
1698 if (!amd_iommu_irq_cache)
1701 irq_lookup_table = (void *)__get_free_pages(
1702 GFP_KERNEL | __GFP_ZERO,
1703 get_order(rlookup_table_size));
1704 if (!irq_lookup_table)
1708 ret = init_memory_definitions(ivrs_base);
1713 /* Don't leak any ACPI memory */
1714 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1720 static int amd_iommu_enable_interrupts(void)
1722 struct amd_iommu *iommu;
1725 for_each_iommu(iommu) {
1726 ret = iommu_init_msi(iommu);
1735 static bool detect_ivrs(void)
1737 struct acpi_table_header *ivrs_base;
1738 acpi_size ivrs_size;
1741 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1742 if (status == AE_NOT_FOUND)
1744 else if (ACPI_FAILURE(status)) {
1745 const char *err = acpi_format_exception(status);
1746 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1750 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1752 /* Make sure ACS will be enabled during PCI probe */
1755 if (!disable_irq_remap)
1756 amd_iommu_irq_remap = true;
1761 static int amd_iommu_init_dma(void)
1765 if (iommu_pass_through)
1766 ret = amd_iommu_init_passthrough();
1768 ret = amd_iommu_init_dma_ops();
1773 amd_iommu_init_api();
1775 amd_iommu_init_notifier();
1780 /****************************************************************************
1782 * AMD IOMMU Initialization State Machine
1784 ****************************************************************************/
1786 static int __init state_next(void)
1790 switch (init_state) {
1791 case IOMMU_START_STATE:
1792 if (!detect_ivrs()) {
1793 init_state = IOMMU_NOT_FOUND;
1796 init_state = IOMMU_IVRS_DETECTED;
1799 case IOMMU_IVRS_DETECTED:
1800 ret = early_amd_iommu_init();
1801 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
1803 case IOMMU_ACPI_FINISHED:
1804 early_enable_iommus();
1805 register_syscore_ops(&amd_iommu_syscore_ops);
1806 x86_platform.iommu_shutdown = disable_iommus;
1807 init_state = IOMMU_ENABLED;
1810 ret = amd_iommu_init_pci();
1811 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
1814 case IOMMU_PCI_INIT:
1815 ret = amd_iommu_enable_interrupts();
1816 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
1818 case IOMMU_INTERRUPTS_EN:
1819 ret = amd_iommu_init_dma();
1820 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
1823 init_state = IOMMU_INITIALIZED;
1825 case IOMMU_INITIALIZED:
1828 case IOMMU_NOT_FOUND:
1829 case IOMMU_INIT_ERROR:
1830 /* Error states => do nothing */
1841 static int __init iommu_go_to_state(enum iommu_init_state state)
1845 while (init_state != state) {
1847 if (init_state == IOMMU_NOT_FOUND ||
1848 init_state == IOMMU_INIT_ERROR)
1858 * This is the core init function for AMD IOMMU hardware in the system.
1859 * This function is called from the generic x86 DMA layer initialization
1862 static int __init amd_iommu_init(void)
1866 ret = iommu_go_to_state(IOMMU_INITIALIZED);
1869 free_on_init_error();
1875 /****************************************************************************
1877 * Early detect code. This code runs at IOMMU detection time in the DMA
1878 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1881 ****************************************************************************/
1882 int __init amd_iommu_detect(void)
1886 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
1889 if (amd_iommu_disabled)
1892 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
1896 amd_iommu_detected = true;
1898 x86_init.iommu.iommu_init = amd_iommu_init;
1903 /****************************************************************************
1905 * Parsing functions for the AMD IOMMU specific kernel command line
1908 ****************************************************************************/
1910 static int __init parse_amd_iommu_dump(char *str)
1912 amd_iommu_dump = true;
1917 static int __init parse_amd_iommu_options(char *str)
1919 for (; *str; ++str) {
1920 if (strncmp(str, "fullflush", 9) == 0)
1921 amd_iommu_unmap_flush = true;
1922 if (strncmp(str, "off", 3) == 0)
1923 amd_iommu_disabled = true;
1924 if (strncmp(str, "force_isolation", 15) == 0)
1925 amd_iommu_force_isolation = true;
1931 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1932 __setup("amd_iommu=", parse_amd_iommu_options);
1934 IOMMU_INIT_FINISH(amd_iommu_detect,
1935 gart_iommu_hole_init,
1939 bool amd_iommu_v2_supported(void)
1941 return amd_iommu_v2_present;
1943 EXPORT_SYMBOL(amd_iommu_v2_supported);