2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dma-direct.h>
32 #include <linux/iommu-helper.h>
33 #include <linux/iommu.h>
34 #include <linux/delay.h>
35 #include <linux/amd-iommu.h>
36 #include <linux/notifier.h>
37 #include <linux/export.h>
38 #include <linux/irq.h>
39 #include <linux/msi.h>
40 #include <linux/dma-contiguous.h>
41 #include <linux/irqdomain.h>
42 #include <linux/percpu.h>
43 #include <linux/iova.h>
44 #include <asm/irq_remapping.h>
45 #include <asm/io_apic.h>
47 #include <asm/hw_irq.h>
48 #include <asm/msidef.h>
49 #include <asm/proto.h>
50 #include <asm/iommu.h>
54 #include "amd_iommu_proto.h"
55 #include "amd_iommu_types.h"
56 #include "irq_remapping.h"
58 #define AMD_IOMMU_MAPPING_ERROR 0
60 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
62 #define LOOP_TIMEOUT 100000
64 /* IO virtual address start page frame number */
65 #define IOVA_START_PFN (1)
66 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
68 /* Reserved IOVA ranges */
69 #define MSI_RANGE_START (0xfee00000)
70 #define MSI_RANGE_END (0xfeefffff)
71 #define HT_RANGE_START (0xfd00000000ULL)
72 #define HT_RANGE_END (0xffffffffffULL)
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
80 * 512GB Pages are not supported due to a hardware bug
82 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
84 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
85 static DEFINE_SPINLOCK(pd_bitmap_lock);
87 /* List of all available dev_data structures */
88 static LLIST_HEAD(dev_data_list);
90 LIST_HEAD(ioapic_map);
92 LIST_HEAD(acpihid_map);
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
98 const struct iommu_ops amd_iommu_ops;
100 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
101 int amd_iommu_max_glx_val = -1;
103 static const struct dma_map_ops amd_iommu_dma_ops;
106 * general struct to manage commands send to an IOMMU
112 struct kmem_cache *amd_iommu_irq_cache;
114 static void update_domain(struct protection_domain *domain);
115 static int protection_domain_init(struct protection_domain *domain);
116 static void detach_device(struct device *dev);
117 static void iova_domain_flush_tlb(struct iova_domain *iovad);
120 * Data container for a dma_ops specific protection domain
122 struct dma_ops_domain {
123 /* generic protection domain information */
124 struct protection_domain domain;
127 struct iova_domain iovad;
130 static struct iova_domain reserved_iova_ranges;
131 static struct lock_class_key reserved_rbtree_key;
133 /****************************************************************************
137 ****************************************************************************/
139 static inline int match_hid_uid(struct device *dev,
140 struct acpihid_map_entry *entry)
142 const char *hid, *uid;
144 hid = acpi_device_hid(ACPI_COMPANION(dev));
145 uid = acpi_device_uid(ACPI_COMPANION(dev));
151 return strcmp(hid, entry->hid);
154 return strcmp(hid, entry->hid);
156 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
159 static inline u16 get_pci_device_id(struct device *dev)
161 struct pci_dev *pdev = to_pci_dev(dev);
163 return PCI_DEVID(pdev->bus->number, pdev->devfn);
166 static inline int get_acpihid_device_id(struct device *dev,
167 struct acpihid_map_entry **entry)
169 struct acpihid_map_entry *p;
171 list_for_each_entry(p, &acpihid_map, list) {
172 if (!match_hid_uid(dev, p)) {
181 static inline int get_device_id(struct device *dev)
186 devid = get_pci_device_id(dev);
188 devid = get_acpihid_device_id(dev, NULL);
193 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
195 return container_of(dom, struct protection_domain, domain);
198 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
200 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
201 return container_of(domain, struct dma_ops_domain, domain);
204 static struct iommu_dev_data *alloc_dev_data(u16 devid)
206 struct iommu_dev_data *dev_data;
208 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
212 dev_data->devid = devid;
213 ratelimit_default_init(&dev_data->rs);
215 llist_add(&dev_data->dev_data_list, &dev_data_list);
219 static struct iommu_dev_data *search_dev_data(u16 devid)
221 struct iommu_dev_data *dev_data;
222 struct llist_node *node;
224 if (llist_empty(&dev_data_list))
227 node = dev_data_list.first;
228 llist_for_each_entry(dev_data, node, dev_data_list) {
229 if (dev_data->devid == devid)
236 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
238 *(u16 *)data = alias;
242 static u16 get_alias(struct device *dev)
244 struct pci_dev *pdev = to_pci_dev(dev);
245 u16 devid, ivrs_alias, pci_alias;
247 /* The callers make sure that get_device_id() does not fail here */
248 devid = get_device_id(dev);
250 /* For ACPI HID devices, we simply return the devid as such */
251 if (!dev_is_pci(dev))
254 ivrs_alias = amd_iommu_alias_table[devid];
256 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
258 if (ivrs_alias == pci_alias)
264 * The IVRS is fairly reliable in telling us about aliases, but it
265 * can't know about every screwy device. If we don't have an IVRS
266 * reported alias, use the PCI reported alias. In that case we may
267 * still need to initialize the rlookup and dev_table entries if the
268 * alias is to a non-existent device.
270 if (ivrs_alias == devid) {
271 if (!amd_iommu_rlookup_table[pci_alias]) {
272 amd_iommu_rlookup_table[pci_alias] =
273 amd_iommu_rlookup_table[devid];
274 memcpy(amd_iommu_dev_table[pci_alias].data,
275 amd_iommu_dev_table[devid].data,
276 sizeof(amd_iommu_dev_table[pci_alias].data));
282 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
283 "for device %s[%04x:%04x], kernel reported alias "
284 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
285 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
286 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
287 PCI_FUNC(pci_alias));
290 * If we don't have a PCI DMA alias and the IVRS alias is on the same
291 * bus, then the IVRS table may know about a quirk that we don't.
293 if (pci_alias == devid &&
294 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
295 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
296 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
297 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
304 static struct iommu_dev_data *find_dev_data(u16 devid)
306 struct iommu_dev_data *dev_data;
307 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
309 dev_data = search_dev_data(devid);
311 if (dev_data == NULL) {
312 dev_data = alloc_dev_data(devid);
316 if (translation_pre_enabled(iommu))
317 dev_data->defer_attach = true;
323 struct iommu_dev_data *get_dev_data(struct device *dev)
325 return dev->archdata.iommu;
327 EXPORT_SYMBOL(get_dev_data);
330 * Find or create an IOMMU group for a acpihid device.
332 static struct iommu_group *acpihid_device_group(struct device *dev)
334 struct acpihid_map_entry *p, *entry = NULL;
337 devid = get_acpihid_device_id(dev, &entry);
339 return ERR_PTR(devid);
341 list_for_each_entry(p, &acpihid_map, list) {
342 if ((devid == p->devid) && p->group)
343 entry->group = p->group;
347 entry->group = generic_device_group(dev);
349 iommu_group_ref_get(entry->group);
354 static bool pci_iommuv2_capable(struct pci_dev *pdev)
356 static const int caps[] = {
359 PCI_EXT_CAP_ID_PASID,
363 if (pci_ats_disabled())
366 for (i = 0; i < 3; ++i) {
367 pos = pci_find_ext_capability(pdev, caps[i]);
375 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
377 struct iommu_dev_data *dev_data;
379 dev_data = get_dev_data(&pdev->dev);
381 return dev_data->errata & (1 << erratum) ? true : false;
385 * This function checks if the driver got a valid device from the caller to
386 * avoid dereferencing invalid pointers.
388 static bool check_device(struct device *dev)
392 if (!dev || !dev->dma_mask)
395 devid = get_device_id(dev);
399 /* Out of our scope? */
400 if (devid > amd_iommu_last_bdf)
403 if (amd_iommu_rlookup_table[devid] == NULL)
409 static void init_iommu_group(struct device *dev)
411 struct iommu_group *group;
413 group = iommu_group_get_for_dev(dev);
417 iommu_group_put(group);
420 static int iommu_init_device(struct device *dev)
422 struct iommu_dev_data *dev_data;
423 struct amd_iommu *iommu;
426 if (dev->archdata.iommu)
429 devid = get_device_id(dev);
433 iommu = amd_iommu_rlookup_table[devid];
435 dev_data = find_dev_data(devid);
439 dev_data->alias = get_alias(dev);
441 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
442 struct amd_iommu *iommu;
444 iommu = amd_iommu_rlookup_table[dev_data->devid];
445 dev_data->iommu_v2 = iommu->is_iommu_v2;
448 dev->archdata.iommu = dev_data;
450 iommu_device_link(&iommu->iommu, dev);
455 static void iommu_ignore_device(struct device *dev)
460 devid = get_device_id(dev);
464 alias = get_alias(dev);
466 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
467 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
469 amd_iommu_rlookup_table[devid] = NULL;
470 amd_iommu_rlookup_table[alias] = NULL;
473 static void iommu_uninit_device(struct device *dev)
475 struct iommu_dev_data *dev_data;
476 struct amd_iommu *iommu;
479 devid = get_device_id(dev);
483 iommu = amd_iommu_rlookup_table[devid];
485 dev_data = search_dev_data(devid);
489 if (dev_data->domain)
492 iommu_device_unlink(&iommu->iommu, dev);
494 iommu_group_remove_device(dev);
500 * We keep dev_data around for unplugged devices and reuse it when the
501 * device is re-plugged - not doing so would introduce a ton of races.
505 /****************************************************************************
507 * Interrupt handling functions
509 ****************************************************************************/
511 static void dump_dte_entry(u16 devid)
515 for (i = 0; i < 4; ++i)
516 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
517 amd_iommu_dev_table[devid].data[i]);
520 static void dump_command(unsigned long phys_addr)
522 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
525 for (i = 0; i < 4; ++i)
526 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
529 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
530 u64 address, int flags)
532 struct iommu_dev_data *dev_data = NULL;
533 struct pci_dev *pdev;
535 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
538 dev_data = get_dev_data(&pdev->dev);
540 if (dev_data && __ratelimit(&dev_data->rs)) {
541 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
542 domain_id, address, flags);
543 } else if (printk_ratelimit()) {
544 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
545 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
546 domain_id, address, flags);
553 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
555 struct device *dev = iommu->iommu.dev;
556 int type, devid, pasid, flags, tag;
557 volatile u32 *event = __evt;
562 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
563 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
564 pasid = PPR_PASID(*(u64 *)&event[0]);
565 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
566 address = (u64)(((u64)event[3]) << 32) | event[2];
569 /* Did we hit the erratum? */
570 if (++count == LOOP_TIMEOUT) {
571 pr_err("AMD-Vi: No event written to event log\n");
578 if (type == EVENT_TYPE_IO_FAULT) {
579 amd_iommu_report_page_fault(devid, pasid, address, flags);
582 dev_err(dev, "AMD-Vi: Event logged [");
586 case EVENT_TYPE_ILL_DEV:
587 dev_err(dev, "ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
588 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
589 pasid, address, flags);
590 dump_dte_entry(devid);
592 case EVENT_TYPE_DEV_TAB_ERR:
593 dev_err(dev, "DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
594 "address=0x%016llx flags=0x%04x]\n",
595 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
598 case EVENT_TYPE_PAGE_TAB_ERR:
599 dev_err(dev, "PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
600 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
601 pasid, address, flags);
603 case EVENT_TYPE_ILL_CMD:
604 dev_err(dev, "ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
605 dump_command(address);
607 case EVENT_TYPE_CMD_HARD_ERR:
608 dev_err(dev, "COMMAND_HARDWARE_ERROR address=0x%016llx flags=0x%04x]\n",
611 case EVENT_TYPE_IOTLB_INV_TO:
612 dev_err(dev, "IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%016llx]\n",
613 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
616 case EVENT_TYPE_INV_DEV_REQ:
617 dev_err(dev, "INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
618 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
619 pasid, address, flags);
621 case EVENT_TYPE_INV_PPR_REQ:
622 pasid = ((event[0] >> 16) & 0xFFFF)
623 | ((event[1] << 6) & 0xF0000);
624 tag = event[1] & 0x03FF;
625 dev_err(dev, "INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
626 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
627 pasid, address, flags);
630 dev_err(dev, "UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
631 event[0], event[1], event[2], event[3]);
634 memset(__evt, 0, 4 * sizeof(u32));
637 static void iommu_poll_events(struct amd_iommu *iommu)
641 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
642 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
644 while (head != tail) {
645 iommu_print_event(iommu, iommu->evt_buf + head);
646 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
649 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
652 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
654 struct amd_iommu_fault fault;
656 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
657 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
661 fault.address = raw[1];
662 fault.pasid = PPR_PASID(raw[0]);
663 fault.device_id = PPR_DEVID(raw[0]);
664 fault.tag = PPR_TAG(raw[0]);
665 fault.flags = PPR_FLAGS(raw[0]);
667 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
670 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
674 if (iommu->ppr_log == NULL)
677 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
678 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
680 while (head != tail) {
685 raw = (u64 *)(iommu->ppr_log + head);
688 * Hardware bug: Interrupt may arrive before the entry is
689 * written to memory. If this happens we need to wait for the
692 for (i = 0; i < LOOP_TIMEOUT; ++i) {
693 if (PPR_REQ_TYPE(raw[0]) != 0)
698 /* Avoid memcpy function-call overhead */
703 * To detect the hardware bug we need to clear the entry
706 raw[0] = raw[1] = 0UL;
708 /* Update head pointer of hardware ring-buffer */
709 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
710 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
712 /* Handle PPR entry */
713 iommu_handle_ppr_entry(iommu, entry);
715 /* Refresh ring-buffer information */
716 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
717 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
721 #ifdef CONFIG_IRQ_REMAP
722 static int (*iommu_ga_log_notifier)(u32);
724 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
726 iommu_ga_log_notifier = notifier;
730 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
732 static void iommu_poll_ga_log(struct amd_iommu *iommu)
734 u32 head, tail, cnt = 0;
736 if (iommu->ga_log == NULL)
739 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
740 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
742 while (head != tail) {
746 raw = (u64 *)(iommu->ga_log + head);
749 /* Avoid memcpy function-call overhead */
752 /* Update head pointer of hardware ring-buffer */
753 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
754 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
756 /* Handle GA entry */
757 switch (GA_REQ_TYPE(log_entry)) {
759 if (!iommu_ga_log_notifier)
762 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
763 __func__, GA_DEVID(log_entry),
766 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
767 pr_err("AMD-Vi: GA log notifier failed.\n");
774 #endif /* CONFIG_IRQ_REMAP */
776 #define AMD_IOMMU_INT_MASK \
777 (MMIO_STATUS_EVT_INT_MASK | \
778 MMIO_STATUS_PPR_INT_MASK | \
779 MMIO_STATUS_GALOG_INT_MASK)
781 irqreturn_t amd_iommu_int_thread(int irq, void *data)
783 struct amd_iommu *iommu = (struct amd_iommu *) data;
784 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
786 while (status & AMD_IOMMU_INT_MASK) {
787 /* Enable EVT and PPR and GA interrupts again */
788 writel(AMD_IOMMU_INT_MASK,
789 iommu->mmio_base + MMIO_STATUS_OFFSET);
791 if (status & MMIO_STATUS_EVT_INT_MASK) {
792 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
793 iommu_poll_events(iommu);
796 if (status & MMIO_STATUS_PPR_INT_MASK) {
797 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
798 iommu_poll_ppr_log(iommu);
801 #ifdef CONFIG_IRQ_REMAP
802 if (status & MMIO_STATUS_GALOG_INT_MASK) {
803 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
804 iommu_poll_ga_log(iommu);
809 * Hardware bug: ERBT1312
810 * When re-enabling interrupt (by writing 1
811 * to clear the bit), the hardware might also try to set
812 * the interrupt bit in the event status register.
813 * In this scenario, the bit will be set, and disable
814 * subsequent interrupts.
816 * Workaround: The IOMMU driver should read back the
817 * status register and check if the interrupt bits are cleared.
818 * If not, driver will need to go through the interrupt handler
819 * again and re-clear the bits
821 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
826 irqreturn_t amd_iommu_int_handler(int irq, void *data)
828 return IRQ_WAKE_THREAD;
831 /****************************************************************************
833 * IOMMU command queuing functions
835 ****************************************************************************/
837 static int wait_on_sem(volatile u64 *sem)
841 while (*sem == 0 && i < LOOP_TIMEOUT) {
846 if (i == LOOP_TIMEOUT) {
847 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
854 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
855 struct iommu_cmd *cmd)
859 target = iommu->cmd_buf + iommu->cmd_buf_tail;
861 iommu->cmd_buf_tail += sizeof(*cmd);
862 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
864 /* Copy command to buffer */
865 memcpy(target, cmd, sizeof(*cmd));
867 /* Tell the IOMMU about it */
868 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
871 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
873 u64 paddr = iommu_virt_to_phys((void *)address);
875 WARN_ON(address & 0x7ULL);
877 memset(cmd, 0, sizeof(*cmd));
878 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
879 cmd->data[1] = upper_32_bits(paddr);
881 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
884 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
886 memset(cmd, 0, sizeof(*cmd));
887 cmd->data[0] = devid;
888 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
891 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
892 size_t size, u16 domid, int pde)
897 pages = iommu_num_pages(address, size, PAGE_SIZE);
902 * If we have to flush more than one page, flush all
903 * TLB entries for this domain
905 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
909 address &= PAGE_MASK;
911 memset(cmd, 0, sizeof(*cmd));
912 cmd->data[1] |= domid;
913 cmd->data[2] = lower_32_bits(address);
914 cmd->data[3] = upper_32_bits(address);
915 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
916 if (s) /* size bit - we flush more than one 4kb page */
917 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
918 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
919 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
922 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
923 u64 address, size_t size)
928 pages = iommu_num_pages(address, size, PAGE_SIZE);
933 * If we have to flush more than one page, flush all
934 * TLB entries for this domain
936 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
940 address &= PAGE_MASK;
942 memset(cmd, 0, sizeof(*cmd));
943 cmd->data[0] = devid;
944 cmd->data[0] |= (qdep & 0xff) << 24;
945 cmd->data[1] = devid;
946 cmd->data[2] = lower_32_bits(address);
947 cmd->data[3] = upper_32_bits(address);
948 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
950 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
953 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
954 u64 address, bool size)
956 memset(cmd, 0, sizeof(*cmd));
958 address &= ~(0xfffULL);
960 cmd->data[0] = pasid;
961 cmd->data[1] = domid;
962 cmd->data[2] = lower_32_bits(address);
963 cmd->data[3] = upper_32_bits(address);
964 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
965 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
967 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
968 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
971 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
972 int qdep, u64 address, bool size)
974 memset(cmd, 0, sizeof(*cmd));
976 address &= ~(0xfffULL);
978 cmd->data[0] = devid;
979 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
980 cmd->data[0] |= (qdep & 0xff) << 24;
981 cmd->data[1] = devid;
982 cmd->data[1] |= (pasid & 0xff) << 16;
983 cmd->data[2] = lower_32_bits(address);
984 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
985 cmd->data[3] = upper_32_bits(address);
987 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
988 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
991 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
992 int status, int tag, bool gn)
994 memset(cmd, 0, sizeof(*cmd));
996 cmd->data[0] = devid;
998 cmd->data[1] = pasid;
999 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1001 cmd->data[3] = tag & 0x1ff;
1002 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1004 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1007 static void build_inv_all(struct iommu_cmd *cmd)
1009 memset(cmd, 0, sizeof(*cmd));
1010 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1013 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1015 memset(cmd, 0, sizeof(*cmd));
1016 cmd->data[0] = devid;
1017 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1021 * Writes the command to the IOMMUs command buffer and informs the
1022 * hardware about the new command.
1024 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1025 struct iommu_cmd *cmd,
1028 unsigned int count = 0;
1029 u32 left, next_tail;
1031 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1033 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1036 /* Skip udelay() the first time around */
1038 if (count == LOOP_TIMEOUT) {
1039 pr_err("AMD-Vi: Command buffer timeout\n");
1046 /* Update head and recheck remaining space */
1047 iommu->cmd_buf_head = readl(iommu->mmio_base +
1048 MMIO_CMD_HEAD_OFFSET);
1053 copy_cmd_to_buffer(iommu, cmd);
1055 /* Do we need to make sure all commands are processed? */
1056 iommu->need_sync = sync;
1061 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1062 struct iommu_cmd *cmd,
1065 unsigned long flags;
1068 raw_spin_lock_irqsave(&iommu->lock, flags);
1069 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1070 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1075 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1077 return iommu_queue_command_sync(iommu, cmd, true);
1081 * This function queues a completion wait command into the command
1082 * buffer of an IOMMU
1084 static int iommu_completion_wait(struct amd_iommu *iommu)
1086 struct iommu_cmd cmd;
1087 unsigned long flags;
1090 if (!iommu->need_sync)
1094 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1096 raw_spin_lock_irqsave(&iommu->lock, flags);
1100 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1104 ret = wait_on_sem(&iommu->cmd_sem);
1107 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1112 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1114 struct iommu_cmd cmd;
1116 build_inv_dte(&cmd, devid);
1118 return iommu_queue_command(iommu, &cmd);
1121 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1125 for (devid = 0; devid <= 0xffff; ++devid)
1126 iommu_flush_dte(iommu, devid);
1128 iommu_completion_wait(iommu);
1132 * This function uses heavy locking and may disable irqs for some time. But
1133 * this is no issue because it is only called during resume.
1135 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1139 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1140 struct iommu_cmd cmd;
1141 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1143 iommu_queue_command(iommu, &cmd);
1146 iommu_completion_wait(iommu);
1149 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1151 struct iommu_cmd cmd;
1153 build_inv_all(&cmd);
1155 iommu_queue_command(iommu, &cmd);
1156 iommu_completion_wait(iommu);
1159 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1161 struct iommu_cmd cmd;
1163 build_inv_irt(&cmd, devid);
1165 iommu_queue_command(iommu, &cmd);
1168 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1172 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1173 iommu_flush_irt(iommu, devid);
1175 iommu_completion_wait(iommu);
1178 void iommu_flush_all_caches(struct amd_iommu *iommu)
1180 if (iommu_feature(iommu, FEATURE_IA)) {
1181 amd_iommu_flush_all(iommu);
1183 amd_iommu_flush_dte_all(iommu);
1184 amd_iommu_flush_irt_all(iommu);
1185 amd_iommu_flush_tlb_all(iommu);
1190 * Command send function for flushing on-device TLB
1192 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1193 u64 address, size_t size)
1195 struct amd_iommu *iommu;
1196 struct iommu_cmd cmd;
1199 qdep = dev_data->ats.qdep;
1200 iommu = amd_iommu_rlookup_table[dev_data->devid];
1202 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1204 return iommu_queue_command(iommu, &cmd);
1208 * Command send function for invalidating a device table entry
1210 static int device_flush_dte(struct iommu_dev_data *dev_data)
1212 struct amd_iommu *iommu;
1216 iommu = amd_iommu_rlookup_table[dev_data->devid];
1217 alias = dev_data->alias;
1219 ret = iommu_flush_dte(iommu, dev_data->devid);
1220 if (!ret && alias != dev_data->devid)
1221 ret = iommu_flush_dte(iommu, alias);
1225 if (dev_data->ats.enabled)
1226 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1232 * TLB invalidation function which is called from the mapping functions.
1233 * It invalidates a single PTE if the range to flush is within a single
1234 * page. Otherwise it flushes the whole TLB of the IOMMU.
1236 static void __domain_flush_pages(struct protection_domain *domain,
1237 u64 address, size_t size, int pde)
1239 struct iommu_dev_data *dev_data;
1240 struct iommu_cmd cmd;
1243 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1245 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1246 if (!domain->dev_iommu[i])
1250 * Devices of this domain are behind this IOMMU
1251 * We need a TLB flush
1253 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1256 list_for_each_entry(dev_data, &domain->dev_list, list) {
1258 if (!dev_data->ats.enabled)
1261 ret |= device_flush_iotlb(dev_data, address, size);
1267 static void domain_flush_pages(struct protection_domain *domain,
1268 u64 address, size_t size)
1270 __domain_flush_pages(domain, address, size, 0);
1273 /* Flush the whole IO/TLB for a given protection domain */
1274 static void domain_flush_tlb(struct protection_domain *domain)
1276 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1279 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1280 static void domain_flush_tlb_pde(struct protection_domain *domain)
1282 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1285 static void domain_flush_complete(struct protection_domain *domain)
1289 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1290 if (domain && !domain->dev_iommu[i])
1294 * Devices of this domain are behind this IOMMU
1295 * We need to wait for completion of all commands.
1297 iommu_completion_wait(amd_iommus[i]);
1303 * This function flushes the DTEs for all devices in domain
1305 static void domain_flush_devices(struct protection_domain *domain)
1307 struct iommu_dev_data *dev_data;
1309 list_for_each_entry(dev_data, &domain->dev_list, list)
1310 device_flush_dte(dev_data);
1313 /****************************************************************************
1315 * The functions below are used the create the page table mappings for
1316 * unity mapped regions.
1318 ****************************************************************************/
1320 static void free_page_list(struct page *freelist)
1322 while (freelist != NULL) {
1323 unsigned long p = (unsigned long)page_address(freelist);
1324 freelist = freelist->freelist;
1329 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1331 struct page *p = virt_to_page((void *)pt);
1333 p->freelist = freelist;
1338 #define DEFINE_FREE_PT_FN(LVL, FN) \
1339 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1347 for (i = 0; i < 512; ++i) { \
1348 /* PTE present? */ \
1349 if (!IOMMU_PTE_PRESENT(pt[i])) \
1353 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1354 PM_PTE_LEVEL(pt[i]) == 7) \
1357 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1358 freelist = FN(p, freelist); \
1361 return free_pt_page((unsigned long)pt, freelist); \
1364 DEFINE_FREE_PT_FN(l2, free_pt_page)
1365 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1366 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1367 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1368 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1370 static struct page *free_sub_pt(unsigned long root, int mode,
1371 struct page *freelist)
1374 case PAGE_MODE_NONE:
1375 case PAGE_MODE_7_LEVEL:
1377 case PAGE_MODE_1_LEVEL:
1378 freelist = free_pt_page(root, freelist);
1380 case PAGE_MODE_2_LEVEL:
1381 freelist = free_pt_l2(root, freelist);
1383 case PAGE_MODE_3_LEVEL:
1384 freelist = free_pt_l3(root, freelist);
1386 case PAGE_MODE_4_LEVEL:
1387 freelist = free_pt_l4(root, freelist);
1389 case PAGE_MODE_5_LEVEL:
1390 freelist = free_pt_l5(root, freelist);
1392 case PAGE_MODE_6_LEVEL:
1393 freelist = free_pt_l6(root, freelist);
1402 static void free_pagetable(struct protection_domain *domain)
1404 unsigned long root = (unsigned long)domain->pt_root;
1405 struct page *freelist = NULL;
1407 BUG_ON(domain->mode < PAGE_MODE_NONE ||
1408 domain->mode > PAGE_MODE_6_LEVEL);
1410 free_sub_pt(root, domain->mode, freelist);
1412 free_page_list(freelist);
1416 * This function is used to add another level to an IO page table. Adding
1417 * another level increases the size of the address space by 9 bits to a size up
1420 static bool increase_address_space(struct protection_domain *domain,
1425 if (domain->mode == PAGE_MODE_6_LEVEL)
1426 /* address space already 64 bit large */
1429 pte = (void *)get_zeroed_page(gfp);
1433 *pte = PM_LEVEL_PDE(domain->mode,
1434 iommu_virt_to_phys(domain->pt_root));
1435 domain->pt_root = pte;
1437 domain->updated = true;
1442 static u64 *alloc_pte(struct protection_domain *domain,
1443 unsigned long address,
1444 unsigned long page_size,
1451 BUG_ON(!is_power_of_2(page_size));
1453 while (address > PM_LEVEL_SIZE(domain->mode))
1454 increase_address_space(domain, gfp);
1456 level = domain->mode - 1;
1457 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1458 address = PAGE_SIZE_ALIGN(address, page_size);
1459 end_lvl = PAGE_SIZE_LEVEL(page_size);
1461 while (level > end_lvl) {
1466 pte_level = PM_PTE_LEVEL(__pte);
1468 if (!IOMMU_PTE_PRESENT(__pte) ||
1469 pte_level == PAGE_MODE_7_LEVEL) {
1470 page = (u64 *)get_zeroed_page(gfp);
1474 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1476 /* pte could have been changed somewhere. */
1477 if (cmpxchg64(pte, __pte, __npte) != __pte)
1478 free_page((unsigned long)page);
1479 else if (pte_level == PAGE_MODE_7_LEVEL)
1480 domain->updated = true;
1485 /* No level skipping support yet */
1486 if (pte_level != level)
1491 pte = IOMMU_PTE_PAGE(__pte);
1493 if (pte_page && level == end_lvl)
1496 pte = &pte[PM_LEVEL_INDEX(level, address)];
1503 * This function checks if there is a PTE for a given dma address. If
1504 * there is one, it returns the pointer to it.
1506 static u64 *fetch_pte(struct protection_domain *domain,
1507 unsigned long address,
1508 unsigned long *page_size)
1515 if (address > PM_LEVEL_SIZE(domain->mode))
1518 level = domain->mode - 1;
1519 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1520 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1525 if (!IOMMU_PTE_PRESENT(*pte))
1529 if (PM_PTE_LEVEL(*pte) == 7 ||
1530 PM_PTE_LEVEL(*pte) == 0)
1533 /* No level skipping support yet */
1534 if (PM_PTE_LEVEL(*pte) != level)
1539 /* Walk to the next level */
1540 pte = IOMMU_PTE_PAGE(*pte);
1541 pte = &pte[PM_LEVEL_INDEX(level, address)];
1542 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1545 if (PM_PTE_LEVEL(*pte) == 0x07) {
1546 unsigned long pte_mask;
1549 * If we have a series of large PTEs, make
1550 * sure to return a pointer to the first one.
1552 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1553 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1554 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1560 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1565 while (cmpxchg64(pte, pteval, 0) != pteval) {
1566 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1570 if (!IOMMU_PTE_PRESENT(pteval))
1573 pt = (unsigned long)IOMMU_PTE_PAGE(pteval);
1574 mode = IOMMU_PTE_MODE(pteval);
1576 return free_sub_pt(pt, mode, freelist);
1580 * Generic mapping functions. It maps a physical address into a DMA
1581 * address space. It allocates the page table pages if necessary.
1582 * In the future it can be extended to a generic mapping function
1583 * supporting all features of AMD IOMMU page tables like level skipping
1584 * and full 64 bit address spaces.
1586 static int iommu_map_page(struct protection_domain *dom,
1587 unsigned long bus_addr,
1588 unsigned long phys_addr,
1589 unsigned long page_size,
1593 struct page *freelist = NULL;
1597 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1598 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1600 if (!(prot & IOMMU_PROT_MASK))
1603 count = PAGE_SIZE_PTE_COUNT(page_size);
1604 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1609 for (i = 0; i < count; ++i)
1610 freelist = free_clear_pte(&pte[i], pte[i], freelist);
1612 if (freelist != NULL)
1613 dom->updated = true;
1616 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1617 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1619 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1621 if (prot & IOMMU_PROT_IR)
1622 __pte |= IOMMU_PTE_IR;
1623 if (prot & IOMMU_PROT_IW)
1624 __pte |= IOMMU_PTE_IW;
1626 for (i = 0; i < count; ++i)
1631 /* Everything flushed out, free pages now */
1632 free_page_list(freelist);
1637 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1638 unsigned long bus_addr,
1639 unsigned long page_size)
1641 unsigned long long unmapped;
1642 unsigned long unmap_size;
1645 BUG_ON(!is_power_of_2(page_size));
1649 while (unmapped < page_size) {
1651 pte = fetch_pte(dom, bus_addr, &unmap_size);
1656 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1657 for (i = 0; i < count; i++)
1661 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1662 unmapped += unmap_size;
1665 BUG_ON(unmapped && !is_power_of_2(unmapped));
1670 /****************************************************************************
1672 * The next functions belong to the address allocator for the dma_ops
1673 * interface functions.
1675 ****************************************************************************/
1678 static unsigned long dma_ops_alloc_iova(struct device *dev,
1679 struct dma_ops_domain *dma_dom,
1680 unsigned int pages, u64 dma_mask)
1682 unsigned long pfn = 0;
1684 pages = __roundup_pow_of_two(pages);
1686 if (dma_mask > DMA_BIT_MASK(32))
1687 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1688 IOVA_PFN(DMA_BIT_MASK(32)), false);
1691 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1692 IOVA_PFN(dma_mask), true);
1694 return (pfn << PAGE_SHIFT);
1697 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1698 unsigned long address,
1701 pages = __roundup_pow_of_two(pages);
1702 address >>= PAGE_SHIFT;
1704 free_iova_fast(&dma_dom->iovad, address, pages);
1707 /****************************************************************************
1709 * The next functions belong to the domain allocation. A domain is
1710 * allocated for every IOMMU as the default domain. If device isolation
1711 * is enabled, every device get its own domain. The most important thing
1712 * about domains is the page table mapping the DMA address space they
1715 ****************************************************************************/
1718 * This function adds a protection domain to the global protection domain list
1720 static void add_domain_to_list(struct protection_domain *domain)
1722 unsigned long flags;
1724 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1725 list_add(&domain->list, &amd_iommu_pd_list);
1726 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1730 * This function removes a protection domain to the global
1731 * protection domain list
1733 static void del_domain_from_list(struct protection_domain *domain)
1735 unsigned long flags;
1737 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1738 list_del(&domain->list);
1739 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1742 static u16 domain_id_alloc(void)
1746 spin_lock(&pd_bitmap_lock);
1747 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1749 if (id > 0 && id < MAX_DOMAIN_ID)
1750 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1753 spin_unlock(&pd_bitmap_lock);
1758 static void domain_id_free(int id)
1760 spin_lock(&pd_bitmap_lock);
1761 if (id > 0 && id < MAX_DOMAIN_ID)
1762 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1763 spin_unlock(&pd_bitmap_lock);
1766 static void free_gcr3_tbl_level1(u64 *tbl)
1771 for (i = 0; i < 512; ++i) {
1772 if (!(tbl[i] & GCR3_VALID))
1775 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1777 free_page((unsigned long)ptr);
1781 static void free_gcr3_tbl_level2(u64 *tbl)
1786 for (i = 0; i < 512; ++i) {
1787 if (!(tbl[i] & GCR3_VALID))
1790 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1792 free_gcr3_tbl_level1(ptr);
1796 static void free_gcr3_table(struct protection_domain *domain)
1798 if (domain->glx == 2)
1799 free_gcr3_tbl_level2(domain->gcr3_tbl);
1800 else if (domain->glx == 1)
1801 free_gcr3_tbl_level1(domain->gcr3_tbl);
1803 BUG_ON(domain->glx != 0);
1805 free_page((unsigned long)domain->gcr3_tbl);
1808 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1810 domain_flush_tlb(&dom->domain);
1811 domain_flush_complete(&dom->domain);
1814 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1816 struct dma_ops_domain *dom;
1818 dom = container_of(iovad, struct dma_ops_domain, iovad);
1820 dma_ops_domain_flush_tlb(dom);
1824 * Free a domain, only used if something went wrong in the
1825 * allocation path and we need to free an already allocated page table
1827 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1832 del_domain_from_list(&dom->domain);
1834 put_iova_domain(&dom->iovad);
1836 free_pagetable(&dom->domain);
1839 domain_id_free(dom->domain.id);
1845 * Allocates a new protection domain usable for the dma_ops functions.
1846 * It also initializes the page table and the address allocator data
1847 * structures required for the dma_ops interface
1849 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1851 struct dma_ops_domain *dma_dom;
1853 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1857 if (protection_domain_init(&dma_dom->domain))
1860 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1861 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1862 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1863 if (!dma_dom->domain.pt_root)
1866 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1868 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1871 /* Initialize reserved ranges */
1872 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1874 add_domain_to_list(&dma_dom->domain);
1879 dma_ops_domain_free(dma_dom);
1885 * little helper function to check whether a given protection domain is a
1888 static bool dma_ops_domain(struct protection_domain *domain)
1890 return domain->flags & PD_DMA_OPS_MASK;
1893 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1899 if (domain->mode != PAGE_MODE_NONE)
1900 pte_root = iommu_virt_to_phys(domain->pt_root);
1902 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1903 << DEV_ENTRY_MODE_SHIFT;
1904 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1906 flags = amd_iommu_dev_table[devid].data[1];
1909 flags |= DTE_FLAG_IOTLB;
1912 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1914 if (iommu_feature(iommu, FEATURE_EPHSUP))
1915 pte_root |= 1ULL << DEV_ENTRY_PPR;
1918 if (domain->flags & PD_IOMMUV2_MASK) {
1919 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1920 u64 glx = domain->glx;
1923 pte_root |= DTE_FLAG_GV;
1924 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1926 /* First mask out possible old values for GCR3 table */
1927 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1930 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1933 /* Encode GCR3 table into DTE */
1934 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1937 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1940 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1944 flags &= ~DEV_DOMID_MASK;
1945 flags |= domain->id;
1947 amd_iommu_dev_table[devid].data[1] = flags;
1948 amd_iommu_dev_table[devid].data[0] = pte_root;
1951 static void clear_dte_entry(u16 devid)
1953 /* remove entry from the device table seen by the hardware */
1954 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1955 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1957 amd_iommu_apply_erratum_63(devid);
1960 static void do_attach(struct iommu_dev_data *dev_data,
1961 struct protection_domain *domain)
1963 struct amd_iommu *iommu;
1967 iommu = amd_iommu_rlookup_table[dev_data->devid];
1968 alias = dev_data->alias;
1969 ats = dev_data->ats.enabled;
1971 /* Update data structures */
1972 dev_data->domain = domain;
1973 list_add(&dev_data->list, &domain->dev_list);
1975 /* Do reference counting */
1976 domain->dev_iommu[iommu->index] += 1;
1977 domain->dev_cnt += 1;
1979 /* Update device table */
1980 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1981 if (alias != dev_data->devid)
1982 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1984 device_flush_dte(dev_data);
1987 static void do_detach(struct iommu_dev_data *dev_data)
1989 struct amd_iommu *iommu;
1992 iommu = amd_iommu_rlookup_table[dev_data->devid];
1993 alias = dev_data->alias;
1995 /* decrease reference counters */
1996 dev_data->domain->dev_iommu[iommu->index] -= 1;
1997 dev_data->domain->dev_cnt -= 1;
1999 /* Update data structures */
2000 dev_data->domain = NULL;
2001 list_del(&dev_data->list);
2002 clear_dte_entry(dev_data->devid);
2003 if (alias != dev_data->devid)
2004 clear_dte_entry(alias);
2006 /* Flush the DTE entry */
2007 device_flush_dte(dev_data);
2011 * If a device is not yet associated with a domain, this function makes the
2012 * device visible in the domain
2014 static int __attach_device(struct iommu_dev_data *dev_data,
2015 struct protection_domain *domain)
2020 spin_lock(&domain->lock);
2023 if (dev_data->domain != NULL)
2026 /* Attach alias group root */
2027 do_attach(dev_data, domain);
2034 spin_unlock(&domain->lock);
2040 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2042 pci_disable_ats(pdev);
2043 pci_disable_pri(pdev);
2044 pci_disable_pasid(pdev);
2047 /* FIXME: Change generic reset-function to do the same */
2048 static int pri_reset_while_enabled(struct pci_dev *pdev)
2053 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2057 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2058 control |= PCI_PRI_CTRL_RESET;
2059 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2064 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2069 /* FIXME: Hardcode number of outstanding requests for now */
2071 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2073 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2075 /* Only allow access to user-accessible pages */
2076 ret = pci_enable_pasid(pdev, 0);
2080 /* First reset the PRI state of the device */
2081 ret = pci_reset_pri(pdev);
2086 ret = pci_enable_pri(pdev, reqs);
2091 ret = pri_reset_while_enabled(pdev);
2096 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2103 pci_disable_pri(pdev);
2104 pci_disable_pasid(pdev);
2109 /* FIXME: Move this to PCI code */
2110 #define PCI_PRI_TLP_OFF (1 << 15)
2112 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2117 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2121 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2123 return (status & PCI_PRI_TLP_OFF) ? true : false;
2127 * If a device is not yet associated with a domain, this function makes the
2128 * device visible in the domain
2130 static int attach_device(struct device *dev,
2131 struct protection_domain *domain)
2133 struct pci_dev *pdev;
2134 struct iommu_dev_data *dev_data;
2135 unsigned long flags;
2138 dev_data = get_dev_data(dev);
2140 if (!dev_is_pci(dev))
2141 goto skip_ats_check;
2143 pdev = to_pci_dev(dev);
2144 if (domain->flags & PD_IOMMUV2_MASK) {
2145 if (!dev_data->passthrough)
2148 if (dev_data->iommu_v2) {
2149 if (pdev_iommuv2_enable(pdev) != 0)
2152 dev_data->ats.enabled = true;
2153 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2154 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2156 } else if (amd_iommu_iotlb_sup &&
2157 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2158 dev_data->ats.enabled = true;
2159 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2163 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2164 ret = __attach_device(dev_data, domain);
2165 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2168 * We might boot into a crash-kernel here. The crashed kernel
2169 * left the caches in the IOMMU dirty. So we have to flush
2170 * here to evict all dirty stuff.
2172 domain_flush_tlb_pde(domain);
2178 * Removes a device from a protection domain (unlocked)
2180 static void __detach_device(struct iommu_dev_data *dev_data)
2182 struct protection_domain *domain;
2184 domain = dev_data->domain;
2186 spin_lock(&domain->lock);
2188 do_detach(dev_data);
2190 spin_unlock(&domain->lock);
2194 * Removes a device from a protection domain (with devtable_lock held)
2196 static void detach_device(struct device *dev)
2198 struct protection_domain *domain;
2199 struct iommu_dev_data *dev_data;
2200 unsigned long flags;
2202 dev_data = get_dev_data(dev);
2203 domain = dev_data->domain;
2206 * First check if the device is still attached. It might already
2207 * be detached from its domain because the generic
2208 * iommu_detach_group code detached it and we try again here in
2209 * our alias handling.
2211 if (WARN_ON(!dev_data->domain))
2214 /* lock device table */
2215 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2216 __detach_device(dev_data);
2217 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2219 if (!dev_is_pci(dev))
2222 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2223 pdev_iommuv2_disable(to_pci_dev(dev));
2224 else if (dev_data->ats.enabled)
2225 pci_disable_ats(to_pci_dev(dev));
2227 dev_data->ats.enabled = false;
2230 static int amd_iommu_add_device(struct device *dev)
2232 struct iommu_dev_data *dev_data;
2233 struct iommu_domain *domain;
2234 struct amd_iommu *iommu;
2237 if (!check_device(dev) || get_dev_data(dev))
2240 devid = get_device_id(dev);
2244 iommu = amd_iommu_rlookup_table[devid];
2246 ret = iommu_init_device(dev);
2248 if (ret != -ENOTSUPP)
2249 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2252 iommu_ignore_device(dev);
2253 dev->dma_ops = &dma_direct_ops;
2256 init_iommu_group(dev);
2258 dev_data = get_dev_data(dev);
2262 if (iommu_pass_through || dev_data->iommu_v2)
2263 iommu_request_dm_for_dev(dev);
2265 /* Domains are initialized for this device - have a look what we ended up with */
2266 domain = iommu_get_domain_for_dev(dev);
2267 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2268 dev_data->passthrough = true;
2270 dev->dma_ops = &amd_iommu_dma_ops;
2273 iommu_completion_wait(iommu);
2278 static void amd_iommu_remove_device(struct device *dev)
2280 struct amd_iommu *iommu;
2283 if (!check_device(dev))
2286 devid = get_device_id(dev);
2290 iommu = amd_iommu_rlookup_table[devid];
2292 iommu_uninit_device(dev);
2293 iommu_completion_wait(iommu);
2296 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2298 if (dev_is_pci(dev))
2299 return pci_device_group(dev);
2301 return acpihid_device_group(dev);
2304 /*****************************************************************************
2306 * The next functions belong to the dma_ops mapping/unmapping code.
2308 *****************************************************************************/
2311 * In the dma_ops path we only have the struct device. This function
2312 * finds the corresponding IOMMU, the protection domain and the
2313 * requestor id for a given device.
2314 * If the device is not yet associated with a domain this is also done
2317 static struct protection_domain *get_domain(struct device *dev)
2319 struct protection_domain *domain;
2320 struct iommu_domain *io_domain;
2322 if (!check_device(dev))
2323 return ERR_PTR(-EINVAL);
2325 domain = get_dev_data(dev)->domain;
2326 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2327 get_dev_data(dev)->defer_attach = false;
2328 io_domain = iommu_get_domain_for_dev(dev);
2329 domain = to_pdomain(io_domain);
2330 attach_device(dev, domain);
2333 return ERR_PTR(-EBUSY);
2335 if (!dma_ops_domain(domain))
2336 return ERR_PTR(-EBUSY);
2341 static void update_device_table(struct protection_domain *domain)
2343 struct iommu_dev_data *dev_data;
2345 list_for_each_entry(dev_data, &domain->dev_list, list) {
2346 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2347 dev_data->iommu_v2);
2349 if (dev_data->devid == dev_data->alias)
2352 /* There is an alias, update device table entry for it */
2353 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2354 dev_data->iommu_v2);
2358 static void update_domain(struct protection_domain *domain)
2360 if (!domain->updated)
2363 update_device_table(domain);
2365 domain_flush_devices(domain);
2366 domain_flush_tlb_pde(domain);
2368 domain->updated = false;
2371 static int dir2prot(enum dma_data_direction direction)
2373 if (direction == DMA_TO_DEVICE)
2374 return IOMMU_PROT_IR;
2375 else if (direction == DMA_FROM_DEVICE)
2376 return IOMMU_PROT_IW;
2377 else if (direction == DMA_BIDIRECTIONAL)
2378 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2384 * This function contains common code for mapping of a physically
2385 * contiguous memory region into DMA address space. It is used by all
2386 * mapping functions provided with this IOMMU driver.
2387 * Must be called with the domain lock held.
2389 static dma_addr_t __map_single(struct device *dev,
2390 struct dma_ops_domain *dma_dom,
2393 enum dma_data_direction direction,
2396 dma_addr_t offset = paddr & ~PAGE_MASK;
2397 dma_addr_t address, start, ret;
2402 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2405 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2406 if (address == AMD_IOMMU_MAPPING_ERROR)
2409 prot = dir2prot(direction);
2412 for (i = 0; i < pages; ++i) {
2413 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2414 PAGE_SIZE, prot, GFP_ATOMIC);
2423 if (unlikely(amd_iommu_np_cache)) {
2424 domain_flush_pages(&dma_dom->domain, address, size);
2425 domain_flush_complete(&dma_dom->domain);
2433 for (--i; i >= 0; --i) {
2435 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2438 domain_flush_tlb(&dma_dom->domain);
2439 domain_flush_complete(&dma_dom->domain);
2441 dma_ops_free_iova(dma_dom, address, pages);
2443 return AMD_IOMMU_MAPPING_ERROR;
2447 * Does the reverse of the __map_single function. Must be called with
2448 * the domain lock held too
2450 static void __unmap_single(struct dma_ops_domain *dma_dom,
2451 dma_addr_t dma_addr,
2455 dma_addr_t i, start;
2458 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2459 dma_addr &= PAGE_MASK;
2462 for (i = 0; i < pages; ++i) {
2463 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2467 if (amd_iommu_unmap_flush) {
2468 domain_flush_tlb(&dma_dom->domain);
2469 domain_flush_complete(&dma_dom->domain);
2470 dma_ops_free_iova(dma_dom, dma_addr, pages);
2472 pages = __roundup_pow_of_two(pages);
2473 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2478 * The exported map_single function for dma_ops.
2480 static dma_addr_t map_page(struct device *dev, struct page *page,
2481 unsigned long offset, size_t size,
2482 enum dma_data_direction dir,
2483 unsigned long attrs)
2485 phys_addr_t paddr = page_to_phys(page) + offset;
2486 struct protection_domain *domain;
2487 struct dma_ops_domain *dma_dom;
2490 domain = get_domain(dev);
2491 if (PTR_ERR(domain) == -EINVAL)
2492 return (dma_addr_t)paddr;
2493 else if (IS_ERR(domain))
2494 return AMD_IOMMU_MAPPING_ERROR;
2496 dma_mask = *dev->dma_mask;
2497 dma_dom = to_dma_ops_domain(domain);
2499 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2503 * The exported unmap_single function for dma_ops.
2505 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2506 enum dma_data_direction dir, unsigned long attrs)
2508 struct protection_domain *domain;
2509 struct dma_ops_domain *dma_dom;
2511 domain = get_domain(dev);
2515 dma_dom = to_dma_ops_domain(domain);
2517 __unmap_single(dma_dom, dma_addr, size, dir);
2520 static int sg_num_pages(struct device *dev,
2521 struct scatterlist *sglist,
2524 unsigned long mask, boundary_size;
2525 struct scatterlist *s;
2528 mask = dma_get_seg_boundary(dev);
2529 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2530 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2532 for_each_sg(sglist, s, nelems, i) {
2535 s->dma_address = npages << PAGE_SHIFT;
2536 p = npages % boundary_size;
2537 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2538 if (p + n > boundary_size)
2539 npages += boundary_size - p;
2547 * The exported map_sg function for dma_ops (handles scatter-gather
2550 static int map_sg(struct device *dev, struct scatterlist *sglist,
2551 int nelems, enum dma_data_direction direction,
2552 unsigned long attrs)
2554 int mapped_pages = 0, npages = 0, prot = 0, i;
2555 struct protection_domain *domain;
2556 struct dma_ops_domain *dma_dom;
2557 struct scatterlist *s;
2558 unsigned long address;
2561 domain = get_domain(dev);
2565 dma_dom = to_dma_ops_domain(domain);
2566 dma_mask = *dev->dma_mask;
2568 npages = sg_num_pages(dev, sglist, nelems);
2570 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2571 if (address == AMD_IOMMU_MAPPING_ERROR)
2574 prot = dir2prot(direction);
2576 /* Map all sg entries */
2577 for_each_sg(sglist, s, nelems, i) {
2578 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2580 for (j = 0; j < pages; ++j) {
2581 unsigned long bus_addr, phys_addr;
2584 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2585 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2586 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2594 /* Everything is mapped - write the right values into s->dma_address */
2595 for_each_sg(sglist, s, nelems, i) {
2596 s->dma_address += address + s->offset;
2597 s->dma_length = s->length;
2603 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2604 dev_name(dev), npages);
2606 for_each_sg(sglist, s, nelems, i) {
2607 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2609 for (j = 0; j < pages; ++j) {
2610 unsigned long bus_addr;
2612 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2613 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2621 free_iova_fast(&dma_dom->iovad, address, npages);
2628 * The exported map_sg function for dma_ops (handles scatter-gather
2631 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2632 int nelems, enum dma_data_direction dir,
2633 unsigned long attrs)
2635 struct protection_domain *domain;
2636 struct dma_ops_domain *dma_dom;
2637 unsigned long startaddr;
2640 domain = get_domain(dev);
2644 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2645 dma_dom = to_dma_ops_domain(domain);
2646 npages = sg_num_pages(dev, sglist, nelems);
2648 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2652 * The exported alloc_coherent function for dma_ops.
2654 static void *alloc_coherent(struct device *dev, size_t size,
2655 dma_addr_t *dma_addr, gfp_t flag,
2656 unsigned long attrs)
2658 u64 dma_mask = dev->coherent_dma_mask;
2659 struct protection_domain *domain;
2660 struct dma_ops_domain *dma_dom;
2663 domain = get_domain(dev);
2664 if (PTR_ERR(domain) == -EINVAL) {
2665 page = alloc_pages(flag, get_order(size));
2666 *dma_addr = page_to_phys(page);
2667 return page_address(page);
2668 } else if (IS_ERR(domain))
2671 dma_dom = to_dma_ops_domain(domain);
2672 size = PAGE_ALIGN(size);
2673 dma_mask = dev->coherent_dma_mask;
2674 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2677 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2679 if (!gfpflags_allow_blocking(flag))
2682 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2683 get_order(size), flag & __GFP_NOWARN);
2689 dma_mask = *dev->dma_mask;
2691 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2692 size, DMA_BIDIRECTIONAL, dma_mask);
2694 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
2697 return page_address(page);
2701 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2702 __free_pages(page, get_order(size));
2708 * The exported free_coherent function for dma_ops.
2710 static void free_coherent(struct device *dev, size_t size,
2711 void *virt_addr, dma_addr_t dma_addr,
2712 unsigned long attrs)
2714 struct protection_domain *domain;
2715 struct dma_ops_domain *dma_dom;
2718 page = virt_to_page(virt_addr);
2719 size = PAGE_ALIGN(size);
2721 domain = get_domain(dev);
2725 dma_dom = to_dma_ops_domain(domain);
2727 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2730 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2731 __free_pages(page, get_order(size));
2735 * This function is called by the DMA layer to find out if we can handle a
2736 * particular device. It is part of the dma_ops.
2738 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2740 if (!dma_direct_supported(dev, mask))
2742 return check_device(dev);
2745 static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2747 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2750 static const struct dma_map_ops amd_iommu_dma_ops = {
2751 .alloc = alloc_coherent,
2752 .free = free_coherent,
2753 .map_page = map_page,
2754 .unmap_page = unmap_page,
2756 .unmap_sg = unmap_sg,
2757 .dma_supported = amd_iommu_dma_supported,
2758 .mapping_error = amd_iommu_mapping_error,
2761 static int init_reserved_iova_ranges(void)
2763 struct pci_dev *pdev = NULL;
2766 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2768 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2769 &reserved_rbtree_key);
2771 /* MSI memory range */
2772 val = reserve_iova(&reserved_iova_ranges,
2773 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2775 pr_err("Reserving MSI range failed\n");
2779 /* HT memory range */
2780 val = reserve_iova(&reserved_iova_ranges,
2781 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2783 pr_err("Reserving HT range failed\n");
2788 * Memory used for PCI resources
2789 * FIXME: Check whether we can reserve the PCI-hole completly
2791 for_each_pci_dev(pdev) {
2794 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2795 struct resource *r = &pdev->resource[i];
2797 if (!(r->flags & IORESOURCE_MEM))
2800 val = reserve_iova(&reserved_iova_ranges,
2804 pr_err("Reserve pci-resource range failed\n");
2813 int __init amd_iommu_init_api(void)
2817 ret = iova_cache_get();
2821 ret = init_reserved_iova_ranges();
2825 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2828 #ifdef CONFIG_ARM_AMBA
2829 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2833 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2840 int __init amd_iommu_init_dma_ops(void)
2842 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2846 * In case we don't initialize SWIOTLB (actually the common case
2847 * when AMD IOMMU is enabled and SME is not active), make sure there
2848 * are global dma_ops set as a fall-back for devices not handled by
2849 * this driver (for example non-PCI devices). When SME is active,
2850 * make sure that swiotlb variable remains set so the global dma_ops
2851 * continue to be SWIOTLB.
2854 dma_ops = &dma_direct_ops;
2856 if (amd_iommu_unmap_flush)
2857 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2859 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2865 /*****************************************************************************
2867 * The following functions belong to the exported interface of AMD IOMMU
2869 * This interface allows access to lower level functions of the IOMMU
2870 * like protection domain handling and assignement of devices to domains
2871 * which is not possible with the dma_ops interface.
2873 *****************************************************************************/
2875 static void cleanup_domain(struct protection_domain *domain)
2877 struct iommu_dev_data *entry;
2878 unsigned long flags;
2880 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2882 while (!list_empty(&domain->dev_list)) {
2883 entry = list_first_entry(&domain->dev_list,
2884 struct iommu_dev_data, list);
2885 BUG_ON(!entry->domain);
2886 __detach_device(entry);
2889 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2892 static void protection_domain_free(struct protection_domain *domain)
2897 del_domain_from_list(domain);
2900 domain_id_free(domain->id);
2905 static int protection_domain_init(struct protection_domain *domain)
2907 spin_lock_init(&domain->lock);
2908 mutex_init(&domain->api_lock);
2909 domain->id = domain_id_alloc();
2912 INIT_LIST_HEAD(&domain->dev_list);
2917 static struct protection_domain *protection_domain_alloc(void)
2919 struct protection_domain *domain;
2921 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2925 if (protection_domain_init(domain))
2928 add_domain_to_list(domain);
2938 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2940 struct protection_domain *pdomain;
2941 struct dma_ops_domain *dma_domain;
2944 case IOMMU_DOMAIN_UNMANAGED:
2945 pdomain = protection_domain_alloc();
2949 pdomain->mode = PAGE_MODE_3_LEVEL;
2950 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2951 if (!pdomain->pt_root) {
2952 protection_domain_free(pdomain);
2956 pdomain->domain.geometry.aperture_start = 0;
2957 pdomain->domain.geometry.aperture_end = ~0ULL;
2958 pdomain->domain.geometry.force_aperture = true;
2961 case IOMMU_DOMAIN_DMA:
2962 dma_domain = dma_ops_domain_alloc();
2964 pr_err("AMD-Vi: Failed to allocate\n");
2967 pdomain = &dma_domain->domain;
2969 case IOMMU_DOMAIN_IDENTITY:
2970 pdomain = protection_domain_alloc();
2974 pdomain->mode = PAGE_MODE_NONE;
2980 return &pdomain->domain;
2983 static void amd_iommu_domain_free(struct iommu_domain *dom)
2985 struct protection_domain *domain;
2986 struct dma_ops_domain *dma_dom;
2988 domain = to_pdomain(dom);
2990 if (domain->dev_cnt > 0)
2991 cleanup_domain(domain);
2993 BUG_ON(domain->dev_cnt != 0);
2998 switch (dom->type) {
2999 case IOMMU_DOMAIN_DMA:
3000 /* Now release the domain */
3001 dma_dom = to_dma_ops_domain(domain);
3002 dma_ops_domain_free(dma_dom);
3005 if (domain->mode != PAGE_MODE_NONE)
3006 free_pagetable(domain);
3008 if (domain->flags & PD_IOMMUV2_MASK)
3009 free_gcr3_table(domain);
3011 protection_domain_free(domain);
3016 static void amd_iommu_detach_device(struct iommu_domain *dom,
3019 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3020 struct amd_iommu *iommu;
3023 if (!check_device(dev))
3026 devid = get_device_id(dev);
3030 if (dev_data->domain != NULL)
3033 iommu = amd_iommu_rlookup_table[devid];
3037 #ifdef CONFIG_IRQ_REMAP
3038 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3039 (dom->type == IOMMU_DOMAIN_UNMANAGED))
3040 dev_data->use_vapic = 0;
3043 iommu_completion_wait(iommu);
3046 static int amd_iommu_attach_device(struct iommu_domain *dom,
3049 struct protection_domain *domain = to_pdomain(dom);
3050 struct iommu_dev_data *dev_data;
3051 struct amd_iommu *iommu;
3054 if (!check_device(dev))
3057 dev_data = dev->archdata.iommu;
3059 iommu = amd_iommu_rlookup_table[dev_data->devid];
3063 if (dev_data->domain)
3066 ret = attach_device(dev, domain);
3068 #ifdef CONFIG_IRQ_REMAP
3069 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3070 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3071 dev_data->use_vapic = 1;
3073 dev_data->use_vapic = 0;
3077 iommu_completion_wait(iommu);
3082 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3083 phys_addr_t paddr, size_t page_size, int iommu_prot)
3085 struct protection_domain *domain = to_pdomain(dom);
3089 if (domain->mode == PAGE_MODE_NONE)
3092 if (iommu_prot & IOMMU_READ)
3093 prot |= IOMMU_PROT_IR;
3094 if (iommu_prot & IOMMU_WRITE)
3095 prot |= IOMMU_PROT_IW;
3097 mutex_lock(&domain->api_lock);
3098 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3099 mutex_unlock(&domain->api_lock);
3104 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3107 struct protection_domain *domain = to_pdomain(dom);
3110 if (domain->mode == PAGE_MODE_NONE)
3113 mutex_lock(&domain->api_lock);
3114 unmap_size = iommu_unmap_page(domain, iova, page_size);
3115 mutex_unlock(&domain->api_lock);
3120 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3123 struct protection_domain *domain = to_pdomain(dom);
3124 unsigned long offset_mask, pte_pgsize;
3127 if (domain->mode == PAGE_MODE_NONE)
3130 pte = fetch_pte(domain, iova, &pte_pgsize);
3132 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3135 offset_mask = pte_pgsize - 1;
3136 __pte = __sme_clr(*pte & PM_ADDR_MASK);
3138 return (__pte & ~offset_mask) | (iova & offset_mask);
3141 static bool amd_iommu_capable(enum iommu_cap cap)
3144 case IOMMU_CAP_CACHE_COHERENCY:
3146 case IOMMU_CAP_INTR_REMAP:
3147 return (irq_remapping_enabled == 1);
3148 case IOMMU_CAP_NOEXEC:
3157 static void amd_iommu_get_resv_regions(struct device *dev,
3158 struct list_head *head)
3160 struct iommu_resv_region *region;
3161 struct unity_map_entry *entry;
3164 devid = get_device_id(dev);
3168 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3172 if (devid < entry->devid_start || devid > entry->devid_end)
3175 length = entry->address_end - entry->address_start;
3176 if (entry->prot & IOMMU_PROT_IR)
3178 if (entry->prot & IOMMU_PROT_IW)
3179 prot |= IOMMU_WRITE;
3181 region = iommu_alloc_resv_region(entry->address_start,
3185 pr_err("Out of memory allocating dm-regions for %s\n",
3189 list_add_tail(®ion->list, head);
3192 region = iommu_alloc_resv_region(MSI_RANGE_START,
3193 MSI_RANGE_END - MSI_RANGE_START + 1,
3197 list_add_tail(®ion->list, head);
3199 region = iommu_alloc_resv_region(HT_RANGE_START,
3200 HT_RANGE_END - HT_RANGE_START + 1,
3201 0, IOMMU_RESV_RESERVED);
3204 list_add_tail(®ion->list, head);
3207 static void amd_iommu_put_resv_regions(struct device *dev,
3208 struct list_head *head)
3210 struct iommu_resv_region *entry, *next;
3212 list_for_each_entry_safe(entry, next, head, list)
3216 static void amd_iommu_apply_resv_region(struct device *dev,
3217 struct iommu_domain *domain,
3218 struct iommu_resv_region *region)
3220 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3221 unsigned long start, end;
3223 start = IOVA_PFN(region->start);
3224 end = IOVA_PFN(region->start + region->length - 1);
3226 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3229 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3232 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3233 return dev_data->defer_attach;
3236 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3238 struct protection_domain *dom = to_pdomain(domain);
3240 domain_flush_tlb_pde(dom);
3241 domain_flush_complete(dom);
3244 static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3245 unsigned long iova, size_t size)
3249 const struct iommu_ops amd_iommu_ops = {
3250 .capable = amd_iommu_capable,
3251 .domain_alloc = amd_iommu_domain_alloc,
3252 .domain_free = amd_iommu_domain_free,
3253 .attach_dev = amd_iommu_attach_device,
3254 .detach_dev = amd_iommu_detach_device,
3255 .map = amd_iommu_map,
3256 .unmap = amd_iommu_unmap,
3257 .iova_to_phys = amd_iommu_iova_to_phys,
3258 .add_device = amd_iommu_add_device,
3259 .remove_device = amd_iommu_remove_device,
3260 .device_group = amd_iommu_device_group,
3261 .get_resv_regions = amd_iommu_get_resv_regions,
3262 .put_resv_regions = amd_iommu_put_resv_regions,
3263 .apply_resv_region = amd_iommu_apply_resv_region,
3264 .is_attach_deferred = amd_iommu_is_attach_deferred,
3265 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3266 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3267 .iotlb_range_add = amd_iommu_iotlb_range_add,
3268 .iotlb_sync = amd_iommu_flush_iotlb_all,
3271 /*****************************************************************************
3273 * The next functions do a basic initialization of IOMMU for pass through
3276 * In passthrough mode the IOMMU is initialized and enabled but not used for
3277 * DMA-API translation.
3279 *****************************************************************************/
3281 /* IOMMUv2 specific functions */
3282 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3284 return atomic_notifier_chain_register(&ppr_notifier, nb);
3286 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3288 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3290 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3292 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3294 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3296 struct protection_domain *domain = to_pdomain(dom);
3297 unsigned long flags;
3299 spin_lock_irqsave(&domain->lock, flags);
3301 /* Update data structure */
3302 domain->mode = PAGE_MODE_NONE;
3303 domain->updated = true;
3305 /* Make changes visible to IOMMUs */
3306 update_domain(domain);
3308 /* Page-table is not visible to IOMMU anymore, so free it */
3309 free_pagetable(domain);
3311 spin_unlock_irqrestore(&domain->lock, flags);
3313 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3315 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3317 struct protection_domain *domain = to_pdomain(dom);
3318 unsigned long flags;
3321 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3324 /* Number of GCR3 table levels required */
3325 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3328 if (levels > amd_iommu_max_glx_val)
3331 spin_lock_irqsave(&domain->lock, flags);
3334 * Save us all sanity checks whether devices already in the
3335 * domain support IOMMUv2. Just force that the domain has no
3336 * devices attached when it is switched into IOMMUv2 mode.
3339 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3343 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3344 if (domain->gcr3_tbl == NULL)
3347 domain->glx = levels;
3348 domain->flags |= PD_IOMMUV2_MASK;
3349 domain->updated = true;
3351 update_domain(domain);
3356 spin_unlock_irqrestore(&domain->lock, flags);
3360 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3362 static int __flush_pasid(struct protection_domain *domain, int pasid,
3363 u64 address, bool size)
3365 struct iommu_dev_data *dev_data;
3366 struct iommu_cmd cmd;
3369 if (!(domain->flags & PD_IOMMUV2_MASK))
3372 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3375 * IOMMU TLB needs to be flushed before Device TLB to
3376 * prevent device TLB refill from IOMMU TLB
3378 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3379 if (domain->dev_iommu[i] == 0)
3382 ret = iommu_queue_command(amd_iommus[i], &cmd);
3387 /* Wait until IOMMU TLB flushes are complete */
3388 domain_flush_complete(domain);
3390 /* Now flush device TLBs */
3391 list_for_each_entry(dev_data, &domain->dev_list, list) {
3392 struct amd_iommu *iommu;
3396 There might be non-IOMMUv2 capable devices in an IOMMUv2
3399 if (!dev_data->ats.enabled)
3402 qdep = dev_data->ats.qdep;
3403 iommu = amd_iommu_rlookup_table[dev_data->devid];
3405 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3406 qdep, address, size);
3408 ret = iommu_queue_command(iommu, &cmd);
3413 /* Wait until all device TLBs are flushed */
3414 domain_flush_complete(domain);
3423 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3426 return __flush_pasid(domain, pasid, address, false);
3429 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3432 struct protection_domain *domain = to_pdomain(dom);
3433 unsigned long flags;
3436 spin_lock_irqsave(&domain->lock, flags);
3437 ret = __amd_iommu_flush_page(domain, pasid, address);
3438 spin_unlock_irqrestore(&domain->lock, flags);
3442 EXPORT_SYMBOL(amd_iommu_flush_page);
3444 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3446 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3450 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3452 struct protection_domain *domain = to_pdomain(dom);
3453 unsigned long flags;
3456 spin_lock_irqsave(&domain->lock, flags);
3457 ret = __amd_iommu_flush_tlb(domain, pasid);
3458 spin_unlock_irqrestore(&domain->lock, flags);
3462 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3464 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3471 index = (pasid >> (9 * level)) & 0x1ff;
3477 if (!(*pte & GCR3_VALID)) {
3481 root = (void *)get_zeroed_page(GFP_ATOMIC);
3485 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3488 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3496 static int __set_gcr3(struct protection_domain *domain, int pasid,
3501 if (domain->mode != PAGE_MODE_NONE)
3504 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3508 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3510 return __amd_iommu_flush_tlb(domain, pasid);
3513 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3517 if (domain->mode != PAGE_MODE_NONE)
3520 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3526 return __amd_iommu_flush_tlb(domain, pasid);
3529 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3532 struct protection_domain *domain = to_pdomain(dom);
3533 unsigned long flags;
3536 spin_lock_irqsave(&domain->lock, flags);
3537 ret = __set_gcr3(domain, pasid, cr3);
3538 spin_unlock_irqrestore(&domain->lock, flags);
3542 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3544 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3546 struct protection_domain *domain = to_pdomain(dom);
3547 unsigned long flags;
3550 spin_lock_irqsave(&domain->lock, flags);
3551 ret = __clear_gcr3(domain, pasid);
3552 spin_unlock_irqrestore(&domain->lock, flags);
3556 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3558 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3559 int status, int tag)
3561 struct iommu_dev_data *dev_data;
3562 struct amd_iommu *iommu;
3563 struct iommu_cmd cmd;
3565 dev_data = get_dev_data(&pdev->dev);
3566 iommu = amd_iommu_rlookup_table[dev_data->devid];
3568 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3569 tag, dev_data->pri_tlp);
3571 return iommu_queue_command(iommu, &cmd);
3573 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3575 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3577 struct protection_domain *pdomain;
3579 pdomain = get_domain(&pdev->dev);
3580 if (IS_ERR(pdomain))
3583 /* Only return IOMMUv2 domains */
3584 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3587 return &pdomain->domain;
3589 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3591 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3593 struct iommu_dev_data *dev_data;
3595 if (!amd_iommu_v2_supported())
3598 dev_data = get_dev_data(&pdev->dev);
3599 dev_data->errata |= (1 << erratum);
3601 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3603 int amd_iommu_device_info(struct pci_dev *pdev,
3604 struct amd_iommu_device_info *info)
3609 if (pdev == NULL || info == NULL)
3612 if (!amd_iommu_v2_supported())
3615 memset(info, 0, sizeof(*info));
3617 if (!pci_ats_disabled()) {
3618 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3620 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3623 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3625 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3627 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3631 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3632 max_pasids = min(max_pasids, (1 << 20));
3634 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3635 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3637 features = pci_pasid_features(pdev);
3638 if (features & PCI_PASID_CAP_EXEC)
3639 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3640 if (features & PCI_PASID_CAP_PRIV)
3641 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3646 EXPORT_SYMBOL(amd_iommu_device_info);
3648 #ifdef CONFIG_IRQ_REMAP
3650 /*****************************************************************************
3652 * Interrupt Remapping Implementation
3654 *****************************************************************************/
3656 static struct irq_chip amd_ir_chip;
3657 static DEFINE_SPINLOCK(iommu_table_lock);
3659 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3663 dte = amd_iommu_dev_table[devid].data[2];
3664 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3665 dte |= iommu_virt_to_phys(table->table);
3666 dte |= DTE_IRQ_REMAP_INTCTL;
3667 dte |= DTE_IRQ_TABLE_LEN;
3668 dte |= DTE_IRQ_REMAP_ENABLE;
3670 amd_iommu_dev_table[devid].data[2] = dte;
3673 static struct irq_remap_table *get_irq_table(u16 devid)
3675 struct irq_remap_table *table;
3677 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3678 "%s: no iommu for devid %x\n", __func__, devid))
3681 table = irq_lookup_table[devid];
3682 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3688 static struct irq_remap_table *__alloc_irq_table(void)
3690 struct irq_remap_table *table;
3692 table = kzalloc(sizeof(*table), GFP_KERNEL);
3696 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3697 if (!table->table) {
3701 raw_spin_lock_init(&table->lock);
3703 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3704 memset(table->table, 0,
3705 MAX_IRQS_PER_TABLE * sizeof(u32));
3707 memset(table->table, 0,
3708 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3712 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3713 struct irq_remap_table *table)
3715 irq_lookup_table[devid] = table;
3716 set_dte_irq_entry(devid, table);
3717 iommu_flush_dte(iommu, devid);
3720 static struct irq_remap_table *alloc_irq_table(u16 devid)
3722 struct irq_remap_table *table = NULL;
3723 struct irq_remap_table *new_table = NULL;
3724 struct amd_iommu *iommu;
3725 unsigned long flags;
3728 spin_lock_irqsave(&iommu_table_lock, flags);
3730 iommu = amd_iommu_rlookup_table[devid];
3734 table = irq_lookup_table[devid];
3738 alias = amd_iommu_alias_table[devid];
3739 table = irq_lookup_table[alias];
3741 set_remap_table_entry(iommu, devid, table);
3744 spin_unlock_irqrestore(&iommu_table_lock, flags);
3746 /* Nothing there yet, allocate new irq remapping table */
3747 new_table = __alloc_irq_table();
3751 spin_lock_irqsave(&iommu_table_lock, flags);
3753 table = irq_lookup_table[devid];
3757 table = irq_lookup_table[alias];
3759 set_remap_table_entry(iommu, devid, table);
3766 set_remap_table_entry(iommu, devid, table);
3768 set_remap_table_entry(iommu, alias, table);
3771 iommu_completion_wait(iommu);
3774 spin_unlock_irqrestore(&iommu_table_lock, flags);
3777 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3783 static int alloc_irq_index(u16 devid, int count, bool align)
3785 struct irq_remap_table *table;
3786 int index, c, alignment = 1;
3787 unsigned long flags;
3788 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3793 table = alloc_irq_table(devid);
3798 alignment = roundup_pow_of_two(count);
3800 raw_spin_lock_irqsave(&table->lock, flags);
3802 /* Scan table for free entries */
3803 for (index = ALIGN(table->min_index, alignment), c = 0;
3804 index < MAX_IRQS_PER_TABLE;) {
3805 if (!iommu->irte_ops->is_allocated(table, index)) {
3809 index = ALIGN(index + 1, alignment);
3815 iommu->irte_ops->set_allocated(table, index - c + 1);
3827 raw_spin_unlock_irqrestore(&table->lock, flags);
3832 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3833 struct amd_ir_data *data)
3835 struct irq_remap_table *table;
3836 struct amd_iommu *iommu;
3837 unsigned long flags;
3838 struct irte_ga *entry;
3840 iommu = amd_iommu_rlookup_table[devid];
3844 table = get_irq_table(devid);
3848 raw_spin_lock_irqsave(&table->lock, flags);
3850 entry = (struct irte_ga *)table->table;
3851 entry = &entry[index];
3852 entry->lo.fields_remap.valid = 0;
3853 entry->hi.val = irte->hi.val;
3854 entry->lo.val = irte->lo.val;
3855 entry->lo.fields_remap.valid = 1;
3859 raw_spin_unlock_irqrestore(&table->lock, flags);
3861 iommu_flush_irt(iommu, devid);
3862 iommu_completion_wait(iommu);
3867 static int modify_irte(u16 devid, int index, union irte *irte)
3869 struct irq_remap_table *table;
3870 struct amd_iommu *iommu;
3871 unsigned long flags;
3873 iommu = amd_iommu_rlookup_table[devid];
3877 table = get_irq_table(devid);
3881 raw_spin_lock_irqsave(&table->lock, flags);
3882 table->table[index] = irte->val;
3883 raw_spin_unlock_irqrestore(&table->lock, flags);
3885 iommu_flush_irt(iommu, devid);
3886 iommu_completion_wait(iommu);
3891 static void free_irte(u16 devid, int index)
3893 struct irq_remap_table *table;
3894 struct amd_iommu *iommu;
3895 unsigned long flags;
3897 iommu = amd_iommu_rlookup_table[devid];
3901 table = get_irq_table(devid);
3905 raw_spin_lock_irqsave(&table->lock, flags);
3906 iommu->irte_ops->clear_allocated(table, index);
3907 raw_spin_unlock_irqrestore(&table->lock, flags);
3909 iommu_flush_irt(iommu, devid);
3910 iommu_completion_wait(iommu);
3913 static void irte_prepare(void *entry,
3914 u32 delivery_mode, u32 dest_mode,
3915 u8 vector, u32 dest_apicid, int devid)
3917 union irte *irte = (union irte *) entry;
3920 irte->fields.vector = vector;
3921 irte->fields.int_type = delivery_mode;
3922 irte->fields.destination = dest_apicid;
3923 irte->fields.dm = dest_mode;
3924 irte->fields.valid = 1;
3927 static void irte_ga_prepare(void *entry,
3928 u32 delivery_mode, u32 dest_mode,
3929 u8 vector, u32 dest_apicid, int devid)
3931 struct irte_ga *irte = (struct irte_ga *) entry;
3935 irte->lo.fields_remap.int_type = delivery_mode;
3936 irte->lo.fields_remap.dm = dest_mode;
3937 irte->hi.fields.vector = vector;
3938 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3939 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3940 irte->lo.fields_remap.valid = 1;
3943 static void irte_activate(void *entry, u16 devid, u16 index)
3945 union irte *irte = (union irte *) entry;
3947 irte->fields.valid = 1;
3948 modify_irte(devid, index, irte);
3951 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3953 struct irte_ga *irte = (struct irte_ga *) entry;
3955 irte->lo.fields_remap.valid = 1;
3956 modify_irte_ga(devid, index, irte, NULL);
3959 static void irte_deactivate(void *entry, u16 devid, u16 index)
3961 union irte *irte = (union irte *) entry;
3963 irte->fields.valid = 0;
3964 modify_irte(devid, index, irte);
3967 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3969 struct irte_ga *irte = (struct irte_ga *) entry;
3971 irte->lo.fields_remap.valid = 0;
3972 modify_irte_ga(devid, index, irte, NULL);
3975 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3976 u8 vector, u32 dest_apicid)
3978 union irte *irte = (union irte *) entry;
3980 irte->fields.vector = vector;
3981 irte->fields.destination = dest_apicid;
3982 modify_irte(devid, index, irte);
3985 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3986 u8 vector, u32 dest_apicid)
3988 struct irte_ga *irte = (struct irte_ga *) entry;
3990 if (!irte->lo.fields_remap.guest_mode) {
3991 irte->hi.fields.vector = vector;
3992 irte->lo.fields_remap.destination =
3993 APICID_TO_IRTE_DEST_LO(dest_apicid);
3994 irte->hi.fields.destination =
3995 APICID_TO_IRTE_DEST_HI(dest_apicid);
3996 modify_irte_ga(devid, index, irte, NULL);
4000 #define IRTE_ALLOCATED (~1U)
4001 static void irte_set_allocated(struct irq_remap_table *table, int index)
4003 table->table[index] = IRTE_ALLOCATED;
4006 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
4008 struct irte_ga *ptr = (struct irte_ga *)table->table;
4009 struct irte_ga *irte = &ptr[index];
4011 memset(&irte->lo.val, 0, sizeof(u64));
4012 memset(&irte->hi.val, 0, sizeof(u64));
4013 irte->hi.fields.vector = 0xff;
4016 static bool irte_is_allocated(struct irq_remap_table *table, int index)
4018 union irte *ptr = (union irte *)table->table;
4019 union irte *irte = &ptr[index];
4021 return irte->val != 0;
4024 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
4026 struct irte_ga *ptr = (struct irte_ga *)table->table;
4027 struct irte_ga *irte = &ptr[index];
4029 return irte->hi.fields.vector != 0;
4032 static void irte_clear_allocated(struct irq_remap_table *table, int index)
4034 table->table[index] = 0;
4037 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
4039 struct irte_ga *ptr = (struct irte_ga *)table->table;
4040 struct irte_ga *irte = &ptr[index];
4042 memset(&irte->lo.val, 0, sizeof(u64));
4043 memset(&irte->hi.val, 0, sizeof(u64));
4046 static int get_devid(struct irq_alloc_info *info)
4050 switch (info->type) {
4051 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4052 devid = get_ioapic_devid(info->ioapic_id);
4054 case X86_IRQ_ALLOC_TYPE_HPET:
4055 devid = get_hpet_devid(info->hpet_id);
4057 case X86_IRQ_ALLOC_TYPE_MSI:
4058 case X86_IRQ_ALLOC_TYPE_MSIX:
4059 devid = get_device_id(&info->msi_dev->dev);
4069 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4071 struct amd_iommu *iommu;
4077 devid = get_devid(info);
4079 iommu = amd_iommu_rlookup_table[devid];
4081 return iommu->ir_domain;
4087 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4089 struct amd_iommu *iommu;
4095 switch (info->type) {
4096 case X86_IRQ_ALLOC_TYPE_MSI:
4097 case X86_IRQ_ALLOC_TYPE_MSIX:
4098 devid = get_device_id(&info->msi_dev->dev);
4102 iommu = amd_iommu_rlookup_table[devid];
4104 return iommu->msi_domain;
4113 struct irq_remap_ops amd_iommu_irq_ops = {
4114 .prepare = amd_iommu_prepare,
4115 .enable = amd_iommu_enable,
4116 .disable = amd_iommu_disable,
4117 .reenable = amd_iommu_reenable,
4118 .enable_faulting = amd_iommu_enable_faulting,
4119 .get_ir_irq_domain = get_ir_irq_domain,
4120 .get_irq_domain = get_irq_domain,
4123 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4124 struct irq_cfg *irq_cfg,
4125 struct irq_alloc_info *info,
4126 int devid, int index, int sub_handle)
4128 struct irq_2_irte *irte_info = &data->irq_2_irte;
4129 struct msi_msg *msg = &data->msi_entry;
4130 struct IO_APIC_route_entry *entry;
4131 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4136 data->irq_2_irte.devid = devid;
4137 data->irq_2_irte.index = index + sub_handle;
4138 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4139 apic->irq_dest_mode, irq_cfg->vector,
4140 irq_cfg->dest_apicid, devid);
4142 switch (info->type) {
4143 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4144 /* Setup IOAPIC entry */
4145 entry = info->ioapic_entry;
4146 info->ioapic_entry = NULL;
4147 memset(entry, 0, sizeof(*entry));
4148 entry->vector = index;
4150 entry->trigger = info->ioapic_trigger;
4151 entry->polarity = info->ioapic_polarity;
4152 /* Mask level triggered irqs. */
4153 if (info->ioapic_trigger)
4157 case X86_IRQ_ALLOC_TYPE_HPET:
4158 case X86_IRQ_ALLOC_TYPE_MSI:
4159 case X86_IRQ_ALLOC_TYPE_MSIX:
4160 msg->address_hi = MSI_ADDR_BASE_HI;
4161 msg->address_lo = MSI_ADDR_BASE_LO;
4162 msg->data = irte_info->index;
4171 struct amd_irte_ops irte_32_ops = {
4172 .prepare = irte_prepare,
4173 .activate = irte_activate,
4174 .deactivate = irte_deactivate,
4175 .set_affinity = irte_set_affinity,
4176 .set_allocated = irte_set_allocated,
4177 .is_allocated = irte_is_allocated,
4178 .clear_allocated = irte_clear_allocated,
4181 struct amd_irte_ops irte_128_ops = {
4182 .prepare = irte_ga_prepare,
4183 .activate = irte_ga_activate,
4184 .deactivate = irte_ga_deactivate,
4185 .set_affinity = irte_ga_set_affinity,
4186 .set_allocated = irte_ga_set_allocated,
4187 .is_allocated = irte_ga_is_allocated,
4188 .clear_allocated = irte_ga_clear_allocated,
4191 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4192 unsigned int nr_irqs, void *arg)
4194 struct irq_alloc_info *info = arg;
4195 struct irq_data *irq_data;
4196 struct amd_ir_data *data = NULL;
4197 struct irq_cfg *cfg;
4203 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4204 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4208 * With IRQ remapping enabled, don't need contiguous CPU vectors
4209 * to support multiple MSI interrupts.
4211 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4212 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4214 devid = get_devid(info);
4218 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4222 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4223 struct irq_remap_table *table;
4224 struct amd_iommu *iommu;
4226 table = alloc_irq_table(devid);
4228 if (!table->min_index) {
4230 * Keep the first 32 indexes free for IOAPIC
4233 table->min_index = 32;
4234 iommu = amd_iommu_rlookup_table[devid];
4235 for (i = 0; i < 32; ++i)
4236 iommu->irte_ops->set_allocated(table, i);
4238 WARN_ON(table->min_index != 32);
4239 index = info->ioapic_pin;
4244 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4246 index = alloc_irq_index(devid, nr_irqs, align);
4249 pr_warn("Failed to allocate IRTE\n");
4251 goto out_free_parent;
4254 for (i = 0; i < nr_irqs; i++) {
4255 irq_data = irq_domain_get_irq_data(domain, virq + i);
4256 cfg = irqd_cfg(irq_data);
4257 if (!irq_data || !cfg) {
4263 data = kzalloc(sizeof(*data), GFP_KERNEL);
4267 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4268 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4270 data->entry = kzalloc(sizeof(struct irte_ga),
4277 irq_data->hwirq = (devid << 16) + i;
4278 irq_data->chip_data = data;
4279 irq_data->chip = &amd_ir_chip;
4280 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4281 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4287 for (i--; i >= 0; i--) {
4288 irq_data = irq_domain_get_irq_data(domain, virq + i);
4290 kfree(irq_data->chip_data);
4292 for (i = 0; i < nr_irqs; i++)
4293 free_irte(devid, index + i);
4295 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4299 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4300 unsigned int nr_irqs)
4302 struct irq_2_irte *irte_info;
4303 struct irq_data *irq_data;
4304 struct amd_ir_data *data;
4307 for (i = 0; i < nr_irqs; i++) {
4308 irq_data = irq_domain_get_irq_data(domain, virq + i);
4309 if (irq_data && irq_data->chip_data) {
4310 data = irq_data->chip_data;
4311 irte_info = &data->irq_2_irte;
4312 free_irte(irte_info->devid, irte_info->index);
4317 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4320 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4321 struct amd_ir_data *ir_data,
4322 struct irq_2_irte *irte_info,
4323 struct irq_cfg *cfg);
4325 static int irq_remapping_activate(struct irq_domain *domain,
4326 struct irq_data *irq_data, bool reserve)
4328 struct amd_ir_data *data = irq_data->chip_data;
4329 struct irq_2_irte *irte_info = &data->irq_2_irte;
4330 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4331 struct irq_cfg *cfg = irqd_cfg(irq_data);
4336 iommu->irte_ops->activate(data->entry, irte_info->devid,
4338 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4342 static void irq_remapping_deactivate(struct irq_domain *domain,
4343 struct irq_data *irq_data)
4345 struct amd_ir_data *data = irq_data->chip_data;
4346 struct irq_2_irte *irte_info = &data->irq_2_irte;
4347 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4350 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4354 static const struct irq_domain_ops amd_ir_domain_ops = {
4355 .alloc = irq_remapping_alloc,
4356 .free = irq_remapping_free,
4357 .activate = irq_remapping_activate,
4358 .deactivate = irq_remapping_deactivate,
4361 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4363 struct amd_iommu *iommu;
4364 struct amd_iommu_pi_data *pi_data = vcpu_info;
4365 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4366 struct amd_ir_data *ir_data = data->chip_data;
4367 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4368 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4369 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4372 * This device has never been set up for guest mode.
4373 * we should not modify the IRTE
4375 if (!dev_data || !dev_data->use_vapic)
4378 pi_data->ir_data = ir_data;
4381 * SVM tries to set up for VAPIC mode, but we are in
4382 * legacy mode. So, we force legacy mode instead.
4384 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4385 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4387 pi_data->is_guest_mode = false;
4390 iommu = amd_iommu_rlookup_table[irte_info->devid];
4394 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4395 if (pi_data->is_guest_mode) {
4397 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4398 irte->hi.fields.vector = vcpu_pi_info->vector;
4399 irte->lo.fields_vapic.ga_log_intr = 1;
4400 irte->lo.fields_vapic.guest_mode = 1;
4401 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4403 ir_data->cached_ga_tag = pi_data->ga_tag;
4406 struct irq_cfg *cfg = irqd_cfg(data);
4410 irte->hi.fields.vector = cfg->vector;
4411 irte->lo.fields_remap.guest_mode = 0;
4412 irte->lo.fields_remap.destination =
4413 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4414 irte->hi.fields.destination =
4415 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4416 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4417 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4420 * This communicates the ga_tag back to the caller
4421 * so that it can do all the necessary clean up.
4423 ir_data->cached_ga_tag = 0;
4426 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4430 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4431 struct amd_ir_data *ir_data,
4432 struct irq_2_irte *irte_info,
4433 struct irq_cfg *cfg)
4437 * Atomically updates the IRTE with the new destination, vector
4438 * and flushes the interrupt entry cache.
4440 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4441 irte_info->index, cfg->vector,
4445 static int amd_ir_set_affinity(struct irq_data *data,
4446 const struct cpumask *mask, bool force)
4448 struct amd_ir_data *ir_data = data->chip_data;
4449 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4450 struct irq_cfg *cfg = irqd_cfg(data);
4451 struct irq_data *parent = data->parent_data;
4452 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4458 ret = parent->chip->irq_set_affinity(parent, mask, force);
4459 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4462 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4464 * After this point, all the interrupts will start arriving
4465 * at the new destination. So, time to cleanup the previous
4466 * vector allocation.
4468 send_cleanup_vector(cfg);
4470 return IRQ_SET_MASK_OK_DONE;
4473 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4475 struct amd_ir_data *ir_data = irq_data->chip_data;
4477 *msg = ir_data->msi_entry;
4480 static struct irq_chip amd_ir_chip = {
4482 .irq_ack = apic_ack_irq,
4483 .irq_set_affinity = amd_ir_set_affinity,
4484 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4485 .irq_compose_msi_msg = ir_compose_msi_msg,
4488 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4490 struct fwnode_handle *fn;
4492 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4495 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4496 irq_domain_free_fwnode(fn);
4497 if (!iommu->ir_domain)
4500 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4501 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4507 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4509 unsigned long flags;
4510 struct amd_iommu *iommu;
4511 struct irq_remap_table *table;
4512 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4513 int devid = ir_data->irq_2_irte.devid;
4514 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4515 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4517 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4518 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4521 iommu = amd_iommu_rlookup_table[devid];
4525 table = get_irq_table(devid);
4529 raw_spin_lock_irqsave(&table->lock, flags);
4531 if (ref->lo.fields_vapic.guest_mode) {
4533 ref->lo.fields_vapic.destination =
4534 APICID_TO_IRTE_DEST_LO(cpu);
4535 ref->hi.fields.destination =
4536 APICID_TO_IRTE_DEST_HI(cpu);
4538 ref->lo.fields_vapic.is_run = is_run;
4542 raw_spin_unlock_irqrestore(&table->lock, flags);
4544 iommu_flush_irt(iommu, devid);
4545 iommu_completion_wait(iommu);
4548 EXPORT_SYMBOL(amd_iommu_update_ga);