1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, Linaro Limited
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/module.h>
11 #include <linux/of_platform.h>
12 #include <dt-bindings/interconnect/qcom,sm8450.h>
14 #include "bcm-voter.h"
15 #include "icc-common.h"
19 static struct qcom_icc_node qhm_qspi = {
21 .id = SM8450_MASTER_QSPI_0,
25 .links = { SM8450_SLAVE_A1NOC_SNOC },
28 static struct qcom_icc_node qhm_qup1 = {
30 .id = SM8450_MASTER_QUP_1,
34 .links = { SM8450_SLAVE_A1NOC_SNOC },
37 static struct qcom_icc_node qnm_a1noc_cfg = {
38 .name = "qnm_a1noc_cfg",
39 .id = SM8450_MASTER_A1NOC_CFG,
43 .links = { SM8450_SLAVE_SERVICE_A1NOC },
46 static struct qcom_icc_node xm_sdc4 = {
48 .id = SM8450_MASTER_SDCC_4,
52 .links = { SM8450_SLAVE_A1NOC_SNOC },
55 static struct qcom_icc_node xm_ufs_mem = {
57 .id = SM8450_MASTER_UFS_MEM,
61 .links = { SM8450_SLAVE_A1NOC_SNOC },
64 static struct qcom_icc_node xm_usb3_0 = {
66 .id = SM8450_MASTER_USB3_0,
70 .links = { SM8450_SLAVE_A1NOC_SNOC },
73 static struct qcom_icc_node qhm_qdss_bam = {
74 .name = "qhm_qdss_bam",
75 .id = SM8450_MASTER_QDSS_BAM,
79 .links = { SM8450_SLAVE_A2NOC_SNOC },
82 static struct qcom_icc_node qhm_qup0 = {
84 .id = SM8450_MASTER_QUP_0,
88 .links = { SM8450_SLAVE_A2NOC_SNOC },
91 static struct qcom_icc_node qhm_qup2 = {
93 .id = SM8450_MASTER_QUP_2,
97 .links = { SM8450_SLAVE_A2NOC_SNOC },
100 static struct qcom_icc_node qnm_a2noc_cfg = {
101 .name = "qnm_a2noc_cfg",
102 .id = SM8450_MASTER_A2NOC_CFG,
106 .links = { SM8450_SLAVE_SERVICE_A2NOC },
109 static struct qcom_icc_node qxm_crypto = {
110 .name = "qxm_crypto",
111 .id = SM8450_MASTER_CRYPTO,
115 .links = { SM8450_SLAVE_A2NOC_SNOC },
118 static struct qcom_icc_node qxm_ipa = {
120 .id = SM8450_MASTER_IPA,
124 .links = { SM8450_SLAVE_A2NOC_SNOC },
127 static struct qcom_icc_node qxm_sensorss_q6 = {
128 .name = "qxm_sensorss_q6",
129 .id = SM8450_MASTER_SENSORS_PROC,
133 .links = { SM8450_SLAVE_A2NOC_SNOC },
136 static struct qcom_icc_node qxm_sp = {
138 .id = SM8450_MASTER_SP,
142 .links = { SM8450_SLAVE_A2NOC_SNOC },
145 static struct qcom_icc_node xm_qdss_etr_0 = {
146 .name = "xm_qdss_etr_0",
147 .id = SM8450_MASTER_QDSS_ETR,
151 .links = { SM8450_SLAVE_A2NOC_SNOC },
154 static struct qcom_icc_node xm_qdss_etr_1 = {
155 .name = "xm_qdss_etr_1",
156 .id = SM8450_MASTER_QDSS_ETR_1,
160 .links = { SM8450_SLAVE_A2NOC_SNOC },
163 static struct qcom_icc_node xm_sdc2 = {
165 .id = SM8450_MASTER_SDCC_2,
169 .links = { SM8450_SLAVE_A2NOC_SNOC },
172 static struct qcom_icc_node qup0_core_master = {
173 .name = "qup0_core_master",
174 .id = SM8450_MASTER_QUP_CORE_0,
178 .links = { SM8450_SLAVE_QUP_CORE_0 },
181 static struct qcom_icc_node qup1_core_master = {
182 .name = "qup1_core_master",
183 .id = SM8450_MASTER_QUP_CORE_1,
187 .links = { SM8450_SLAVE_QUP_CORE_1 },
190 static struct qcom_icc_node qup2_core_master = {
191 .name = "qup2_core_master",
192 .id = SM8450_MASTER_QUP_CORE_2,
196 .links = { SM8450_SLAVE_QUP_CORE_2 },
199 static struct qcom_icc_node qnm_gemnoc_cnoc = {
200 .name = "qnm_gemnoc_cnoc",
201 .id = SM8450_MASTER_GEM_NOC_CNOC,
205 .links = { SM8450_SLAVE_AHB2PHY_SOUTH, SM8450_SLAVE_AHB2PHY_NORTH,
206 SM8450_SLAVE_AOSS, SM8450_SLAVE_CAMERA_CFG,
207 SM8450_SLAVE_CLK_CTL, SM8450_SLAVE_CDSP_CFG,
208 SM8450_SLAVE_RBCPR_CX_CFG, SM8450_SLAVE_RBCPR_MMCX_CFG,
209 SM8450_SLAVE_RBCPR_MXA_CFG, SM8450_SLAVE_RBCPR_MXC_CFG,
210 SM8450_SLAVE_CRYPTO_0_CFG, SM8450_SLAVE_CX_RDPM,
211 SM8450_SLAVE_DISPLAY_CFG, SM8450_SLAVE_GFX3D_CFG,
212 SM8450_SLAVE_IMEM_CFG, SM8450_SLAVE_IPA_CFG,
213 SM8450_SLAVE_IPC_ROUTER_CFG, SM8450_SLAVE_LPASS,
214 SM8450_SLAVE_CNOC_MSS, SM8450_SLAVE_MX_RDPM,
215 SM8450_SLAVE_PCIE_0_CFG, SM8450_SLAVE_PCIE_1_CFG,
216 SM8450_SLAVE_PDM, SM8450_SLAVE_PIMEM_CFG,
217 SM8450_SLAVE_PRNG, SM8450_SLAVE_QDSS_CFG,
218 SM8450_SLAVE_QSPI_0, SM8450_SLAVE_QUP_0,
219 SM8450_SLAVE_QUP_1, SM8450_SLAVE_QUP_2,
220 SM8450_SLAVE_SDCC_2, SM8450_SLAVE_SDCC_4,
221 SM8450_SLAVE_SPSS_CFG, SM8450_SLAVE_TCSR,
222 SM8450_SLAVE_TLMM, SM8450_SLAVE_TME_CFG,
223 SM8450_SLAVE_UFS_MEM_CFG, SM8450_SLAVE_USB3_0,
224 SM8450_SLAVE_VENUS_CFG, SM8450_SLAVE_VSENSE_CTRL_CFG,
225 SM8450_SLAVE_A1NOC_CFG, SM8450_SLAVE_A2NOC_CFG,
226 SM8450_SLAVE_DDRSS_CFG, SM8450_SLAVE_CNOC_MNOC_CFG,
227 SM8450_SLAVE_PCIE_ANOC_CFG, SM8450_SLAVE_SNOC_CFG,
228 SM8450_SLAVE_IMEM, SM8450_SLAVE_PIMEM,
229 SM8450_SLAVE_SERVICE_CNOC, SM8450_SLAVE_QDSS_STM,
233 static struct qcom_icc_node qnm_gemnoc_pcie = {
234 .name = "qnm_gemnoc_pcie",
235 .id = SM8450_MASTER_GEM_NOC_PCIE_SNOC,
239 .links = { SM8450_SLAVE_PCIE_0, SM8450_SLAVE_PCIE_1 },
242 static struct qcom_icc_node alm_gpu_tcu = {
243 .name = "alm_gpu_tcu",
244 .id = SM8450_MASTER_GPU_TCU,
248 .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
251 static struct qcom_icc_node alm_sys_tcu = {
252 .name = "alm_sys_tcu",
253 .id = SM8450_MASTER_SYS_TCU,
257 .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
260 static struct qcom_icc_node chm_apps = {
262 .id = SM8450_MASTER_APPSS_PROC,
266 .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC,
267 SM8450_SLAVE_MEM_NOC_PCIE_SNOC },
270 static struct qcom_icc_node qnm_gpu = {
272 .id = SM8450_MASTER_GFX3D,
276 .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
279 static struct qcom_icc_node qnm_mdsp = {
281 .id = SM8450_MASTER_MSS_PROC,
285 .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC,
286 SM8450_SLAVE_MEM_NOC_PCIE_SNOC },
289 static struct qcom_icc_node qnm_mnoc_hf = {
290 .name = "qnm_mnoc_hf",
291 .id = SM8450_MASTER_MNOC_HF_MEM_NOC,
295 .links = { SM8450_SLAVE_LLCC },
298 static struct qcom_icc_node qnm_mnoc_sf = {
299 .name = "qnm_mnoc_sf",
300 .id = SM8450_MASTER_MNOC_SF_MEM_NOC,
304 .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
307 static struct qcom_icc_node qnm_nsp_gemnoc = {
308 .name = "qnm_nsp_gemnoc",
309 .id = SM8450_MASTER_COMPUTE_NOC,
313 .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
316 static struct qcom_icc_node qnm_pcie = {
318 .id = SM8450_MASTER_ANOC_PCIE_GEM_NOC,
322 .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
325 static struct qcom_icc_node qnm_snoc_gc = {
326 .name = "qnm_snoc_gc",
327 .id = SM8450_MASTER_SNOC_GC_MEM_NOC,
331 .links = { SM8450_SLAVE_LLCC },
334 static struct qcom_icc_node qnm_snoc_sf = {
335 .name = "qnm_snoc_sf",
336 .id = SM8450_MASTER_SNOC_SF_MEM_NOC,
340 .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC,
341 SM8450_SLAVE_MEM_NOC_PCIE_SNOC },
344 static struct qcom_icc_node qhm_config_noc = {
345 .name = "qhm_config_noc",
346 .id = SM8450_MASTER_CNOC_LPASS_AG_NOC,
350 .links = { SM8450_SLAVE_LPASS_CORE_CFG, SM8450_SLAVE_LPASS_LPI_CFG,
351 SM8450_SLAVE_LPASS_MPU_CFG, SM8450_SLAVE_LPASS_TOP_CFG,
352 SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC },
355 static struct qcom_icc_node qxm_lpass_dsp = {
356 .name = "qxm_lpass_dsp",
357 .id = SM8450_MASTER_LPASS_PROC,
361 .links = { SM8450_SLAVE_LPASS_TOP_CFG, SM8450_SLAVE_LPASS_SNOC,
362 SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC },
365 static struct qcom_icc_node llcc_mc = {
367 .id = SM8450_MASTER_LLCC,
371 .links = { SM8450_SLAVE_EBI1 },
374 static struct qcom_icc_node qnm_camnoc_hf = {
375 .name = "qnm_camnoc_hf",
376 .id = SM8450_MASTER_CAMNOC_HF,
380 .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC },
383 static struct qcom_icc_node qnm_camnoc_icp = {
384 .name = "qnm_camnoc_icp",
385 .id = SM8450_MASTER_CAMNOC_ICP,
389 .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
392 static struct qcom_icc_node qnm_camnoc_sf = {
393 .name = "qnm_camnoc_sf",
394 .id = SM8450_MASTER_CAMNOC_SF,
398 .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
401 static struct qcom_icc_node qnm_mdp = {
403 .id = SM8450_MASTER_MDP,
407 .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC },
410 static struct qcom_icc_node qnm_mnoc_cfg = {
411 .name = "qnm_mnoc_cfg",
412 .id = SM8450_MASTER_CNOC_MNOC_CFG,
416 .links = { SM8450_SLAVE_SERVICE_MNOC },
419 static struct qcom_icc_node qnm_rot = {
421 .id = SM8450_MASTER_ROTATOR,
425 .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
428 static struct qcom_icc_node qnm_vapss_hcp = {
429 .name = "qnm_vapss_hcp",
430 .id = SM8450_MASTER_CDSP_HCP,
434 .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
437 static struct qcom_icc_node qnm_video = {
439 .id = SM8450_MASTER_VIDEO,
443 .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
446 static struct qcom_icc_node qnm_video_cv_cpu = {
447 .name = "qnm_video_cv_cpu",
448 .id = SM8450_MASTER_VIDEO_CV_PROC,
452 .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
455 static struct qcom_icc_node qnm_video_cvp = {
456 .name = "qnm_video_cvp",
457 .id = SM8450_MASTER_VIDEO_PROC,
461 .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
464 static struct qcom_icc_node qnm_video_v_cpu = {
465 .name = "qnm_video_v_cpu",
466 .id = SM8450_MASTER_VIDEO_V_PROC,
470 .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
473 static struct qcom_icc_node qhm_nsp_noc_config = {
474 .name = "qhm_nsp_noc_config",
475 .id = SM8450_MASTER_CDSP_NOC_CFG,
479 .links = { SM8450_SLAVE_SERVICE_NSP_NOC },
482 static struct qcom_icc_node qxm_nsp = {
484 .id = SM8450_MASTER_CDSP_PROC,
488 .links = { SM8450_SLAVE_CDSP_MEM_NOC },
491 static struct qcom_icc_node qnm_pcie_anoc_cfg = {
492 .name = "qnm_pcie_anoc_cfg",
493 .id = SM8450_MASTER_PCIE_ANOC_CFG,
497 .links = { SM8450_SLAVE_SERVICE_PCIE_ANOC },
500 static struct qcom_icc_node xm_pcie3_0 = {
501 .name = "xm_pcie3_0",
502 .id = SM8450_MASTER_PCIE_0,
506 .links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC },
509 static struct qcom_icc_node xm_pcie3_1 = {
510 .name = "xm_pcie3_1",
511 .id = SM8450_MASTER_PCIE_1,
515 .links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC },
518 static struct qcom_icc_node qhm_gic = {
520 .id = SM8450_MASTER_GIC_AHB,
524 .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
527 static struct qcom_icc_node qnm_aggre1_noc = {
528 .name = "qnm_aggre1_noc",
529 .id = SM8450_MASTER_A1NOC_SNOC,
533 .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
536 static struct qcom_icc_node qnm_aggre2_noc = {
537 .name = "qnm_aggre2_noc",
538 .id = SM8450_MASTER_A2NOC_SNOC,
542 .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
545 static struct qcom_icc_node qnm_lpass_noc = {
546 .name = "qnm_lpass_noc",
547 .id = SM8450_MASTER_LPASS_ANOC,
551 .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
554 static struct qcom_icc_node qnm_snoc_cfg = {
555 .name = "qnm_snoc_cfg",
556 .id = SM8450_MASTER_SNOC_CFG,
560 .links = { SM8450_SLAVE_SERVICE_SNOC },
563 static struct qcom_icc_node qxm_pimem = {
565 .id = SM8450_MASTER_PIMEM,
569 .links = { SM8450_SLAVE_SNOC_GEM_NOC_GC },
572 static struct qcom_icc_node xm_gic = {
574 .id = SM8450_MASTER_GIC,
578 .links = { SM8450_SLAVE_SNOC_GEM_NOC_GC },
581 static struct qcom_icc_node qnm_mnoc_hf_disp = {
582 .name = "qnm_mnoc_hf_disp",
583 .id = SM8450_MASTER_MNOC_HF_MEM_NOC_DISP,
587 .links = { SM8450_SLAVE_LLCC_DISP },
590 static struct qcom_icc_node qnm_mnoc_sf_disp = {
591 .name = "qnm_mnoc_sf_disp",
592 .id = SM8450_MASTER_MNOC_SF_MEM_NOC_DISP,
596 .links = { SM8450_SLAVE_LLCC_DISP },
599 static struct qcom_icc_node qnm_pcie_disp = {
600 .name = "qnm_pcie_disp",
601 .id = SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP,
605 .links = { SM8450_SLAVE_LLCC_DISP },
608 static struct qcom_icc_node llcc_mc_disp = {
609 .name = "llcc_mc_disp",
610 .id = SM8450_MASTER_LLCC_DISP,
614 .links = { SM8450_SLAVE_EBI1_DISP },
617 static struct qcom_icc_node qnm_mdp_disp = {
618 .name = "qnm_mdp_disp",
619 .id = SM8450_MASTER_MDP_DISP,
623 .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP },
626 static struct qcom_icc_node qnm_rot_disp = {
627 .name = "qnm_rot_disp",
628 .id = SM8450_MASTER_ROTATOR_DISP,
632 .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP },
635 static struct qcom_icc_node qns_a1noc_snoc = {
636 .name = "qns_a1noc_snoc",
637 .id = SM8450_SLAVE_A1NOC_SNOC,
641 .links = { SM8450_MASTER_A1NOC_SNOC },
644 static struct qcom_icc_node srvc_aggre1_noc = {
645 .name = "srvc_aggre1_noc",
646 .id = SM8450_SLAVE_SERVICE_A1NOC,
652 static struct qcom_icc_node qns_a2noc_snoc = {
653 .name = "qns_a2noc_snoc",
654 .id = SM8450_SLAVE_A2NOC_SNOC,
658 .links = { SM8450_MASTER_A2NOC_SNOC },
661 static struct qcom_icc_node srvc_aggre2_noc = {
662 .name = "srvc_aggre2_noc",
663 .id = SM8450_SLAVE_SERVICE_A2NOC,
669 static struct qcom_icc_node qup0_core_slave = {
670 .name = "qup0_core_slave",
671 .id = SM8450_SLAVE_QUP_CORE_0,
677 static struct qcom_icc_node qup1_core_slave = {
678 .name = "qup1_core_slave",
679 .id = SM8450_SLAVE_QUP_CORE_1,
685 static struct qcom_icc_node qup2_core_slave = {
686 .name = "qup2_core_slave",
687 .id = SM8450_SLAVE_QUP_CORE_2,
693 static struct qcom_icc_node qhs_ahb2phy0 = {
694 .name = "qhs_ahb2phy0",
695 .id = SM8450_SLAVE_AHB2PHY_SOUTH,
701 static struct qcom_icc_node qhs_ahb2phy1 = {
702 .name = "qhs_ahb2phy1",
703 .id = SM8450_SLAVE_AHB2PHY_NORTH,
709 static struct qcom_icc_node qhs_aoss = {
711 .id = SM8450_SLAVE_AOSS,
717 static struct qcom_icc_node qhs_camera_cfg = {
718 .name = "qhs_camera_cfg",
719 .id = SM8450_SLAVE_CAMERA_CFG,
725 static struct qcom_icc_node qhs_clk_ctl = {
726 .name = "qhs_clk_ctl",
727 .id = SM8450_SLAVE_CLK_CTL,
733 static struct qcom_icc_node qhs_compute_cfg = {
734 .name = "qhs_compute_cfg",
735 .id = SM8450_SLAVE_CDSP_CFG,
739 .links = { MASTER_CDSP_NOC_CFG },
742 static struct qcom_icc_node qhs_cpr_cx = {
743 .name = "qhs_cpr_cx",
744 .id = SM8450_SLAVE_RBCPR_CX_CFG,
750 static struct qcom_icc_node qhs_cpr_mmcx = {
751 .name = "qhs_cpr_mmcx",
752 .id = SM8450_SLAVE_RBCPR_MMCX_CFG,
758 static struct qcom_icc_node qhs_cpr_mxa = {
759 .name = "qhs_cpr_mxa",
760 .id = SM8450_SLAVE_RBCPR_MXA_CFG,
766 static struct qcom_icc_node qhs_cpr_mxc = {
767 .name = "qhs_cpr_mxc",
768 .id = SM8450_SLAVE_RBCPR_MXC_CFG,
774 static struct qcom_icc_node qhs_crypto0_cfg = {
775 .name = "qhs_crypto0_cfg",
776 .id = SM8450_SLAVE_CRYPTO_0_CFG,
782 static struct qcom_icc_node qhs_cx_rdpm = {
783 .name = "qhs_cx_rdpm",
784 .id = SM8450_SLAVE_CX_RDPM,
790 static struct qcom_icc_node qhs_display_cfg = {
791 .name = "qhs_display_cfg",
792 .id = SM8450_SLAVE_DISPLAY_CFG,
798 static struct qcom_icc_node qhs_gpuss_cfg = {
799 .name = "qhs_gpuss_cfg",
800 .id = SM8450_SLAVE_GFX3D_CFG,
806 static struct qcom_icc_node qhs_imem_cfg = {
807 .name = "qhs_imem_cfg",
808 .id = SM8450_SLAVE_IMEM_CFG,
814 static struct qcom_icc_node qhs_ipa = {
816 .id = SM8450_SLAVE_IPA_CFG,
822 static struct qcom_icc_node qhs_ipc_router = {
823 .name = "qhs_ipc_router",
824 .id = SM8450_SLAVE_IPC_ROUTER_CFG,
830 static struct qcom_icc_node qhs_lpass_cfg = {
831 .name = "qhs_lpass_cfg",
832 .id = SM8450_SLAVE_LPASS,
836 .links = { MASTER_CNOC_LPASS_AG_NOC },
839 static struct qcom_icc_node qhs_mss_cfg = {
840 .name = "qhs_mss_cfg",
841 .id = SM8450_SLAVE_CNOC_MSS,
847 static struct qcom_icc_node qhs_mx_rdpm = {
848 .name = "qhs_mx_rdpm",
849 .id = SM8450_SLAVE_MX_RDPM,
855 static struct qcom_icc_node qhs_pcie0_cfg = {
856 .name = "qhs_pcie0_cfg",
857 .id = SM8450_SLAVE_PCIE_0_CFG,
863 static struct qcom_icc_node qhs_pcie1_cfg = {
864 .name = "qhs_pcie1_cfg",
865 .id = SM8450_SLAVE_PCIE_1_CFG,
871 static struct qcom_icc_node qhs_pdm = {
873 .id = SM8450_SLAVE_PDM,
879 static struct qcom_icc_node qhs_pimem_cfg = {
880 .name = "qhs_pimem_cfg",
881 .id = SM8450_SLAVE_PIMEM_CFG,
887 static struct qcom_icc_node qhs_prng = {
889 .id = SM8450_SLAVE_PRNG,
895 static struct qcom_icc_node qhs_qdss_cfg = {
896 .name = "qhs_qdss_cfg",
897 .id = SM8450_SLAVE_QDSS_CFG,
903 static struct qcom_icc_node qhs_qspi = {
905 .id = SM8450_SLAVE_QSPI_0,
911 static struct qcom_icc_node qhs_qup0 = {
913 .id = SM8450_SLAVE_QUP_0,
919 static struct qcom_icc_node qhs_qup1 = {
921 .id = SM8450_SLAVE_QUP_1,
927 static struct qcom_icc_node qhs_qup2 = {
929 .id = SM8450_SLAVE_QUP_2,
935 static struct qcom_icc_node qhs_sdc2 = {
937 .id = SM8450_SLAVE_SDCC_2,
943 static struct qcom_icc_node qhs_sdc4 = {
945 .id = SM8450_SLAVE_SDCC_4,
951 static struct qcom_icc_node qhs_spss_cfg = {
952 .name = "qhs_spss_cfg",
953 .id = SM8450_SLAVE_SPSS_CFG,
959 static struct qcom_icc_node qhs_tcsr = {
961 .id = SM8450_SLAVE_TCSR,
967 static struct qcom_icc_node qhs_tlmm = {
969 .id = SM8450_SLAVE_TLMM,
975 static struct qcom_icc_node qhs_tme_cfg = {
976 .name = "qhs_tme_cfg",
977 .id = SM8450_SLAVE_TME_CFG,
983 static struct qcom_icc_node qhs_ufs_mem_cfg = {
984 .name = "qhs_ufs_mem_cfg",
985 .id = SM8450_SLAVE_UFS_MEM_CFG,
991 static struct qcom_icc_node qhs_usb3_0 = {
992 .name = "qhs_usb3_0",
993 .id = SM8450_SLAVE_USB3_0,
999 static struct qcom_icc_node qhs_venus_cfg = {
1000 .name = "qhs_venus_cfg",
1001 .id = SM8450_SLAVE_VENUS_CFG,
1007 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1008 .name = "qhs_vsense_ctrl_cfg",
1009 .id = SM8450_SLAVE_VSENSE_CTRL_CFG,
1015 static struct qcom_icc_node qns_a1_noc_cfg = {
1016 .name = "qns_a1_noc_cfg",
1017 .id = SM8450_SLAVE_A1NOC_CFG,
1021 .links = { SM8450_MASTER_A1NOC_CFG },
1024 static struct qcom_icc_node qns_a2_noc_cfg = {
1025 .name = "qns_a2_noc_cfg",
1026 .id = SM8450_SLAVE_A2NOC_CFG,
1030 .links = { SM8450_MASTER_A2NOC_CFG },
1033 static struct qcom_icc_node qns_ddrss_cfg = {
1034 .name = "qns_ddrss_cfg",
1035 .id = SM8450_SLAVE_DDRSS_CFG,
1039 //FIXME where is link
1042 static struct qcom_icc_node qns_mnoc_cfg = {
1043 .name = "qns_mnoc_cfg",
1044 .id = SM8450_SLAVE_CNOC_MNOC_CFG,
1048 .links = { SM8450_MASTER_CNOC_MNOC_CFG },
1051 static struct qcom_icc_node qns_pcie_anoc_cfg = {
1052 .name = "qns_pcie_anoc_cfg",
1053 .id = SM8450_SLAVE_PCIE_ANOC_CFG,
1057 .links = { SM8450_MASTER_PCIE_ANOC_CFG },
1060 static struct qcom_icc_node qns_snoc_cfg = {
1061 .name = "qns_snoc_cfg",
1062 .id = SM8450_SLAVE_SNOC_CFG,
1066 .links = { SM8450_MASTER_SNOC_CFG },
1069 static struct qcom_icc_node qxs_imem = {
1071 .id = SM8450_SLAVE_IMEM,
1077 static struct qcom_icc_node qxs_pimem = {
1078 .name = "qxs_pimem",
1079 .id = SM8450_SLAVE_PIMEM,
1085 static struct qcom_icc_node srvc_cnoc = {
1086 .name = "srvc_cnoc",
1087 .id = SM8450_SLAVE_SERVICE_CNOC,
1093 static struct qcom_icc_node xs_pcie_0 = {
1094 .name = "xs_pcie_0",
1095 .id = SM8450_SLAVE_PCIE_0,
1101 static struct qcom_icc_node xs_pcie_1 = {
1102 .name = "xs_pcie_1",
1103 .id = SM8450_SLAVE_PCIE_1,
1109 static struct qcom_icc_node xs_qdss_stm = {
1110 .name = "xs_qdss_stm",
1111 .id = SM8450_SLAVE_QDSS_STM,
1117 static struct qcom_icc_node xs_sys_tcu_cfg = {
1118 .name = "xs_sys_tcu_cfg",
1119 .id = SM8450_SLAVE_TCU,
1125 static struct qcom_icc_node qns_gem_noc_cnoc = {
1126 .name = "qns_gem_noc_cnoc",
1127 .id = SM8450_SLAVE_GEM_NOC_CNOC,
1131 .links = { SM8450_MASTER_GEM_NOC_CNOC },
1134 static struct qcom_icc_node qns_llcc = {
1136 .id = SM8450_SLAVE_LLCC,
1140 .links = { SM8450_MASTER_LLCC },
1143 static struct qcom_icc_node qns_pcie = {
1145 .id = SM8450_SLAVE_MEM_NOC_PCIE_SNOC,
1149 .links = { SM8450_MASTER_GEM_NOC_PCIE_SNOC },
1152 static struct qcom_icc_node qhs_lpass_core = {
1153 .name = "qhs_lpass_core",
1154 .id = SM8450_SLAVE_LPASS_CORE_CFG,
1160 static struct qcom_icc_node qhs_lpass_lpi = {
1161 .name = "qhs_lpass_lpi",
1162 .id = SM8450_SLAVE_LPASS_LPI_CFG,
1168 static struct qcom_icc_node qhs_lpass_mpu = {
1169 .name = "qhs_lpass_mpu",
1170 .id = SM8450_SLAVE_LPASS_MPU_CFG,
1176 static struct qcom_icc_node qhs_lpass_top = {
1177 .name = "qhs_lpass_top",
1178 .id = SM8450_SLAVE_LPASS_TOP_CFG,
1184 static struct qcom_icc_node qns_sysnoc = {
1185 .name = "qns_sysnoc",
1186 .id = SM8450_SLAVE_LPASS_SNOC,
1190 .links = { SM8450_MASTER_LPASS_ANOC },
1193 static struct qcom_icc_node srvc_niu_aml_noc = {
1194 .name = "srvc_niu_aml_noc",
1195 .id = SM8450_SLAVE_SERVICES_LPASS_AML_NOC,
1201 static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1202 .name = "srvc_niu_lpass_agnoc",
1203 .id = SM8450_SLAVE_SERVICE_LPASS_AG_NOC,
1209 static struct qcom_icc_node ebi = {
1211 .id = SM8450_SLAVE_EBI1,
1217 static struct qcom_icc_node qns_mem_noc_hf = {
1218 .name = "qns_mem_noc_hf",
1219 .id = SM8450_SLAVE_MNOC_HF_MEM_NOC,
1223 .links = { SM8450_MASTER_MNOC_HF_MEM_NOC },
1226 static struct qcom_icc_node qns_mem_noc_sf = {
1227 .name = "qns_mem_noc_sf",
1228 .id = SM8450_SLAVE_MNOC_SF_MEM_NOC,
1232 .links = { SM8450_MASTER_MNOC_SF_MEM_NOC },
1235 static struct qcom_icc_node srvc_mnoc = {
1236 .name = "srvc_mnoc",
1237 .id = SM8450_SLAVE_SERVICE_MNOC,
1243 static struct qcom_icc_node qns_nsp_gemnoc = {
1244 .name = "qns_nsp_gemnoc",
1245 .id = SM8450_SLAVE_CDSP_MEM_NOC,
1249 .links = { SM8450_MASTER_COMPUTE_NOC },
1252 static struct qcom_icc_node service_nsp_noc = {
1253 .name = "service_nsp_noc",
1254 .id = SM8450_SLAVE_SERVICE_NSP_NOC,
1260 static struct qcom_icc_node qns_pcie_mem_noc = {
1261 .name = "qns_pcie_mem_noc",
1262 .id = SM8450_SLAVE_ANOC_PCIE_GEM_NOC,
1266 .links = { SM8450_MASTER_ANOC_PCIE_GEM_NOC },
1269 static struct qcom_icc_node srvc_pcie_aggre_noc = {
1270 .name = "srvc_pcie_aggre_noc",
1271 .id = SM8450_SLAVE_SERVICE_PCIE_ANOC,
1277 static struct qcom_icc_node qns_gemnoc_gc = {
1278 .name = "qns_gemnoc_gc",
1279 .id = SM8450_SLAVE_SNOC_GEM_NOC_GC,
1283 .links = { SM8450_MASTER_SNOC_GC_MEM_NOC },
1286 static struct qcom_icc_node qns_gemnoc_sf = {
1287 .name = "qns_gemnoc_sf",
1288 .id = SM8450_SLAVE_SNOC_GEM_NOC_SF,
1292 .links = { SM8450_MASTER_SNOC_SF_MEM_NOC },
1295 static struct qcom_icc_node srvc_snoc = {
1296 .name = "srvc_snoc",
1297 .id = SM8450_SLAVE_SERVICE_SNOC,
1303 static struct qcom_icc_node qns_llcc_disp = {
1304 .name = "qns_llcc_disp",
1305 .id = SM8450_SLAVE_LLCC_DISP,
1309 .links = { SM8450_MASTER_LLCC_DISP },
1312 static struct qcom_icc_node ebi_disp = {
1314 .id = SM8450_SLAVE_EBI1_DISP,
1320 static struct qcom_icc_node qns_mem_noc_hf_disp = {
1321 .name = "qns_mem_noc_hf_disp",
1322 .id = SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP,
1326 .links = { SM8450_MASTER_MNOC_HF_MEM_NOC_DISP },
1329 static struct qcom_icc_node qns_mem_noc_sf_disp = {
1330 .name = "qns_mem_noc_sf_disp",
1331 .id = SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP,
1335 .links = { SM8450_MASTER_MNOC_SF_MEM_NOC_DISP },
1338 static struct qcom_icc_bcm bcm_acv = {
1344 static struct qcom_icc_bcm bcm_ce0 = {
1347 .nodes = { &qxm_crypto },
1350 static struct qcom_icc_bcm bcm_cn0 = {
1354 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
1355 &qhs_ahb2phy0, &qhs_ahb2phy1,
1356 &qhs_aoss, &qhs_camera_cfg,
1357 &qhs_clk_ctl, &qhs_compute_cfg,
1358 &qhs_cpr_cx, &qhs_cpr_mmcx,
1359 &qhs_cpr_mxa, &qhs_cpr_mxc,
1360 &qhs_crypto0_cfg, &qhs_cx_rdpm,
1361 &qhs_display_cfg, &qhs_gpuss_cfg,
1362 &qhs_imem_cfg, &qhs_ipa,
1363 &qhs_ipc_router, &qhs_lpass_cfg,
1364 &qhs_mss_cfg, &qhs_mx_rdpm,
1365 &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1366 &qhs_pdm, &qhs_pimem_cfg,
1367 &qhs_prng, &qhs_qdss_cfg,
1368 &qhs_qspi, &qhs_qup0,
1369 &qhs_qup1, &qhs_qup2,
1370 &qhs_sdc2, &qhs_sdc4,
1371 &qhs_spss_cfg, &qhs_tcsr,
1372 &qhs_tlmm, &qhs_tme_cfg,
1373 &qhs_ufs_mem_cfg, &qhs_usb3_0,
1374 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
1375 &qns_a1_noc_cfg, &qns_a2_noc_cfg,
1376 &qns_ddrss_cfg, &qns_mnoc_cfg,
1377 &qns_pcie_anoc_cfg, &qns_snoc_cfg,
1378 &qxs_imem, &qxs_pimem,
1379 &srvc_cnoc, &xs_pcie_0,
1380 &xs_pcie_1, &xs_qdss_stm,
1384 static struct qcom_icc_bcm bcm_co0 = {
1387 .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1390 static struct qcom_icc_bcm bcm_mc0 = {
1397 static struct qcom_icc_bcm bcm_mm0 = {
1401 .nodes = { &qns_mem_noc_hf },
1404 static struct qcom_icc_bcm bcm_mm1 = {
1407 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
1408 &qnm_camnoc_sf, &qnm_mdp,
1409 &qnm_mnoc_cfg, &qnm_rot,
1410 &qnm_vapss_hcp, &qnm_video,
1411 &qnm_video_cv_cpu, &qnm_video_cvp,
1412 &qnm_video_v_cpu, &qns_mem_noc_sf },
1415 static struct qcom_icc_bcm bcm_qup0 = {
1420 .nodes = { &qup0_core_slave },
1423 static struct qcom_icc_bcm bcm_qup1 = {
1428 .nodes = { &qup1_core_slave },
1431 static struct qcom_icc_bcm bcm_qup2 = {
1436 .nodes = { &qup2_core_slave },
1439 static struct qcom_icc_bcm bcm_sh0 = {
1443 .nodes = { &qns_llcc },
1446 static struct qcom_icc_bcm bcm_sh1 = {
1449 .nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1450 &qnm_nsp_gemnoc, &qnm_pcie,
1451 &qnm_snoc_gc, &qns_gem_noc_cnoc,
1455 static struct qcom_icc_bcm bcm_sn0 = {
1459 .nodes = { &qns_gemnoc_sf },
1462 static struct qcom_icc_bcm bcm_sn1 = {
1465 .nodes = { &qhm_gic, &qxm_pimem,
1466 &xm_gic, &qns_gemnoc_gc },
1469 static struct qcom_icc_bcm bcm_sn2 = {
1472 .nodes = { &qnm_aggre1_noc },
1475 static struct qcom_icc_bcm bcm_sn3 = {
1478 .nodes = { &qnm_aggre2_noc },
1481 static struct qcom_icc_bcm bcm_sn4 = {
1484 .nodes = { &qnm_lpass_noc },
1487 static struct qcom_icc_bcm bcm_sn7 = {
1490 .nodes = { &qns_pcie_mem_noc },
1493 static struct qcom_icc_bcm bcm_acv_disp = {
1496 .nodes = { &ebi_disp },
1499 static struct qcom_icc_bcm bcm_mc0_disp = {
1502 .nodes = { &ebi_disp },
1505 static struct qcom_icc_bcm bcm_mm0_disp = {
1508 .nodes = { &qns_mem_noc_hf_disp },
1511 static struct qcom_icc_bcm bcm_mm1_disp = {
1514 .nodes = { &qnm_mdp_disp, &qnm_rot_disp,
1515 &qns_mem_noc_sf_disp },
1518 static struct qcom_icc_bcm bcm_sh0_disp = {
1521 .nodes = { &qns_llcc_disp },
1524 static struct qcom_icc_bcm bcm_sh1_disp = {
1527 .nodes = { &qnm_pcie_disp },
1530 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1533 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1534 [MASTER_QSPI_0] = &qhm_qspi,
1535 [MASTER_QUP_1] = &qhm_qup1,
1536 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
1537 [MASTER_SDCC_4] = &xm_sdc4,
1538 [MASTER_UFS_MEM] = &xm_ufs_mem,
1539 [MASTER_USB3_0] = &xm_usb3_0,
1540 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1541 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1544 static const struct qcom_icc_desc sm8450_aggre1_noc = {
1545 .nodes = aggre1_noc_nodes,
1546 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1547 .bcms = aggre1_noc_bcms,
1548 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1551 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1555 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1556 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1557 [MASTER_QUP_0] = &qhm_qup0,
1558 [MASTER_QUP_2] = &qhm_qup2,
1559 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
1560 [MASTER_CRYPTO] = &qxm_crypto,
1561 [MASTER_IPA] = &qxm_ipa,
1562 [MASTER_SENSORS_PROC] = &qxm_sensorss_q6,
1563 [MASTER_SP] = &qxm_sp,
1564 [MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1565 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1566 [MASTER_SDCC_2] = &xm_sdc2,
1567 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1568 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1571 static const struct qcom_icc_desc sm8450_aggre2_noc = {
1572 .nodes = aggre2_noc_nodes,
1573 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1574 .bcms = aggre2_noc_bcms,
1575 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1578 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1584 static struct qcom_icc_node * const clk_virt_nodes[] = {
1585 [MASTER_QUP_CORE_0] = &qup0_core_master,
1586 [MASTER_QUP_CORE_1] = &qup1_core_master,
1587 [MASTER_QUP_CORE_2] = &qup2_core_master,
1588 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1589 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1590 [SLAVE_QUP_CORE_2] = &qup2_core_slave,
1593 static const struct qcom_icc_desc sm8450_clk_virt = {
1594 .nodes = clk_virt_nodes,
1595 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1596 .bcms = clk_virt_bcms,
1597 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1600 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1604 static struct qcom_icc_node * const config_noc_nodes[] = {
1605 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1606 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1607 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1608 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1609 [SLAVE_AOSS] = &qhs_aoss,
1610 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1611 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1612 [SLAVE_CDSP_CFG] = &qhs_compute_cfg,
1613 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1614 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1615 [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa,
1616 [SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc,
1617 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1618 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1619 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1620 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1621 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1622 [SLAVE_IPA_CFG] = &qhs_ipa,
1623 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1624 [SLAVE_LPASS] = &qhs_lpass_cfg,
1625 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1626 [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1627 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1628 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1629 [SLAVE_PDM] = &qhs_pdm,
1630 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1631 [SLAVE_PRNG] = &qhs_prng,
1632 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1633 [SLAVE_QSPI_0] = &qhs_qspi,
1634 [SLAVE_QUP_0] = &qhs_qup0,
1635 [SLAVE_QUP_1] = &qhs_qup1,
1636 [SLAVE_QUP_2] = &qhs_qup2,
1637 [SLAVE_SDCC_2] = &qhs_sdc2,
1638 [SLAVE_SDCC_4] = &qhs_sdc4,
1639 [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1640 [SLAVE_TCSR] = &qhs_tcsr,
1641 [SLAVE_TLMM] = &qhs_tlmm,
1642 [SLAVE_TME_CFG] = &qhs_tme_cfg,
1643 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1644 [SLAVE_USB3_0] = &qhs_usb3_0,
1645 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1646 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1647 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
1648 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
1649 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1650 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
1651 [SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg,
1652 [SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1653 [SLAVE_IMEM] = &qxs_imem,
1654 [SLAVE_PIMEM] = &qxs_pimem,
1655 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1656 [SLAVE_PCIE_0] = &xs_pcie_0,
1657 [SLAVE_PCIE_1] = &xs_pcie_1,
1658 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1659 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1662 static const struct qcom_icc_desc sm8450_config_noc = {
1663 .nodes = config_noc_nodes,
1664 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1665 .bcms = config_noc_bcms,
1666 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1669 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1676 static struct qcom_icc_node * const gem_noc_nodes[] = {
1677 [MASTER_GPU_TCU] = &alm_gpu_tcu,
1678 [MASTER_SYS_TCU] = &alm_sys_tcu,
1679 [MASTER_APPSS_PROC] = &chm_apps,
1680 [MASTER_GFX3D] = &qnm_gpu,
1681 [MASTER_MSS_PROC] = &qnm_mdsp,
1682 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1683 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1684 [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
1685 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1686 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1687 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1688 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1689 [SLAVE_LLCC] = &qns_llcc,
1690 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1691 [MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
1692 [MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp,
1693 [MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp,
1694 [SLAVE_LLCC_DISP] = &qns_llcc_disp,
1697 static const struct qcom_icc_desc sm8450_gem_noc = {
1698 .nodes = gem_noc_nodes,
1699 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1700 .bcms = gem_noc_bcms,
1701 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1704 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1707 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1708 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
1709 [MASTER_LPASS_PROC] = &qxm_lpass_dsp,
1710 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
1711 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
1712 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
1713 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
1714 [SLAVE_LPASS_SNOC] = &qns_sysnoc,
1715 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
1716 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
1719 static const struct qcom_icc_desc sm8450_lpass_ag_noc = {
1720 .nodes = lpass_ag_noc_nodes,
1721 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1722 .bcms = lpass_ag_noc_bcms,
1723 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1726 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1733 static struct qcom_icc_node * const mc_virt_nodes[] = {
1734 [MASTER_LLCC] = &llcc_mc,
1735 [SLAVE_EBI1] = &ebi,
1736 [MASTER_LLCC_DISP] = &llcc_mc_disp,
1737 [SLAVE_EBI1_DISP] = &ebi_disp,
1740 static const struct qcom_icc_desc sm8450_mc_virt = {
1741 .nodes = mc_virt_nodes,
1742 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1743 .bcms = mc_virt_bcms,
1744 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1747 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1754 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1755 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1756 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1757 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1758 [MASTER_MDP] = &qnm_mdp,
1759 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
1760 [MASTER_ROTATOR] = &qnm_rot,
1761 [MASTER_CDSP_HCP] = &qnm_vapss_hcp,
1762 [MASTER_VIDEO] = &qnm_video,
1763 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
1764 [MASTER_VIDEO_PROC] = &qnm_video_cvp,
1765 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1766 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1767 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1768 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1769 [MASTER_MDP_DISP] = &qnm_mdp_disp,
1770 [MASTER_ROTATOR_DISP] = &qnm_rot_disp,
1771 [SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
1772 [SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp,
1775 static const struct qcom_icc_desc sm8450_mmss_noc = {
1776 .nodes = mmss_noc_nodes,
1777 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1778 .bcms = mmss_noc_bcms,
1779 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1782 static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1786 static struct qcom_icc_node * const nsp_noc_nodes[] = {
1787 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
1788 [MASTER_CDSP_PROC] = &qxm_nsp,
1789 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1790 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
1793 static const struct qcom_icc_desc sm8450_nsp_noc = {
1794 .nodes = nsp_noc_nodes,
1795 .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1796 .bcms = nsp_noc_bcms,
1797 .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1800 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
1804 static struct qcom_icc_node * const pcie_anoc_nodes[] = {
1805 [MASTER_PCIE_ANOC_CFG] = &qnm_pcie_anoc_cfg,
1806 [MASTER_PCIE_0] = &xm_pcie3_0,
1807 [MASTER_PCIE_1] = &xm_pcie3_1,
1808 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1809 [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
1812 static const struct qcom_icc_desc sm8450_pcie_anoc = {
1813 .nodes = pcie_anoc_nodes,
1814 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
1815 .bcms = pcie_anoc_bcms,
1816 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
1819 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1827 static struct qcom_icc_node * const system_noc_nodes[] = {
1828 [MASTER_GIC_AHB] = &qhm_gic,
1829 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1830 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1831 [MASTER_LPASS_ANOC] = &qnm_lpass_noc,
1832 [MASTER_SNOC_CFG] = &qnm_snoc_cfg,
1833 [MASTER_PIMEM] = &qxm_pimem,
1834 [MASTER_GIC] = &xm_gic,
1835 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1836 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1837 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
1840 static const struct qcom_icc_desc sm8450_system_noc = {
1841 .nodes = system_noc_nodes,
1842 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1843 .bcms = system_noc_bcms,
1844 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1847 static int qnoc_probe(struct platform_device *pdev)
1849 const struct qcom_icc_desc *desc;
1850 struct icc_onecell_data *data;
1851 struct icc_provider *provider;
1852 struct qcom_icc_node * const *qnodes;
1853 struct qcom_icc_provider *qp;
1854 struct icc_node *node;
1855 size_t num_nodes, i;
1858 desc = device_get_match_data(&pdev->dev);
1862 qnodes = desc->nodes;
1863 num_nodes = desc->num_nodes;
1865 qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
1869 data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
1873 provider = &qp->provider;
1874 provider->dev = &pdev->dev;
1875 provider->set = qcom_icc_set;
1876 provider->pre_aggregate = qcom_icc_pre_aggregate;
1877 provider->aggregate = qcom_icc_aggregate;
1878 provider->xlate_extended = qcom_icc_xlate_extended;
1879 INIT_LIST_HEAD(&provider->nodes);
1880 provider->data = data;
1882 qp->dev = &pdev->dev;
1883 qp->bcms = desc->bcms;
1884 qp->num_bcms = desc->num_bcms;
1886 qp->voter = of_bcm_voter_get(qp->dev, NULL);
1887 if (IS_ERR(qp->voter))
1888 return PTR_ERR(qp->voter);
1890 ret = icc_provider_add(provider);
1892 dev_err(&pdev->dev, "error adding interconnect provider\n");
1896 for (i = 0; i < qp->num_bcms; i++)
1897 qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
1899 for (i = 0; i < num_nodes; i++) {
1905 node = icc_node_create(qnodes[i]->id);
1907 ret = PTR_ERR(node);
1911 node->name = qnodes[i]->name;
1912 node->data = qnodes[i];
1913 icc_node_add(node, provider);
1915 for (j = 0; j < qnodes[i]->num_links; j++)
1916 icc_link_create(node, qnodes[i]->links[j]);
1918 data->nodes[i] = node;
1920 data->num_nodes = num_nodes;
1922 platform_set_drvdata(pdev, qp);
1926 icc_nodes_remove(provider);
1927 icc_provider_del(provider);
1931 static int qnoc_remove(struct platform_device *pdev)
1933 struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
1935 icc_nodes_remove(&qp->provider);
1936 icc_provider_del(&qp->provider);
1941 static const struct of_device_id qnoc_of_match[] = {
1942 { .compatible = "qcom,sm8450-aggre1-noc",
1943 .data = &sm8450_aggre1_noc},
1944 { .compatible = "qcom,sm8450-aggre2-noc",
1945 .data = &sm8450_aggre2_noc},
1946 { .compatible = "qcom,sm8450-clk-virt",
1947 .data = &sm8450_clk_virt},
1948 { .compatible = "qcom,sm8450-config-noc",
1949 .data = &sm8450_config_noc},
1950 { .compatible = "qcom,sm8450-gem-noc",
1951 .data = &sm8450_gem_noc},
1952 { .compatible = "qcom,sm8450-lpass-ag-noc",
1953 .data = &sm8450_lpass_ag_noc},
1954 { .compatible = "qcom,sm8450-mc-virt",
1955 .data = &sm8450_mc_virt},
1956 { .compatible = "qcom,sm8450-mmss-noc",
1957 .data = &sm8450_mmss_noc},
1958 { .compatible = "qcom,sm8450-nsp-noc",
1959 .data = &sm8450_nsp_noc},
1960 { .compatible = "qcom,sm8450-pcie-anoc",
1961 .data = &sm8450_pcie_anoc},
1962 { .compatible = "qcom,sm8450-system-noc",
1963 .data = &sm8450_system_noc},
1966 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1968 static struct platform_driver qnoc_driver = {
1969 .probe = qnoc_probe,
1970 .remove = qnoc_remove,
1972 .name = "qnoc-sm8450",
1973 .of_match_table = qnoc_of_match,
1977 static int __init qnoc_driver_init(void)
1979 return platform_driver_register(&qnoc_driver);
1981 core_initcall(qnoc_driver_init);
1983 static void __exit qnoc_driver_exit(void)
1985 platform_driver_unregister(&qnoc_driver);
1987 module_exit(qnoc_driver_exit);
1989 MODULE_DESCRIPTION("sm8450 NoC driver");
1990 MODULE_LICENSE("GPL v2");