1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, Linaro Limited
8 #include <linux/interconnect-provider.h>
9 #include <linux/module.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/platform_device.h>
12 #include <dt-bindings/interconnect/qcom,sm8350.h>
14 #include "bcm-voter.h"
18 static struct qcom_icc_node qhm_qspi = {
20 .id = SM8350_MASTER_QSPI_0,
24 .links = { SM8350_SLAVE_A1NOC_SNOC },
27 static struct qcom_icc_node qhm_qup0 = {
29 .id = SM8350_MASTER_QUP_0,
33 .links = { SM8350_SLAVE_A2NOC_SNOC },
36 static struct qcom_icc_node qhm_qup1 = {
38 .id = SM8350_MASTER_QUP_1,
42 .links = { SM8350_SLAVE_A1NOC_SNOC },
45 static struct qcom_icc_node qhm_qup2 = {
47 .id = SM8350_MASTER_QUP_2,
51 .links = { SM8350_SLAVE_A2NOC_SNOC },
54 static struct qcom_icc_node qnm_a1noc_cfg = {
55 .name = "qnm_a1noc_cfg",
56 .id = SM8350_MASTER_A1NOC_CFG,
60 .links = { SM8350_SLAVE_SERVICE_A1NOC },
63 static struct qcom_icc_node xm_sdc4 = {
65 .id = SM8350_MASTER_SDCC_4,
69 .links = { SM8350_SLAVE_A1NOC_SNOC },
72 static struct qcom_icc_node xm_ufs_mem = {
74 .id = SM8350_MASTER_UFS_MEM,
78 .links = { SM8350_SLAVE_A1NOC_SNOC },
81 static struct qcom_icc_node xm_usb3_0 = {
83 .id = SM8350_MASTER_USB3_0,
87 .links = { SM8350_SLAVE_A1NOC_SNOC },
90 static struct qcom_icc_node xm_usb3_1 = {
92 .id = SM8350_MASTER_USB3_1,
96 .links = { SM8350_SLAVE_A1NOC_SNOC },
99 static struct qcom_icc_node qhm_qdss_bam = {
100 .name = "qhm_qdss_bam",
101 .id = SM8350_MASTER_QDSS_BAM,
105 .links = { SM8350_SLAVE_A2NOC_SNOC },
108 static struct qcom_icc_node qnm_a2noc_cfg = {
109 .name = "qnm_a2noc_cfg",
110 .id = SM8350_MASTER_A2NOC_CFG,
114 .links = { SM8350_SLAVE_SERVICE_A2NOC },
117 static struct qcom_icc_node qxm_crypto = {
118 .name = "qxm_crypto",
119 .id = SM8350_MASTER_CRYPTO,
123 .links = { SM8350_SLAVE_A2NOC_SNOC },
126 static struct qcom_icc_node qxm_ipa = {
128 .id = SM8350_MASTER_IPA,
132 .links = { SM8350_SLAVE_A2NOC_SNOC },
135 static struct qcom_icc_node xm_pcie3_0 = {
136 .name = "xm_pcie3_0",
137 .id = SM8350_MASTER_PCIE_0,
141 .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC },
144 static struct qcom_icc_node xm_pcie3_1 = {
145 .name = "xm_pcie3_1",
146 .id = SM8350_MASTER_PCIE_1,
150 .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC },
153 static struct qcom_icc_node xm_qdss_etr = {
154 .name = "xm_qdss_etr",
155 .id = SM8350_MASTER_QDSS_ETR,
159 .links = { SM8350_SLAVE_A2NOC_SNOC },
162 static struct qcom_icc_node xm_sdc2 = {
164 .id = SM8350_MASTER_SDCC_2,
168 .links = { SM8350_SLAVE_A2NOC_SNOC },
171 static struct qcom_icc_node xm_ufs_card = {
172 .name = "xm_ufs_card",
173 .id = SM8350_MASTER_UFS_CARD,
177 .links = { SM8350_SLAVE_A2NOC_SNOC },
180 static struct qcom_icc_node qnm_gemnoc_cnoc = {
181 .name = "qnm_gemnoc_cnoc",
182 .id = SM8350_MASTER_GEM_NOC_CNOC,
186 .links = { SM8350_SLAVE_AHB2PHY_SOUTH,
187 SM8350_SLAVE_AHB2PHY_NORTH,
190 SM8350_SLAVE_CAMERA_CFG,
191 SM8350_SLAVE_CLK_CTL,
192 SM8350_SLAVE_CDSP_CFG,
193 SM8350_SLAVE_RBCPR_CX_CFG,
194 SM8350_SLAVE_RBCPR_MMCX_CFG,
195 SM8350_SLAVE_RBCPR_MX_CFG,
196 SM8350_SLAVE_CRYPTO_0_CFG,
197 SM8350_SLAVE_CX_RDPM,
198 SM8350_SLAVE_DCC_CFG,
199 SM8350_SLAVE_DISPLAY_CFG,
200 SM8350_SLAVE_GFX3D_CFG,
202 SM8350_SLAVE_IMEM_CFG,
203 SM8350_SLAVE_IPA_CFG,
204 SM8350_SLAVE_IPC_ROUTER_CFG,
206 SM8350_SLAVE_CNOC_MSS,
207 SM8350_SLAVE_MX_RDPM,
208 SM8350_SLAVE_PCIE_0_CFG,
209 SM8350_SLAVE_PCIE_1_CFG,
211 SM8350_SLAVE_PIMEM_CFG,
212 SM8350_SLAVE_PKA_WRAPPER_CFG,
213 SM8350_SLAVE_PMU_WRAPPER_CFG,
214 SM8350_SLAVE_QDSS_CFG,
221 SM8350_SLAVE_SECURITY,
222 SM8350_SLAVE_SPSS_CFG,
225 SM8350_SLAVE_UFS_CARD_CFG,
226 SM8350_SLAVE_UFS_MEM_CFG,
229 SM8350_SLAVE_VENUS_CFG,
230 SM8350_SLAVE_VSENSE_CTRL_CFG,
231 SM8350_SLAVE_A1NOC_CFG,
232 SM8350_SLAVE_A2NOC_CFG,
233 SM8350_SLAVE_DDRSS_CFG,
234 SM8350_SLAVE_CNOC_MNOC_CFG,
235 SM8350_SLAVE_SNOC_CFG,
236 SM8350_SLAVE_BOOT_IMEM,
239 SM8350_SLAVE_SERVICE_CNOC,
240 SM8350_SLAVE_QDSS_STM,
245 static struct qcom_icc_node qnm_gemnoc_pcie = {
246 .name = "qnm_gemnoc_pcie",
247 .id = SM8350_MASTER_GEM_NOC_PCIE_SNOC,
251 .links = { SM8350_SLAVE_PCIE_0,
256 static struct qcom_icc_node xm_qdss_dap = {
257 .name = "xm_qdss_dap",
258 .id = SM8350_MASTER_QDSS_DAP,
262 .links = { SM8350_SLAVE_AHB2PHY_SOUTH,
263 SM8350_SLAVE_AHB2PHY_NORTH,
266 SM8350_SLAVE_CAMERA_CFG,
267 SM8350_SLAVE_CLK_CTL,
268 SM8350_SLAVE_CDSP_CFG,
269 SM8350_SLAVE_RBCPR_CX_CFG,
270 SM8350_SLAVE_RBCPR_MMCX_CFG,
271 SM8350_SLAVE_RBCPR_MX_CFG,
272 SM8350_SLAVE_CRYPTO_0_CFG,
273 SM8350_SLAVE_CX_RDPM,
274 SM8350_SLAVE_DCC_CFG,
275 SM8350_SLAVE_DISPLAY_CFG,
276 SM8350_SLAVE_GFX3D_CFG,
278 SM8350_SLAVE_IMEM_CFG,
279 SM8350_SLAVE_IPA_CFG,
280 SM8350_SLAVE_IPC_ROUTER_CFG,
282 SM8350_SLAVE_CNOC_MSS,
283 SM8350_SLAVE_MX_RDPM,
284 SM8350_SLAVE_PCIE_0_CFG,
285 SM8350_SLAVE_PCIE_1_CFG,
287 SM8350_SLAVE_PIMEM_CFG,
288 SM8350_SLAVE_PKA_WRAPPER_CFG,
289 SM8350_SLAVE_PMU_WRAPPER_CFG,
290 SM8350_SLAVE_QDSS_CFG,
297 SM8350_SLAVE_SECURITY,
298 SM8350_SLAVE_SPSS_CFG,
301 SM8350_SLAVE_UFS_CARD_CFG,
302 SM8350_SLAVE_UFS_MEM_CFG,
305 SM8350_SLAVE_VENUS_CFG,
306 SM8350_SLAVE_VSENSE_CTRL_CFG,
307 SM8350_SLAVE_A1NOC_CFG,
308 SM8350_SLAVE_A2NOC_CFG,
309 SM8350_SLAVE_DDRSS_CFG,
310 SM8350_SLAVE_CNOC_MNOC_CFG,
311 SM8350_SLAVE_SNOC_CFG,
312 SM8350_SLAVE_BOOT_IMEM,
315 SM8350_SLAVE_SERVICE_CNOC,
316 SM8350_SLAVE_QDSS_STM,
321 static struct qcom_icc_node qnm_cnoc_dc_noc = {
322 .name = "qnm_cnoc_dc_noc",
323 .id = SM8350_MASTER_CNOC_DC_NOC,
327 .links = { SM8350_SLAVE_LLCC_CFG,
328 SM8350_SLAVE_GEM_NOC_CFG
332 static struct qcom_icc_node alm_gpu_tcu = {
333 .name = "alm_gpu_tcu",
334 .id = SM8350_MASTER_GPU_TCU,
338 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
343 static struct qcom_icc_node alm_sys_tcu = {
344 .name = "alm_sys_tcu",
345 .id = SM8350_MASTER_SYS_TCU,
349 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
354 static struct qcom_icc_node chm_apps = {
356 .id = SM8350_MASTER_APPSS_PROC,
360 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
362 SM8350_SLAVE_MEM_NOC_PCIE_SNOC
366 static struct qcom_icc_node qnm_cmpnoc = {
367 .name = "qnm_cmpnoc",
368 .id = SM8350_MASTER_COMPUTE_NOC,
372 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
377 static struct qcom_icc_node qnm_gemnoc_cfg = {
378 .name = "qnm_gemnoc_cfg",
379 .id = SM8350_MASTER_GEM_NOC_CFG,
383 .links = { SM8350_SLAVE_MSS_PROC_MS_MPU_CFG,
384 SM8350_SLAVE_MCDMA_MS_MPU_CFG,
385 SM8350_SLAVE_SERVICE_GEM_NOC_1,
386 SM8350_SLAVE_SERVICE_GEM_NOC_2,
387 SM8350_SLAVE_SERVICE_GEM_NOC
391 static struct qcom_icc_node qnm_gpu = {
393 .id = SM8350_MASTER_GFX3D,
397 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
402 static struct qcom_icc_node qnm_mnoc_hf = {
403 .name = "qnm_mnoc_hf",
404 .id = SM8350_MASTER_MNOC_HF_MEM_NOC,
408 .links = { SM8350_SLAVE_LLCC },
411 static struct qcom_icc_node qnm_mnoc_sf = {
412 .name = "qnm_mnoc_sf",
413 .id = SM8350_MASTER_MNOC_SF_MEM_NOC,
417 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
422 static struct qcom_icc_node qnm_pcie = {
424 .id = SM8350_MASTER_ANOC_PCIE_GEM_NOC,
428 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
433 static struct qcom_icc_node qnm_snoc_gc = {
434 .name = "qnm_snoc_gc",
435 .id = SM8350_MASTER_SNOC_GC_MEM_NOC,
439 .links = { SM8350_SLAVE_LLCC },
442 static struct qcom_icc_node qnm_snoc_sf = {
443 .name = "qnm_snoc_sf",
444 .id = SM8350_MASTER_SNOC_SF_MEM_NOC,
448 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
450 SM8350_SLAVE_MEM_NOC_PCIE_SNOC
454 static struct qcom_icc_node qhm_config_noc = {
455 .name = "qhm_config_noc",
456 .id = SM8350_MASTER_CNOC_LPASS_AG_NOC,
460 .links = { SM8350_SLAVE_LPASS_CORE_CFG,
461 SM8350_SLAVE_LPASS_LPI_CFG,
462 SM8350_SLAVE_LPASS_MPU_CFG,
463 SM8350_SLAVE_LPASS_TOP_CFG,
464 SM8350_SLAVE_SERVICES_LPASS_AML_NOC,
465 SM8350_SLAVE_SERVICE_LPASS_AG_NOC
469 static struct qcom_icc_node llcc_mc = {
471 .id = SM8350_MASTER_LLCC,
475 .links = { SM8350_SLAVE_EBI1 },
478 static struct qcom_icc_node qnm_camnoc_hf = {
479 .name = "qnm_camnoc_hf",
480 .id = SM8350_MASTER_CAMNOC_HF,
484 .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC },
487 static struct qcom_icc_node qnm_camnoc_icp = {
488 .name = "qnm_camnoc_icp",
489 .id = SM8350_MASTER_CAMNOC_ICP,
493 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
496 static struct qcom_icc_node qnm_camnoc_sf = {
497 .name = "qnm_camnoc_sf",
498 .id = SM8350_MASTER_CAMNOC_SF,
502 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
505 static struct qcom_icc_node qnm_mnoc_cfg = {
506 .name = "qnm_mnoc_cfg",
507 .id = SM8350_MASTER_CNOC_MNOC_CFG,
511 .links = { SM8350_SLAVE_SERVICE_MNOC },
514 static struct qcom_icc_node qnm_video0 = {
515 .name = "qnm_video0",
516 .id = SM8350_MASTER_VIDEO_P0,
520 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
523 static struct qcom_icc_node qnm_video1 = {
524 .name = "qnm_video1",
525 .id = SM8350_MASTER_VIDEO_P1,
529 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
532 static struct qcom_icc_node qnm_video_cvp = {
533 .name = "qnm_video_cvp",
534 .id = SM8350_MASTER_VIDEO_PROC,
538 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
541 static struct qcom_icc_node qxm_mdp0 = {
543 .id = SM8350_MASTER_MDP0,
547 .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC },
550 static struct qcom_icc_node qxm_mdp1 = {
552 .id = SM8350_MASTER_MDP1,
556 .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC },
559 static struct qcom_icc_node qxm_rot = {
561 .id = SM8350_MASTER_ROTATOR,
565 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
568 static struct qcom_icc_node qhm_nsp_noc_config = {
569 .name = "qhm_nsp_noc_config",
570 .id = SM8350_MASTER_CDSP_NOC_CFG,
574 .links = { SM8350_SLAVE_SERVICE_NSP_NOC },
577 static struct qcom_icc_node qxm_nsp = {
579 .id = SM8350_MASTER_CDSP_PROC,
583 .links = { SM8350_SLAVE_CDSP_MEM_NOC },
586 static struct qcom_icc_node qnm_aggre1_noc = {
587 .name = "qnm_aggre1_noc",
588 .id = SM8350_MASTER_A1NOC_SNOC,
592 .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF },
595 static struct qcom_icc_node qnm_aggre2_noc = {
596 .name = "qnm_aggre2_noc",
597 .id = SM8350_MASTER_A2NOC_SNOC,
601 .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF },
604 static struct qcom_icc_node qnm_snoc_cfg = {
605 .name = "qnm_snoc_cfg",
606 .id = SM8350_MASTER_SNOC_CFG,
610 .links = { SM8350_SLAVE_SERVICE_SNOC },
613 static struct qcom_icc_node qxm_pimem = {
615 .id = SM8350_MASTER_PIMEM,
619 .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC },
622 static struct qcom_icc_node xm_gic = {
624 .id = SM8350_MASTER_GIC,
628 .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC },
631 static struct qcom_icc_node qnm_mnoc_hf_disp = {
632 .name = "qnm_mnoc_hf_disp",
633 .id = SM8350_MASTER_MNOC_HF_MEM_NOC_DISP,
637 .links = { SM8350_SLAVE_LLCC_DISP },
640 static struct qcom_icc_node qnm_mnoc_sf_disp = {
641 .name = "qnm_mnoc_sf_disp",
642 .id = SM8350_MASTER_MNOC_SF_MEM_NOC_DISP,
646 .links = { SM8350_SLAVE_LLCC_DISP },
649 static struct qcom_icc_node llcc_mc_disp = {
650 .name = "llcc_mc_disp",
651 .id = SM8350_MASTER_LLCC_DISP,
655 .links = { SM8350_SLAVE_EBI1_DISP },
658 static struct qcom_icc_node qxm_mdp0_disp = {
659 .name = "qxm_mdp0_disp",
660 .id = SM8350_MASTER_MDP0_DISP,
664 .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP },
667 static struct qcom_icc_node qxm_mdp1_disp = {
668 .name = "qxm_mdp1_disp",
669 .id = SM8350_MASTER_MDP1_DISP,
673 .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP },
676 static struct qcom_icc_node qxm_rot_disp = {
677 .name = "qxm_rot_disp",
678 .id = SM8350_MASTER_ROTATOR_DISP,
682 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP },
685 static struct qcom_icc_node qns_a1noc_snoc = {
686 .name = "qns_a1noc_snoc",
687 .id = SM8350_SLAVE_A1NOC_SNOC,
691 .links = { SM8350_MASTER_A1NOC_SNOC },
694 static struct qcom_icc_node srvc_aggre1_noc = {
695 .name = "srvc_aggre1_noc",
696 .id = SM8350_SLAVE_SERVICE_A1NOC,
701 static struct qcom_icc_node qns_a2noc_snoc = {
702 .name = "qns_a2noc_snoc",
703 .id = SM8350_SLAVE_A2NOC_SNOC,
707 .links = { SM8350_MASTER_A2NOC_SNOC },
710 static struct qcom_icc_node qns_pcie_mem_noc = {
711 .name = "qns_pcie_mem_noc",
712 .id = SM8350_SLAVE_ANOC_PCIE_GEM_NOC,
716 .links = { SM8350_MASTER_ANOC_PCIE_GEM_NOC },
719 static struct qcom_icc_node srvc_aggre2_noc = {
720 .name = "srvc_aggre2_noc",
721 .id = SM8350_SLAVE_SERVICE_A2NOC,
726 static struct qcom_icc_node qhs_ahb2phy0 = {
727 .name = "qhs_ahb2phy0",
728 .id = SM8350_SLAVE_AHB2PHY_SOUTH,
733 static struct qcom_icc_node qhs_ahb2phy1 = {
734 .name = "qhs_ahb2phy1",
735 .id = SM8350_SLAVE_AHB2PHY_NORTH,
740 static struct qcom_icc_node qhs_aoss = {
742 .id = SM8350_SLAVE_AOSS,
747 static struct qcom_icc_node qhs_apss = {
749 .id = SM8350_SLAVE_APPSS,
754 static struct qcom_icc_node qhs_camera_cfg = {
755 .name = "qhs_camera_cfg",
756 .id = SM8350_SLAVE_CAMERA_CFG,
761 static struct qcom_icc_node qhs_clk_ctl = {
762 .name = "qhs_clk_ctl",
763 .id = SM8350_SLAVE_CLK_CTL,
768 static struct qcom_icc_node qhs_compute_cfg = {
769 .name = "qhs_compute_cfg",
770 .id = SM8350_SLAVE_CDSP_CFG,
775 static struct qcom_icc_node qhs_cpr_cx = {
776 .name = "qhs_cpr_cx",
777 .id = SM8350_SLAVE_RBCPR_CX_CFG,
782 static struct qcom_icc_node qhs_cpr_mmcx = {
783 .name = "qhs_cpr_mmcx",
784 .id = SM8350_SLAVE_RBCPR_MMCX_CFG,
789 static struct qcom_icc_node qhs_cpr_mx = {
790 .name = "qhs_cpr_mx",
791 .id = SM8350_SLAVE_RBCPR_MX_CFG,
796 static struct qcom_icc_node qhs_crypto0_cfg = {
797 .name = "qhs_crypto0_cfg",
798 .id = SM8350_SLAVE_CRYPTO_0_CFG,
803 static struct qcom_icc_node qhs_cx_rdpm = {
804 .name = "qhs_cx_rdpm",
805 .id = SM8350_SLAVE_CX_RDPM,
810 static struct qcom_icc_node qhs_dcc_cfg = {
811 .name = "qhs_dcc_cfg",
812 .id = SM8350_SLAVE_DCC_CFG,
817 static struct qcom_icc_node qhs_display_cfg = {
818 .name = "qhs_display_cfg",
819 .id = SM8350_SLAVE_DISPLAY_CFG,
824 static struct qcom_icc_node qhs_gpuss_cfg = {
825 .name = "qhs_gpuss_cfg",
826 .id = SM8350_SLAVE_GFX3D_CFG,
831 static struct qcom_icc_node qhs_hwkm = {
833 .id = SM8350_SLAVE_HWKM,
838 static struct qcom_icc_node qhs_imem_cfg = {
839 .name = "qhs_imem_cfg",
840 .id = SM8350_SLAVE_IMEM_CFG,
845 static struct qcom_icc_node qhs_ipa = {
847 .id = SM8350_SLAVE_IPA_CFG,
852 static struct qcom_icc_node qhs_ipc_router = {
853 .name = "qhs_ipc_router",
854 .id = SM8350_SLAVE_IPC_ROUTER_CFG,
859 static struct qcom_icc_node qhs_lpass_cfg = {
860 .name = "qhs_lpass_cfg",
861 .id = SM8350_SLAVE_LPASS,
865 .links = { SM8350_MASTER_CNOC_LPASS_AG_NOC },
868 static struct qcom_icc_node qhs_mss_cfg = {
869 .name = "qhs_mss_cfg",
870 .id = SM8350_SLAVE_CNOC_MSS,
875 static struct qcom_icc_node qhs_mx_rdpm = {
876 .name = "qhs_mx_rdpm",
877 .id = SM8350_SLAVE_MX_RDPM,
882 static struct qcom_icc_node qhs_pcie0_cfg = {
883 .name = "qhs_pcie0_cfg",
884 .id = SM8350_SLAVE_PCIE_0_CFG,
889 static struct qcom_icc_node qhs_pcie1_cfg = {
890 .name = "qhs_pcie1_cfg",
891 .id = SM8350_SLAVE_PCIE_1_CFG,
896 static struct qcom_icc_node qhs_pdm = {
898 .id = SM8350_SLAVE_PDM,
903 static struct qcom_icc_node qhs_pimem_cfg = {
904 .name = "qhs_pimem_cfg",
905 .id = SM8350_SLAVE_PIMEM_CFG,
910 static struct qcom_icc_node qhs_pka_wrapper_cfg = {
911 .name = "qhs_pka_wrapper_cfg",
912 .id = SM8350_SLAVE_PKA_WRAPPER_CFG,
917 static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
918 .name = "qhs_pmu_wrapper_cfg",
919 .id = SM8350_SLAVE_PMU_WRAPPER_CFG,
924 static struct qcom_icc_node qhs_qdss_cfg = {
925 .name = "qhs_qdss_cfg",
926 .id = SM8350_SLAVE_QDSS_CFG,
931 static struct qcom_icc_node qhs_qspi = {
933 .id = SM8350_SLAVE_QSPI_0,
938 static struct qcom_icc_node qhs_qup0 = {
940 .id = SM8350_SLAVE_QUP_0,
945 static struct qcom_icc_node qhs_qup1 = {
947 .id = SM8350_SLAVE_QUP_1,
952 static struct qcom_icc_node qhs_qup2 = {
954 .id = SM8350_SLAVE_QUP_2,
959 static struct qcom_icc_node qhs_sdc2 = {
961 .id = SM8350_SLAVE_SDCC_2,
966 static struct qcom_icc_node qhs_sdc4 = {
968 .id = SM8350_SLAVE_SDCC_4,
973 static struct qcom_icc_node qhs_security = {
974 .name = "qhs_security",
975 .id = SM8350_SLAVE_SECURITY,
980 static struct qcom_icc_node qhs_spss_cfg = {
981 .name = "qhs_spss_cfg",
982 .id = SM8350_SLAVE_SPSS_CFG,
987 static struct qcom_icc_node qhs_tcsr = {
989 .id = SM8350_SLAVE_TCSR,
994 static struct qcom_icc_node qhs_tlmm = {
996 .id = SM8350_SLAVE_TLMM,
1001 static struct qcom_icc_node qhs_ufs_card_cfg = {
1002 .name = "qhs_ufs_card_cfg",
1003 .id = SM8350_SLAVE_UFS_CARD_CFG,
1008 static struct qcom_icc_node qhs_ufs_mem_cfg = {
1009 .name = "qhs_ufs_mem_cfg",
1010 .id = SM8350_SLAVE_UFS_MEM_CFG,
1015 static struct qcom_icc_node qhs_usb3_0 = {
1016 .name = "qhs_usb3_0",
1017 .id = SM8350_SLAVE_USB3_0,
1022 static struct qcom_icc_node qhs_usb3_1 = {
1023 .name = "qhs_usb3_1",
1024 .id = SM8350_SLAVE_USB3_1,
1029 static struct qcom_icc_node qhs_venus_cfg = {
1030 .name = "qhs_venus_cfg",
1031 .id = SM8350_SLAVE_VENUS_CFG,
1036 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1037 .name = "qhs_vsense_ctrl_cfg",
1038 .id = SM8350_SLAVE_VSENSE_CTRL_CFG,
1043 static struct qcom_icc_node qns_a1_noc_cfg = {
1044 .name = "qns_a1_noc_cfg",
1045 .id = SM8350_SLAVE_A1NOC_CFG,
1050 static struct qcom_icc_node qns_a2_noc_cfg = {
1051 .name = "qns_a2_noc_cfg",
1052 .id = SM8350_SLAVE_A2NOC_CFG,
1057 static struct qcom_icc_node qns_ddrss_cfg = {
1058 .name = "qns_ddrss_cfg",
1059 .id = SM8350_SLAVE_DDRSS_CFG,
1064 static struct qcom_icc_node qns_mnoc_cfg = {
1065 .name = "qns_mnoc_cfg",
1066 .id = SM8350_SLAVE_CNOC_MNOC_CFG,
1071 static struct qcom_icc_node qns_snoc_cfg = {
1072 .name = "qns_snoc_cfg",
1073 .id = SM8350_SLAVE_SNOC_CFG,
1078 static struct qcom_icc_node qxs_boot_imem = {
1079 .name = "qxs_boot_imem",
1080 .id = SM8350_SLAVE_BOOT_IMEM,
1085 static struct qcom_icc_node qxs_imem = {
1087 .id = SM8350_SLAVE_IMEM,
1092 static struct qcom_icc_node qxs_pimem = {
1093 .name = "qxs_pimem",
1094 .id = SM8350_SLAVE_PIMEM,
1099 static struct qcom_icc_node srvc_cnoc = {
1100 .name = "srvc_cnoc",
1101 .id = SM8350_SLAVE_SERVICE_CNOC,
1106 static struct qcom_icc_node xs_pcie_0 = {
1107 .name = "xs_pcie_0",
1108 .id = SM8350_SLAVE_PCIE_0,
1113 static struct qcom_icc_node xs_pcie_1 = {
1114 .name = "xs_pcie_1",
1115 .id = SM8350_SLAVE_PCIE_1,
1120 static struct qcom_icc_node xs_qdss_stm = {
1121 .name = "xs_qdss_stm",
1122 .id = SM8350_SLAVE_QDSS_STM,
1127 static struct qcom_icc_node xs_sys_tcu_cfg = {
1128 .name = "xs_sys_tcu_cfg",
1129 .id = SM8350_SLAVE_TCU,
1134 static struct qcom_icc_node qhs_llcc = {
1136 .id = SM8350_SLAVE_LLCC_CFG,
1141 static struct qcom_icc_node qns_gemnoc = {
1142 .name = "qns_gemnoc",
1143 .id = SM8350_SLAVE_GEM_NOC_CFG,
1148 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1149 .name = "qhs_mdsp_ms_mpu_cfg",
1150 .id = SM8350_SLAVE_MSS_PROC_MS_MPU_CFG,
1155 static struct qcom_icc_node qhs_modem_ms_mpu_cfg = {
1156 .name = "qhs_modem_ms_mpu_cfg",
1157 .id = SM8350_SLAVE_MCDMA_MS_MPU_CFG,
1162 static struct qcom_icc_node qns_gem_noc_cnoc = {
1163 .name = "qns_gem_noc_cnoc",
1164 .id = SM8350_SLAVE_GEM_NOC_CNOC,
1168 .links = { SM8350_MASTER_GEM_NOC_CNOC },
1171 static struct qcom_icc_node qns_llcc = {
1173 .id = SM8350_SLAVE_LLCC,
1177 .links = { SM8350_MASTER_LLCC },
1180 static struct qcom_icc_node qns_pcie = {
1182 .id = SM8350_SLAVE_MEM_NOC_PCIE_SNOC,
1187 static struct qcom_icc_node srvc_even_gemnoc = {
1188 .name = "srvc_even_gemnoc",
1189 .id = SM8350_SLAVE_SERVICE_GEM_NOC_1,
1194 static struct qcom_icc_node srvc_odd_gemnoc = {
1195 .name = "srvc_odd_gemnoc",
1196 .id = SM8350_SLAVE_SERVICE_GEM_NOC_2,
1201 static struct qcom_icc_node srvc_sys_gemnoc = {
1202 .name = "srvc_sys_gemnoc",
1203 .id = SM8350_SLAVE_SERVICE_GEM_NOC,
1208 static struct qcom_icc_node qhs_lpass_core = {
1209 .name = "qhs_lpass_core",
1210 .id = SM8350_SLAVE_LPASS_CORE_CFG,
1215 static struct qcom_icc_node qhs_lpass_lpi = {
1216 .name = "qhs_lpass_lpi",
1217 .id = SM8350_SLAVE_LPASS_LPI_CFG,
1222 static struct qcom_icc_node qhs_lpass_mpu = {
1223 .name = "qhs_lpass_mpu",
1224 .id = SM8350_SLAVE_LPASS_MPU_CFG,
1229 static struct qcom_icc_node qhs_lpass_top = {
1230 .name = "qhs_lpass_top",
1231 .id = SM8350_SLAVE_LPASS_TOP_CFG,
1236 static struct qcom_icc_node srvc_niu_aml_noc = {
1237 .name = "srvc_niu_aml_noc",
1238 .id = SM8350_SLAVE_SERVICES_LPASS_AML_NOC,
1243 static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1244 .name = "srvc_niu_lpass_agnoc",
1245 .id = SM8350_SLAVE_SERVICE_LPASS_AG_NOC,
1250 static struct qcom_icc_node ebi = {
1252 .id = SM8350_SLAVE_EBI1,
1257 static struct qcom_icc_node qns_mem_noc_hf = {
1258 .name = "qns_mem_noc_hf",
1259 .id = SM8350_SLAVE_MNOC_HF_MEM_NOC,
1263 .links = { SM8350_MASTER_MNOC_HF_MEM_NOC },
1266 static struct qcom_icc_node qns_mem_noc_sf = {
1267 .name = "qns_mem_noc_sf",
1268 .id = SM8350_SLAVE_MNOC_SF_MEM_NOC,
1272 .links = { SM8350_MASTER_MNOC_SF_MEM_NOC },
1275 static struct qcom_icc_node srvc_mnoc = {
1276 .name = "srvc_mnoc",
1277 .id = SM8350_SLAVE_SERVICE_MNOC,
1282 static struct qcom_icc_node qns_nsp_gemnoc = {
1283 .name = "qns_nsp_gemnoc",
1284 .id = SM8350_SLAVE_CDSP_MEM_NOC,
1288 .links = { SM8350_MASTER_COMPUTE_NOC },
1291 static struct qcom_icc_node service_nsp_noc = {
1292 .name = "service_nsp_noc",
1293 .id = SM8350_SLAVE_SERVICE_NSP_NOC,
1298 static struct qcom_icc_node qns_gemnoc_gc = {
1299 .name = "qns_gemnoc_gc",
1300 .id = SM8350_SLAVE_SNOC_GEM_NOC_GC,
1304 .links = { SM8350_MASTER_SNOC_GC_MEM_NOC },
1307 static struct qcom_icc_node qns_gemnoc_sf = {
1308 .name = "qns_gemnoc_sf",
1309 .id = SM8350_SLAVE_SNOC_GEM_NOC_SF,
1313 .links = { SM8350_MASTER_SNOC_SF_MEM_NOC },
1316 static struct qcom_icc_node srvc_snoc = {
1317 .name = "srvc_snoc",
1318 .id = SM8350_SLAVE_SERVICE_SNOC,
1323 static struct qcom_icc_node qns_llcc_disp = {
1324 .name = "qns_llcc_disp",
1325 .id = SM8350_SLAVE_LLCC_DISP,
1329 .links = { SM8350_MASTER_LLCC_DISP },
1332 static struct qcom_icc_node ebi_disp = {
1334 .id = SM8350_SLAVE_EBI1_DISP,
1339 static struct qcom_icc_node qns_mem_noc_hf_disp = {
1340 .name = "qns_mem_noc_hf_disp",
1341 .id = SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP,
1345 .links = { SM8350_MASTER_MNOC_HF_MEM_NOC_DISP },
1348 static struct qcom_icc_node qns_mem_noc_sf_disp = {
1349 .name = "qns_mem_noc_sf_disp",
1350 .id = SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP,
1354 .links = { SM8350_MASTER_MNOC_SF_MEM_NOC_DISP },
1357 static struct qcom_icc_bcm bcm_acv = {
1359 .enable_mask = BIT(3),
1365 static struct qcom_icc_bcm bcm_ce0 = {
1369 .nodes = { &qxm_crypto },
1372 static struct qcom_icc_bcm bcm_cn0 = {
1376 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
1379 static struct qcom_icc_bcm bcm_cn1 = {
1383 .nodes = { &xm_qdss_dap,
1408 &qhs_pka_wrapper_cfg,
1409 &qhs_pmu_wrapper_cfg,
1423 &qhs_vsense_ctrl_cfg,
1433 static struct qcom_icc_bcm bcm_cn2 = {
1437 .nodes = { &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4 },
1440 static struct qcom_icc_bcm bcm_co0 = {
1444 .nodes = { &qns_nsp_gemnoc },
1447 static struct qcom_icc_bcm bcm_co3 = {
1451 .nodes = { &qxm_nsp },
1454 static struct qcom_icc_bcm bcm_mc0 = {
1461 static struct qcom_icc_bcm bcm_mm0 = {
1465 .nodes = { &qns_mem_noc_hf },
1468 static struct qcom_icc_bcm bcm_mm1 = {
1472 .nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 },
1475 static struct qcom_icc_bcm bcm_mm4 = {
1479 .nodes = { &qns_mem_noc_sf },
1482 static struct qcom_icc_bcm bcm_mm5 = {
1486 .nodes = { &qnm_camnoc_icp,
1495 static struct qcom_icc_bcm bcm_sh0 = {
1499 .nodes = { &qns_llcc },
1502 static struct qcom_icc_bcm bcm_sh2 = {
1506 .nodes = { &alm_gpu_tcu, &alm_sys_tcu },
1509 static struct qcom_icc_bcm bcm_sh3 = {
1513 .nodes = { &qnm_cmpnoc },
1516 static struct qcom_icc_bcm bcm_sh4 = {
1520 .nodes = { &chm_apps },
1523 static struct qcom_icc_bcm bcm_sn0 = {
1527 .nodes = { &qns_gemnoc_sf },
1530 static struct qcom_icc_bcm bcm_sn2 = {
1534 .nodes = { &qns_gemnoc_gc },
1537 static struct qcom_icc_bcm bcm_sn3 = {
1541 .nodes = { &qxs_pimem },
1544 static struct qcom_icc_bcm bcm_sn4 = {
1548 .nodes = { &xs_qdss_stm },
1551 static struct qcom_icc_bcm bcm_sn5 = {
1555 .nodes = { &xm_pcie3_0 },
1558 static struct qcom_icc_bcm bcm_sn6 = {
1562 .nodes = { &xm_pcie3_1 },
1565 static struct qcom_icc_bcm bcm_sn7 = {
1569 .nodes = { &qnm_aggre1_noc },
1572 static struct qcom_icc_bcm bcm_sn8 = {
1576 .nodes = { &qnm_aggre2_noc },
1579 static struct qcom_icc_bcm bcm_sn14 = {
1583 .nodes = { &qns_pcie_mem_noc },
1586 static struct qcom_icc_bcm bcm_acv_disp = {
1590 .nodes = { &ebi_disp },
1593 static struct qcom_icc_bcm bcm_mc0_disp = {
1597 .nodes = { &ebi_disp },
1600 static struct qcom_icc_bcm bcm_mm0_disp = {
1604 .nodes = { &qns_mem_noc_hf_disp },
1607 static struct qcom_icc_bcm bcm_mm1_disp = {
1611 .nodes = { &qxm_mdp0_disp, &qxm_mdp1_disp },
1614 static struct qcom_icc_bcm bcm_mm4_disp = {
1618 .nodes = { &qns_mem_noc_sf_disp },
1621 static struct qcom_icc_bcm bcm_mm5_disp = {
1625 .nodes = { &qxm_rot_disp },
1628 static struct qcom_icc_bcm bcm_sh0_disp = {
1632 .nodes = { &qns_llcc_disp },
1635 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1638 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1639 [MASTER_QSPI_0] = &qhm_qspi,
1640 [MASTER_QUP_1] = &qhm_qup1,
1641 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
1642 [MASTER_SDCC_4] = &xm_sdc4,
1643 [MASTER_UFS_MEM] = &xm_ufs_mem,
1644 [MASTER_USB3_0] = &xm_usb3_0,
1645 [MASTER_USB3_1] = &xm_usb3_1,
1646 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1647 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1650 static const struct qcom_icc_desc sm8350_aggre1_noc = {
1651 .nodes = aggre1_noc_nodes,
1652 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1653 .bcms = aggre1_noc_bcms,
1654 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1657 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1664 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1665 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1666 [MASTER_QUP_0] = &qhm_qup0,
1667 [MASTER_QUP_2] = &qhm_qup2,
1668 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
1669 [MASTER_CRYPTO] = &qxm_crypto,
1670 [MASTER_IPA] = &qxm_ipa,
1671 [MASTER_PCIE_0] = &xm_pcie3_0,
1672 [MASTER_PCIE_1] = &xm_pcie3_1,
1673 [MASTER_QDSS_ETR] = &xm_qdss_etr,
1674 [MASTER_SDCC_2] = &xm_sdc2,
1675 [MASTER_UFS_CARD] = &xm_ufs_card,
1676 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1677 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1678 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1681 static const struct qcom_icc_desc sm8350_aggre2_noc = {
1682 .nodes = aggre2_noc_nodes,
1683 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1684 .bcms = aggre2_noc_bcms,
1685 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1688 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1696 static struct qcom_icc_node * const config_noc_nodes[] = {
1697 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1698 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1699 [MASTER_QDSS_DAP] = &xm_qdss_dap,
1700 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1701 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1702 [SLAVE_AOSS] = &qhs_aoss,
1703 [SLAVE_APPSS] = &qhs_apss,
1704 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1705 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1706 [SLAVE_CDSP_CFG] = &qhs_compute_cfg,
1707 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1708 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1709 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1710 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1711 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1712 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
1713 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1714 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1715 [SLAVE_HWKM] = &qhs_hwkm,
1716 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1717 [SLAVE_IPA_CFG] = &qhs_ipa,
1718 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1719 [SLAVE_LPASS] = &qhs_lpass_cfg,
1720 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1721 [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1722 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1723 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1724 [SLAVE_PDM] = &qhs_pdm,
1725 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1726 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg,
1727 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
1728 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1729 [SLAVE_QSPI_0] = &qhs_qspi,
1730 [SLAVE_QUP_0] = &qhs_qup0,
1731 [SLAVE_QUP_1] = &qhs_qup1,
1732 [SLAVE_QUP_2] = &qhs_qup2,
1733 [SLAVE_SDCC_2] = &qhs_sdc2,
1734 [SLAVE_SDCC_4] = &qhs_sdc4,
1735 [SLAVE_SECURITY] = &qhs_security,
1736 [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1737 [SLAVE_TCSR] = &qhs_tcsr,
1738 [SLAVE_TLMM] = &qhs_tlmm,
1739 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
1740 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1741 [SLAVE_USB3_0] = &qhs_usb3_0,
1742 [SLAVE_USB3_1] = &qhs_usb3_1,
1743 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1744 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1745 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
1746 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
1747 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1748 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
1749 [SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1750 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1751 [SLAVE_IMEM] = &qxs_imem,
1752 [SLAVE_PIMEM] = &qxs_pimem,
1753 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1754 [SLAVE_PCIE_0] = &xs_pcie_0,
1755 [SLAVE_PCIE_1] = &xs_pcie_1,
1756 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1757 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1760 static const struct qcom_icc_desc sm8350_config_noc = {
1761 .nodes = config_noc_nodes,
1762 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1763 .bcms = config_noc_bcms,
1764 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1767 static struct qcom_icc_bcm * const dc_noc_bcms[] = {
1770 static struct qcom_icc_node * const dc_noc_nodes[] = {
1771 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
1772 [SLAVE_LLCC_CFG] = &qhs_llcc,
1773 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
1776 static const struct qcom_icc_desc sm8350_dc_noc = {
1777 .nodes = dc_noc_nodes,
1778 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1779 .bcms = dc_noc_bcms,
1780 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
1783 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1791 static struct qcom_icc_node * const gem_noc_nodes[] = {
1792 [MASTER_GPU_TCU] = &alm_gpu_tcu,
1793 [MASTER_SYS_TCU] = &alm_sys_tcu,
1794 [MASTER_APPSS_PROC] = &chm_apps,
1795 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
1796 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
1797 [MASTER_GFX3D] = &qnm_gpu,
1798 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1799 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1800 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1801 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1802 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1803 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1804 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg,
1805 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1806 [SLAVE_LLCC] = &qns_llcc,
1807 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1808 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
1809 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
1810 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
1811 [MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
1812 [MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp,
1813 [SLAVE_LLCC_DISP] = &qns_llcc_disp,
1816 static const struct qcom_icc_desc sm8350_gem_noc = {
1817 .nodes = gem_noc_nodes,
1818 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1819 .bcms = gem_noc_bcms,
1820 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1823 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1826 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1827 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
1828 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
1829 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
1830 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
1831 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
1832 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
1833 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
1836 static const struct qcom_icc_desc sm8350_lpass_ag_noc = {
1837 .nodes = lpass_ag_noc_nodes,
1838 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1839 .bcms = lpass_ag_noc_bcms,
1840 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1843 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1850 static struct qcom_icc_node * const mc_virt_nodes[] = {
1851 [MASTER_LLCC] = &llcc_mc,
1852 [SLAVE_EBI1] = &ebi,
1853 [MASTER_LLCC_DISP] = &llcc_mc_disp,
1854 [SLAVE_EBI1_DISP] = &ebi_disp,
1857 static const struct qcom_icc_desc sm8350_mc_virt = {
1858 .nodes = mc_virt_nodes,
1859 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1860 .bcms = mc_virt_bcms,
1861 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1864 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1875 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1876 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1877 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1878 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1879 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
1880 [MASTER_VIDEO_P0] = &qnm_video0,
1881 [MASTER_VIDEO_P1] = &qnm_video1,
1882 [MASTER_VIDEO_PROC] = &qnm_video_cvp,
1883 [MASTER_MDP0] = &qxm_mdp0,
1884 [MASTER_MDP1] = &qxm_mdp1,
1885 [MASTER_ROTATOR] = &qxm_rot,
1886 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1887 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1888 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1889 [MASTER_MDP0_DISP] = &qxm_mdp0_disp,
1890 [MASTER_MDP1_DISP] = &qxm_mdp1_disp,
1891 [MASTER_ROTATOR_DISP] = &qxm_rot_disp,
1892 [SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
1893 [SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp,
1896 static const struct qcom_icc_desc sm8350_mmss_noc = {
1897 .nodes = mmss_noc_nodes,
1898 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1899 .bcms = mmss_noc_bcms,
1900 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1903 static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1908 static struct qcom_icc_node * const nsp_noc_nodes[] = {
1909 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
1910 [MASTER_CDSP_PROC] = &qxm_nsp,
1911 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1912 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
1915 static const struct qcom_icc_desc sm8350_compute_noc = {
1916 .nodes = nsp_noc_nodes,
1917 .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1918 .bcms = nsp_noc_bcms,
1919 .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1922 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1929 static struct qcom_icc_node * const system_noc_nodes[] = {
1930 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1931 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1932 [MASTER_SNOC_CFG] = &qnm_snoc_cfg,
1933 [MASTER_PIMEM] = &qxm_pimem,
1934 [MASTER_GIC] = &xm_gic,
1935 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1936 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1937 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
1940 static const struct qcom_icc_desc sm8350_system_noc = {
1941 .nodes = system_noc_nodes,
1942 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1943 .bcms = system_noc_bcms,
1944 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1947 static const struct of_device_id qnoc_of_match[] = {
1948 { .compatible = "qcom,sm8350-aggre1-noc", .data = &sm8350_aggre1_noc},
1949 { .compatible = "qcom,sm8350-aggre2-noc", .data = &sm8350_aggre2_noc},
1950 { .compatible = "qcom,sm8350-config-noc", .data = &sm8350_config_noc},
1951 { .compatible = "qcom,sm8350-dc-noc", .data = &sm8350_dc_noc},
1952 { .compatible = "qcom,sm8350-gem-noc", .data = &sm8350_gem_noc},
1953 { .compatible = "qcom,sm8350-lpass-ag-noc", .data = &sm8350_lpass_ag_noc},
1954 { .compatible = "qcom,sm8350-mc-virt", .data = &sm8350_mc_virt},
1955 { .compatible = "qcom,sm8350-mmss-noc", .data = &sm8350_mmss_noc},
1956 { .compatible = "qcom,sm8350-compute-noc", .data = &sm8350_compute_noc},
1957 { .compatible = "qcom,sm8350-system-noc", .data = &sm8350_system_noc},
1960 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1962 static struct platform_driver qnoc_driver = {
1963 .probe = qcom_icc_rpmh_probe,
1964 .remove = qcom_icc_rpmh_remove,
1966 .name = "qnoc-sm8350",
1967 .of_match_table = qnoc_of_match,
1970 module_platform_driver(qnoc_driver);
1972 MODULE_DESCRIPTION("SM8350 NoC driver");
1973 MODULE_LICENSE("GPL v2");