1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
6 #include <linux/device.h>
7 #include <linux/interconnect.h>
8 #include <linux/interconnect-provider.h>
9 #include <linux/module.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/platform_device.h>
13 #include <dt-bindings/interconnect/qcom,sdm845.h>
15 #include "bcm-voter.h"
19 static struct qcom_icc_node qhm_a1noc_cfg = {
20 .name = "qhm_a1noc_cfg",
21 .id = SDM845_MASTER_A1NOC_CFG,
25 .links = { SDM845_SLAVE_SERVICE_A1NOC },
28 static struct qcom_icc_node qhm_qup1 = {
30 .id = SDM845_MASTER_BLSP_1,
34 .links = { SDM845_SLAVE_A1NOC_SNOC },
37 static struct qcom_icc_node qhm_tsif = {
39 .id = SDM845_MASTER_TSIF,
43 .links = { SDM845_SLAVE_A1NOC_SNOC },
46 static struct qcom_icc_node xm_sdc2 = {
48 .id = SDM845_MASTER_SDCC_2,
52 .links = { SDM845_SLAVE_A1NOC_SNOC },
55 static struct qcom_icc_node xm_sdc4 = {
57 .id = SDM845_MASTER_SDCC_4,
61 .links = { SDM845_SLAVE_A1NOC_SNOC },
64 static struct qcom_icc_node xm_ufs_card = {
65 .name = "xm_ufs_card",
66 .id = SDM845_MASTER_UFS_CARD,
70 .links = { SDM845_SLAVE_A1NOC_SNOC },
73 static struct qcom_icc_node xm_ufs_mem = {
75 .id = SDM845_MASTER_UFS_MEM,
79 .links = { SDM845_SLAVE_A1NOC_SNOC },
82 static struct qcom_icc_node xm_pcie_0 = {
84 .id = SDM845_MASTER_PCIE_0,
88 .links = { SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC },
91 static struct qcom_icc_node qhm_a2noc_cfg = {
92 .name = "qhm_a2noc_cfg",
93 .id = SDM845_MASTER_A2NOC_CFG,
97 .links = { SDM845_SLAVE_SERVICE_A2NOC },
100 static struct qcom_icc_node qhm_qdss_bam = {
101 .name = "qhm_qdss_bam",
102 .id = SDM845_MASTER_QDSS_BAM,
106 .links = { SDM845_SLAVE_A2NOC_SNOC },
109 static struct qcom_icc_node qhm_qup2 = {
111 .id = SDM845_MASTER_BLSP_2,
115 .links = { SDM845_SLAVE_A2NOC_SNOC },
118 static struct qcom_icc_node qnm_cnoc = {
120 .id = SDM845_MASTER_CNOC_A2NOC,
124 .links = { SDM845_SLAVE_A2NOC_SNOC },
127 static struct qcom_icc_node qxm_crypto = {
128 .name = "qxm_crypto",
129 .id = SDM845_MASTER_CRYPTO,
133 .links = { SDM845_SLAVE_A2NOC_SNOC },
136 static struct qcom_icc_node qxm_ipa = {
138 .id = SDM845_MASTER_IPA,
142 .links = { SDM845_SLAVE_A2NOC_SNOC },
145 static struct qcom_icc_node xm_pcie3_1 = {
146 .name = "xm_pcie3_1",
147 .id = SDM845_MASTER_PCIE_1,
151 .links = { SDM845_SLAVE_ANOC_PCIE_SNOC },
154 static struct qcom_icc_node xm_qdss_etr = {
155 .name = "xm_qdss_etr",
156 .id = SDM845_MASTER_QDSS_ETR,
160 .links = { SDM845_SLAVE_A2NOC_SNOC },
163 static struct qcom_icc_node xm_usb3_0 = {
165 .id = SDM845_MASTER_USB3_0,
169 .links = { SDM845_SLAVE_A2NOC_SNOC },
172 static struct qcom_icc_node xm_usb3_1 = {
174 .id = SDM845_MASTER_USB3_1,
178 .links = { SDM845_SLAVE_A2NOC_SNOC },
181 static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
182 .name = "qxm_camnoc_hf0_uncomp",
183 .id = SDM845_MASTER_CAMNOC_HF0_UNCOMP,
187 .links = { SDM845_SLAVE_CAMNOC_UNCOMP },
190 static struct qcom_icc_node qxm_camnoc_hf1_uncomp = {
191 .name = "qxm_camnoc_hf1_uncomp",
192 .id = SDM845_MASTER_CAMNOC_HF1_UNCOMP,
196 .links = { SDM845_SLAVE_CAMNOC_UNCOMP },
199 static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
200 .name = "qxm_camnoc_sf_uncomp",
201 .id = SDM845_MASTER_CAMNOC_SF_UNCOMP,
205 .links = { SDM845_SLAVE_CAMNOC_UNCOMP },
208 static struct qcom_icc_node qhm_spdm = {
210 .id = SDM845_MASTER_SPDM,
214 .links = { SDM845_SLAVE_CNOC_A2NOC },
217 static struct qcom_icc_node qhm_tic = {
219 .id = SDM845_MASTER_TIC,
223 .links = { SDM845_SLAVE_A1NOC_CFG,
224 SDM845_SLAVE_A2NOC_CFG,
227 SDM845_SLAVE_CAMERA_CFG,
228 SDM845_SLAVE_CLK_CTL,
229 SDM845_SLAVE_CDSP_CFG,
230 SDM845_SLAVE_RBCPR_CX_CFG,
231 SDM845_SLAVE_CRYPTO_0_CFG,
232 SDM845_SLAVE_DCC_CFG,
233 SDM845_SLAVE_CNOC_DDRSS,
234 SDM845_SLAVE_DISPLAY_CFG,
236 SDM845_SLAVE_GFX3D_CFG,
237 SDM845_SLAVE_IMEM_CFG,
238 SDM845_SLAVE_IPA_CFG,
239 SDM845_SLAVE_CNOC_MNOC_CFG,
240 SDM845_SLAVE_PCIE_0_CFG,
241 SDM845_SLAVE_PCIE_1_CFG,
243 SDM845_SLAVE_SOUTH_PHY_CFG,
244 SDM845_SLAVE_PIMEM_CFG,
246 SDM845_SLAVE_QDSS_CFG,
251 SDM845_SLAVE_SNOC_CFG,
252 SDM845_SLAVE_SPDM_WRAPPER,
253 SDM845_SLAVE_SPSS_CFG,
255 SDM845_SLAVE_TLMM_NORTH,
256 SDM845_SLAVE_TLMM_SOUTH,
258 SDM845_SLAVE_UFS_CARD_CFG,
259 SDM845_SLAVE_UFS_MEM_CFG,
262 SDM845_SLAVE_VENUS_CFG,
263 SDM845_SLAVE_VSENSE_CTRL_CFG,
264 SDM845_SLAVE_CNOC_A2NOC,
265 SDM845_SLAVE_SERVICE_CNOC
269 static struct qcom_icc_node qnm_snoc = {
271 .id = SDM845_MASTER_SNOC_CNOC,
275 .links = { SDM845_SLAVE_A1NOC_CFG,
276 SDM845_SLAVE_A2NOC_CFG,
279 SDM845_SLAVE_CAMERA_CFG,
280 SDM845_SLAVE_CLK_CTL,
281 SDM845_SLAVE_CDSP_CFG,
282 SDM845_SLAVE_RBCPR_CX_CFG,
283 SDM845_SLAVE_CRYPTO_0_CFG,
284 SDM845_SLAVE_DCC_CFG,
285 SDM845_SLAVE_CNOC_DDRSS,
286 SDM845_SLAVE_DISPLAY_CFG,
288 SDM845_SLAVE_GFX3D_CFG,
289 SDM845_SLAVE_IMEM_CFG,
290 SDM845_SLAVE_IPA_CFG,
291 SDM845_SLAVE_CNOC_MNOC_CFG,
292 SDM845_SLAVE_PCIE_0_CFG,
293 SDM845_SLAVE_PCIE_1_CFG,
295 SDM845_SLAVE_SOUTH_PHY_CFG,
296 SDM845_SLAVE_PIMEM_CFG,
298 SDM845_SLAVE_QDSS_CFG,
303 SDM845_SLAVE_SNOC_CFG,
304 SDM845_SLAVE_SPDM_WRAPPER,
305 SDM845_SLAVE_SPSS_CFG,
307 SDM845_SLAVE_TLMM_NORTH,
308 SDM845_SLAVE_TLMM_SOUTH,
310 SDM845_SLAVE_UFS_CARD_CFG,
311 SDM845_SLAVE_UFS_MEM_CFG,
314 SDM845_SLAVE_VENUS_CFG,
315 SDM845_SLAVE_VSENSE_CTRL_CFG,
316 SDM845_SLAVE_SERVICE_CNOC
320 static struct qcom_icc_node xm_qdss_dap = {
321 .name = "xm_qdss_dap",
322 .id = SDM845_MASTER_QDSS_DAP,
326 .links = { SDM845_SLAVE_A1NOC_CFG,
327 SDM845_SLAVE_A2NOC_CFG,
330 SDM845_SLAVE_CAMERA_CFG,
331 SDM845_SLAVE_CLK_CTL,
332 SDM845_SLAVE_CDSP_CFG,
333 SDM845_SLAVE_RBCPR_CX_CFG,
334 SDM845_SLAVE_CRYPTO_0_CFG,
335 SDM845_SLAVE_DCC_CFG,
336 SDM845_SLAVE_CNOC_DDRSS,
337 SDM845_SLAVE_DISPLAY_CFG,
339 SDM845_SLAVE_GFX3D_CFG,
340 SDM845_SLAVE_IMEM_CFG,
341 SDM845_SLAVE_IPA_CFG,
342 SDM845_SLAVE_CNOC_MNOC_CFG,
343 SDM845_SLAVE_PCIE_0_CFG,
344 SDM845_SLAVE_PCIE_1_CFG,
346 SDM845_SLAVE_SOUTH_PHY_CFG,
347 SDM845_SLAVE_PIMEM_CFG,
349 SDM845_SLAVE_QDSS_CFG,
354 SDM845_SLAVE_SNOC_CFG,
355 SDM845_SLAVE_SPDM_WRAPPER,
356 SDM845_SLAVE_SPSS_CFG,
358 SDM845_SLAVE_TLMM_NORTH,
359 SDM845_SLAVE_TLMM_SOUTH,
361 SDM845_SLAVE_UFS_CARD_CFG,
362 SDM845_SLAVE_UFS_MEM_CFG,
365 SDM845_SLAVE_VENUS_CFG,
366 SDM845_SLAVE_VSENSE_CTRL_CFG,
367 SDM845_SLAVE_CNOC_A2NOC,
368 SDM845_SLAVE_SERVICE_CNOC
372 static struct qcom_icc_node qhm_cnoc = {
374 .id = SDM845_MASTER_CNOC_DC_NOC,
378 .links = { SDM845_SLAVE_LLCC_CFG,
379 SDM845_SLAVE_MEM_NOC_CFG
383 static struct qcom_icc_node acm_l3 = {
385 .id = SDM845_MASTER_APPSS_PROC,
389 .links = { SDM845_SLAVE_GNOC_SNOC,
390 SDM845_SLAVE_GNOC_MEM_NOC,
391 SDM845_SLAVE_SERVICE_GNOC
395 static struct qcom_icc_node pm_gnoc_cfg = {
396 .name = "pm_gnoc_cfg",
397 .id = SDM845_MASTER_GNOC_CFG,
401 .links = { SDM845_SLAVE_SERVICE_GNOC },
404 static struct qcom_icc_node llcc_mc = {
406 .id = SDM845_MASTER_LLCC,
410 .links = { SDM845_SLAVE_EBI1 },
413 static struct qcom_icc_node acm_tcu = {
415 .id = SDM845_MASTER_TCU_0,
419 .links = { SDM845_SLAVE_MEM_NOC_GNOC,
421 SDM845_SLAVE_MEM_NOC_SNOC
425 static struct qcom_icc_node qhm_memnoc_cfg = {
426 .name = "qhm_memnoc_cfg",
427 .id = SDM845_MASTER_MEM_NOC_CFG,
431 .links = { SDM845_SLAVE_MSS_PROC_MS_MPU_CFG,
432 SDM845_SLAVE_SERVICE_MEM_NOC
436 static struct qcom_icc_node qnm_apps = {
438 .id = SDM845_MASTER_GNOC_MEM_NOC,
442 .links = { SDM845_SLAVE_LLCC },
445 static struct qcom_icc_node qnm_mnoc_hf = {
446 .name = "qnm_mnoc_hf",
447 .id = SDM845_MASTER_MNOC_HF_MEM_NOC,
451 .links = { SDM845_SLAVE_MEM_NOC_GNOC,
456 static struct qcom_icc_node qnm_mnoc_sf = {
457 .name = "qnm_mnoc_sf",
458 .id = SDM845_MASTER_MNOC_SF_MEM_NOC,
462 .links = { SDM845_SLAVE_MEM_NOC_GNOC,
464 SDM845_SLAVE_MEM_NOC_SNOC
468 static struct qcom_icc_node qnm_snoc_gc = {
469 .name = "qnm_snoc_gc",
470 .id = SDM845_MASTER_SNOC_GC_MEM_NOC,
474 .links = { SDM845_SLAVE_LLCC },
477 static struct qcom_icc_node qnm_snoc_sf = {
478 .name = "qnm_snoc_sf",
479 .id = SDM845_MASTER_SNOC_SF_MEM_NOC,
483 .links = { SDM845_SLAVE_MEM_NOC_GNOC,
488 static struct qcom_icc_node qxm_gpu = {
490 .id = SDM845_MASTER_GFX3D,
494 .links = { SDM845_SLAVE_MEM_NOC_GNOC,
496 SDM845_SLAVE_MEM_NOC_SNOC
500 static struct qcom_icc_node qhm_mnoc_cfg = {
501 .name = "qhm_mnoc_cfg",
502 .id = SDM845_MASTER_CNOC_MNOC_CFG,
506 .links = { SDM845_SLAVE_SERVICE_MNOC },
509 static struct qcom_icc_node qxm_camnoc_hf0 = {
510 .name = "qxm_camnoc_hf0",
511 .id = SDM845_MASTER_CAMNOC_HF0,
515 .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
518 static struct qcom_icc_node qxm_camnoc_hf1 = {
519 .name = "qxm_camnoc_hf1",
520 .id = SDM845_MASTER_CAMNOC_HF1,
524 .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
527 static struct qcom_icc_node qxm_camnoc_sf = {
528 .name = "qxm_camnoc_sf",
529 .id = SDM845_MASTER_CAMNOC_SF,
533 .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
536 static struct qcom_icc_node qxm_mdp0 = {
538 .id = SDM845_MASTER_MDP0,
542 .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
545 static struct qcom_icc_node qxm_mdp1 = {
547 .id = SDM845_MASTER_MDP1,
551 .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
554 static struct qcom_icc_node qxm_rot = {
556 .id = SDM845_MASTER_ROTATOR,
560 .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
563 static struct qcom_icc_node qxm_venus0 = {
564 .name = "qxm_venus0",
565 .id = SDM845_MASTER_VIDEO_P0,
569 .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
572 static struct qcom_icc_node qxm_venus1 = {
573 .name = "qxm_venus1",
574 .id = SDM845_MASTER_VIDEO_P1,
578 .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
581 static struct qcom_icc_node qxm_venus_arm9 = {
582 .name = "qxm_venus_arm9",
583 .id = SDM845_MASTER_VIDEO_PROC,
587 .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
590 static struct qcom_icc_node qhm_snoc_cfg = {
591 .name = "qhm_snoc_cfg",
592 .id = SDM845_MASTER_SNOC_CFG,
596 .links = { SDM845_SLAVE_SERVICE_SNOC },
599 static struct qcom_icc_node qnm_aggre1_noc = {
600 .name = "qnm_aggre1_noc",
601 .id = SDM845_MASTER_A1NOC_SNOC,
605 .links = { SDM845_SLAVE_APPSS,
606 SDM845_SLAVE_SNOC_CNOC,
607 SDM845_SLAVE_SNOC_MEM_NOC_SF,
610 SDM845_SLAVE_QDSS_STM
614 static struct qcom_icc_node qnm_aggre2_noc = {
615 .name = "qnm_aggre2_noc",
616 .id = SDM845_MASTER_A2NOC_SNOC,
620 .links = { SDM845_SLAVE_APPSS,
621 SDM845_SLAVE_SNOC_CNOC,
622 SDM845_SLAVE_SNOC_MEM_NOC_SF,
627 SDM845_SLAVE_QDSS_STM,
632 static struct qcom_icc_node qnm_gladiator_sodv = {
633 .name = "qnm_gladiator_sodv",
634 .id = SDM845_MASTER_GNOC_SNOC,
638 .links = { SDM845_SLAVE_APPSS,
639 SDM845_SLAVE_SNOC_CNOC,
644 SDM845_SLAVE_QDSS_STM,
649 static struct qcom_icc_node qnm_memnoc = {
650 .name = "qnm_memnoc",
651 .id = SDM845_MASTER_MEM_NOC_SNOC,
655 .links = { SDM845_SLAVE_APPSS,
656 SDM845_SLAVE_SNOC_CNOC,
659 SDM845_SLAVE_QDSS_STM
663 static struct qcom_icc_node qnm_pcie_anoc = {
664 .name = "qnm_pcie_anoc",
665 .id = SDM845_MASTER_ANOC_PCIE_SNOC,
669 .links = { SDM845_SLAVE_APPSS,
670 SDM845_SLAVE_SNOC_CNOC,
671 SDM845_SLAVE_SNOC_MEM_NOC_SF,
673 SDM845_SLAVE_QDSS_STM
677 static struct qcom_icc_node qxm_pimem = {
679 .id = SDM845_MASTER_PIMEM,
683 .links = { SDM845_SLAVE_SNOC_MEM_NOC_GC,
688 static struct qcom_icc_node xm_gic = {
690 .id = SDM845_MASTER_GIC,
694 .links = { SDM845_SLAVE_SNOC_MEM_NOC_GC,
699 static struct qcom_icc_node qns_a1noc_snoc = {
700 .name = "qns_a1noc_snoc",
701 .id = SDM845_SLAVE_A1NOC_SNOC,
705 .links = { SDM845_MASTER_A1NOC_SNOC },
708 static struct qcom_icc_node srvc_aggre1_noc = {
709 .name = "srvc_aggre1_noc",
710 .id = SDM845_SLAVE_SERVICE_A1NOC,
717 static struct qcom_icc_node qns_pcie_a1noc_snoc = {
718 .name = "qns_pcie_a1noc_snoc",
719 .id = SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC,
723 .links = { SDM845_MASTER_ANOC_PCIE_SNOC },
726 static struct qcom_icc_node qns_a2noc_snoc = {
727 .name = "qns_a2noc_snoc",
728 .id = SDM845_SLAVE_A2NOC_SNOC,
732 .links = { SDM845_MASTER_A2NOC_SNOC },
735 static struct qcom_icc_node qns_pcie_snoc = {
736 .name = "qns_pcie_snoc",
737 .id = SDM845_SLAVE_ANOC_PCIE_SNOC,
741 .links = { SDM845_MASTER_ANOC_PCIE_SNOC },
744 static struct qcom_icc_node srvc_aggre2_noc = {
745 .name = "srvc_aggre2_noc",
746 .id = SDM845_SLAVE_SERVICE_A2NOC,
751 static struct qcom_icc_node qns_camnoc_uncomp = {
752 .name = "qns_camnoc_uncomp",
753 .id = SDM845_SLAVE_CAMNOC_UNCOMP,
758 static struct qcom_icc_node qhs_a1_noc_cfg = {
759 .name = "qhs_a1_noc_cfg",
760 .id = SDM845_SLAVE_A1NOC_CFG,
764 .links = { SDM845_MASTER_A1NOC_CFG },
767 static struct qcom_icc_node qhs_a2_noc_cfg = {
768 .name = "qhs_a2_noc_cfg",
769 .id = SDM845_SLAVE_A2NOC_CFG,
773 .links = { SDM845_MASTER_A2NOC_CFG },
776 static struct qcom_icc_node qhs_aop = {
778 .id = SDM845_SLAVE_AOP,
783 static struct qcom_icc_node qhs_aoss = {
785 .id = SDM845_SLAVE_AOSS,
790 static struct qcom_icc_node qhs_camera_cfg = {
791 .name = "qhs_camera_cfg",
792 .id = SDM845_SLAVE_CAMERA_CFG,
797 static struct qcom_icc_node qhs_clk_ctl = {
798 .name = "qhs_clk_ctl",
799 .id = SDM845_SLAVE_CLK_CTL,
804 static struct qcom_icc_node qhs_compute_dsp_cfg = {
805 .name = "qhs_compute_dsp_cfg",
806 .id = SDM845_SLAVE_CDSP_CFG,
811 static struct qcom_icc_node qhs_cpr_cx = {
812 .name = "qhs_cpr_cx",
813 .id = SDM845_SLAVE_RBCPR_CX_CFG,
818 static struct qcom_icc_node qhs_crypto0_cfg = {
819 .name = "qhs_crypto0_cfg",
820 .id = SDM845_SLAVE_CRYPTO_0_CFG,
825 static struct qcom_icc_node qhs_dcc_cfg = {
826 .name = "qhs_dcc_cfg",
827 .id = SDM845_SLAVE_DCC_CFG,
831 .links = { SDM845_MASTER_CNOC_DC_NOC },
834 static struct qcom_icc_node qhs_ddrss_cfg = {
835 .name = "qhs_ddrss_cfg",
836 .id = SDM845_SLAVE_CNOC_DDRSS,
841 static struct qcom_icc_node qhs_display_cfg = {
842 .name = "qhs_display_cfg",
843 .id = SDM845_SLAVE_DISPLAY_CFG,
848 static struct qcom_icc_node qhs_glm = {
850 .id = SDM845_SLAVE_GLM,
855 static struct qcom_icc_node qhs_gpuss_cfg = {
856 .name = "qhs_gpuss_cfg",
857 .id = SDM845_SLAVE_GFX3D_CFG,
862 static struct qcom_icc_node qhs_imem_cfg = {
863 .name = "qhs_imem_cfg",
864 .id = SDM845_SLAVE_IMEM_CFG,
869 static struct qcom_icc_node qhs_ipa = {
871 .id = SDM845_SLAVE_IPA_CFG,
876 static struct qcom_icc_node qhs_mnoc_cfg = {
877 .name = "qhs_mnoc_cfg",
878 .id = SDM845_SLAVE_CNOC_MNOC_CFG,
882 .links = { SDM845_MASTER_CNOC_MNOC_CFG },
885 static struct qcom_icc_node qhs_pcie0_cfg = {
886 .name = "qhs_pcie0_cfg",
887 .id = SDM845_SLAVE_PCIE_0_CFG,
892 static struct qcom_icc_node qhs_pcie_gen3_cfg = {
893 .name = "qhs_pcie_gen3_cfg",
894 .id = SDM845_SLAVE_PCIE_1_CFG,
899 static struct qcom_icc_node qhs_pdm = {
901 .id = SDM845_SLAVE_PDM,
906 static struct qcom_icc_node qhs_phy_refgen_south = {
907 .name = "qhs_phy_refgen_south",
908 .id = SDM845_SLAVE_SOUTH_PHY_CFG,
913 static struct qcom_icc_node qhs_pimem_cfg = {
914 .name = "qhs_pimem_cfg",
915 .id = SDM845_SLAVE_PIMEM_CFG,
920 static struct qcom_icc_node qhs_prng = {
922 .id = SDM845_SLAVE_PRNG,
927 static struct qcom_icc_node qhs_qdss_cfg = {
928 .name = "qhs_qdss_cfg",
929 .id = SDM845_SLAVE_QDSS_CFG,
934 static struct qcom_icc_node qhs_qupv3_north = {
935 .name = "qhs_qupv3_north",
936 .id = SDM845_SLAVE_BLSP_2,
941 static struct qcom_icc_node qhs_qupv3_south = {
942 .name = "qhs_qupv3_south",
943 .id = SDM845_SLAVE_BLSP_1,
948 static struct qcom_icc_node qhs_sdc2 = {
950 .id = SDM845_SLAVE_SDCC_2,
955 static struct qcom_icc_node qhs_sdc4 = {
957 .id = SDM845_SLAVE_SDCC_4,
962 static struct qcom_icc_node qhs_snoc_cfg = {
963 .name = "qhs_snoc_cfg",
964 .id = SDM845_SLAVE_SNOC_CFG,
968 .links = { SDM845_MASTER_SNOC_CFG },
971 static struct qcom_icc_node qhs_spdm = {
973 .id = SDM845_SLAVE_SPDM_WRAPPER,
978 static struct qcom_icc_node qhs_spss_cfg = {
979 .name = "qhs_spss_cfg",
980 .id = SDM845_SLAVE_SPSS_CFG,
985 static struct qcom_icc_node qhs_tcsr = {
987 .id = SDM845_SLAVE_TCSR,
992 static struct qcom_icc_node qhs_tlmm_north = {
993 .name = "qhs_tlmm_north",
994 .id = SDM845_SLAVE_TLMM_NORTH,
999 static struct qcom_icc_node qhs_tlmm_south = {
1000 .name = "qhs_tlmm_south",
1001 .id = SDM845_SLAVE_TLMM_SOUTH,
1006 static struct qcom_icc_node qhs_tsif = {
1008 .id = SDM845_SLAVE_TSIF,
1013 static struct qcom_icc_node qhs_ufs_card_cfg = {
1014 .name = "qhs_ufs_card_cfg",
1015 .id = SDM845_SLAVE_UFS_CARD_CFG,
1020 static struct qcom_icc_node qhs_ufs_mem_cfg = {
1021 .name = "qhs_ufs_mem_cfg",
1022 .id = SDM845_SLAVE_UFS_MEM_CFG,
1027 static struct qcom_icc_node qhs_usb3_0 = {
1028 .name = "qhs_usb3_0",
1029 .id = SDM845_SLAVE_USB3_0,
1034 static struct qcom_icc_node qhs_usb3_1 = {
1035 .name = "qhs_usb3_1",
1036 .id = SDM845_SLAVE_USB3_1,
1041 static struct qcom_icc_node qhs_venus_cfg = {
1042 .name = "qhs_venus_cfg",
1043 .id = SDM845_SLAVE_VENUS_CFG,
1048 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1049 .name = "qhs_vsense_ctrl_cfg",
1050 .id = SDM845_SLAVE_VSENSE_CTRL_CFG,
1055 static struct qcom_icc_node qns_cnoc_a2noc = {
1056 .name = "qns_cnoc_a2noc",
1057 .id = SDM845_SLAVE_CNOC_A2NOC,
1061 .links = { SDM845_MASTER_CNOC_A2NOC },
1064 static struct qcom_icc_node srvc_cnoc = {
1065 .name = "srvc_cnoc",
1066 .id = SDM845_SLAVE_SERVICE_CNOC,
1071 static struct qcom_icc_node qhs_llcc = {
1073 .id = SDM845_SLAVE_LLCC_CFG,
1078 static struct qcom_icc_node qhs_memnoc = {
1079 .name = "qhs_memnoc",
1080 .id = SDM845_SLAVE_MEM_NOC_CFG,
1084 .links = { SDM845_MASTER_MEM_NOC_CFG },
1087 static struct qcom_icc_node qns_gladiator_sodv = {
1088 .name = "qns_gladiator_sodv",
1089 .id = SDM845_SLAVE_GNOC_SNOC,
1093 .links = { SDM845_MASTER_GNOC_SNOC },
1096 static struct qcom_icc_node qns_gnoc_memnoc = {
1097 .name = "qns_gnoc_memnoc",
1098 .id = SDM845_SLAVE_GNOC_MEM_NOC,
1102 .links = { SDM845_MASTER_GNOC_MEM_NOC },
1105 static struct qcom_icc_node srvc_gnoc = {
1106 .name = "srvc_gnoc",
1107 .id = SDM845_SLAVE_SERVICE_GNOC,
1112 static struct qcom_icc_node ebi = {
1114 .id = SDM845_SLAVE_EBI1,
1119 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1120 .name = "qhs_mdsp_ms_mpu_cfg",
1121 .id = SDM845_SLAVE_MSS_PROC_MS_MPU_CFG,
1126 static struct qcom_icc_node qns_apps_io = {
1127 .name = "qns_apps_io",
1128 .id = SDM845_SLAVE_MEM_NOC_GNOC,
1133 static struct qcom_icc_node qns_llcc = {
1135 .id = SDM845_SLAVE_LLCC,
1139 .links = { SDM845_MASTER_LLCC },
1142 static struct qcom_icc_node qns_memnoc_snoc = {
1143 .name = "qns_memnoc_snoc",
1144 .id = SDM845_SLAVE_MEM_NOC_SNOC,
1148 .links = { SDM845_MASTER_MEM_NOC_SNOC },
1151 static struct qcom_icc_node srvc_memnoc = {
1152 .name = "srvc_memnoc",
1153 .id = SDM845_SLAVE_SERVICE_MEM_NOC,
1158 static struct qcom_icc_node qns2_mem_noc = {
1159 .name = "qns2_mem_noc",
1160 .id = SDM845_SLAVE_MNOC_SF_MEM_NOC,
1164 .links = { SDM845_MASTER_MNOC_SF_MEM_NOC },
1167 static struct qcom_icc_node qns_mem_noc_hf = {
1168 .name = "qns_mem_noc_hf",
1169 .id = SDM845_SLAVE_MNOC_HF_MEM_NOC,
1173 .links = { SDM845_MASTER_MNOC_HF_MEM_NOC },
1176 static struct qcom_icc_node srvc_mnoc = {
1177 .name = "srvc_mnoc",
1178 .id = SDM845_SLAVE_SERVICE_MNOC,
1183 static struct qcom_icc_node qhs_apss = {
1185 .id = SDM845_SLAVE_APPSS,
1190 static struct qcom_icc_node qns_cnoc = {
1192 .id = SDM845_SLAVE_SNOC_CNOC,
1196 .links = { SDM845_MASTER_SNOC_CNOC },
1199 static struct qcom_icc_node qns_memnoc_gc = {
1200 .name = "qns_memnoc_gc",
1201 .id = SDM845_SLAVE_SNOC_MEM_NOC_GC,
1205 .links = { SDM845_MASTER_SNOC_GC_MEM_NOC },
1208 static struct qcom_icc_node qns_memnoc_sf = {
1209 .name = "qns_memnoc_sf",
1210 .id = SDM845_SLAVE_SNOC_MEM_NOC_SF,
1214 .links = { SDM845_MASTER_SNOC_SF_MEM_NOC },
1217 static struct qcom_icc_node qxs_imem = {
1219 .id = SDM845_SLAVE_IMEM,
1224 static struct qcom_icc_node qxs_pcie = {
1226 .id = SDM845_SLAVE_PCIE_0,
1231 static struct qcom_icc_node qxs_pcie_gen3 = {
1232 .name = "qxs_pcie_gen3",
1233 .id = SDM845_SLAVE_PCIE_1,
1238 static struct qcom_icc_node qxs_pimem = {
1239 .name = "qxs_pimem",
1240 .id = SDM845_SLAVE_PIMEM,
1245 static struct qcom_icc_node srvc_snoc = {
1246 .name = "srvc_snoc",
1247 .id = SDM845_SLAVE_SERVICE_SNOC,
1252 static struct qcom_icc_node xs_qdss_stm = {
1253 .name = "xs_qdss_stm",
1254 .id = SDM845_SLAVE_QDSS_STM,
1259 static struct qcom_icc_node xs_sys_tcu_cfg = {
1260 .name = "xs_sys_tcu_cfg",
1261 .id = SDM845_SLAVE_TCU,
1266 static struct qcom_icc_bcm bcm_acv = {
1268 .enable_mask = BIT(3),
1274 static struct qcom_icc_bcm bcm_mc0 = {
1281 static struct qcom_icc_bcm bcm_sh0 = {
1285 .nodes = { &qns_llcc },
1288 static struct qcom_icc_bcm bcm_mm0 = {
1292 .nodes = { &qns_mem_noc_hf },
1295 static struct qcom_icc_bcm bcm_sh1 = {
1299 .nodes = { &qns_apps_io },
1302 static struct qcom_icc_bcm bcm_mm1 = {
1306 .nodes = { &qxm_camnoc_hf0_uncomp,
1307 &qxm_camnoc_hf1_uncomp,
1308 &qxm_camnoc_sf_uncomp,
1316 static struct qcom_icc_bcm bcm_sh2 = {
1320 .nodes = { &qns_memnoc_snoc },
1323 static struct qcom_icc_bcm bcm_mm2 = {
1327 .nodes = { &qns2_mem_noc },
1330 static struct qcom_icc_bcm bcm_sh3 = {
1334 .nodes = { &acm_tcu },
1337 static struct qcom_icc_bcm bcm_mm3 = {
1341 .nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 },
1344 static struct qcom_icc_bcm bcm_sh5 = {
1348 .nodes = { &qnm_apps },
1351 static struct qcom_icc_bcm bcm_sn0 = {
1355 .nodes = { &qns_memnoc_sf },
1358 static struct qcom_icc_bcm bcm_ce0 = {
1362 .nodes = { &qxm_crypto },
1365 static struct qcom_icc_bcm bcm_cn0 = {
1369 .nodes = { &qhm_spdm,
1379 &qhs_compute_dsp_cfg,
1393 &qhs_phy_refgen_south,
1413 &qhs_vsense_ctrl_cfg,
1419 static struct qcom_icc_bcm bcm_qup0 = {
1423 .nodes = { &qhm_qup1, &qhm_qup2 },
1426 static struct qcom_icc_bcm bcm_sn1 = {
1430 .nodes = { &qxs_imem },
1433 static struct qcom_icc_bcm bcm_sn2 = {
1437 .nodes = { &qns_memnoc_gc },
1440 static struct qcom_icc_bcm bcm_sn3 = {
1444 .nodes = { &qns_cnoc },
1447 static struct qcom_icc_bcm bcm_sn4 = {
1451 .nodes = { &qxm_pimem },
1454 static struct qcom_icc_bcm bcm_sn5 = {
1458 .nodes = { &xs_qdss_stm },
1461 static struct qcom_icc_bcm bcm_sn6 = {
1465 .nodes = { &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg },
1468 static struct qcom_icc_bcm bcm_sn7 = {
1472 .nodes = { &qxs_pcie },
1475 static struct qcom_icc_bcm bcm_sn8 = {
1479 .nodes = { &qxs_pcie_gen3 },
1482 static struct qcom_icc_bcm bcm_sn9 = {
1486 .nodes = { &srvc_aggre1_noc, &qnm_aggre1_noc },
1489 static struct qcom_icc_bcm bcm_sn11 = {
1493 .nodes = { &srvc_aggre2_noc, &qnm_aggre2_noc },
1496 static struct qcom_icc_bcm bcm_sn12 = {
1500 .nodes = { &qnm_gladiator_sodv, &xm_gic },
1503 static struct qcom_icc_bcm bcm_sn14 = {
1507 .nodes = { &qnm_pcie_anoc },
1510 static struct qcom_icc_bcm bcm_sn15 = {
1514 .nodes = { &qnm_memnoc },
1517 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1522 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1523 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
1524 [MASTER_TSIF] = &qhm_tsif,
1525 [MASTER_SDCC_2] = &xm_sdc2,
1526 [MASTER_SDCC_4] = &xm_sdc4,
1527 [MASTER_UFS_CARD] = &xm_ufs_card,
1528 [MASTER_UFS_MEM] = &xm_ufs_mem,
1529 [MASTER_PCIE_0] = &xm_pcie_0,
1530 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1531 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1532 [SLAVE_ANOC_PCIE_A1NOC_SNOC] = &qns_pcie_a1noc_snoc,
1533 [MASTER_QUP_1] = &qhm_qup1,
1536 static const struct qcom_icc_desc sdm845_aggre1_noc = {
1537 .nodes = aggre1_noc_nodes,
1538 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1539 .bcms = aggre1_noc_bcms,
1540 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1543 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1549 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1550 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
1551 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1552 [MASTER_CNOC_A2NOC] = &qnm_cnoc,
1553 [MASTER_CRYPTO] = &qxm_crypto,
1554 [MASTER_IPA] = &qxm_ipa,
1555 [MASTER_PCIE_1] = &xm_pcie3_1,
1556 [MASTER_QDSS_ETR] = &xm_qdss_etr,
1557 [MASTER_USB3_0] = &xm_usb3_0,
1558 [MASTER_USB3_1] = &xm_usb3_1,
1559 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1560 [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc,
1561 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1562 [MASTER_QUP_2] = &qhm_qup2,
1565 static const struct qcom_icc_desc sdm845_aggre2_noc = {
1566 .nodes = aggre2_noc_nodes,
1567 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1568 .bcms = aggre2_noc_bcms,
1569 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1572 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1576 static struct qcom_icc_node * const config_noc_nodes[] = {
1577 [MASTER_SPDM] = &qhm_spdm,
1578 [MASTER_TIC] = &qhm_tic,
1579 [MASTER_SNOC_CNOC] = &qnm_snoc,
1580 [MASTER_QDSS_DAP] = &xm_qdss_dap,
1581 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
1582 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
1583 [SLAVE_AOP] = &qhs_aop,
1584 [SLAVE_AOSS] = &qhs_aoss,
1585 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1586 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1587 [SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg,
1588 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1589 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1590 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
1591 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
1592 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1593 [SLAVE_GLM] = &qhs_glm,
1594 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1595 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1596 [SLAVE_IPA_CFG] = &qhs_ipa,
1597 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
1598 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1599 [SLAVE_PCIE_1_CFG] = &qhs_pcie_gen3_cfg,
1600 [SLAVE_PDM] = &qhs_pdm,
1601 [SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south,
1602 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1603 [SLAVE_PRNG] = &qhs_prng,
1604 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1605 [SLAVE_BLSP_2] = &qhs_qupv3_north,
1606 [SLAVE_BLSP_1] = &qhs_qupv3_south,
1607 [SLAVE_SDCC_2] = &qhs_sdc2,
1608 [SLAVE_SDCC_4] = &qhs_sdc4,
1609 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
1610 [SLAVE_SPDM_WRAPPER] = &qhs_spdm,
1611 [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1612 [SLAVE_TCSR] = &qhs_tcsr,
1613 [SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
1614 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
1615 [SLAVE_TSIF] = &qhs_tsif,
1616 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
1617 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1618 [SLAVE_USB3_0] = &qhs_usb3_0,
1619 [SLAVE_USB3_1] = &qhs_usb3_1,
1620 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1621 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1622 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
1623 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1626 static const struct qcom_icc_desc sdm845_config_noc = {
1627 .nodes = config_noc_nodes,
1628 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1629 .bcms = config_noc_bcms,
1630 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1633 static struct qcom_icc_bcm * const dc_noc_bcms[] = {
1636 static struct qcom_icc_node * const dc_noc_nodes[] = {
1637 [MASTER_CNOC_DC_NOC] = &qhm_cnoc,
1638 [SLAVE_LLCC_CFG] = &qhs_llcc,
1639 [SLAVE_MEM_NOC_CFG] = &qhs_memnoc,
1642 static const struct qcom_icc_desc sdm845_dc_noc = {
1643 .nodes = dc_noc_nodes,
1644 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1645 .bcms = dc_noc_bcms,
1646 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
1649 static struct qcom_icc_bcm * const gladiator_noc_bcms[] = {
1652 static struct qcom_icc_node * const gladiator_noc_nodes[] = {
1653 [MASTER_APPSS_PROC] = &acm_l3,
1654 [MASTER_GNOC_CFG] = &pm_gnoc_cfg,
1655 [SLAVE_GNOC_SNOC] = &qns_gladiator_sodv,
1656 [SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc,
1657 [SLAVE_SERVICE_GNOC] = &srvc_gnoc,
1660 static const struct qcom_icc_desc sdm845_gladiator_noc = {
1661 .nodes = gladiator_noc_nodes,
1662 .num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
1663 .bcms = gladiator_noc_bcms,
1664 .num_bcms = ARRAY_SIZE(gladiator_noc_bcms),
1667 static struct qcom_icc_bcm * const mem_noc_bcms[] = {
1677 static struct qcom_icc_node * const mem_noc_nodes[] = {
1678 [MASTER_TCU_0] = &acm_tcu,
1679 [MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg,
1680 [MASTER_GNOC_MEM_NOC] = &qnm_apps,
1681 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1682 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1683 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1684 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1685 [MASTER_GFX3D] = &qxm_gpu,
1686 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1687 [SLAVE_MEM_NOC_GNOC] = &qns_apps_io,
1688 [SLAVE_LLCC] = &qns_llcc,
1689 [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc,
1690 [SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc,
1691 [MASTER_LLCC] = &llcc_mc,
1692 [SLAVE_EBI1] = &ebi,
1695 static const struct qcom_icc_desc sdm845_mem_noc = {
1696 .nodes = mem_noc_nodes,
1697 .num_nodes = ARRAY_SIZE(mem_noc_nodes),
1698 .bcms = mem_noc_bcms,
1699 .num_bcms = ARRAY_SIZE(mem_noc_bcms),
1702 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1709 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1710 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
1711 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
1712 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
1713 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
1714 [MASTER_MDP0] = &qxm_mdp0,
1715 [MASTER_MDP1] = &qxm_mdp1,
1716 [MASTER_ROTATOR] = &qxm_rot,
1717 [MASTER_VIDEO_P0] = &qxm_venus0,
1718 [MASTER_VIDEO_P1] = &qxm_venus1,
1719 [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
1720 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
1721 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1722 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1723 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
1724 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
1725 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
1726 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
1729 static const struct qcom_icc_desc sdm845_mmss_noc = {
1730 .nodes = mmss_noc_nodes,
1731 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1732 .bcms = mmss_noc_bcms,
1733 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1736 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1753 static struct qcom_icc_node * const system_noc_nodes[] = {
1754 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
1755 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1756 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1757 [MASTER_GNOC_SNOC] = &qnm_gladiator_sodv,
1758 [MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
1759 [MASTER_ANOC_PCIE_SNOC] = &qnm_pcie_anoc,
1760 [MASTER_PIMEM] = &qxm_pimem,
1761 [MASTER_GIC] = &xm_gic,
1762 [SLAVE_APPSS] = &qhs_apss,
1763 [SLAVE_SNOC_CNOC] = &qns_cnoc,
1764 [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc,
1765 [SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf,
1766 [SLAVE_IMEM] = &qxs_imem,
1767 [SLAVE_PCIE_0] = &qxs_pcie,
1768 [SLAVE_PCIE_1] = &qxs_pcie_gen3,
1769 [SLAVE_PIMEM] = &qxs_pimem,
1770 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
1771 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1772 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1775 static const struct qcom_icc_desc sdm845_system_noc = {
1776 .nodes = system_noc_nodes,
1777 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1778 .bcms = system_noc_bcms,
1779 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1782 static const struct of_device_id qnoc_of_match[] = {
1783 { .compatible = "qcom,sdm845-aggre1-noc",
1784 .data = &sdm845_aggre1_noc},
1785 { .compatible = "qcom,sdm845-aggre2-noc",
1786 .data = &sdm845_aggre2_noc},
1787 { .compatible = "qcom,sdm845-config-noc",
1788 .data = &sdm845_config_noc},
1789 { .compatible = "qcom,sdm845-dc-noc",
1790 .data = &sdm845_dc_noc},
1791 { .compatible = "qcom,sdm845-gladiator-noc",
1792 .data = &sdm845_gladiator_noc},
1793 { .compatible = "qcom,sdm845-mem-noc",
1794 .data = &sdm845_mem_noc},
1795 { .compatible = "qcom,sdm845-mmss-noc",
1796 .data = &sdm845_mmss_noc},
1797 { .compatible = "qcom,sdm845-system-noc",
1798 .data = &sdm845_system_noc},
1801 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1803 static struct platform_driver qnoc_driver = {
1804 .probe = qcom_icc_rpmh_probe,
1805 .remove = qcom_icc_rpmh_remove,
1807 .name = "qnoc-sdm845",
1808 .of_match_table = qnoc_of_match,
1809 .sync_state = icc_sync_state,
1812 module_platform_driver(qnoc_driver);
1814 MODULE_AUTHOR("David Dai <daidavid1@codeaurora.org>");
1815 MODULE_DESCRIPTION("Qualcomm sdm845 NoC driver");
1816 MODULE_LICENSE("GPL v2");