drivers/interconnect/qcom/sc8180x.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2021, Linaro Ltd.
   5  */
   6
   7 #include <linux/device.h>
   8 #include <linux/interconnect-provider.h>
   9 #include <linux/module.h>
  10 #include <linux/of_device.h>
  11
  12 #include <dt-bindings/interconnect/qcom,sc8180x.h>
  13
  14 #include "bcm-voter.h"
  15 #include "icc-rpmh.h"
  16 #include "sc8180x.h"
  17
  18 static struct qcom_icc_node mas_qhm_a1noc_cfg = {
  19         .name = "mas_qhm_a1noc_cfg",
  20         .id = SC8180X_MASTER_A1NOC_CFG,
  21         .channels = 1,
  22         .buswidth = 4,
  23         .num_links = 1,
  24         .links = { SC8180X_SLAVE_SERVICE_A1NOC }
  25 };
  26
  27 static struct qcom_icc_node mas_xm_ufs_card = {
  28         .name = "mas_xm_ufs_card",
  29         .id = SC8180X_MASTER_UFS_CARD,
  30         .channels = 1,
  31         .buswidth = 8,
  32         .num_links = 1,
  33         .links = { SC8180X_A1NOC_SNOC_SLV }
  34 };
  35
  36 static struct qcom_icc_node mas_xm_ufs_g4 = {
  37         .name = "mas_xm_ufs_g4",
  38         .id = SC8180X_MASTER_UFS_GEN4,
  39         .channels = 1,
  40         .buswidth = 8,
  41         .num_links = 1,
  42         .links = { SC8180X_A1NOC_SNOC_SLV }
  43 };
  44
  45 static struct qcom_icc_node mas_xm_ufs_mem = {
  46         .name = "mas_xm_ufs_mem",
  47         .id = SC8180X_MASTER_UFS_MEM,
  48         .channels = 1,
  49         .buswidth = 8,
  50         .num_links = 1,
  51         .links = { SC8180X_A1NOC_SNOC_SLV }
  52 };
  53
  54 static struct qcom_icc_node mas_xm_usb3_0 = {
  55         .name = "mas_xm_usb3_0",
  56         .id = SC8180X_MASTER_USB3,
  57         .channels = 1,
  58         .buswidth = 8,
  59         .num_links = 1,
  60         .links = { SC8180X_A1NOC_SNOC_SLV }
  61 };
  62
  63 static struct qcom_icc_node mas_xm_usb3_1 = {
  64         .name = "mas_xm_usb3_1",
  65         .id = SC8180X_MASTER_USB3_1,
  66         .channels = 1,
  67         .buswidth = 8,
  68         .num_links = 1,
  69         .links = { SC8180X_A1NOC_SNOC_SLV }
  70 };
  71
  72 static struct qcom_icc_node mas_xm_usb3_2 = {
  73         .name = "mas_xm_usb3_2",
  74         .id = SC8180X_MASTER_USB3_2,
  75         .channels = 1,
  76         .buswidth = 16,
  77         .num_links = 1,
  78         .links = { SC8180X_A1NOC_SNOC_SLV }
  79 };
  80
  81 static struct qcom_icc_node mas_qhm_a2noc_cfg = {
  82         .name = "mas_qhm_a2noc_cfg",
  83         .id = SC8180X_MASTER_A2NOC_CFG,
  84         .channels = 1,
  85         .buswidth = 4,
  86         .num_links = 1,
  87         .links = { SC8180X_SLAVE_SERVICE_A2NOC }
  88 };
  89
  90 static struct qcom_icc_node mas_qhm_qdss_bam = {
  91         .name = "mas_qhm_qdss_bam",
  92         .id = SC8180X_MASTER_QDSS_BAM,
  93         .channels = 1,
  94         .buswidth = 4,
  95         .num_links = 1,
  96         .links = { SC8180X_A2NOC_SNOC_SLV }
  97 };
  98
  99 static struct qcom_icc_node mas_qhm_qspi = {
 100         .name = "mas_qhm_qspi",
 101         .id = SC8180X_MASTER_QSPI_0,
 102         .channels = 1,
 103         .buswidth = 4,
 104         .num_links = 1,
 105         .links = { SC8180X_A2NOC_SNOC_SLV }
 106 };
 107
 108 static struct qcom_icc_node mas_qhm_qspi1 = {
 109         .name = "mas_qhm_qspi1",
 110         .id = SC8180X_MASTER_QSPI_1,
 111         .channels = 1,
 112         .buswidth = 4,
 113         .num_links = 1,
 114         .links = { SC8180X_A2NOC_SNOC_SLV }
 115 };
 116
 117 static struct qcom_icc_node mas_qhm_qup0 = {
 118         .name = "mas_qhm_qup0",
 119         .id = SC8180X_MASTER_QUP_0,
 120         .channels = 1,
 121         .buswidth = 4,
 122         .num_links = 1,
 123         .links = { SC8180X_A2NOC_SNOC_SLV }
 124 };
 125
 126 static struct qcom_icc_node mas_qhm_qup1 = {
 127         .name = "mas_qhm_qup1",
 128         .id = SC8180X_MASTER_QUP_1,
 129         .channels = 1,
 130         .buswidth = 4,
 131         .num_links = 1,
 132         .links = { SC8180X_A2NOC_SNOC_SLV }
 133 };
 134
 135 static struct qcom_icc_node mas_qhm_qup2 = {
 136         .name = "mas_qhm_qup2",
 137         .id = SC8180X_MASTER_QUP_2,
 138         .channels = 1,
 139         .buswidth = 4,
 140         .num_links = 1,
 141         .links = { SC8180X_A2NOC_SNOC_SLV }
 142 };
 143
 144 static struct qcom_icc_node mas_qhm_sensorss_ahb = {
 145         .name = "mas_qhm_sensorss_ahb",
 146         .id = SC8180X_MASTER_SENSORS_AHB,
 147         .channels = 1,
 148         .buswidth = 4,
 149         .num_links = 1,
 150         .links = { SC8180X_A2NOC_SNOC_SLV }
 151 };
 152
 153 static struct qcom_icc_node mas_qxm_crypto = {
 154         .name = "mas_qxm_crypto",
 155         .id = SC8180X_MASTER_CRYPTO_CORE_0,
 156         .channels = 1,
 157         .buswidth = 8,
 158         .num_links = 1,
 159         .links = { SC8180X_A2NOC_SNOC_SLV }
 160 };
 161
 162 static struct qcom_icc_node mas_qxm_ipa = {
 163         .name = "mas_qxm_ipa",
 164         .id = SC8180X_MASTER_IPA,
 165         .channels = 1,
 166         .buswidth = 8,
 167         .num_links = 1,
 168         .links = { SC8180X_A2NOC_SNOC_SLV }
 169 };
 170
 171 static struct qcom_icc_node mas_xm_emac = {
 172         .name = "mas_xm_emac",
 173         .id = SC8180X_MASTER_EMAC,
 174         .channels = 1,
 175         .buswidth = 8,
 176         .num_links = 1,
 177         .links = { SC8180X_A2NOC_SNOC_SLV }
 178 };
 179
 180 static struct qcom_icc_node mas_xm_pcie3_0 = {
 181         .name = "mas_xm_pcie3_0",
 182         .id = SC8180X_MASTER_PCIE,
 183         .channels = 1,
 184         .buswidth = 8,
 185         .num_links = 1,
 186         .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC }
 187 };
 188
 189 static struct qcom_icc_node mas_xm_pcie3_1 = {
 190         .name = "mas_xm_pcie3_1",
 191         .id = SC8180X_MASTER_PCIE_1,
 192         .channels = 1,
 193         .buswidth = 16,
 194         .num_links = 1,
 195         .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC }
 196 };
 197
 198 static struct qcom_icc_node mas_xm_pcie3_2 = {
 199         .name = "mas_xm_pcie3_2",
 200         .id = SC8180X_MASTER_PCIE_2,
 201         .channels = 1,
 202         .buswidth = 8,
 203         .num_links = 1,
 204         .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC }
 205 };
 206
 207 static struct qcom_icc_node mas_xm_pcie3_3 = {
 208         .name = "mas_xm_pcie3_3",
 209         .id = SC8180X_MASTER_PCIE_3,
 210         .channels = 1,
 211         .buswidth = 16,
 212         .num_links = 1,
 213         .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC }
 214 };
 215
 216 static struct qcom_icc_node mas_xm_qdss_etr = {
 217         .name = "mas_xm_qdss_etr",
 218         .id = SC8180X_MASTER_QDSS_ETR,
 219         .channels = 1,
 220         .buswidth = 8,
 221         .num_links = 1,
 222         .links = { SC8180X_A2NOC_SNOC_SLV }
 223 };
 224
 225 static struct qcom_icc_node mas_xm_sdc2 = {
 226         .name = "mas_xm_sdc2",
 227         .id = SC8180X_MASTER_SDCC_2,
 228         .channels = 1,
 229         .buswidth = 8,
 230         .num_links = 1,
 231         .links = { SC8180X_A2NOC_SNOC_SLV }
 232 };
 233
 234 static struct qcom_icc_node mas_xm_sdc4 = {
 235         .name = "mas_xm_sdc4",
 236         .id = SC8180X_MASTER_SDCC_4,
 237         .channels = 1,
 238         .buswidth = 8,
 239         .num_links = 1,
 240         .links = { SC8180X_A2NOC_SNOC_SLV }
 241 };
 242
 243 static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp = {
 244         .name = "mas_qxm_camnoc_hf0_uncomp",
 245         .id = SC8180X_MASTER_CAMNOC_HF0_UNCOMP,
 246         .channels = 1,
 247         .buswidth = 32,
 248         .num_links = 1,
 249         .links = { SC8180X_SLAVE_CAMNOC_UNCOMP }
 250 };
 251
 252 static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp = {
 253         .name = "mas_qxm_camnoc_hf1_uncomp",
 254         .id = SC8180X_MASTER_CAMNOC_HF1_UNCOMP,
 255         .channels = 1,
 256         .buswidth = 32,
 257         .num_links = 1,
 258         .links = { SC8180X_SLAVE_CAMNOC_UNCOMP }
 259 };
 260
 261 static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp = {
 262         .name = "mas_qxm_camnoc_sf_uncomp",
 263         .id = SC8180X_MASTER_CAMNOC_SF_UNCOMP,
 264         .channels = 1,
 265         .buswidth = 32,
 266         .num_links = 1,
 267         .links = { SC8180X_SLAVE_CAMNOC_UNCOMP }
 268 };
 269
 270 static struct qcom_icc_node mas_qnm_npu = {
 271         .name = "mas_qnm_npu",
 272         .id = SC8180X_MASTER_NPU,
 273         .channels = 1,
 274         .buswidth = 32,
 275         .num_links = 1,
 276         .links = { SC8180X_SLAVE_CDSP_MEM_NOC }
 277 };
 278
 279 static struct qcom_icc_node mas_qnm_snoc = {
 280         .name = "mas_qnm_snoc",
 281         .id = SC8180X_SNOC_CNOC_MAS,
 282         .channels = 1,
 283         .buswidth = 8,
 284         .num_links = 56,
 285         .links = { SC8180X_SLAVE_TLMM_SOUTH,
 286                    SC8180X_SLAVE_CDSP_CFG,
 287                    SC8180X_SLAVE_SPSS_CFG,
 288                    SC8180X_SLAVE_CAMERA_CFG,
 289                    SC8180X_SLAVE_SDCC_4,
 290                    SC8180X_SLAVE_AHB2PHY_CENTER,
 291                    SC8180X_SLAVE_SDCC_2,
 292                    SC8180X_SLAVE_PCIE_2_CFG,
 293                    SC8180X_SLAVE_CNOC_MNOC_CFG,
 294                    SC8180X_SLAVE_EMAC_CFG,
 295                    SC8180X_SLAVE_QSPI_0,
 296                    SC8180X_SLAVE_QSPI_1,
 297                    SC8180X_SLAVE_TLMM_EAST,
 298                    SC8180X_SLAVE_SNOC_CFG,
 299                    SC8180X_SLAVE_AHB2PHY_EAST,
 300                    SC8180X_SLAVE_GLM,
 301                    SC8180X_SLAVE_PDM,
 302                    SC8180X_SLAVE_PCIE_1_CFG,
 303                    SC8180X_SLAVE_A2NOC_CFG,
 304                    SC8180X_SLAVE_QDSS_CFG,
 305                    SC8180X_SLAVE_DISPLAY_CFG,
 306                    SC8180X_SLAVE_TCSR,
 307                    SC8180X_SLAVE_UFS_MEM_0_CFG,
 308                    SC8180X_SLAVE_CNOC_DDRSS,
 309                    SC8180X_SLAVE_PCIE_0_CFG,
 310                    SC8180X_SLAVE_QUP_1,
 311                    SC8180X_SLAVE_QUP_2,
 312                    SC8180X_SLAVE_NPU_CFG,
 313                    SC8180X_SLAVE_CRYPTO_0_CFG,
 314                    SC8180X_SLAVE_GRAPHICS_3D_CFG,
 315                    SC8180X_SLAVE_VENUS_CFG,
 316                    SC8180X_SLAVE_TSIF,
 317                    SC8180X_SLAVE_IPA_CFG,
 318                    SC8180X_SLAVE_CLK_CTL,
 319                    SC8180X_SLAVE_SECURITY,
 320                    SC8180X_SLAVE_AOP,
 321                    SC8180X_SLAVE_AHB2PHY_WEST,
 322                    SC8180X_SLAVE_AHB2PHY_SOUTH,
 323                    SC8180X_SLAVE_SERVICE_CNOC,
 324                    SC8180X_SLAVE_UFS_CARD_CFG,
 325                    SC8180X_SLAVE_USB3_1,
 326                    SC8180X_SLAVE_USB3_2,
 327                    SC8180X_SLAVE_PCIE_3_CFG,
 328                    SC8180X_SLAVE_RBCPR_CX_CFG,
 329                    SC8180X_SLAVE_TLMM_WEST,
 330                    SC8180X_SLAVE_A1NOC_CFG,
 331                    SC8180X_SLAVE_AOSS,
 332                    SC8180X_SLAVE_PRNG,
 333                    SC8180X_SLAVE_VSENSE_CTRL_CFG,
 334                    SC8180X_SLAVE_QUP_0,
 335                    SC8180X_SLAVE_USB3,
 336                    SC8180X_SLAVE_RBCPR_MMCX_CFG,
 337                    SC8180X_SLAVE_PIMEM_CFG,
 338                    SC8180X_SLAVE_UFS_MEM_1_CFG,
 339                    SC8180X_SLAVE_RBCPR_MX_CFG,
 340                    SC8180X_SLAVE_IMEM_CFG }
 341 };
 342
 343 static struct qcom_icc_node mas_qhm_cnoc_dc_noc = {
 344         .name = "mas_qhm_cnoc_dc_noc",
 345         .id = SC8180X_MASTER_CNOC_DC_NOC,
 346         .channels = 1,
 347         .buswidth = 4,
 348         .num_links = 2,
 349         .links = { SC8180X_SLAVE_LLCC_CFG,
 350                    SC8180X_SLAVE_GEM_NOC_CFG }
 351 };
 352
 353 static struct qcom_icc_node mas_acm_apps = {
 354         .name = "mas_acm_apps",
 355         .id = SC8180X_MASTER_AMPSS_M0,
 356         .channels = 4,
 357         .buswidth = 64,
 358         .num_links = 3,
 359         .links = { SC8180X_SLAVE_ECC,
 360                    SC8180X_SLAVE_LLCC,
 361                    SC8180X_SLAVE_GEM_NOC_SNOC }
 362 };
 363
 364 static struct qcom_icc_node mas_acm_gpu_tcu = {
 365         .name = "mas_acm_gpu_tcu",
 366         .id = SC8180X_MASTER_GPU_TCU,
 367         .channels = 1,
 368         .buswidth = 8,
 369         .num_links = 2,
 370         .links = { SC8180X_SLAVE_LLCC,
 371                    SC8180X_SLAVE_GEM_NOC_SNOC }
 372 };
 373
 374 static struct qcom_icc_node mas_acm_sys_tcu = {
 375         .name = "mas_acm_sys_tcu",
 376         .id = SC8180X_MASTER_SYS_TCU,
 377         .channels = 1,
 378         .buswidth = 8,
 379         .num_links = 2,
 380         .links = { SC8180X_SLAVE_LLCC,
 381                    SC8180X_SLAVE_GEM_NOC_SNOC }
 382 };
 383
 384 static struct qcom_icc_node mas_qhm_gemnoc_cfg = {
 385         .name = "mas_qhm_gemnoc_cfg",
 386         .id = SC8180X_MASTER_GEM_NOC_CFG,
 387         .channels = 1,
 388         .buswidth = 4,
 389         .num_links = 3,
 390         .links = { SC8180X_SLAVE_SERVICE_GEM_NOC_1,
 391                    SC8180X_SLAVE_SERVICE_GEM_NOC,
 392                    SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG }
 393 };
 394
 395 static struct qcom_icc_node mas_qnm_cmpnoc = {
 396         .name = "mas_qnm_cmpnoc",
 397         .id = SC8180X_MASTER_COMPUTE_NOC,
 398         .channels = 2,
 399         .buswidth = 32,
 400         .num_links = 3,
 401         .links = { SC8180X_SLAVE_ECC,
 402                    SC8180X_SLAVE_LLCC,
 403                    SC8180X_SLAVE_GEM_NOC_SNOC }
 404 };
 405
 406 static struct qcom_icc_node mas_qnm_gpu = {
 407         .name = "mas_qnm_gpu",
 408         .id = SC8180X_MASTER_GRAPHICS_3D,
 409         .channels = 4,
 410         .buswidth = 32,
 411         .num_links = 2,
 412         .links = { SC8180X_SLAVE_LLCC,
 413                    SC8180X_SLAVE_GEM_NOC_SNOC }
 414 };
 415
 416 static struct qcom_icc_node mas_qnm_mnoc_hf = {
 417         .name = "mas_qnm_mnoc_hf",
 418         .id = SC8180X_MASTER_MNOC_HF_MEM_NOC,
 419         .channels = 2,
 420         .buswidth = 32,
 421         .num_links = 1,
 422         .links = { SC8180X_SLAVE_LLCC }
 423 };
 424
 425 static struct qcom_icc_node mas_qnm_mnoc_sf = {
 426         .name = "mas_qnm_mnoc_sf",
 427         .id = SC8180X_MASTER_MNOC_SF_MEM_NOC,
 428         .channels = 1,
 429         .buswidth = 32,
 430         .num_links = 2,
 431         .links = { SC8180X_SLAVE_LLCC,
 432                    SC8180X_SLAVE_GEM_NOC_SNOC }
 433 };
 434
 435 static struct qcom_icc_node mas_qnm_pcie = {
 436         .name = "mas_qnm_pcie",
 437         .id = SC8180X_MASTER_GEM_NOC_PCIE_SNOC,
 438         .channels = 1,
 439         .buswidth = 32,
 440         .num_links = 2,
 441         .links = { SC8180X_SLAVE_LLCC,
 442                    SC8180X_SLAVE_GEM_NOC_SNOC }
 443 };
 444
 445 static struct qcom_icc_node mas_qnm_snoc_gc = {
 446         .name = "mas_qnm_snoc_gc",
 447         .id = SC8180X_MASTER_SNOC_GC_MEM_NOC,
 448         .channels = 1,
 449         .buswidth = 8,
 450         .num_links = 1,
 451         .links = { SC8180X_SLAVE_LLCC }
 452 };
 453
 454 static struct qcom_icc_node mas_qnm_snoc_sf = {
 455         .name = "mas_qnm_snoc_sf",
 456         .id = SC8180X_MASTER_SNOC_SF_MEM_NOC,
 457         .channels = 1,
 458         .buswidth = 32,
 459         .num_links = 1,
 460         .links = { SC8180X_SLAVE_LLCC }
 461 };
 462
 463 static struct qcom_icc_node mas_qxm_ecc = {
 464         .name = "mas_qxm_ecc",
 465         .id = SC8180X_MASTER_ECC,
 466         .channels = 2,
 467         .buswidth = 32,
 468         .num_links = 1,
 469         .links = { SC8180X_SLAVE_LLCC }
 470 };
 471
 472 static struct qcom_icc_node mas_ipa_core_master = {
 473         .name = "mas_ipa_core_master",
 474         .id = SC8180X_MASTER_IPA_CORE,
 475         .channels = 1,
 476         .buswidth = 8,
 477         .num_links = 1,
 478         .links = { SC8180X_SLAVE_IPA_CORE }
 479 };
 480
 481 static struct qcom_icc_node mas_llcc_mc = {
 482         .name = "mas_llcc_mc",
 483         .id = SC8180X_MASTER_LLCC,
 484         .channels = 8,
 485         .buswidth = 4,
 486         .num_links = 1,
 487         .links = { SC8180X_SLAVE_EBI_CH0 }
 488 };
 489
 490 static struct qcom_icc_node mas_qhm_mnoc_cfg = {
 491         .name = "mas_qhm_mnoc_cfg",
 492         .id = SC8180X_MASTER_CNOC_MNOC_CFG,
 493         .channels = 1,
 494         .buswidth = 4,
 495         .num_links = 1,
 496         .links = { SC8180X_SLAVE_SERVICE_MNOC }
 497 };
 498
 499 static struct qcom_icc_node mas_qxm_camnoc_hf0 = {
 500         .name = "mas_qxm_camnoc_hf0",
 501         .id = SC8180X_MASTER_CAMNOC_HF0,
 502         .channels = 1,
 503         .buswidth = 32,
 504         .num_links = 1,
 505         .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC }
 506 };
 507
 508 static struct qcom_icc_node mas_qxm_camnoc_hf1 = {
 509         .name = "mas_qxm_camnoc_hf1",
 510         .id = SC8180X_MASTER_CAMNOC_HF1,
 511         .channels = 1,
 512         .buswidth = 32,
 513         .num_links = 1,
 514         .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC }
 515 };
 516
 517 static struct qcom_icc_node mas_qxm_camnoc_sf = {
 518         .name = "mas_qxm_camnoc_sf",
 519         .id = SC8180X_MASTER_CAMNOC_SF,
 520         .channels = 1,
 521         .buswidth = 32,
 522         .num_links = 1,
 523         .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC }
 524 };
 525
 526 static struct qcom_icc_node mas_qxm_mdp0 = {
 527         .name = "mas_qxm_mdp0",
 528         .id = SC8180X_MASTER_MDP_PORT0,
 529         .channels = 1,
 530         .buswidth = 32,
 531         .num_links = 1,
 532         .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC }
 533 };
 534
 535 static struct qcom_icc_node mas_qxm_mdp1 = {
 536         .name = "mas_qxm_mdp1",
 537         .id = SC8180X_MASTER_MDP_PORT1,
 538         .channels = 1,
 539         .buswidth = 32,
 540         .num_links = 1,
 541         .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC }
 542 };
 543
 544 static struct qcom_icc_node mas_qxm_rot = {
 545         .name = "mas_qxm_rot",
 546         .id = SC8180X_MASTER_ROTATOR,
 547         .channels = 1,
 548         .buswidth = 32,
 549         .num_links = 1,
 550         .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC }
 551 };
 552
 553 static struct qcom_icc_node mas_qxm_venus0 = {
 554         .name = "mas_qxm_venus0",
 555         .id = SC8180X_MASTER_VIDEO_P0,
 556         .channels = 1,
 557         .buswidth = 32,
 558         .num_links = 1,
 559         .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC }
 560 };
 561
 562 static struct qcom_icc_node mas_qxm_venus1 = {
 563         .name = "mas_qxm_venus1",
 564         .id = SC8180X_MASTER_VIDEO_P1,
 565         .channels = 1,
 566         .buswidth = 32,
 567         .num_links = 1,
 568         .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC }
 569 };
 570
 571 static struct qcom_icc_node mas_qxm_venus_arm9 = {
 572         .name = "mas_qxm_venus_arm9",
 573         .id = SC8180X_MASTER_VIDEO_PROC,
 574         .channels = 1,
 575         .buswidth = 8,
 576         .num_links = 1,
 577         .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC }
 578 };
 579
 580 static struct qcom_icc_node mas_qhm_snoc_cfg = {
 581         .name = "mas_qhm_snoc_cfg",
 582         .id = SC8180X_MASTER_SNOC_CFG,
 583         .channels = 1,
 584         .buswidth = 4,
 585         .num_links = 1,
 586         .links = { SC8180X_SLAVE_SERVICE_SNOC }
 587 };
 588
 589 static struct qcom_icc_node mas_qnm_aggre1_noc = {
 590         .name = "mas_qnm_aggre1_noc",
 591         .id = SC8180X_A1NOC_SNOC_MAS,
 592         .channels = 1,
 593         .buswidth = 32,
 594         .num_links = 6,
 595         .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF,
 596                    SC8180X_SLAVE_PIMEM,
 597                    SC8180X_SLAVE_OCIMEM,
 598                    SC8180X_SLAVE_APPSS,
 599                    SC8180X_SNOC_CNOC_SLV,
 600                    SC8180X_SLAVE_QDSS_STM }
 601 };
 602
 603 static struct qcom_icc_node mas_qnm_aggre2_noc = {
 604         .name = "mas_qnm_aggre2_noc",
 605         .id = SC8180X_A2NOC_SNOC_MAS,
 606         .channels = 1,
 607         .buswidth = 16,
 608         .num_links = 11,
 609         .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF,
 610                    SC8180X_SLAVE_PIMEM,
 611                    SC8180X_SLAVE_PCIE_3,
 612                    SC8180X_SLAVE_OCIMEM,
 613                    SC8180X_SLAVE_APPSS,
 614                    SC8180X_SLAVE_PCIE_2,
 615                    SC8180X_SNOC_CNOC_SLV,
 616                    SC8180X_SLAVE_PCIE_0,
 617                    SC8180X_SLAVE_PCIE_1,
 618                    SC8180X_SLAVE_TCU,
 619                    SC8180X_SLAVE_QDSS_STM }
 620 };
 621
 622 static struct qcom_icc_node mas_qnm_gemnoc = {
 623         .name = "mas_qnm_gemnoc",
 624         .id = SC8180X_MASTER_GEM_NOC_SNOC,
 625         .channels = 1,
 626         .buswidth = 8,
 627         .num_links = 6,
 628         .links = { SC8180X_SLAVE_PIMEM,
 629                    SC8180X_SLAVE_OCIMEM,
 630                    SC8180X_SLAVE_APPSS,
 631                    SC8180X_SNOC_CNOC_SLV,
 632                    SC8180X_SLAVE_TCU,
 633                    SC8180X_SLAVE_QDSS_STM }
 634 };
 635
 636 static struct qcom_icc_node mas_qxm_pimem = {
 637         .name = "mas_qxm_pimem",
 638         .id = SC8180X_MASTER_PIMEM,
 639         .channels = 1,
 640         .buswidth = 8,
 641         .num_links = 2,
 642         .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC,
 643                    SC8180X_SLAVE_OCIMEM }
 644 };
 645
 646 static struct qcom_icc_node mas_xm_gic = {
 647         .name = "mas_xm_gic",
 648         .id = SC8180X_MASTER_GIC,
 649         .channels = 1,
 650         .buswidth = 8,
 651         .num_links = 2,
 652         .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC,
 653                    SC8180X_SLAVE_OCIMEM }
 654 };
 655
 656 static struct qcom_icc_node mas_qup_core_0 = {
 657         .name = "mas_qup_core_0",
 658         .id = SC8180X_MASTER_QUP_CORE_0,
 659         .channels = 1,
 660         .buswidth = 4,
 661         .num_links = 1,
 662         .links = { SC8180X_SLAVE_QUP_CORE_0 }
 663 };
 664
 665 static struct qcom_icc_node mas_qup_core_1 = {
 666         .name = "mas_qup_core_1",
 667         .id = SC8180X_MASTER_QUP_CORE_1,
 668         .channels = 1,
 669         .buswidth = 4,
 670         .num_links = 1,
 671         .links = { SC8180X_SLAVE_QUP_CORE_1 }
 672 };
 673
 674 static struct qcom_icc_node mas_qup_core_2 = {
 675         .name = "mas_qup_core_2",
 676         .id = SC8180X_MASTER_QUP_CORE_2,
 677         .channels = 1,
 678         .buswidth = 4,
 679         .num_links = 1,
 680         .links = { SC8180X_SLAVE_QUP_CORE_2 }
 681 };
 682
 683 static struct qcom_icc_node slv_qns_a1noc_snoc = {
 684         .name = "slv_qns_a1noc_snoc",
 685         .id = SC8180X_A1NOC_SNOC_SLV,
 686         .channels = 1,
 687         .buswidth = 32,
 688         .num_links = 1,
 689         .links = { SC8180X_A1NOC_SNOC_MAS }
 690 };
 691
 692 static struct qcom_icc_node slv_srvc_aggre1_noc = {
 693         .name = "slv_srvc_aggre1_noc",
 694         .id = SC8180X_SLAVE_SERVICE_A1NOC,
 695         .channels = 1,
 696         .buswidth = 4
 697 };
 698
 699 static struct qcom_icc_node slv_qns_a2noc_snoc = {
 700         .name = "slv_qns_a2noc_snoc",
 701         .id = SC8180X_A2NOC_SNOC_SLV,
 702         .channels = 1,
 703         .buswidth = 16,
 704         .num_links = 1,
 705         .links = { SC8180X_A2NOC_SNOC_MAS }
 706 };
 707
 708 static struct qcom_icc_node slv_qns_pcie_mem_noc = {
 709         .name = "slv_qns_pcie_mem_noc",
 710         .id = SC8180X_SLAVE_ANOC_PCIE_GEM_NOC,
 711         .channels = 1,
 712         .buswidth = 32,
 713         .num_links = 1,
 714         .links = { SC8180X_MASTER_GEM_NOC_PCIE_SNOC }
 715 };
 716
 717 static struct qcom_icc_node slv_srvc_aggre2_noc = {
 718         .name = "slv_srvc_aggre2_noc",
 719         .id = SC8180X_SLAVE_SERVICE_A2NOC,
 720         .channels = 1,
 721         .buswidth = 4
 722 };
 723
 724 static struct qcom_icc_node slv_qns_camnoc_uncomp = {
 725         .name = "slv_qns_camnoc_uncomp",
 726         .id = SC8180X_SLAVE_CAMNOC_UNCOMP,
 727         .channels = 1,
 728         .buswidth = 32
 729 };
 730
 731 static struct qcom_icc_node slv_qns_cdsp_mem_noc = {
 732         .name = "slv_qns_cdsp_mem_noc",
 733         .id = SC8180X_SLAVE_CDSP_MEM_NOC,
 734         .channels = 2,
 735         .buswidth = 32,
 736         .num_links = 1,
 737         .links = { SC8180X_MASTER_COMPUTE_NOC }
 738 };
 739
 740 static struct qcom_icc_node slv_qhs_a1_noc_cfg = {
 741         .name = "slv_qhs_a1_noc_cfg",
 742         .id = SC8180X_SLAVE_A1NOC_CFG,
 743         .channels = 1,
 744         .buswidth = 4,
 745         .num_links = 1,
 746         .links = { SC8180X_MASTER_A1NOC_CFG }
 747 };
 748
 749 static struct qcom_icc_node slv_qhs_a2_noc_cfg = {
 750         .name = "slv_qhs_a2_noc_cfg",
 751         .id = SC8180X_SLAVE_A2NOC_CFG,
 752         .channels = 1,
 753         .buswidth = 4,
 754         .num_links = 1,
 755         .links = { SC8180X_MASTER_A2NOC_CFG }
 756 };
 757
 758 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center = {
 759         .name = "slv_qhs_ahb2phy_refgen_center",
 760         .id = SC8180X_SLAVE_AHB2PHY_CENTER,
 761         .channels = 1,
 762         .buswidth = 4
 763 };
 764
 765 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east = {
 766         .name = "slv_qhs_ahb2phy_refgen_east",
 767         .id = SC8180X_SLAVE_AHB2PHY_EAST,
 768         .channels = 1,
 769         .buswidth = 4
 770 };
 771
 772 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west = {
 773         .name = "slv_qhs_ahb2phy_refgen_west",
 774         .id = SC8180X_SLAVE_AHB2PHY_WEST,
 775         .channels = 1,
 776         .buswidth = 4
 777 };
 778
 779 static struct qcom_icc_node slv_qhs_ahb2phy_south = {
 780         .name = "slv_qhs_ahb2phy_south",
 781         .id = SC8180X_SLAVE_AHB2PHY_SOUTH,
 782         .channels = 1,
 783         .buswidth = 4
 784 };
 785
 786 static struct qcom_icc_node slv_qhs_aop = {
 787         .name = "slv_qhs_aop",
 788         .id = SC8180X_SLAVE_AOP,
 789         .channels = 1,
 790         .buswidth = 4
 791 };
 792
 793 static struct qcom_icc_node slv_qhs_aoss = {
 794         .name = "slv_qhs_aoss",
 795         .id = SC8180X_SLAVE_AOSS,
 796         .channels = 1,
 797         .buswidth = 4
 798 };
 799
 800 static struct qcom_icc_node slv_qhs_camera_cfg = {
 801         .name = "slv_qhs_camera_cfg",
 802         .id = SC8180X_SLAVE_CAMERA_CFG,
 803         .channels = 1,
 804         .buswidth = 4
 805 };
 806
 807 static struct qcom_icc_node slv_qhs_clk_ctl = {
 808         .name = "slv_qhs_clk_ctl",
 809         .id = SC8180X_SLAVE_CLK_CTL,
 810         .channels = 1,
 811         .buswidth = 4
 812 };
 813
 814 static struct qcom_icc_node slv_qhs_compute_dsp = {
 815         .name = "slv_qhs_compute_dsp",
 816         .id = SC8180X_SLAVE_CDSP_CFG,
 817         .channels = 1,
 818         .buswidth = 4
 819 };
 820
 821 static struct qcom_icc_node slv_qhs_cpr_cx = {
 822         .name = "slv_qhs_cpr_cx",
 823         .id = SC8180X_SLAVE_RBCPR_CX_CFG,
 824         .channels = 1,
 825         .buswidth = 4
 826 };
 827
 828 static struct qcom_icc_node slv_qhs_cpr_mmcx = {
 829         .name = "slv_qhs_cpr_mmcx",
 830         .id = SC8180X_SLAVE_RBCPR_MMCX_CFG,
 831         .channels = 1,
 832         .buswidth = 4
 833 };
 834
 835 static struct qcom_icc_node slv_qhs_cpr_mx = {
 836         .name = "slv_qhs_cpr_mx",
 837         .id = SC8180X_SLAVE_RBCPR_MX_CFG,
 838         .channels = 1,
 839         .buswidth = 4
 840 };
 841
 842 static struct qcom_icc_node slv_qhs_crypto0_cfg = {
 843         .name = "slv_qhs_crypto0_cfg",
 844         .id = SC8180X_SLAVE_CRYPTO_0_CFG,
 845         .channels = 1,
 846         .buswidth = 4
 847 };
 848
 849 static struct qcom_icc_node slv_qhs_ddrss_cfg = {
 850         .name = "slv_qhs_ddrss_cfg",
 851         .id = SC8180X_SLAVE_CNOC_DDRSS,
 852         .channels = 1,
 853         .buswidth = 4,
 854         .num_links = 1,
 855         .links = { SC8180X_MASTER_CNOC_DC_NOC }
 856 };
 857
 858 static struct qcom_icc_node slv_qhs_display_cfg = {
 859         .name = "slv_qhs_display_cfg",
 860         .id = SC8180X_SLAVE_DISPLAY_CFG,
 861         .channels = 1,
 862         .buswidth = 4
 863 };
 864
 865 static struct qcom_icc_node slv_qhs_emac_cfg = {
 866         .name = "slv_qhs_emac_cfg",
 867         .id = SC8180X_SLAVE_EMAC_CFG,
 868         .channels = 1,
 869         .buswidth = 4
 870 };
 871
 872 static struct qcom_icc_node slv_qhs_glm = {
 873         .name = "slv_qhs_glm",
 874         .id = SC8180X_SLAVE_GLM,
 875         .channels = 1,
 876         .buswidth = 4
 877 };
 878
 879 static struct qcom_icc_node slv_qhs_gpuss_cfg = {
 880         .name = "slv_qhs_gpuss_cfg",
 881         .id = SC8180X_SLAVE_GRAPHICS_3D_CFG,
 882         .channels = 1,
 883         .buswidth = 8
 884 };
 885
 886 static struct qcom_icc_node slv_qhs_imem_cfg = {
 887         .name = "slv_qhs_imem_cfg",
 888         .id = SC8180X_SLAVE_IMEM_CFG,
 889         .channels = 1,
 890         .buswidth = 4
 891 };
 892
 893 static struct qcom_icc_node slv_qhs_ipa = {
 894         .name = "slv_qhs_ipa",
 895         .id = SC8180X_SLAVE_IPA_CFG,
 896         .channels = 1,
 897         .buswidth = 4
 898 };
 899
 900 static struct qcom_icc_node slv_qhs_mnoc_cfg = {
 901         .name = "slv_qhs_mnoc_cfg",
 902         .id = SC8180X_SLAVE_CNOC_MNOC_CFG,
 903         .channels = 1,
 904         .buswidth = 4,
 905         .num_links = 1,
 906         .links = { SC8180X_MASTER_CNOC_MNOC_CFG }
 907 };
 908
 909 static struct qcom_icc_node slv_qhs_npu_cfg = {
 910         .name = "slv_qhs_npu_cfg",
 911         .id = SC8180X_SLAVE_NPU_CFG,
 912         .channels = 1,
 913         .buswidth = 4
 914 };
 915
 916 static struct qcom_icc_node slv_qhs_pcie0_cfg = {
 917         .name = "slv_qhs_pcie0_cfg",
 918         .id = SC8180X_SLAVE_PCIE_0_CFG,
 919         .channels = 1,
 920         .buswidth = 4
 921 };
 922
 923 static struct qcom_icc_node slv_qhs_pcie1_cfg = {
 924         .name = "slv_qhs_pcie1_cfg",
 925         .id = SC8180X_SLAVE_PCIE_1_CFG,
 926         .channels = 1,
 927         .buswidth = 4
 928 };
 929
 930 static struct qcom_icc_node slv_qhs_pcie2_cfg = {
 931         .name = "slv_qhs_pcie2_cfg",
 932         .id = SC8180X_SLAVE_PCIE_2_CFG,
 933         .channels = 1,
 934         .buswidth = 4
 935 };
 936
 937 static struct qcom_icc_node slv_qhs_pcie3_cfg = {
 938         .name = "slv_qhs_pcie3_cfg",
 939         .id = SC8180X_SLAVE_PCIE_3_CFG,
 940         .channels = 1,
 941         .buswidth = 4
 942 };
 943
 944 static struct qcom_icc_node slv_qhs_pdm = {
 945         .name = "slv_qhs_pdm",
 946         .id = SC8180X_SLAVE_PDM,
 947         .channels = 1,
 948         .buswidth = 4
 949 };
 950
 951 static struct qcom_icc_node slv_qhs_pimem_cfg = {
 952         .name = "slv_qhs_pimem_cfg",
 953         .id = SC8180X_SLAVE_PIMEM_CFG,
 954         .channels = 1,
 955         .buswidth = 4
 956 };
 957
 958 static struct qcom_icc_node slv_qhs_prng = {
 959         .name = "slv_qhs_prng",
 960         .id = SC8180X_SLAVE_PRNG,
 961         .channels = 1,
 962         .buswidth = 4
 963 };
 964
 965 static struct qcom_icc_node slv_qhs_qdss_cfg = {
 966         .name = "slv_qhs_qdss_cfg",
 967         .id = SC8180X_SLAVE_QDSS_CFG,
 968         .channels = 1,
 969         .buswidth = 4
 970 };
 971
 972 static struct qcom_icc_node slv_qhs_qspi_0 = {
 973         .name = "slv_qhs_qspi_0",
 974         .id = SC8180X_SLAVE_QSPI_0,
 975         .channels = 1,
 976         .buswidth = 4
 977 };
 978
 979 static struct qcom_icc_node slv_qhs_qspi_1 = {
 980         .name = "slv_qhs_qspi_1",
 981         .id = SC8180X_SLAVE_QSPI_1,
 982         .channels = 1,
 983         .buswidth = 4
 984 };
 985
 986 static struct qcom_icc_node slv_qhs_qupv3_east0 = {
 987         .name = "slv_qhs_qupv3_east0",
 988         .id = SC8180X_SLAVE_QUP_1,
 989         .channels = 1,
 990         .buswidth = 4
 991 };
 992
 993 static struct qcom_icc_node slv_qhs_qupv3_east1 = {
 994         .name = "slv_qhs_qupv3_east1",
 995         .id = SC8180X_SLAVE_QUP_2,
 996         .channels = 1,
 997         .buswidth = 4
 998 };
 999
1000 static struct qcom_icc_node slv_qhs_qupv3_west = {
1001         .name = "slv_qhs_qupv3_west",
1002         .id = SC8180X_SLAVE_QUP_0,
1003         .channels = 1,
1004         .buswidth = 4
1005 };
1006
1007 static struct qcom_icc_node slv_qhs_sdc2 = {
1008         .name = "slv_qhs_sdc2",
1009         .id = SC8180X_SLAVE_SDCC_2,
1010         .channels = 1,
1011         .buswidth = 4
1012 };
1013
1014 static struct qcom_icc_node slv_qhs_sdc4 = {
1015         .name = "slv_qhs_sdc4",
1016         .id = SC8180X_SLAVE_SDCC_4,
1017         .channels = 1,
1018         .buswidth = 4
1019 };
1020
1021 static struct qcom_icc_node slv_qhs_security = {
1022         .name = "slv_qhs_security",
1023         .id = SC8180X_SLAVE_SECURITY,
1024         .channels = 1,
1025         .buswidth = 4
1026 };
1027
1028 static struct qcom_icc_node slv_qhs_snoc_cfg = {
1029         .name = "slv_qhs_snoc_cfg",
1030         .id = SC8180X_SLAVE_SNOC_CFG,
1031         .channels = 1,
1032         .buswidth = 4,
1033         .num_links = 1,
1034         .links = { SC8180X_MASTER_SNOC_CFG }
1035 };
1036
1037 static struct qcom_icc_node slv_qhs_spss_cfg = {
1038         .name = "slv_qhs_spss_cfg",
1039         .id = SC8180X_SLAVE_SPSS_CFG,
1040         .channels = 1,
1041         .buswidth = 4
1042 };
1043
1044 static struct qcom_icc_node slv_qhs_tcsr = {
1045         .name = "slv_qhs_tcsr",
1046         .id = SC8180X_SLAVE_TCSR,
1047         .channels = 1,
1048         .buswidth = 4
1049 };
1050
1051 static struct qcom_icc_node slv_qhs_tlmm_east = {
1052         .name = "slv_qhs_tlmm_east",
1053         .id = SC8180X_SLAVE_TLMM_EAST,
1054         .channels = 1,
1055         .buswidth = 4
1056 };
1057
1058 static struct qcom_icc_node slv_qhs_tlmm_south = {
1059         .name = "slv_qhs_tlmm_south",
1060         .id = SC8180X_SLAVE_TLMM_SOUTH,
1061         .channels = 1,
1062         .buswidth = 4
1063 };
1064
1065 static struct qcom_icc_node slv_qhs_tlmm_west = {
1066         .name = "slv_qhs_tlmm_west",
1067         .id = SC8180X_SLAVE_TLMM_WEST,
1068         .channels = 1,
1069         .buswidth = 4
1070 };
1071
1072 static struct qcom_icc_node slv_qhs_tsif = {
1073         .name = "slv_qhs_tsif",
1074         .id = SC8180X_SLAVE_TSIF,
1075         .channels = 1,
1076         .buswidth = 4
1077 };
1078
1079 static struct qcom_icc_node slv_qhs_ufs_card_cfg = {
1080         .name = "slv_qhs_ufs_card_cfg",
1081         .id = SC8180X_SLAVE_UFS_CARD_CFG,
1082         .channels = 1,
1083         .buswidth = 4
1084 };
1085
1086 static struct qcom_icc_node slv_qhs_ufs_mem0_cfg = {
1087         .name = "slv_qhs_ufs_mem0_cfg",
1088         .id = SC8180X_SLAVE_UFS_MEM_0_CFG,
1089         .channels = 1,
1090         .buswidth = 4
1091 };
1092
1093 static struct qcom_icc_node slv_qhs_ufs_mem1_cfg = {
1094         .name = "slv_qhs_ufs_mem1_cfg",
1095         .id = SC8180X_SLAVE_UFS_MEM_1_CFG,
1096         .channels = 1,
1097         .buswidth = 4
1098 };
1099
1100 static struct qcom_icc_node slv_qhs_usb3_0 = {
1101         .name = "slv_qhs_usb3_0",
1102         .id = SC8180X_SLAVE_USB3,
1103         .channels = 1,
1104         .buswidth = 4
1105 };
1106
1107 static struct qcom_icc_node slv_qhs_usb3_1 = {
1108         .name = "slv_qhs_usb3_1",
1109         .id = SC8180X_SLAVE_USB3_1,
1110         .channels = 1,
1111         .buswidth = 4
1112 };
1113
1114 static struct qcom_icc_node slv_qhs_usb3_2 = {
1115         .name = "slv_qhs_usb3_2",
1116         .id = SC8180X_SLAVE_USB3_2,
1117         .channels = 1,
1118         .buswidth = 4
1119 };
1120
1121 static struct qcom_icc_node slv_qhs_venus_cfg = {
1122         .name = "slv_qhs_venus_cfg",
1123         .id = SC8180X_SLAVE_VENUS_CFG,
1124         .channels = 1,
1125         .buswidth = 4
1126 };
1127
1128 static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg = {
1129         .name = "slv_qhs_vsense_ctrl_cfg",
1130         .id = SC8180X_SLAVE_VSENSE_CTRL_CFG,
1131         .channels = 1,
1132         .buswidth = 4
1133 };
1134
1135 static struct qcom_icc_node slv_srvc_cnoc = {
1136         .name = "slv_srvc_cnoc",
1137         .id = SC8180X_SLAVE_SERVICE_CNOC,
1138         .channels = 1,
1139         .buswidth = 4
1140 };
1141
1142 static struct qcom_icc_node slv_qhs_gemnoc = {
1143         .name = "slv_qhs_gemnoc",
1144         .id = SC8180X_SLAVE_GEM_NOC_CFG,
1145         .channels = 1,
1146         .buswidth = 4,
1147         .num_links = 1,
1148         .links = { SC8180X_MASTER_GEM_NOC_CFG }
1149 };
1150
1151 static struct qcom_icc_node slv_qhs_llcc = {
1152         .name = "slv_qhs_llcc",
1153         .id = SC8180X_SLAVE_LLCC_CFG,
1154         .channels = 1,
1155         .buswidth = 4
1156 };
1157
1158 static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg = {
1159         .name = "slv_qhs_mdsp_ms_mpu_cfg",
1160         .id = SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG,
1161         .channels = 1,
1162         .buswidth = 4
1163 };
1164
1165 static struct qcom_icc_node slv_qns_ecc = {
1166         .name = "slv_qns_ecc",
1167         .id = SC8180X_SLAVE_ECC,
1168         .channels = 1,
1169         .buswidth = 32
1170 };
1171
1172 static struct qcom_icc_node slv_qns_gem_noc_snoc = {
1173         .name = "slv_qns_gem_noc_snoc",
1174         .id = SC8180X_SLAVE_GEM_NOC_SNOC,
1175         .channels = 1,
1176         .buswidth = 8,
1177         .num_links = 1,
1178         .links = { SC8180X_MASTER_GEM_NOC_SNOC }
1179 };
1180
1181 static struct qcom_icc_node slv_qns_llcc = {
1182         .name = "slv_qns_llcc",
1183         .id = SC8180X_SLAVE_LLCC,
1184         .channels = 8,
1185         .buswidth = 16,
1186         .num_links = 1,
1187         .links = { SC8180X_MASTER_LLCC }
1188 };
1189
1190 static struct qcom_icc_node slv_srvc_gemnoc = {
1191         .name = "slv_srvc_gemnoc",
1192         .id = SC8180X_SLAVE_SERVICE_GEM_NOC,
1193         .channels = 1,
1194         .buswidth = 4
1195 };
1196
1197 static struct qcom_icc_node slv_srvc_gemnoc1 = {
1198         .name = "slv_srvc_gemnoc1",
1199         .id = SC8180X_SLAVE_SERVICE_GEM_NOC_1,
1200         .channels = 1,
1201         .buswidth = 4
1202 };
1203
1204 static struct qcom_icc_node slv_ipa_core_slave = {
1205         .name = "slv_ipa_core_slave",
1206         .id = SC8180X_SLAVE_IPA_CORE,
1207         .channels = 1,
1208         .buswidth = 8
1209 };
1210
1211 static struct qcom_icc_node slv_ebi = {
1212         .name = "slv_ebi",
1213         .id = SC8180X_SLAVE_EBI_CH0,
1214         .channels = 8,
1215         .buswidth = 4
1216 };
1217
1218 static struct qcom_icc_node slv_qns2_mem_noc = {
1219         .name = "slv_qns2_mem_noc",
1220         .id = SC8180X_SLAVE_MNOC_SF_MEM_NOC,
1221         .channels = 1,
1222         .buswidth = 32,
1223         .num_links = 1,
1224         .links = { SC8180X_MASTER_MNOC_SF_MEM_NOC }
1225 };
1226
1227 static struct qcom_icc_node slv_qns_mem_noc_hf = {
1228         .name = "slv_qns_mem_noc_hf",
1229         .id = SC8180X_SLAVE_MNOC_HF_MEM_NOC,
1230         .channels = 2,
1231         .buswidth = 32,
1232         .num_links = 1,
1233         .links = { SC8180X_MASTER_MNOC_HF_MEM_NOC }
1234 };
1235
1236 static struct qcom_icc_node slv_srvc_mnoc = {
1237         .name = "slv_srvc_mnoc",
1238         .id = SC8180X_SLAVE_SERVICE_MNOC,
1239         .channels = 1,
1240         .buswidth = 4
1241 };
1242
1243 static struct qcom_icc_node slv_qhs_apss = {
1244         .name = "slv_qhs_apss",
1245         .id = SC8180X_SLAVE_APPSS,
1246         .channels = 1,
1247         .buswidth = 8
1248 };
1249
1250 static struct qcom_icc_node slv_qns_cnoc = {
1251         .name = "slv_qns_cnoc",
1252         .id = SC8180X_SNOC_CNOC_SLV,
1253         .channels = 1,
1254         .buswidth = 8,
1255         .num_links = 1,
1256         .links = { SC8180X_SNOC_CNOC_MAS }
1257 };
1258
1259 static struct qcom_icc_node slv_qns_gemnoc_gc = {
1260         .name = "slv_qns_gemnoc_gc",
1261         .id = SC8180X_SLAVE_SNOC_GEM_NOC_GC,
1262         .channels = 1,
1263         .buswidth = 8,
1264         .num_links = 1,
1265         .links = { SC8180X_MASTER_SNOC_GC_MEM_NOC }
1266 };
1267
1268 static struct qcom_icc_node slv_qns_gemnoc_sf = {
1269         .name = "slv_qns_gemnoc_sf",
1270         .id = SC8180X_SLAVE_SNOC_GEM_NOC_SF,
1271         .channels = 1,
1272         .buswidth = 32,
1273         .num_links = 1,
1274         .links = { SC8180X_MASTER_SNOC_SF_MEM_NOC }
1275 };
1276
1277 static struct qcom_icc_node slv_qxs_imem = {
1278         .name = "slv_qxs_imem",
1279         .id = SC8180X_SLAVE_OCIMEM,
1280         .channels = 1,
1281         .buswidth = 8
1282 };
1283
1284 static struct qcom_icc_node slv_qxs_pimem = {
1285         .name = "slv_qxs_pimem",
1286         .id = SC8180X_SLAVE_PIMEM,
1287         .channels = 1,
1288         .buswidth = 8
1289 };
1290
1291 static struct qcom_icc_node slv_srvc_snoc = {
1292         .name = "slv_srvc_snoc",
1293         .id = SC8180X_SLAVE_SERVICE_SNOC,
1294         .channels = 1,
1295         .buswidth = 4
1296 };
1297
1298 static struct qcom_icc_node slv_xs_pcie_0 = {
1299         .name = "slv_xs_pcie_0",
1300         .id = SC8180X_SLAVE_PCIE_0,
1301         .channels = 1,
1302         .buswidth = 8
1303 };
1304
1305 static struct qcom_icc_node slv_xs_pcie_1 = {
1306         .name = "slv_xs_pcie_1",
1307         .id = SC8180X_SLAVE_PCIE_1,
1308         .channels = 1,
1309         .buswidth = 8
1310 };
1311
1312 static struct qcom_icc_node slv_xs_pcie_2 = {
1313         .name = "slv_xs_pcie_2",
1314         .id = SC8180X_SLAVE_PCIE_2,
1315         .channels = 1,
1316         .buswidth = 8
1317 };
1318
1319 static struct qcom_icc_node slv_xs_pcie_3 = {
1320         .name = "slv_xs_pcie_3",
1321         .id = SC8180X_SLAVE_PCIE_3,
1322         .channels = 1,
1323         .buswidth = 8
1324 };
1325
1326 static struct qcom_icc_node slv_xs_qdss_stm = {
1327         .name = "slv_xs_qdss_stm",
1328         .id = SC8180X_SLAVE_QDSS_STM,
1329         .channels = 1,
1330         .buswidth = 4
1331 };
1332
1333 static struct qcom_icc_node slv_xs_sys_tcu_cfg = {
1334         .name = "slv_xs_sys_tcu_cfg",
1335         .id = SC8180X_SLAVE_TCU,
1336         .channels = 1,
1337         .buswidth = 8
1338 };
1339
1340 static struct qcom_icc_node slv_qup_core_0 = {
1341         .name = "slv_qup_core_0",
1342         .id = SC8180X_SLAVE_QUP_CORE_0,
1343         .channels = 1,
1344         .buswidth = 4
1345 };
1346
1347 static struct qcom_icc_node slv_qup_core_1 = {
1348         .name = "slv_qup_core_1",
1349         .id = SC8180X_SLAVE_QUP_CORE_1,
1350         .channels = 1,
1351         .buswidth = 4
1352 };
1353
1354 static struct qcom_icc_node slv_qup_core_2 = {
1355         .name = "slv_qup_core_2",
1356         .id = SC8180X_SLAVE_QUP_CORE_2,
1357         .channels = 1,
1358         .buswidth = 4
1359 };
1360
1361 static struct qcom_icc_bcm bcm_acv = {
1362         .name = "ACV",
1363         .num_nodes = 1,
1364         .nodes = { &slv_ebi }
1365 };
1366
1367 static struct qcom_icc_bcm bcm_mc0 = {
1368         .name = "MC0",
1369         .keepalive = true,
1370         .num_nodes = 1,
1371         .nodes = { &slv_ebi }
1372 };
1373
1374 static struct qcom_icc_bcm bcm_sh0 = {
1375         .name = "SH0",
1376         .keepalive = true,
1377         .num_nodes = 1,
1378         .nodes = { &slv_qns_llcc }
1379 };
1380
1381 static struct qcom_icc_bcm bcm_mm0 = {
1382         .name = "MM0",
1383         .num_nodes = 1,
1384         .nodes = { &slv_qns_mem_noc_hf }
1385 };
1386
1387 static struct qcom_icc_bcm bcm_co0 = {
1388         .name = "CO0",
1389         .num_nodes = 1,
1390         .nodes = { &slv_qns_cdsp_mem_noc }
1391 };
1392
1393 static struct qcom_icc_bcm bcm_ce0 = {
1394         .name = "CE0",
1395         .num_nodes = 1,
1396         .nodes = { &mas_qxm_crypto }
1397 };
1398
1399 static struct qcom_icc_bcm bcm_cn0 = {
1400         .name = "CN0",
1401         .keepalive = true,
1402         .num_nodes = 57,
1403         .nodes = { &mas_qnm_snoc,
1404                    &slv_qhs_a1_noc_cfg,
1405                    &slv_qhs_a2_noc_cfg,
1406                    &slv_qhs_ahb2phy_refgen_center,
1407                    &slv_qhs_ahb2phy_refgen_east,
1408                    &slv_qhs_ahb2phy_refgen_west,
1409                    &slv_qhs_ahb2phy_south,
1410                    &slv_qhs_aop,
1411                    &slv_qhs_aoss,
1412                    &slv_qhs_camera_cfg,
1413                    &slv_qhs_clk_ctl,
1414                    &slv_qhs_compute_dsp,
1415                    &slv_qhs_cpr_cx,
1416                    &slv_qhs_cpr_mmcx,
1417                    &slv_qhs_cpr_mx,
1418                    &slv_qhs_crypto0_cfg,
1419                    &slv_qhs_ddrss_cfg,
1420                    &slv_qhs_display_cfg,
1421                    &slv_qhs_emac_cfg,
1422                    &slv_qhs_glm,
1423                    &slv_qhs_gpuss_cfg,
1424                    &slv_qhs_imem_cfg,
1425                    &slv_qhs_ipa,
1426                    &slv_qhs_mnoc_cfg,
1427                    &slv_qhs_npu_cfg,
1428                    &slv_qhs_pcie0_cfg,
1429                    &slv_qhs_pcie1_cfg,
1430                    &slv_qhs_pcie2_cfg,
1431                    &slv_qhs_pcie3_cfg,
1432                    &slv_qhs_pdm,
1433                    &slv_qhs_pimem_cfg,
1434                    &slv_qhs_prng,
1435                    &slv_qhs_qdss_cfg,
1436                    &slv_qhs_qspi_0,
1437                    &slv_qhs_qspi_1,
1438                    &slv_qhs_qupv3_east0,
1439                    &slv_qhs_qupv3_east1,
1440                    &slv_qhs_qupv3_west,
1441                    &slv_qhs_sdc2,
1442                    &slv_qhs_sdc4,
1443                    &slv_qhs_security,
1444                    &slv_qhs_snoc_cfg,
1445                    &slv_qhs_spss_cfg,
1446                    &slv_qhs_tcsr,
1447                    &slv_qhs_tlmm_east,
1448                    &slv_qhs_tlmm_south,
1449                    &slv_qhs_tlmm_west,
1450                    &slv_qhs_tsif,
1451                    &slv_qhs_ufs_card_cfg,
1452                    &slv_qhs_ufs_mem0_cfg,
1453                    &slv_qhs_ufs_mem1_cfg,
1454                    &slv_qhs_usb3_0,
1455                    &slv_qhs_usb3_1,
1456                    &slv_qhs_usb3_2,
1457                    &slv_qhs_venus_cfg,
1458                    &slv_qhs_vsense_ctrl_cfg,
1459                    &slv_srvc_cnoc }
1460 };
1461
1462 static struct qcom_icc_bcm bcm_mm1 = {
1463         .name = "MM1",
1464         .num_nodes = 7,
1465         .nodes = { &mas_qxm_camnoc_hf0_uncomp,
1466                    &mas_qxm_camnoc_hf1_uncomp,
1467                    &mas_qxm_camnoc_sf_uncomp,
1468                    &mas_qxm_camnoc_hf0,
1469                    &mas_qxm_camnoc_hf1,
1470                    &mas_qxm_mdp0,
1471                    &mas_qxm_mdp1 }
1472 };
1473
1474 static struct qcom_icc_bcm bcm_qup0 = {
1475         .name = "QUP0",
1476         .num_nodes = 3,
1477         .nodes = { &mas_qup_core_0,
1478                    &mas_qup_core_1,
1479                    &mas_qup_core_2 }
1480 };
1481
1482 static struct qcom_icc_bcm bcm_sh2 = {
1483         .name = "SH2",
1484         .num_nodes = 1,
1485         .nodes = { &slv_qns_gem_noc_snoc }
1486 };
1487
1488 static struct qcom_icc_bcm bcm_mm2 = {
1489         .name = "MM2",
1490         .num_nodes = 6,
1491         .nodes = { &mas_qxm_camnoc_sf,
1492                    &mas_qxm_rot,
1493                    &mas_qxm_venus0,
1494                    &mas_qxm_venus1,
1495                    &mas_qxm_venus_arm9,
1496                    &slv_qns2_mem_noc }
1497 };
1498
1499 static struct qcom_icc_bcm bcm_sh3 = {
1500         .name = "SH3",
1501         .keepalive = true,
1502         .num_nodes = 1,
1503         .nodes = { &mas_acm_apps }
1504 };
1505
1506 static struct qcom_icc_bcm bcm_sn0 = {
1507         .name = "SN0",
1508         .nodes = { &slv_qns_gemnoc_sf }
1509 };
1510
1511 static struct qcom_icc_bcm bcm_sn1 = {
1512         .name = "SN1",
1513         .nodes = { &slv_qxs_imem }
1514 };
1515
1516 static struct qcom_icc_bcm bcm_sn2 = {
1517         .name = "SN2",
1518         .keepalive = true,
1519         .nodes = { &slv_qns_gemnoc_gc }
1520 };
1521
1522 static struct qcom_icc_bcm bcm_co2 = {
1523         .name = "CO2",
1524         .nodes = { &mas_qnm_npu }
1525 };
1526
1527 static struct qcom_icc_bcm bcm_ip0 = {
1528         .name = "IP0",
1529         .nodes = { &slv_ipa_core_slave }
1530 };
1531
1532 static struct qcom_icc_bcm bcm_sn3 = {
1533         .name = "SN3",
1534         .keepalive = true,
1535         .nodes = { &slv_srvc_aggre1_noc,
1536                   &slv_qns_cnoc }
1537 };
1538
1539 static struct qcom_icc_bcm bcm_sn4 = {
1540         .name = "SN4",
1541         .nodes = { &slv_qxs_pimem }
1542 };
1543
1544 static struct qcom_icc_bcm bcm_sn8 = {
1545         .name = "SN8",
1546         .num_nodes = 4,
1547         .nodes = { &slv_xs_pcie_0,
1548                    &slv_xs_pcie_1,
1549                    &slv_xs_pcie_2,
1550                    &slv_xs_pcie_3 }
1551 };
1552
1553 static struct qcom_icc_bcm bcm_sn9 = {
1554         .name = "SN9",
1555         .num_nodes = 1,
1556         .nodes = { &mas_qnm_aggre1_noc }
1557 };
1558
1559 static struct qcom_icc_bcm bcm_sn11 = {
1560         .name = "SN11",
1561         .num_nodes = 1,
1562         .nodes = { &mas_qnm_aggre2_noc }
1563 };
1564
1565 static struct qcom_icc_bcm bcm_sn14 = {
1566         .name = "SN14",
1567         .num_nodes = 1,
1568         .nodes = { &slv_qns_pcie_mem_noc }
1569 };
1570
1571 static struct qcom_icc_bcm bcm_sn15 = {
1572         .name = "SN15",
1573         .keepalive = true,
1574         .num_nodes = 1,
1575         .nodes = { &mas_qnm_gemnoc }
1576 };
1577
1578 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1579         &bcm_sn3,
1580         &bcm_ce0,
1581 };
1582
1583 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1584         &bcm_sn14,
1585         &bcm_ce0,
1586 };
1587
1588 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
1589         &bcm_mm1,
1590 };
1591
1592 static struct qcom_icc_bcm * const compute_noc_bcms[] = {
1593         &bcm_co0,
1594         &bcm_co2,
1595 };
1596
1597 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1598         &bcm_cn0,
1599 };
1600
1601 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1602         &bcm_sh0,
1603         &bcm_sh2,
1604         &bcm_sh3,
1605 };
1606
1607 static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
1608         &bcm_ip0,
1609 };
1610
1611 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1612         &bcm_mc0,
1613         &bcm_acv,
1614 };
1615
1616 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1617         &bcm_mm0,
1618         &bcm_mm1,
1619         &bcm_mm2,
1620 };
1621
1622 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1623         &bcm_sn0,
1624         &bcm_sn1,
1625         &bcm_sn2,
1626         &bcm_sn3,
1627         &bcm_sn4,
1628         &bcm_sn8,
1629         &bcm_sn9,
1630         &bcm_sn11,
1631         &bcm_sn15,
1632 };
1633
1634 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1635         [MASTER_A1NOC_CFG] = &mas_qhm_a1noc_cfg,
1636         [MASTER_UFS_CARD] = &mas_xm_ufs_card,
1637         [MASTER_UFS_GEN4] = &mas_xm_ufs_g4,
1638         [MASTER_UFS_MEM] = &mas_xm_ufs_mem,
1639         [MASTER_USB3] = &mas_xm_usb3_0,
1640         [MASTER_USB3_1] = &mas_xm_usb3_1,
1641         [MASTER_USB3_2] = &mas_xm_usb3_2,
1642         [A1NOC_SNOC_SLV] = &slv_qns_a1noc_snoc,
1643         [SLAVE_SERVICE_A1NOC] = &slv_srvc_aggre1_noc,
1644 };
1645
1646 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1647         [MASTER_A2NOC_CFG] = &mas_qhm_a2noc_cfg,
1648         [MASTER_QDSS_BAM] = &mas_qhm_qdss_bam,
1649         [MASTER_QSPI_0] = &mas_qhm_qspi,
1650         [MASTER_QSPI_1] = &mas_qhm_qspi1,
1651         [MASTER_QUP_0] = &mas_qhm_qup0,
1652         [MASTER_QUP_1] = &mas_qhm_qup1,
1653         [MASTER_QUP_2] = &mas_qhm_qup2,
1654         [MASTER_SENSORS_AHB] = &mas_qhm_sensorss_ahb,
1655         [MASTER_CRYPTO_CORE_0] = &mas_qxm_crypto,
1656         [MASTER_IPA] = &mas_qxm_ipa,
1657         [MASTER_EMAC] = &mas_xm_emac,
1658         [MASTER_PCIE] = &mas_xm_pcie3_0,
1659         [MASTER_PCIE_1] = &mas_xm_pcie3_1,
1660         [MASTER_PCIE_2] = &mas_xm_pcie3_2,
1661         [MASTER_PCIE_3] = &mas_xm_pcie3_3,
1662         [MASTER_QDSS_ETR] = &mas_xm_qdss_etr,
1663         [MASTER_SDCC_2] = &mas_xm_sdc2,
1664         [MASTER_SDCC_4] = &mas_xm_sdc4,
1665         [A2NOC_SNOC_SLV] = &slv_qns_a2noc_snoc,
1666         [SLAVE_ANOC_PCIE_GEM_NOC] = &slv_qns_pcie_mem_noc,
1667         [SLAVE_SERVICE_A2NOC] = &slv_srvc_aggre2_noc,
1668 };
1669
1670 static struct qcom_icc_node * const camnoc_virt_nodes[] = {
1671         [MASTER_CAMNOC_HF0_UNCOMP] = &mas_qxm_camnoc_hf0_uncomp,
1672         [MASTER_CAMNOC_HF1_UNCOMP] = &mas_qxm_camnoc_hf1_uncomp,
1673         [MASTER_CAMNOC_SF_UNCOMP] = &mas_qxm_camnoc_sf_uncomp,
1674         [SLAVE_CAMNOC_UNCOMP] = &slv_qns_camnoc_uncomp,
1675 };
1676
1677 static struct qcom_icc_node * const compute_noc_nodes[] = {
1678         [MASTER_NPU] = &mas_qnm_npu,
1679         [SLAVE_CDSP_MEM_NOC] = &slv_qns_cdsp_mem_noc,
1680 };
1681
1682 static struct qcom_icc_node * const config_noc_nodes[] = {
1683         [SNOC_CNOC_MAS] = &mas_qnm_snoc,
1684         [SLAVE_A1NOC_CFG] = &slv_qhs_a1_noc_cfg,
1685         [SLAVE_A2NOC_CFG] = &slv_qhs_a2_noc_cfg,
1686         [SLAVE_AHB2PHY_CENTER] = &slv_qhs_ahb2phy_refgen_center,
1687         [SLAVE_AHB2PHY_EAST] = &slv_qhs_ahb2phy_refgen_east,
1688         [SLAVE_AHB2PHY_WEST] = &slv_qhs_ahb2phy_refgen_west,
1689         [SLAVE_AHB2PHY_SOUTH] = &slv_qhs_ahb2phy_south,
1690         [SLAVE_AOP] = &slv_qhs_aop,
1691         [SLAVE_AOSS] = &slv_qhs_aoss,
1692         [SLAVE_CAMERA_CFG] = &slv_qhs_camera_cfg,
1693         [SLAVE_CLK_CTL] = &slv_qhs_clk_ctl,
1694         [SLAVE_CDSP_CFG] = &slv_qhs_compute_dsp,
1695         [SLAVE_RBCPR_CX_CFG] = &slv_qhs_cpr_cx,
1696         [SLAVE_RBCPR_MMCX_CFG] = &slv_qhs_cpr_mmcx,
1697         [SLAVE_RBCPR_MX_CFG] = &slv_qhs_cpr_mx,
1698         [SLAVE_CRYPTO_0_CFG] = &slv_qhs_crypto0_cfg,
1699         [SLAVE_CNOC_DDRSS] = &slv_qhs_ddrss_cfg,
1700         [SLAVE_DISPLAY_CFG] = &slv_qhs_display_cfg,
1701         [SLAVE_EMAC_CFG] = &slv_qhs_emac_cfg,
1702         [SLAVE_GLM] = &slv_qhs_glm,
1703         [SLAVE_GRAPHICS_3D_CFG] = &slv_qhs_gpuss_cfg,
1704         [SLAVE_IMEM_CFG] = &slv_qhs_imem_cfg,
1705         [SLAVE_IPA_CFG] = &slv_qhs_ipa,
1706         [SLAVE_CNOC_MNOC_CFG] = &slv_qhs_mnoc_cfg,
1707         [SLAVE_NPU_CFG] = &slv_qhs_npu_cfg,
1708         [SLAVE_PCIE_0_CFG] = &slv_qhs_pcie0_cfg,
1709         [SLAVE_PCIE_1_CFG] = &slv_qhs_pcie1_cfg,
1710         [SLAVE_PCIE_2_CFG] = &slv_qhs_pcie2_cfg,
1711         [SLAVE_PCIE_3_CFG] = &slv_qhs_pcie3_cfg,
1712         [SLAVE_PDM] = &slv_qhs_pdm,
1713         [SLAVE_PIMEM_CFG] = &slv_qhs_pimem_cfg,
1714         [SLAVE_PRNG] = &slv_qhs_prng,
1715         [SLAVE_QDSS_CFG] = &slv_qhs_qdss_cfg,
1716         [SLAVE_QSPI_0] = &slv_qhs_qspi_0,
1717         [SLAVE_QSPI_1] = &slv_qhs_qspi_1,
1718         [SLAVE_QUP_1] = &slv_qhs_qupv3_east0,
1719         [SLAVE_QUP_2] = &slv_qhs_qupv3_east1,
1720         [SLAVE_QUP_0] = &slv_qhs_qupv3_west,
1721         [SLAVE_SDCC_2] = &slv_qhs_sdc2,
1722         [SLAVE_SDCC_4] = &slv_qhs_sdc4,
1723         [SLAVE_SECURITY] = &slv_qhs_security,
1724         [SLAVE_SNOC_CFG] = &slv_qhs_snoc_cfg,
1725         [SLAVE_SPSS_CFG] = &slv_qhs_spss_cfg,
1726         [SLAVE_TCSR] = &slv_qhs_tcsr,
1727         [SLAVE_TLMM_EAST] = &slv_qhs_tlmm_east,
1728         [SLAVE_TLMM_SOUTH] = &slv_qhs_tlmm_south,
1729         [SLAVE_TLMM_WEST] = &slv_qhs_tlmm_west,
1730         [SLAVE_TSIF] = &slv_qhs_tsif,
1731         [SLAVE_UFS_CARD_CFG] = &slv_qhs_ufs_card_cfg,
1732         [SLAVE_UFS_MEM_0_CFG] = &slv_qhs_ufs_mem0_cfg,
1733         [SLAVE_UFS_MEM_1_CFG] = &slv_qhs_ufs_mem1_cfg,
1734         [SLAVE_USB3] = &slv_qhs_usb3_0,
1735         [SLAVE_USB3_1] = &slv_qhs_usb3_1,
1736         [SLAVE_USB3_2] = &slv_qhs_usb3_2,
1737         [SLAVE_VENUS_CFG] = &slv_qhs_venus_cfg,
1738         [SLAVE_VSENSE_CTRL_CFG] = &slv_qhs_vsense_ctrl_cfg,
1739         [SLAVE_SERVICE_CNOC] = &slv_srvc_cnoc,
1740 };
1741
1742 static struct qcom_icc_node * const dc_noc_nodes[] = {
1743         [MASTER_CNOC_DC_NOC] = &mas_qhm_cnoc_dc_noc,
1744         [SLAVE_GEM_NOC_CFG] = &slv_qhs_gemnoc,
1745         [SLAVE_LLCC_CFG] = &slv_qhs_llcc,
1746 };
1747
1748 static struct qcom_icc_node * const gem_noc_nodes[] = {
1749         [MASTER_AMPSS_M0] = &mas_acm_apps,
1750         [MASTER_GPU_TCU] = &mas_acm_gpu_tcu,
1751         [MASTER_SYS_TCU] = &mas_acm_sys_tcu,
1752         [MASTER_GEM_NOC_CFG] = &mas_qhm_gemnoc_cfg,
1753         [MASTER_COMPUTE_NOC] = &mas_qnm_cmpnoc,
1754         [MASTER_GRAPHICS_3D] = &mas_qnm_gpu,
1755         [MASTER_MNOC_HF_MEM_NOC] = &mas_qnm_mnoc_hf,
1756         [MASTER_MNOC_SF_MEM_NOC] = &mas_qnm_mnoc_sf,
1757         [MASTER_GEM_NOC_PCIE_SNOC] = &mas_qnm_pcie,
1758         [MASTER_SNOC_GC_MEM_NOC] = &mas_qnm_snoc_gc,
1759         [MASTER_SNOC_SF_MEM_NOC] = &mas_qnm_snoc_sf,
1760         [MASTER_ECC] = &mas_qxm_ecc,
1761         [SLAVE_MSS_PROC_MS_MPU_CFG] = &slv_qhs_mdsp_ms_mpu_cfg,
1762         [SLAVE_ECC] = &slv_qns_ecc,
1763         [SLAVE_GEM_NOC_SNOC] = &slv_qns_gem_noc_snoc,
1764         [SLAVE_LLCC] = &slv_qns_llcc,
1765         [SLAVE_SERVICE_GEM_NOC] = &slv_srvc_gemnoc,
1766         [SLAVE_SERVICE_GEM_NOC_1] = &slv_srvc_gemnoc1,
1767 };
1768
1769 static struct qcom_icc_node * const ipa_virt_nodes[] = {
1770         [MASTER_IPA_CORE] = &mas_ipa_core_master,
1771         [SLAVE_IPA_CORE] = &slv_ipa_core_slave,
1772 };
1773
1774 static struct qcom_icc_node * const mc_virt_nodes[] = {
1775         [MASTER_LLCC] = &mas_llcc_mc,
1776         [SLAVE_EBI_CH0] = &slv_ebi,
1777 };
1778
1779 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1780         [MASTER_CNOC_MNOC_CFG] = &mas_qhm_mnoc_cfg,
1781         [MASTER_CAMNOC_HF0] = &mas_qxm_camnoc_hf0,
1782         [MASTER_CAMNOC_HF1] = &mas_qxm_camnoc_hf1,
1783         [MASTER_CAMNOC_SF] = &mas_qxm_camnoc_sf,
1784         [MASTER_MDP_PORT0] = &mas_qxm_mdp0,
1785         [MASTER_MDP_PORT1] = &mas_qxm_mdp1,
1786         [MASTER_ROTATOR] = &mas_qxm_rot,
1787         [MASTER_VIDEO_P0] = &mas_qxm_venus0,
1788         [MASTER_VIDEO_P1] = &mas_qxm_venus1,
1789         [MASTER_VIDEO_PROC] = &mas_qxm_venus_arm9,
1790         [SLAVE_MNOC_SF_MEM_NOC] = &slv_qns2_mem_noc,
1791         [SLAVE_MNOC_HF_MEM_NOC] = &slv_qns_mem_noc_hf,
1792         [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc,
1793 };
1794
1795 static struct qcom_icc_node * const system_noc_nodes[] = {
1796         [MASTER_SNOC_CFG] = &mas_qhm_snoc_cfg,
1797         [A1NOC_SNOC_MAS] = &mas_qnm_aggre1_noc,
1798         [A2NOC_SNOC_MAS] = &mas_qnm_aggre2_noc,
1799         [MASTER_GEM_NOC_SNOC] = &mas_qnm_gemnoc,
1800         [MASTER_PIMEM] = &mas_qxm_pimem,
1801         [MASTER_GIC] = &mas_xm_gic,
1802         [SLAVE_APPSS] = &slv_qhs_apss,
1803         [SNOC_CNOC_SLV] = &slv_qns_cnoc,
1804         [SLAVE_SNOC_GEM_NOC_GC] = &slv_qns_gemnoc_gc,
1805         [SLAVE_SNOC_GEM_NOC_SF] = &slv_qns_gemnoc_sf,
1806         [SLAVE_OCIMEM] = &slv_qxs_imem,
1807         [SLAVE_PIMEM] = &slv_qxs_pimem,
1808         [SLAVE_SERVICE_SNOC] = &slv_srvc_snoc,
1809         [SLAVE_QDSS_STM] = &slv_xs_qdss_stm,
1810         [SLAVE_TCU] = &slv_xs_sys_tcu_cfg,
1811 };
1812
1813 static const struct qcom_icc_desc sc8180x_aggre1_noc = {
1814         .nodes = aggre1_noc_nodes,
1815         .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1816         .bcms = aggre1_noc_bcms,
1817         .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1818 };
1819
1820 static const struct qcom_icc_desc sc8180x_aggre2_noc = {
1821         .nodes = aggre2_noc_nodes,
1822         .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1823         .bcms = aggre2_noc_bcms,
1824         .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1825 };
1826
1827 static const struct qcom_icc_desc sc8180x_camnoc_virt = {
1828         .nodes = camnoc_virt_nodes,
1829         .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
1830         .bcms = camnoc_virt_bcms,
1831         .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
1832 };
1833
1834 static const struct qcom_icc_desc sc8180x_compute_noc = {
1835         .nodes = compute_noc_nodes,
1836         .num_nodes = ARRAY_SIZE(compute_noc_nodes),
1837         .bcms = compute_noc_bcms,
1838         .num_bcms = ARRAY_SIZE(compute_noc_bcms),
1839 };
1840
1841 static const struct qcom_icc_desc sc8180x_config_noc = {
1842         .nodes = config_noc_nodes,
1843         .num_nodes = ARRAY_SIZE(config_noc_nodes),
1844         .bcms = config_noc_bcms,
1845         .num_bcms = ARRAY_SIZE(config_noc_bcms),
1846 };
1847
1848 static const struct qcom_icc_desc sc8180x_dc_noc = {
1849         .nodes = dc_noc_nodes,
1850         .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1851 };
1852
1853 static const struct qcom_icc_desc sc8180x_gem_noc  = {
1854         .nodes = gem_noc_nodes,
1855         .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1856         .bcms = gem_noc_bcms,
1857         .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1858 };
1859
1860 static const struct qcom_icc_desc sc8180x_ipa_virt  = {
1861         .nodes = ipa_virt_nodes,
1862         .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
1863         .bcms = ipa_virt_bcms,
1864         .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
1865 };
1866
1867 static const struct qcom_icc_desc sc8180x_mc_virt  = {
1868         .nodes = mc_virt_nodes,
1869         .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1870         .bcms = mc_virt_bcms,
1871         .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1872 };
1873
1874 static const struct qcom_icc_desc sc8180x_mmss_noc  = {
1875         .nodes = mmss_noc_nodes,
1876         .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1877         .bcms = mmss_noc_bcms,
1878         .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1879 };
1880
1881 static const struct qcom_icc_desc sc8180x_system_noc  = {
1882         .nodes = system_noc_nodes,
1883         .num_nodes = ARRAY_SIZE(system_noc_nodes),
1884         .bcms = system_noc_bcms,
1885         .num_bcms = ARRAY_SIZE(system_noc_bcms),
1886 };
1887
1888 static struct qcom_icc_bcm * const qup_virt_bcms[] = {
1889         &bcm_qup0,
1890 };
1891
1892 static struct qcom_icc_node *qup_virt_nodes[] = {
1893         [MASTER_QUP_CORE_0] = &mas_qup_core_0,
1894         [MASTER_QUP_CORE_1] = &mas_qup_core_1,
1895         [MASTER_QUP_CORE_2] = &mas_qup_core_2,
1896         [SLAVE_QUP_CORE_0] = &slv_qup_core_0,
1897         [SLAVE_QUP_CORE_1] = &slv_qup_core_1,
1898         [SLAVE_QUP_CORE_2] = &slv_qup_core_2,
1899 };
1900
1901 static const struct qcom_icc_desc sc8180x_qup_virt = {
1902         .nodes = qup_virt_nodes,
1903         .num_nodes = ARRAY_SIZE(qup_virt_nodes),
1904         .bcms = qup_virt_bcms,
1905         .num_bcms = ARRAY_SIZE(qup_virt_bcms),
1906 };
1907
1908 static const struct of_device_id qnoc_of_match[] = {
1909         { .compatible = "qcom,sc8180x-aggre1-noc", .data = &sc8180x_aggre1_noc },
1910         { .compatible = "qcom,sc8180x-aggre2-noc", .data = &sc8180x_aggre2_noc },
1911         { .compatible = "qcom,sc8180x-camnoc-virt", .data = &sc8180x_camnoc_virt },
1912         { .compatible = "qcom,sc8180x-compute-noc", .data = &sc8180x_compute_noc, },
1913         { .compatible = "qcom,sc8180x-config-noc", .data = &sc8180x_config_noc },
1914         { .compatible = "qcom,sc8180x-dc-noc", .data = &sc8180x_dc_noc },
1915         { .compatible = "qcom,sc8180x-gem-noc", .data = &sc8180x_gem_noc },
1916         { .compatible = "qcom,sc8180x-ipa-virt", .data = &sc8180x_ipa_virt },
1917         { .compatible = "qcom,sc8180x-mc-virt", .data = &sc8180x_mc_virt },
1918         { .compatible = "qcom,sc8180x-mmss-noc", .data = &sc8180x_mmss_noc },
1919         { .compatible = "qcom,sc8180x-qup-virt", .data = &sc8180x_qup_virt },
1920         { .compatible = "qcom,sc8180x-system-noc", .data = &sc8180x_system_noc },
1921         { }
1922 };
1923 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1924
1925 static struct platform_driver qnoc_driver = {
1926         .probe = qcom_icc_rpmh_probe,
1927         .remove = qcom_icc_rpmh_remove,
1928         .driver = {
1929                 .name = "qnoc-sc8180x",
1930                 .of_match_table = qnoc_of_match,
1931                 .sync_state = icc_sync_state,
1932         },
1933 };
1934 module_platform_driver(qnoc_driver);
1935
1936 MODULE_DESCRIPTION("Qualcomm sc8180x NoC driver");
1937 MODULE_LICENSE("GPL v2");