2 * Driver for Pixcir I2C touchscreen controllers.
4 * Copyright (C) 2010-2011 Pixcir, Inc.
6 * pixcir_i2c_ts.c V3.ss0 from v3.0 support TangoC solution and remove the previous soltutions
8 * pixcir_i2c_ts.c V3.1 Add bootloader function 7
12 * Add BOOTLOADER_STU 16
14 * Add Write/Read Interface for APP software
16 * pixcir_i2c_ts.c V3.2.0A for INT_MODE 0x0A
17 * arrange to pixcir 10 slot
19 * This software is licensed under the terms of the GNU General Public
20 * License version 2, as published by the Free Software Foundation, and
21 * may be copied, distributed, and modified under those terms.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public
29 * License along with this library; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 #include <linux/i2c.h>
34 #include <linux/input.h>
35 #include <linux/gpio.h>
36 #include <linux/earlysuspend.h>
37 #include <linux/interrupt.h>
38 #include <linux/delay.h>
39 #include <linux/miscdevice.h>
40 #include <linux/firmware.h>
41 #include <linux/platform_device.h>
43 #include <linux/slab.h>
44 #include <linux/miscdevice.h>
45 #include <linux/module.h>
46 #include <linux/mutex.h>
48 #include <linux/device.h>
49 #include <linux/interrupt.h>
50 #include <linux/delay.h>
51 #include <linux/sysctl.h>
52 #include <linux/input/mt.h>
53 #include <asm/uaccess.h>
55 #include <linux/sched.h>
56 #include <linux/kthread.h>
57 #include <linux/completion.h>
58 #include <linux/err.h>
60 #include <linux/regulator/consumer.h>
61 #include <linux/i2c/msg2138.h>
62 #include <soc/sprd/regulator.h>
64 #include <soc/sprd/board.h>
65 #ifdef CONFIG_HAS_EARLYSUSPEND
66 #include <linux/earlysuspend.h>
68 #if defined(CONFIG_I2C_SPRD) || defined(CONFIG_I2C_SPRD_V1)
69 #include <soc/sprd/i2c-sprd.h>
72 #include <linux/of_device.h>
73 #include <linux/of_address.h>
74 #include <linux/of_gpio.h>
76 /*********************************Bee-0928-TOP****************************************/
77 //#define SYSFS_DEBUG //cg,20130929
78 //#define PIXCIR_DEBUG
79 //#define PIXCIR_CQ_CALL 0
81 #define PIXCIR_DBG(format, ...) \
82 printk(KERN_INFO "PIXCIR_TS " format "\n", ## __VA_ARGS__)
83 #define TPD_DEBUG(format, ...) \
84 printk(KERN_INFO "PIXCIR_TS " format "\n", ## __VA_ARGS__)
86 #define PIXCIR_DBG(format, ...)
87 #define TPD_DEBUG(format, ...)
90 #define USE_WAIT_QUEUE 1
91 #define USE_THREADED_IRQ 0
92 #define USE_WORK_QUEUE 0
94 #define TOUCH_VIRTUAL_KEYS
96 #define TP_XY_CHANGE 0
97 #define SLAVE_ADDR 0x48
98 #define BOOTLOADER_ADDR 0x5d
101 #define I2C_MAJOR 125
104 #define I2C_MINORS 256
105 #define CALIBRATION_FLAG 1
108 #define ENABLE_IRQ 10
109 #define DISABLE_IRQ 11
110 #define BOOTLOADER_STU 16
111 #define ATTB_VALUE 17
112 #define MAX_FINGER_NUM 5
117 #define TPD_REG_BASE 0x00
118 #define TPD_SOFT_RESET_MODE 0x01
119 #define TPD_OP_MODE 0x00
120 #define TPD_LOW_PWR_MODE 0x04
121 #define TPD_SYSINFO_MODE 0x10
122 #define GET_HSTMODE(reg) ((reg & 0x70) >> 4) // in op mode or not
123 #define GET_BOOTLOADERMODE(reg) ((reg & 0x10) >> 4) // in bl mode
124 //#define __FIRMWARE_UPDATE__
125 #define REG_RT_PRIO(x) ((x) | 0x10000000)
126 #define RTPM_PRIO_TPD REG_RT_PRIO(4)
129 static struct task_struct *thread = NULL;
130 static DECLARE_WAIT_QUEUE_HEAD(waiter);
131 static int tpd_flag = 0;
134 struct pixcir_i2c_ts_data {
135 struct i2c_client *client;
136 struct input_dev *input;
138 struct work_struct pen_event_work;
139 struct workqueue_struct *ts_workqueue;
141 #ifdef CONFIG_HAS_EARLYSUSPEND
142 struct work_struct resume_work;
143 struct workqueue_struct *ts_resume_workqueue;
144 struct early_suspend early_suspend;
146 struct msg2138_ts_platform_data *platform_data;
147 //const struct pixcir_ts_platform_data *chip;
151 static unsigned char bl_cmd[] = {
158 struct tpd_operation_data_t {
159 unsigned char hst_mode;
160 unsigned char tt_mode;
161 unsigned char tt_stat;
163 unsigned char x1_M,x1_L;
164 unsigned char y1_M,y1_L;
166 unsigned char evnt_id;
168 unsigned char x2_M,x2_L;
169 unsigned char y2_M,y2_L;
171 unsigned char gest_cnt;
172 unsigned char gest_id;
174 struct tpd_bootloader_data_t {
175 unsigned char bl_file;
176 unsigned char bl_status;
177 unsigned char bl_error;
178 unsigned char blver_hi,blver_lo;
179 unsigned char bld_blver_hi,bld_blver_lo;
181 unsigned char ttspver_hi,ttspver_lo;
182 unsigned char appid_hi,appid_lo;
183 unsigned char appver_hi,appver_lo;
189 struct tpd_sysinfo_data_t {
190 unsigned char hst_mode;
191 unsigned char mfg_cmd;
192 unsigned char mfg_stat;
193 unsigned char cid[3];
194 unsigned char tt_undef1;
196 unsigned char uid[8];
197 unsigned char bl_verh;
198 unsigned char bl_verl;
200 unsigned char tts_verh;
201 unsigned char tts_verl;
203 unsigned char app_idh;
204 unsigned char app_idl;
205 unsigned char app_verh;
206 unsigned char app_verl;
208 unsigned char tt_undef2[6];
209 unsigned char act_intrvl;
210 unsigned char tch_tmout;
211 unsigned char lp_intrvl;
223 struct list_head list;
224 struct i2c_adapter *adap;
228 static struct i2c_client * msg21xx_i2c_client;
229 static struct pixcir_i2c_ts_data *msg21xx_i2c_ts_data;
230 //static unsigned char status_reg = 0;
231 static int global_irq;
232 static struct i2c_driver pixcir_i2c_ts_driver;
233 static struct class *i2c_dev_class;
234 static int MS_TS_MSG21XX_X_MAX = 0;
235 static int MS_TS_MSG21XX_Y_MAX = 0;
237 static LIST_HEAD(i2c_dev_list);
238 static DEFINE_SPINLOCK(i2c_dev_list_lock);
240 static int suspend_flag;
241 static struct early_suspend pixcir_early_suspend;
243 static ssize_t pixcir_set_calibrate(struct device* cd, struct device_attribute *attr,
244 const char* buf, size_t len);
245 static ssize_t pixcir_show_suspend(struct device* cd,struct device_attribute *attr, char* buf);
246 static ssize_t pixcir_store_suspend(struct device* cd, struct device_attribute *attr,const char* buf, size_t len);
247 static void pixcir_ts_suspend(struct early_suspend *handler);
248 static void pixcir_ts_resume(struct early_suspend *handler);
250 //static struct tpd_operation_data_t g_operation_data;
251 static struct tpd_bootloader_data_t g_bootloader_data;
252 static struct tpd_sysinfo_data_t g_sysinfo_data;
254 static char *cg_fw_version = NULL;
257 #define CTP_ID_MSG21XX 1
258 #define CTP_ID_MSG21XXA 2
259 #define FW_ADDR_MSG21XX (0xC4>>1)
260 static int HalTscrCReadI2CSeq(u8 addr, u8* read_data, u16 size)
262 //according to your platform.
265 struct i2c_msg msgs[] =
275 rc = i2c_transfer(msg21xx_i2c_client->adapter, msgs, 1);
278 printk("HalTscrCReadI2CSeq error %d\n", rc);
283 static int HalTscrCDevWriteI2CSeq(u8 addr, u8* data, u16 size)
285 //according to your platform.
287 struct i2c_msg msgs[] =
296 rc = i2c_transfer(msg21xx_i2c_client->adapter, msgs, 1);
299 printk("HalTscrCDevWriteI2CSeq error %d,addr = %d\n", rc,addr);
304 #ifdef __FIRMWARE_UPDATE__
305 #define FW_ADDR_MSG21XX_TP (0x4C>>1)
306 #define FW_UPDATE_ADDR_MSG21XX (0x92>>1)
307 #define TP_DEBUG printk//(x) //x//
308 #define DBUG printk//(x) //x
309 static char *fw_version = NULL;
311 static u8 temp[94][1024];
314 static u8 g_dwiic_info_data[1024]; // Buffer for info data
315 static int FwDataCnt;
316 struct class *firmware_class;
317 struct device *firmware_cmd_dev;
319 static void dbbusDWIICEnterSerialDebugMode(void)
323 // Enter the Serial Debug Mode
329 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, data, 5);
332 static void dbbusDWIICStopMCU(void)
338 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, data, 1);
341 static void dbbusDWIICIICUseBus(void)
347 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, data, 1);
350 static void dbbusDWIICIICReshape(void)
356 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, data, 1);
359 static void dbbusDWIICIICNotUseBus(void)
365 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, data, 1);
368 static void dbbusDWIICNotStopMCU(void)
374 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, data, 1);
377 static void dbbusDWIICExitSerialDebugMode(void)
381 // Exit the Serial Debug Mode
383 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, data, 1);
385 // Delay some interval to guard the next transaction
386 udelay ( 150);//200 ); // delay about 0.2ms
389 static void drvISP_EntryIspMode(void)
393 0x4D, 0x53, 0x54, 0x41, 0x52
395 printk("\n******%s come in*******\n",__FUNCTION__);
396 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, bWriteData, 5);
397 udelay ( 150 );//200 ); // delay about 0.1ms
400 static u8 drvISP_Read(u8 n, u8* pDataToRead) //First it needs send 0x11 to notify we want to get flash data back.
403 unsigned char dbbus_rx_data[2] = {0};
404 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, &Read_cmd, 1);
405 //msctpc_LoopDelay ( 1 ); // delay about 100us*****
406 udelay( 800 );//200);
409 HalTscrCReadI2CSeq(FW_UPDATE_ADDR_MSG21XX, &dbbus_rx_data[0], 2);
410 *pDataToRead = dbbus_rx_data[0];
411 TP_DEBUG("dbbus=%d,%d===drvISP_Read=====\n",dbbus_rx_data[0],dbbus_rx_data[1]);
415 HalTscrCReadI2CSeq(FW_UPDATE_ADDR_MSG21XX, pDataToRead, n);
421 static void drvISP_WriteEnable(void)
427 u8 bWriteData1 = 0x12;
428 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, bWriteData, 2);
430 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, &bWriteData1, 1);
434 static void drvISP_ExitIspMode(void)
436 u8 bWriteData = 0x24;
437 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, &bWriteData, 1);
438 udelay( 150 );//200);
441 static u8 drvISP_ReadStatus(void)
448 u8 bWriteData1 = 0x12;
450 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, bWriteData, 2);
451 //msctpc_LoopDelay ( 1 ); // delay about 100us*****
453 drvISP_Read(1, &bReadData);
454 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, &bWriteData1, 1);
459 static void drvISP_BlockErase(u32 addr)
461 u8 bWriteData[5] = { 0x00, 0x00, 0x00, 0x00, 0x00 };
462 u8 bWriteData1 = 0x12;
463 printk("\n******%s come in*******\n",__FUNCTION__);
465 drvISP_WriteEnable();
467 //Enable write status register
468 bWriteData[0] = 0x10;
469 bWriteData[1] = 0x50;
470 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, bWriteData, 2);
471 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, &bWriteData1, 1);
474 bWriteData[0] = 0x10;
475 bWriteData[1] = 0x01;
476 bWriteData[2] = 0x00;
477 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, bWriteData, 3);
478 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, &bWriteData1, 1);
481 bWriteData[0] = 0x10;
482 bWriteData[1] = 0x04;
483 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, bWriteData, 2);
484 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, &bWriteData1, 1);
485 //msctpc_LoopDelay ( 1 ); // delay about 100us*****
488 while ( ( drvISP_ReadStatus() & 0x01 ) == 0x01 )
491 if ( timeOutCount >= 100000 ) break; /* around 1 sec timeout */
493 drvISP_WriteEnable();
495 bWriteData[0] = 0x10;
496 bWriteData[1] = 0xC7;//0xD8; //Block Erase
497 //bWriteData[2] = ((addr >> 16) & 0xFF) ;
498 //bWriteData[3] = ((addr >> 8) & 0xFF) ;
499 //bWriteData[4] = (addr & 0xFF) ;
500 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, bWriteData, 2);
501 //HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, &bWriteData, 5);
502 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, &bWriteData1, 1);
503 //msctpc_LoopDelay ( 1 ); // delay about 100us*****
506 while ( ( drvISP_ReadStatus() & 0x01 ) == 0x01 )
509 if ( timeOutCount >= 500000 ) break; /* around 5 sec timeout */
513 static void drvISP_Program(u16 k, u8* pDataToWrite)
519 u8 bWriteData1 = 0x12;
522 for (j = 0; j < 8; j++) //128*8 cycle
525 TX_data[1] = 0x02;// Page Program CMD
526 TX_data[2] = (addr + 128 * j) >> 16;
527 TX_data[3] = (addr + 128 * j) >> 8;
528 TX_data[4] = (addr + 128 * j);
529 for (i = 0; i < 128; i++)
531 TX_data[5 + i] = pDataToWrite[j * 128 + i];
533 //msctpc_LoopDelay ( 1 ); // delay about 100us*****
537 while ( ( drvISP_ReadStatus() & 0x01 ) == 0x01 )
540 if ( timeOutCount >= 100000 ) break; /* around 1 sec timeout */
543 drvISP_WriteEnable();
544 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, TX_data, 133); //write 133 byte per cycle
545 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, &bWriteData1, 1);
549 static ssize_t firmware_update_show ( struct device *dev,
550 struct device_attribute *attr, char *buf )
552 return sprintf ( buf, "%s\n", fw_version );
555 static void _HalTscrHWReset(void)
557 struct msg2138_ts_platform_data *pdata = msg21xx_i2c_ts_data->platform_data;
558 gpio_direction_output(pdata->reset_gpio_number, 1);
559 gpio_set_value(pdata->reset_gpio_number, 1);
560 gpio_set_value(pdata->reset_gpio_number, 0);
561 mdelay(10); /* Note that the RST must be in LOW 10ms at least */
562 gpio_set_value(pdata->reset_gpio_number, 1);
563 /* Enable the interrupt service thread/routine for INT after 50ms */
567 static void drvISP_Verify ( u16 k, u8* pDataToVerify )
570 u8 bWriteData[5] ={ 0x10, 0x03, 0, 0, 0 };
572 u8 bWriteData1 = 0x12;
576 for ( j = 0; j < 8; j++ ) //128*8 cycle
578 bWriteData[2] = ( u8 ) ( ( addr + j * 128 ) >> 16 );
579 bWriteData[3] = ( u8 ) ( ( addr + j * 128 ) >> 8 );
580 bWriteData[4] = ( u8 ) ( addr + j * 128 );
581 udelay ( 100 ); // delay about 100us*****
584 while ( ( drvISP_ReadStatus() & 0x01 ) == 0x01 )
587 if ( timeOutCount >= 100000 ) break; /* around 1 sec timeout */
590 HalTscrCDevWriteI2CSeq ( FW_UPDATE_ADDR_MSG21XX, bWriteData, 5 ); //write read flash addr
591 udelay ( 100 ); // delay about 100us*****
592 drvISP_Read ( 128, RX_data );
593 HalTscrCDevWriteI2CSeq ( FW_UPDATE_ADDR_MSG21XX, &bWriteData1, 1 ); //cmd end
594 for ( i = 0; i < 128; i++ ) //log out if verify error
596 if ( ( RX_data[i] != 0 ) && index < 10 )
598 //TP_DEBUG("j=%d,RX_data[%d]=0x%x\n",j,i,RX_data[i]);
601 if ( RX_data[i] != pDataToVerify[128 * j + i] )
603 TP_DEBUG ( "k=%d,j=%d,i=%d===============Update Firmware Error================", k, j, i );
609 static void drvISP_ChipErase()
611 u8 bWriteData[5] = { 0x00, 0x00, 0x00, 0x00, 0x00 };
612 u8 bWriteData1 = 0x12;
613 u32 timeOutCount = 0;
614 drvISP_WriteEnable();
616 //Enable write status register
617 bWriteData[0] = 0x10;
618 bWriteData[1] = 0x50;
619 HalTscrCDevWriteI2CSeq ( FW_UPDATE_ADDR_MSG21XX, bWriteData, 2 );
620 HalTscrCDevWriteI2CSeq ( FW_UPDATE_ADDR_MSG21XX, &bWriteData1, 1 );
623 bWriteData[0] = 0x10;
624 bWriteData[1] = 0x01;
625 bWriteData[2] = 0x00;
626 HalTscrCDevWriteI2CSeq ( FW_UPDATE_ADDR_MSG21XX, bWriteData, 3 );
627 HalTscrCDevWriteI2CSeq ( FW_UPDATE_ADDR_MSG21XX, &bWriteData1, 1 );
630 bWriteData[0] = 0x10;
631 bWriteData[1] = 0x04;
632 HalTscrCDevWriteI2CSeq ( FW_UPDATE_ADDR_MSG21XX, bWriteData, 2 );
633 HalTscrCDevWriteI2CSeq ( FW_UPDATE_ADDR_MSG21XX, &bWriteData1, 1 );
634 udelay ( 100 ); // delay about 100us*****
636 while ( ( drvISP_ReadStatus() & 0x01 ) == 0x01 )
639 if ( timeOutCount >= 100000 ) break; /* around 1 sec timeout */
641 drvISP_WriteEnable();
643 bWriteData[0] = 0x10;
644 bWriteData[1] = 0xC7;
646 HalTscrCDevWriteI2CSeq ( FW_UPDATE_ADDR_MSG21XX, bWriteData, 2 );
647 HalTscrCDevWriteI2CSeq ( FW_UPDATE_ADDR_MSG21XX, &bWriteData1, 1 );
648 udelay ( 100 ); // delay about 100us*****
650 while ( ( drvISP_ReadStatus() & 0x01 ) == 0x01 )
653 if ( timeOutCount >= 500000 ) break; /* around 5 sec timeout */
657 /* update the firmware part, used by apk*/
658 /*show the fw version*/
660 static ssize_t firmware_update_c2 ( struct device *dev,
661 struct device_attribute *attr, const char *buf, size_t size )
665 unsigned char dbbus_rx_data[2] = {0};
668 dbbus_tx_data[0] = 0x10;
669 dbbus_tx_data[1] = 0x11;
670 dbbus_tx_data[2] = 0xE2;
671 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 3 );
672 dbbus_rx_data[0] = 0;
673 dbbus_rx_data[1] = 0;
674 HalTscrCReadI2CSeq ( FW_ADDR_MSG21XX, &dbbus_rx_data[0], 2 );
675 TP_DEBUG ( "dbbus_rx_data[0]=0x%x", dbbus_rx_data[0] );
676 dbbus_tx_data[3] = dbbus_rx_data[0] & 0xF7; //Clear Bit 3
677 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
679 // set MCU clock,SPI clock =FRO
680 dbbus_tx_data[0] = 0x10;
681 dbbus_tx_data[1] = 0x1E;
682 dbbus_tx_data[2] = 0x22;
683 dbbus_tx_data[3] = 0x00;
684 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
686 dbbus_tx_data[0] = 0x10;
687 dbbus_tx_data[1] = 0x1E;
688 dbbus_tx_data[2] = 0x23;
689 dbbus_tx_data[3] = 0x00;
690 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
692 // Enable slave's ISP ECO mode
693 dbbus_tx_data[0] = 0x10;
694 dbbus_tx_data[1] = 0x08;
695 dbbus_tx_data[2] = 0x0c;
696 dbbus_tx_data[3] = 0x08;
697 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
700 dbbus_tx_data[0] = 0x10;
701 dbbus_tx_data[1] = 0x1E;
702 dbbus_tx_data[2] = 0x02;
703 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 3 );
704 HalTscrCReadI2CSeq ( FW_ADDR_MSG21XX, &dbbus_rx_data[0], 2 );
705 TP_DEBUG ( "dbbus_rx_data[0]=0x%x", dbbus_rx_data[0] );
706 dbbus_tx_data[3] = ( dbbus_rx_data[0] | 0x20 ); //Set Bit 5
707 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
710 dbbus_tx_data[0] = 0x10;
711 dbbus_tx_data[1] = 0x1E;
712 dbbus_tx_data[2] = 0x0E;
713 dbbus_tx_data[3] = 0x02;
714 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
717 dbbus_tx_data[0] = 0x10;
718 dbbus_tx_data[1] = 0x1E;
719 dbbus_tx_data[2] = 0x10;
720 dbbus_tx_data[3] = 0x08;
721 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
723 dbbusDWIICIICNotUseBus();
724 dbbusDWIICNotStopMCU();
725 dbbusDWIICExitSerialDebugMode();
727 drvISP_EntryIspMode();
732 // Program and Verify
733 dbbusDWIICEnterSerialDebugMode();
735 dbbusDWIICIICUseBus();
736 dbbusDWIICIICReshape();
738 // Disable the Watchdog
739 dbbus_tx_data[0] = 0x10;
740 dbbus_tx_data[1] = 0x3C;
741 dbbus_tx_data[2] = 0x60;
742 dbbus_tx_data[3] = 0x55;
743 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
744 dbbus_tx_data[0] = 0x10;
745 dbbus_tx_data[1] = 0x3C;
746 dbbus_tx_data[2] = 0x61;
747 dbbus_tx_data[3] = 0xAA;
748 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
751 dbbus_tx_data[0] = 0x10;
752 dbbus_tx_data[1] = 0x0F;
753 dbbus_tx_data[2] = 0xE6;
754 dbbus_tx_data[3] = 0x01;
755 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
758 dbbus_tx_data[0] = 0x10;
759 dbbus_tx_data[1] = 0x11;
760 dbbus_tx_data[2] = 0xE2;
761 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 3 );
762 dbbus_rx_data[0] = 0;
763 dbbus_rx_data[1] = 0;
764 HalTscrCReadI2CSeq ( FW_ADDR_MSG21XX, &dbbus_rx_data[0], 2 );
765 TP_DEBUG ( "dbbus_rx_data[0]=0x%x", dbbus_rx_data[0] );
766 dbbus_tx_data[3] = dbbus_rx_data[0] & 0xF7; //Clear Bit 3
767 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
769 // set MCU clock,SPI clock =FRO
770 dbbus_tx_data[0] = 0x10;
771 dbbus_tx_data[1] = 0x1E;
772 dbbus_tx_data[2] = 0x22;
773 dbbus_tx_data[3] = 0x00;
774 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
776 dbbus_tx_data[0] = 0x10;
777 dbbus_tx_data[1] = 0x1E;
778 dbbus_tx_data[2] = 0x23;
779 dbbus_tx_data[3] = 0x00;
780 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
782 // Enable slave's ISP ECO mode
783 dbbus_tx_data[0] = 0x10;
784 dbbus_tx_data[1] = 0x08;
785 dbbus_tx_data[2] = 0x0c;
786 dbbus_tx_data[3] = 0x08;
787 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
790 dbbus_tx_data[0] = 0x10;
791 dbbus_tx_data[1] = 0x1E;
792 dbbus_tx_data[2] = 0x02;
793 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 3 );
794 HalTscrCReadI2CSeq ( FW_ADDR_MSG21XX, &dbbus_rx_data[0], 2 );
795 TP_DEBUG ( "dbbus_rx_data[0]=0x%x", dbbus_rx_data[0] );
796 dbbus_tx_data[3] = ( dbbus_rx_data[0] | 0x20 ); //Set Bit 5
797 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
800 dbbus_tx_data[0] = 0x10;
801 dbbus_tx_data[1] = 0x1E;
802 dbbus_tx_data[2] = 0x0E;
803 dbbus_tx_data[3] = 0x02;
804 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
807 dbbus_tx_data[0] = 0x10;
808 dbbus_tx_data[1] = 0x1E;
809 dbbus_tx_data[2] = 0x10;
810 dbbus_tx_data[3] = 0x08;
811 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
813 dbbusDWIICIICNotUseBus();
814 dbbusDWIICNotStopMCU();
815 dbbusDWIICExitSerialDebugMode();
817 ///////////////////////////////////////
818 // Start to load firmware
819 ///////////////////////////////////////
820 drvISP_EntryIspMode();
822 for ( i = 0; i < 94; i++ ) // total 94 KB : 1 byte per R/W
824 drvISP_Program ( i, temp[i] ); // program to slave's flash
825 drvISP_Verify ( i, temp[i] ); //verify data
827 TP_DEBUG ( "update OK\n" );
828 drvISP_ExitIspMode();
833 static u32 Reflect ( u32 ref, char ch ) //unsigned int Reflect(unsigned int ref, char ch)
838 for ( i = 1; i < ( ch + 1 ); i++ )
842 value |= 1 << ( ch - i );
849 u32 Get_CRC ( u32 text, u32 prevCRC, u32 *crc32_table )
852 ulCRC = ( ulCRC >> 8 ) ^ crc32_table[ ( ulCRC & 0xFF ) ^ text];
855 static void Init_CRC32_Table ( u32 *crc32_table )
857 u32 magicnumber = 0x04c11db7;
860 for ( i = 0; i <= 0xFF; i++ )
862 crc32_table[i] = Reflect ( i, 8 ) << 24;
863 for ( j = 0; j < 8; j++ )
865 crc32_table[i] = ( crc32_table[i] << 1 ) ^ ( crc32_table[i] & ( 0x80000000L ) ? magicnumber : 0 );
867 crc32_table[i] = Reflect ( crc32_table[i], 32 );
878 static void drvDB_WriteReg8Bit ( u8 bank, u8 addr, u8 data )
880 u8 tx_data[4] = {0x10, bank, addr, data};
881 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, tx_data, 4 );
884 static void drvDB_WriteReg ( u8 bank, u8 addr, u16 data )
886 u8 tx_data[5] = {0x10, bank, addr, data & 0xFF, data >> 8};
887 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, tx_data, 5 );
890 static unsigned short drvDB_ReadReg ( u8 bank, u8 addr )
892 u8 tx_data[3] = {0x10, bank, addr};
895 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, tx_data, 3 );
896 HalTscrCReadI2CSeq ( FW_ADDR_MSG21XX, &rx_data[0], 2 );
897 return ( rx_data[1] << 8 | rx_data[0] );
900 static int drvTP_erase_emem_c32 ( void )
902 /////////////////////////
904 /////////////////////////
907 drvDB_WriteReg ( 0x16, 0x1E, 0xBEAF );
909 // before gpio mode, set the control pin as the orginal status
910 drvDB_WriteReg ( 0x16, 0x08, 0x0000 );
911 drvDB_WriteReg8Bit ( 0x16, 0x0E, 0x10 );
912 mdelay ( 10 ); //MCR_CLBK_DEBUG_DELAY ( 10, MCU_LOOP_DELAY_COUNT_MS );
914 // ptrim = 1, h'04[2]
915 drvDB_WriteReg8Bit ( 0x16, 0x08, 0x04 );
916 drvDB_WriteReg8Bit ( 0x16, 0x0E, 0x10 );
917 mdelay ( 10 ); //MCR_CLBK_DEBUG_DELAY ( 10, MCU_LOOP_DELAY_COUNT_MS );
919 // ptm = 6, h'04[12:14] = b'110
920 drvDB_WriteReg8Bit ( 0x16, 0x09, 0x60 );
921 drvDB_WriteReg8Bit ( 0x16, 0x0E, 0x10 );
923 // pmasi = 1, h'04[6]
924 drvDB_WriteReg8Bit ( 0x16, 0x08, 0x44 );
926 drvDB_WriteReg8Bit ( 0x16, 0x09, 0x68 );
927 // perase = 1, h'04[7]
928 drvDB_WriteReg8Bit ( 0x16, 0x08, 0xC4 );
929 // pnvstr = 1, h'04[5]
930 drvDB_WriteReg8Bit ( 0x16, 0x08, 0xE4 );
932 drvDB_WriteReg8Bit ( 0x16, 0x09, 0x6A );
934 drvDB_WriteReg8Bit ( 0x16, 0x0E, 0x10 );
939 static ssize_t firmware_update_c32 ( struct device *dev, struct device_attribute *attr,
940 const char *buf, size_t size, EMEM_TYPE_t emem_type )
943 u8 dbbus_rx_data[2] = {0};
944 // Buffer for slave's firmware
947 u32 crc_main, crc_main_tp;
948 u32 crc_info, crc_info_tp;
951 crc_main = 0xffffffff;
952 crc_info = 0xffffffff;
955 /////////////////////////
957 /////////////////////////
958 drvTP_erase_emem_c32();
959 mdelay ( 1000 ); //MCR_CLBK_DEBUG_DELAY ( 1000, MCU_LOOP_DELAY_COUNT_MS );
963 //drvDB_EnterDBBUS();
964 dbbusDWIICEnterSerialDebugMode();
966 dbbusDWIICIICUseBus();
967 dbbusDWIICIICReshape();
971 drvDB_WriteReg8Bit ( 0x3C, 0x60, 0x55 );
972 drvDB_WriteReg8Bit ( 0x3C, 0x61, 0xAA );
974 /////////////////////////
976 /////////////////////////
978 //polling 0x3CE4 is 0x1C70
981 reg_data = drvDB_ReadReg ( 0x3C, 0xE4 );
983 while ( reg_data != 0x1C70 );
986 drvDB_WriteReg ( 0x3C, 0xE4, 0xE38F ); // for all-blocks
988 //polling 0x3CE4 is 0x2F43
991 reg_data = drvDB_ReadReg ( 0x3C, 0xE4 );
993 while ( reg_data != 0x2F43 );
997 Init_CRC32_Table ( &crc_tab[0] );
999 for ( i = 0; i < 33; i++ ) // total 33 KB : 2 byte per R/W
1001 if ( i < 32 ) //emem_main
1005 temp[i][1014] = 0x5A; //Fmr_Loader[1014]=0x5A;
1006 temp[i][1015] = 0xA5; //Fmr_Loader[1015]=0xA5;
1008 for ( j = 0; j < 1016; j++ )
1010 //crc_main=Get_CRC(Fmr_Loader[j],crc_main,&crc_tab[0]);
1011 crc_main = Get_CRC ( temp[i][j], crc_main, &crc_tab[0] );
1016 for ( j = 0; j < 1024; j++ )
1018 //crc_main=Get_CRC(Fmr_Loader[j],crc_main,&crc_tab[0]);
1019 crc_main = Get_CRC ( temp[i][j], crc_main, &crc_tab[0] );
1025 for ( j = 0; j < 1024; j++ )
1027 //crc_info=Get_CRC(Fmr_Loader[j],crc_info,&crc_tab[0]);
1028 crc_info = Get_CRC ( temp[i][j], crc_info, &crc_tab[0] );
1032 //drvDWIIC_MasterTransmit( DWIIC_MODE_DWIIC_ID, 1024, Fmr_Loader );
1033 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX_TP, temp[i], 1024 );
1035 // polling 0x3CE4 is 0xD0BC
1038 reg_data = drvDB_ReadReg ( 0x3C, 0xE4 );
1040 while ( reg_data != 0xD0BC );
1042 drvDB_WriteReg ( 0x3C, 0xE4, 0x2F43 );
1046 drvDB_WriteReg ( 0x3C, 0xE4, 0x1380 );
1048 mdelay ( 10 ); //MCR_CLBK_DEBUG_DELAY ( 10, MCU_LOOP_DELAY_COUNT_MS );
1049 // polling 0x3CE4 is 0x9432
1052 reg_data = drvDB_ReadReg ( 0x3C, 0xE4 );
1054 while ( reg_data != 0x9432 );
1056 crc_main = crc_main ^ 0xffffffff;
1057 crc_info = crc_info ^ 0xffffffff;
1060 crc_main_tp = drvDB_ReadReg ( 0x3C, 0x80 );
1061 crc_main_tp = ( crc_main_tp << 16 ) | drvDB_ReadReg ( 0x3C, 0x82 );
1064 crc_info_tp = drvDB_ReadReg ( 0x3C, 0xA0 );
1065 crc_info_tp = ( crc_info_tp << 16 ) | drvDB_ReadReg ( 0x3C, 0xA2 );
1067 TP_DEBUG ( "crc_main=0x%x, crc_info=0x%x, crc_main_tp=0x%x, crc_info_tp=0x%x\n",
1068 crc_main, crc_info, crc_main_tp, crc_info_tp );
1070 //drvDB_ExitDBBUS();
1071 if ( ( crc_main_tp != crc_main ) || ( crc_info_tp != crc_info ) )
1073 printk ( "update FAILED\n" );
1076 enable_irq(global_irq);
1080 printk ( "update OK\n" );
1083 enable_irq(global_irq);
1089 static int drvTP_erase_emem_c33 ( EMEM_TYPE_t emem_type )
1092 drvDB_WriteReg ( 0x0F, 0xE6, 0x0001 );
1095 drvDB_WriteReg8Bit ( 0x3C, 0x60, 0x55 );
1096 drvDB_WriteReg8Bit ( 0x3C, 0x61, 0xAA );
1098 // set PROGRAM password
1099 drvDB_WriteReg8Bit ( 0x16, 0x1A, 0xBA );
1100 drvDB_WriteReg8Bit ( 0x16, 0x1B, 0xAB );
1102 //proto.MstarWriteReg(F1.loopDevice, 0x1618, 0x80);
1103 drvDB_WriteReg8Bit ( 0x16, 0x18, 0x80 );
1105 if ( emem_type == EMEM_ALL )
1107 drvDB_WriteReg8Bit ( 0x16, 0x08, 0x10 ); //mark
1110 drvDB_WriteReg8Bit ( 0x16, 0x18, 0x40 );
1113 drvDB_WriteReg8Bit ( 0x16, 0x18, 0x80 );
1116 if ( emem_type == EMEM_MAIN )
1118 drvDB_WriteReg8Bit ( 0x16, 0x0E, 0x04 ); //erase main
1122 drvDB_WriteReg8Bit ( 0x16, 0x0E, 0x08 ); //erase all block
1128 static int drvTP_read_emem_dbbus_c33 ( EMEM_TYPE_t emem_type, u16 addr, size_t size, u8 *p, size_t set_pce_high )
1132 // Set the starting address ( must before enabling burst mode and enter riu mode )
1133 drvDB_WriteReg ( 0x16, 0x00, addr );
1135 // Enable the burst mode ( must before enter riu mode )
1136 drvDB_WriteReg ( 0x16, 0x0C, drvDB_ReadReg ( 0x16, 0x0C ) | 0x0001 );
1138 // Set the RIU password
1139 drvDB_WriteReg ( 0x16, 0x1A, 0xABBA );
1141 // Enable the information block if pifren is HIGH
1142 if ( emem_type == EMEM_INFO )
1145 drvDB_WriteReg ( 0x16, 0x18, drvDB_ReadReg ( 0x16, 0x18 ) | 0x0080 );
1148 // Set the PIFREN to be HIGH
1149 drvDB_WriteReg ( 0x16, 0x08, 0x0010 );
1152 // Set the PCE to be HIGH
1153 drvDB_WriteReg ( 0x16, 0x18, drvDB_ReadReg ( 0x16, 0x18 ) | 0x0040 );
1156 // Wait pce becomes 1 ( read data ready )
1157 while ( ( drvDB_ReadReg ( 0x16, 0x10 ) & 0x0004 ) != 0x0004 );
1159 for ( i = 0; i < size; i += 4 )
1161 // Fire the FASTREAD command
1162 drvDB_WriteReg ( 0x16, 0x0E, drvDB_ReadReg ( 0x16, 0x0E ) | 0x0001 );
1164 // Wait the operation is done
1165 while ( ( drvDB_ReadReg ( 0x16, 0x10 ) & 0x0001 ) != 0x0001 );
1167 p[i + 0] = drvDB_ReadReg ( 0x16, 0x04 ) & 0xFF;
1168 p[i + 1] = ( drvDB_ReadReg ( 0x16, 0x04 ) >> 8 ) & 0xFF;
1169 p[i + 2] = drvDB_ReadReg ( 0x16, 0x06 ) & 0xFF;
1170 p[i + 3] = ( drvDB_ReadReg ( 0x16, 0x06 ) >> 8 ) & 0xFF;
1173 // Disable the burst mode
1174 drvDB_WriteReg ( 0x16, 0x0C, drvDB_ReadReg ( 0x16, 0x0C ) & ( ~0x0001 ) );
1176 // Clear the starting address
1177 drvDB_WriteReg ( 0x16, 0x00, 0x0000 );
1179 //Always return to main block
1180 if ( emem_type == EMEM_INFO )
1182 // Clear the PCE before change block
1183 drvDB_WriteReg ( 0x16, 0x18, drvDB_ReadReg ( 0x16, 0x18 ) | 0x0080 );
1185 // Set the PIFREN to be LOW
1186 drvDB_WriteReg ( 0x16, 0x08, drvDB_ReadReg ( 0x16, 0x08 ) & ( ~0x0010 ) );
1188 drvDB_WriteReg ( 0x16, 0x18, drvDB_ReadReg ( 0x16, 0x18 ) | 0x0040 );
1189 while ( ( drvDB_ReadReg ( 0x16, 0x10 ) & 0x0004 ) != 0x0004 );
1192 // Clear the RIU password
1193 drvDB_WriteReg ( 0x16, 0x1A, 0x0000 );
1197 // Set the PCE to be HIGH before jumping back to e-flash codes
1198 drvDB_WriteReg ( 0x16, 0x18, drvDB_ReadReg ( 0x16, 0x18 ) | 0x0040 );
1199 while ( ( drvDB_ReadReg ( 0x16, 0x10 ) & 0x0004 ) != 0x0004 );
1206 static int drvTP_read_info_dwiic_c33 ( void )
1208 u8 dwiic_tx_data[5];
1209 u8 dwiic_rx_data[4];
1214 drvDB_WriteReg8Bit ( 0x3C, 0x60, 0x55 );
1215 drvDB_WriteReg8Bit ( 0x3C, 0x61, 0xAA );
1217 drvDB_WriteReg ( 0x3C, 0xE4, 0xA4AB );
1219 drvDB_WriteReg ( 0x1E, 0x04, 0x7d60 );
1222 drvDB_WriteReg ( 0x1E, 0x04, 0x829F );
1224 dwiic_tx_data[0] = 0x10;
1225 dwiic_tx_data[1] = 0x0F;
1226 dwiic_tx_data[2] = 0xE6;
1227 dwiic_tx_data[3] = 0x00;
1228 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dwiic_tx_data, 4 );
1232 reg_data = drvDB_ReadReg ( 0x3C, 0xE4 );
1234 while ( reg_data != 0x5B58 );
1236 dwiic_tx_data[0] = 0x72;
1237 dwiic_tx_data[1] = 0x80;
1238 dwiic_tx_data[2] = 0x00;
1239 dwiic_tx_data[3] = 0x04;
1240 dwiic_tx_data[4] = 0x00;
1241 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX_TP , dwiic_tx_data, 5 );
1246 HalTscrCReadI2CSeq ( FW_ADDR_MSG21XX_TP, &g_dwiic_info_data[0], 1024 );
1251 static int drvTP_info_updata_C33 ( u16 start_index, u8 *data, u16 size )
1253 // size != 0, start_index+size !> 1024
1255 for ( i = 0; i < size; i++ )
1257 g_dwiic_info_data[start_index] = * ( data + i );
1263 static ssize_t firmware_update_c33 ( struct device *dev, struct device_attribute *attr,
1264 const char *buf, size_t size, EMEM_TYPE_t emem_type )
1266 u8 dbbus_tx_data[4];
1267 u8 dbbus_rx_data[2] = {0};
1270 u32 crc_main, crc_main_tp;
1271 u32 crc_info, crc_info_tp;
1273 int update_pass = 1;
1276 crc_main = 0xffffffff;
1277 crc_info = 0xffffffff;
1279 drvTP_read_info_dwiic_c33();
1281 if ( g_dwiic_info_data[0] == 'M' && g_dwiic_info_data[1] == 'S' && g_dwiic_info_data[2] == 'T' && g_dwiic_info_data[3] == 'A' && g_dwiic_info_data[4] == 'R' && g_dwiic_info_data[5] == 'T' && g_dwiic_info_data[6] == 'P' && g_dwiic_info_data[7] == 'C' )
1283 // updata FW Version
1284 //drvTP_info_updata_C33 ( 8, &temp[32][8], 5 );
1286 g_dwiic_info_data[8]=temp[32][8];
1287 g_dwiic_info_data[9]=temp[32][9];
1288 g_dwiic_info_data[10]=temp[32][10];
1289 g_dwiic_info_data[11]=temp[32][11];
1290 // updata life counter
1291 life_counter[1] = (( ( (g_dwiic_info_data[13] << 8 ) | g_dwiic_info_data[12]) + 1 ) >> 8 ) & 0xFF;
1292 life_counter[0] = ( ( (g_dwiic_info_data[13] << 8 ) | g_dwiic_info_data[12]) + 1 ) & 0xFF;
1293 g_dwiic_info_data[12]=life_counter[0];
1294 g_dwiic_info_data[13]=life_counter[1];
1295 //drvTP_info_updata_C33 ( 10, &life_counter[0], 3 );
1296 drvDB_WriteReg ( 0x3C, 0xE4, 0x78C5 );
1297 drvDB_WriteReg ( 0x1E, 0x04, 0x7d60 );
1299 drvDB_WriteReg ( 0x1E, 0x04, 0x829F );
1303 //polling 0x3CE4 is 0x2F43
1306 reg_data = drvDB_ReadReg ( 0x3C, 0xE4 );
1309 while ( reg_data != 0x2F43 );
1311 // transmit lk info data
1312 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX_TP , &g_dwiic_info_data[0], 1024 );
1314 //polling 0x3CE4 is 0xD0BC
1317 reg_data = drvDB_ReadReg ( 0x3C, 0xE4 );
1319 while ( reg_data != 0xD0BC );
1324 drvTP_erase_emem_c33 ( EMEM_MAIN );
1330 //drvDB_EnterDBBUS();
1331 dbbusDWIICEnterSerialDebugMode();
1332 dbbusDWIICStopMCU();
1333 dbbusDWIICIICUseBus();
1334 dbbusDWIICIICReshape();
1337 /////////////////////////
1339 /////////////////////////
1341 //polling 0x3CE4 is 0x1C70
1342 if ( ( emem_type == EMEM_ALL ) || ( emem_type == EMEM_MAIN ) )
1346 reg_data = drvDB_ReadReg ( 0x3C, 0xE4 );
1348 while ( reg_data != 0x1C70 );
1351 switch ( emem_type )
1354 drvDB_WriteReg ( 0x3C, 0xE4, 0xE38F ); // for all-blocks
1357 drvDB_WriteReg ( 0x3C, 0xE4, 0x7731 ); // for main block
1360 drvDB_WriteReg ( 0x3C, 0xE4, 0x7731 ); // for info block
1362 drvDB_WriteReg8Bit ( 0x0F, 0xE6, 0x01 );
1364 drvDB_WriteReg8Bit ( 0x3C, 0xE4, 0xC5 ); //
1365 drvDB_WriteReg8Bit ( 0x3C, 0xE5, 0x78 ); //
1367 drvDB_WriteReg8Bit ( 0x1E, 0x04, 0x9F );
1368 drvDB_WriteReg8Bit ( 0x1E, 0x05, 0x82 );
1370 drvDB_WriteReg8Bit ( 0x0F, 0xE6, 0x00 );
1375 // polling 0x3CE4 is 0x2F43
1378 reg_data = drvDB_ReadReg ( 0x3C, 0xE4 );
1380 while ( reg_data != 0x2F43 );
1383 Init_CRC32_Table ( &crc_tab[0] );
1385 for ( i = 0; i < 33; i++ ) // total 33 KB : 2 byte per R/W
1387 if ( emem_type == EMEM_INFO )
1390 if ( i < 32 ) //emem_main
1394 temp[i][1014] = 0x5A; //Fmr_Loader[1014]=0x5A;
1395 temp[i][1015] = 0xA5; //Fmr_Loader[1015]=0xA5;
1397 for ( j = 0; j < 1016; j++ )
1399 //crc_main=Get_CRC(Fmr_Loader[j],crc_main,&crc_tab[0]);
1400 crc_main = Get_CRC ( temp[i][j], crc_main, &crc_tab[0] );
1405 for ( j = 0; j < 1024; j++ )
1407 //crc_main=Get_CRC(Fmr_Loader[j],crc_main,&crc_tab[0]);
1408 crc_main = Get_CRC ( temp[i][j], crc_main, &crc_tab[0] );
1414 for ( j = 0; j < 1024; j++ )
1416 //crc_info=Get_CRC(Fmr_Loader[j],crc_info,&crc_tab[0]);
1417 crc_info = Get_CRC ( g_dwiic_info_data[j], crc_info, &crc_tab[0] );
1419 if ( emem_type == EMEM_MAIN ) break;
1422 //drvDWIIC_MasterTransmit( DWIIC_MODE_DWIIC_ID, 1024, Fmr_Loader );
1423 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX_TP, temp[i], 1024 );
1425 // polling 0x3CE4 is 0xD0BC
1428 reg_data = drvDB_ReadReg ( 0x3C, 0xE4 );
1430 while ( reg_data != 0xD0BC );
1432 drvDB_WriteReg ( 0x3C, 0xE4, 0x2F43 );
1435 if ( ( emem_type == EMEM_ALL ) || ( emem_type == EMEM_MAIN ) )
1437 // write file done and check crc
1438 drvDB_WriteReg ( 0x3C, 0xE4, 0x1380 );
1440 mdelay ( 10 ); //MCR_CLBK_DEBUG_DELAY ( 10, MCU_LOOP_DELAY_COUNT_MS );
1442 if ( ( emem_type == EMEM_ALL ) || ( emem_type == EMEM_MAIN ) )
1444 // polling 0x3CE4 is 0x9432
1447 reg_data = drvDB_ReadReg ( 0x3C, 0xE4 );
1448 }while ( reg_data != 0x9432 );
1451 crc_main = crc_main ^ 0xffffffff;
1452 crc_info = crc_info ^ 0xffffffff;
1454 if ( ( emem_type == EMEM_ALL ) || ( emem_type == EMEM_MAIN ) )
1457 crc_main_tp = drvDB_ReadReg ( 0x3C, 0x80 );
1458 crc_main_tp = ( crc_main_tp << 16 ) | drvDB_ReadReg ( 0x3C, 0x82 );
1461 crc_info_tp = drvDB_ReadReg ( 0x3C, 0xA0 );
1462 crc_info_tp = ( crc_info_tp << 16 ) | drvDB_ReadReg ( 0x3C, 0xA2 );
1464 TP_DEBUG ( "crc_main=0x%x, crc_info=0x%x, crc_main_tp=0x%x, crc_info_tp=0x%x\n",
1465 crc_main, crc_info, crc_main_tp, crc_info_tp );
1467 //drvDB_ExitDBBUS();
1470 if ( ( emem_type == EMEM_ALL ) || ( emem_type == EMEM_MAIN ) )
1472 if ( crc_main_tp != crc_main )
1475 if ( crc_info_tp != crc_info )
1481 printk ( "update FAILED\n" );
1484 enable_irq(global_irq);
1488 printk ( "update OK\n" );
1491 enable_irq(global_irq);
1495 #define _FW_UPDATE_C3_
1496 #ifdef _FW_UPDATE_C3_
1497 static ssize_t firmware_update_store ( struct device *dev,
1498 struct device_attribute *attr, const char *buf, size_t size )
1501 u8 dbbus_tx_data[4];
1502 unsigned char dbbus_rx_data[2] = {0};
1503 disable_irq(global_irq);
1507 // Erase TP Flash first
1508 dbbusDWIICEnterSerialDebugMode();
1509 dbbusDWIICStopMCU();
1510 dbbusDWIICIICUseBus();
1511 dbbusDWIICIICReshape();
1514 // Disable the Watchdog
1515 dbbus_tx_data[0] = 0x10;
1516 dbbus_tx_data[1] = 0x3C;
1517 dbbus_tx_data[2] = 0x60;
1518 dbbus_tx_data[3] = 0x55;
1519 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1520 dbbus_tx_data[0] = 0x10;
1521 dbbus_tx_data[1] = 0x3C;
1522 dbbus_tx_data[2] = 0x61;
1523 dbbus_tx_data[3] = 0xAA;
1524 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1526 dbbus_tx_data[0] = 0x10;
1527 dbbus_tx_data[1] = 0x0F;
1528 dbbus_tx_data[2] = 0xE6;
1529 dbbus_tx_data[3] = 0x01;
1530 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1531 /////////////////////////
1532 // Difference between C2 and C3
1533 /////////////////////////
1534 // c2:2133 c32:2133a(2) c33:2138
1536 dbbus_tx_data[0] = 0x10;
1537 dbbus_tx_data[1] = 0x1E;
1538 dbbus_tx_data[2] = 0xCC;
1539 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 3 );
1540 HalTscrCReadI2CSeq ( FW_ADDR_MSG21XX, &dbbus_rx_data[0], 2 );
1541 if ( dbbus_rx_data[0] == 2 )
1544 dbbus_tx_data[0] = 0x10;
1545 dbbus_tx_data[1] = 0x3C;
1546 dbbus_tx_data[2] = 0xEA;
1547 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 3 );
1548 HalTscrCReadI2CSeq ( FW_ADDR_MSG21XX, &dbbus_rx_data[0], 2 );
1549 TP_DEBUG ( "dbbus_rx version[0]=0x%x", dbbus_rx_data[0] );
1551 if ( dbbus_rx_data[0] == 3 ){
1552 return firmware_update_c33 ( dev, attr, buf, size, EMEM_MAIN );
1556 return firmware_update_c32 ( dev, attr, buf, size, EMEM_ALL );
1561 return firmware_update_c2 ( dev, attr, buf, size );
1565 static ssize_t firmware_update_store ( struct device *dev,
1566 struct device_attribute *attr, const char *buf, size_t size )
1569 u8 dbbus_tx_data[4];
1570 unsigned char dbbus_rx_data[2] = {0};
1574 // 1. Erase TP Flash first
1575 dbbusDWIICEnterSerialDebugMode();
1576 dbbusDWIICStopMCU();
1577 dbbusDWIICIICUseBus();
1578 dbbusDWIICIICReshape();
1581 // Disable the Watchdog
1582 dbbus_tx_data[0] = 0x10;
1583 dbbus_tx_data[1] = 0x3C;
1584 dbbus_tx_data[2] = 0x60;
1585 dbbus_tx_data[3] = 0x55;
1586 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1587 dbbus_tx_data[0] = 0x10;
1588 dbbus_tx_data[1] = 0x3C;
1589 dbbus_tx_data[2] = 0x61;
1590 dbbus_tx_data[3] = 0xAA;
1591 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1594 dbbus_tx_data[0] = 0x10;
1595 dbbus_tx_data[1] = 0x0F;
1596 dbbus_tx_data[2] = 0xE6;
1597 dbbus_tx_data[3] = 0x01;
1598 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1601 dbbus_tx_data[0] = 0x10;
1602 dbbus_tx_data[1] = 0x11;
1603 dbbus_tx_data[2] = 0xE2;
1604 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 3 );
1605 dbbus_rx_data[0] = 0;
1606 dbbus_rx_data[1] = 0;
1607 HalTscrCReadI2CSeq ( FW_ADDR_MSG21XX, &dbbus_rx_data[0], 2 );
1608 TP_DEBUG ( "dbbus_rx_data[0]=0x%x", dbbus_rx_data[0] );
1609 dbbus_tx_data[3] = dbbus_rx_data[0] & 0xF7; //Clear Bit 3
1610 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1612 // set MCU clock,SPI clock =FRO
1613 dbbus_tx_data[0] = 0x10;
1614 dbbus_tx_data[1] = 0x1E;
1615 dbbus_tx_data[2] = 0x22;
1616 dbbus_tx_data[3] = 0x00;
1617 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1619 dbbus_tx_data[0] = 0x10;
1620 dbbus_tx_data[1] = 0x1E;
1621 dbbus_tx_data[2] = 0x23;
1622 dbbus_tx_data[3] = 0x00;
1623 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1625 // Enable slave's ISP ECO mode
1626 dbbus_tx_data[0] = 0x10;
1627 dbbus_tx_data[1] = 0x08;
1628 dbbus_tx_data[2] = 0x0c;
1629 dbbus_tx_data[3] = 0x08;
1630 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1633 dbbus_tx_data[0] = 0x10;
1634 dbbus_tx_data[1] = 0x1E;
1635 dbbus_tx_data[2] = 0x02;
1636 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 3 );
1637 HalTscrCReadI2CSeq ( FW_ADDR_MSG21XX, &dbbus_rx_data[0], 2 );
1638 TP_DEBUG ( "dbbus_rx_data[0]=0x%x", dbbus_rx_data[0] );
1639 dbbus_tx_data[3] = ( dbbus_rx_data[0] | 0x20 ); //Set Bit 5
1640 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1643 dbbus_tx_data[0] = 0x10;
1644 dbbus_tx_data[1] = 0x1E;
1645 dbbus_tx_data[2] = 0x0E;
1646 dbbus_tx_data[3] = 0x02;
1647 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1650 dbbus_tx_data[0] = 0x10;
1651 dbbus_tx_data[1] = 0x1E;
1652 dbbus_tx_data[2] = 0x10;
1653 dbbus_tx_data[3] = 0x08;
1654 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1656 dbbusDWIICIICNotUseBus();
1657 dbbusDWIICNotStopMCU();
1658 dbbusDWIICExitSerialDebugMode();
1660 drvISP_EntryIspMode();
1665 // 2.Program and Verify
1666 dbbusDWIICEnterSerialDebugMode();
1667 dbbusDWIICStopMCU();
1668 dbbusDWIICIICUseBus();
1669 dbbusDWIICIICReshape();
1671 // Disable the Watchdog
1672 dbbus_tx_data[0] = 0x10;
1673 dbbus_tx_data[1] = 0x3C;
1674 dbbus_tx_data[2] = 0x60;
1675 dbbus_tx_data[3] = 0x55;
1676 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1677 dbbus_tx_data[0] = 0x10;
1678 dbbus_tx_data[1] = 0x3C;
1679 dbbus_tx_data[2] = 0x61;
1680 dbbus_tx_data[3] = 0xAA;
1681 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1684 dbbus_tx_data[0] = 0x10;
1685 dbbus_tx_data[1] = 0x0F;
1686 dbbus_tx_data[2] = 0xE6;
1687 dbbus_tx_data[3] = 0x01;
1688 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1691 dbbus_tx_data[0] = 0x10;
1692 dbbus_tx_data[1] = 0x11;
1693 dbbus_tx_data[2] = 0xE2;
1694 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 3 );
1695 dbbus_rx_data[0] = 0;
1696 dbbus_rx_data[1] = 0;
1697 HalTscrCReadI2CSeq ( FW_ADDR_MSG21XX, &dbbus_rx_data[0], 2 );
1698 TP_DEBUG ( "dbbus_rx_data[0]=0x%x", dbbus_rx_data[0] );
1699 dbbus_tx_data[3] = dbbus_rx_data[0] & 0xF7; //Clear Bit 3
1700 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1702 // set MCU clock,SPI clock =FRO
1703 dbbus_tx_data[0] = 0x10;
1704 dbbus_tx_data[1] = 0x1E;
1705 dbbus_tx_data[2] = 0x22;
1706 dbbus_tx_data[3] = 0x00;
1707 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1709 dbbus_tx_data[0] = 0x10;
1710 dbbus_tx_data[1] = 0x1E;
1711 dbbus_tx_data[2] = 0x23;
1712 dbbus_tx_data[3] = 0x00;
1713 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1715 // Enable slave's ISP ECO mode
1716 dbbus_tx_data[0] = 0x10;
1717 dbbus_tx_data[1] = 0x08;
1718 dbbus_tx_data[2] = 0x0c;
1719 dbbus_tx_data[3] = 0x08;
1720 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1723 dbbus_tx_data[0] = 0x10;
1724 dbbus_tx_data[1] = 0x1E;
1725 dbbus_tx_data[2] = 0x02;
1726 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 3 );
1727 HalTscrCReadI2CSeq ( FW_ADDR_MSG21XX, &dbbus_rx_data[0], 2 );
1728 TP_DEBUG ( "dbbus_rx_data[0]=0x%x", dbbus_rx_data[0] );
1729 dbbus_tx_data[3] = ( dbbus_rx_data[0] | 0x20 ); //Set Bit 5
1730 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1733 dbbus_tx_data[0] = 0x10;
1734 dbbus_tx_data[1] = 0x1E;
1735 dbbus_tx_data[2] = 0x0E;
1736 dbbus_tx_data[3] = 0x02;
1737 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1740 dbbus_tx_data[0] = 0x10;
1741 dbbus_tx_data[1] = 0x1E;
1742 dbbus_tx_data[2] = 0x10;
1743 dbbus_tx_data[3] = 0x08;
1744 HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 4 );
1746 dbbusDWIICIICNotUseBus();
1747 dbbusDWIICNotStopMCU();
1748 dbbusDWIICExitSerialDebugMode();
1750 ///////////////////////////////////////
1751 // Start to load firmware
1752 ///////////////////////////////////////
1753 drvISP_EntryIspMode();
1755 for ( i = 0; i < 94; i++ ) // total 94 KB : 1 byte per R/W
1757 drvISP_Program ( i, temp[i] ); // program to slave's flash
1758 drvISP_Verify ( i, temp[i] ); //verify data
1760 TP_DEBUG ( "update OK\n" );
1761 drvISP_ExitIspMode();
1767 static DEVICE_ATTR(update, 0664, firmware_update_show, firmware_update_store);
1769 /*test=================*/
1770 static ssize_t firmware_clear_show(struct device *dev,
1771 struct device_attribute *attr, char *buf)
1773 printk(" +++++++ [%s] Enter!++++++\n", __func__);
1774 u16 k=0,i = 0, j = 0;
1780 u8 bWriteData1 = 0x12;
1783 for (k = 0; k < 94; i++) // total 94 KB : 1 byte per R/W
1786 for (j = 0; j < 8; j++) //128*8 cycle
1788 bWriteData[2] = (u8)((addr + j * 128) >> 16);
1789 bWriteData[3] = (u8)((addr + j * 128) >> 8);
1790 bWriteData[4] = (u8)(addr + j * 128);
1791 //msctpc_LoopDelay ( 1 ); // delay about 100us*****
1795 while ( ( drvISP_ReadStatus() & 0x01 ) == 0x01 )
1798 if ( timeOutCount >= 100000 )
1799 break; /* around 1 sec timeout */
1802 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, bWriteData, 5); //write read flash addr
1803 //msctpc_LoopDelay ( 1 ); // delay about 100us*****
1805 drvISP_Read(128, RX_data);
1806 HalTscrCDevWriteI2CSeq(FW_UPDATE_ADDR_MSG21XX, &bWriteData1, 1); //cmd end
1807 for (i = 0; i < 128; i++) //log out if verify error
1809 if (RX_data[i] != 0xFF)
1811 //TP_DEBUG(printk("k=%d,j=%d,i=%d===============erase not clean================",k,j,i);)
1812 printk("k=%d,j=%d,i=%d erase not clean !!",k,j,i);
1817 TP_DEBUG("read finish\n");
1818 return sprintf(buf, "%s\n", fw_version);
1821 static ssize_t firmware_clear_store(struct device *dev,
1822 struct device_attribute *attr, const char *buf, size_t size)
1825 u8 dbbus_tx_data[4];
1826 unsigned char dbbus_rx_data[2] = {0};
1827 printk(" +++++++ [%s] Enter!++++++\n", __func__);
1828 //msctpc_LoopDelay ( 100 ); // delay about 100ms*****
1830 // Enable slave's ISP ECO mode
1832 dbbus_tx_data[0] = 0x10;
1833 dbbus_tx_data[1] = 0x08;
1834 dbbus_tx_data[2] = 0x0c;
1835 dbbus_tx_data[3] = 0x08;
1837 // Disable the Watchdog
1838 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, dbbus_tx_data, 4);
1840 dbbus_tx_data[0] = 0x10;
1841 dbbus_tx_data[1] = 0x11;
1842 dbbus_tx_data[2] = 0xE2;
1843 dbbus_tx_data[3] = 0x00;
1844 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, dbbus_tx_data, 4);
1846 dbbus_tx_data[0] = 0x10;
1847 dbbus_tx_data[1] = 0x3C;
1848 dbbus_tx_data[2] = 0x60;
1849 dbbus_tx_data[3] = 0x55;
1850 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, dbbus_tx_data, 4);
1852 dbbus_tx_data[0] = 0x10;
1853 dbbus_tx_data[1] = 0x3C;
1854 dbbus_tx_data[2] = 0x61;
1855 dbbus_tx_data[3] = 0xAA;
1856 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, dbbus_tx_data, 4);
1859 dbbus_tx_data[0] = 0x10;
1860 dbbus_tx_data[1] = 0x0F;
1861 dbbus_tx_data[2] = 0xE6;
1862 dbbus_tx_data[3] = 0x01;
1863 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, dbbus_tx_data, 4);
1866 dbbus_tx_data[0] = 0x10;
1867 dbbus_tx_data[1] = 0x1E;
1868 dbbus_tx_data[2] = 0x02;
1869 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, dbbus_tx_data, 3);
1870 HalTscrCReadI2CSeq(FW_ADDR_MSG21XX, &dbbus_rx_data[0], 2);
1871 TP_DEBUG(printk("dbbus_rx_data[0]=0x%x", dbbus_rx_data[0]);)
1872 dbbus_tx_data[3] = (dbbus_rx_data[0] | 0x20); //Set Bit 5
1873 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, dbbus_tx_data, 4);
1875 dbbus_tx_data[0] = 0x10;
1876 dbbus_tx_data[1] = 0x1E;
1877 dbbus_tx_data[2] = 0x25;
1878 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, dbbus_tx_data, 3);
1880 dbbus_rx_data[0] = 0;
1881 dbbus_rx_data[1] = 0;
1882 HalTscrCReadI2CSeq(FW_ADDR_MSG21XX, &dbbus_rx_data[0], 2);
1883 TP_DEBUG(printk("dbbus_rx_data[0]=0x%x", dbbus_rx_data[0]);)
1884 dbbus_tx_data[3] = dbbus_rx_data[0] & 0xFC; //Clear Bit 1,0
1885 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, dbbus_tx_data, 4);
1888 dbbus_tx_data[0] = 0x10;
1889 dbbus_tx_data[1] = 0x1E;
1890 dbbus_tx_data[2] = 0x0E;
1891 dbbus_tx_data[3] = 0x02;
1892 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, dbbus_tx_data, 4);
1896 dbbus_tx_data[0] = 0x10;
1897 dbbus_tx_data[1] = 0x1E;
1898 dbbus_tx_data[2] = 0x10;
1899 dbbus_tx_data[3] = 0x08;
1900 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, dbbus_tx_data, 4);
1902 dbbus_tx_data[0] = 0x10;
1903 dbbus_tx_data[1] = 0x11;
1904 dbbus_tx_data[2] = 0xE2;
1905 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, dbbus_tx_data, 3);
1906 dbbus_rx_data[0] = 0;
1907 dbbus_rx_data[1] = 0;
1908 HalTscrCReadI2CSeq(FW_ADDR_MSG21XX, &dbbus_rx_data[0], 2);
1909 TP_DEBUG(printk("dbbus_rx_data[0]=0x%x", dbbus_rx_data[0]);)
1910 dbbus_tx_data[3] = dbbus_rx_data[0] & 0xF7; //Clear Bit 1,0
1911 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX, dbbus_tx_data, 4);
1913 dbbusDWIICIICNotUseBus();
1914 dbbusDWIICNotStopMCU();
1915 dbbusDWIICExitSerialDebugMode();
1917 ///////////////////////////////////////
1918 // Start to load firmware
1919 ///////////////////////////////////////
1920 drvISP_EntryIspMode();
1921 TP_DEBUG(printk("chip erase+\n");)
1922 drvISP_BlockErase(0x00000);
1923 TP_DEBUG(printk("chip erase-\n");)
1924 drvISP_ExitIspMode();
1927 static DEVICE_ATTR(clear, 0664, firmware_clear_show, firmware_clear_store);
1929 /*test=================*/
1930 /*Add by Tracy.Lin for update touch panel firmware and get fw version*/
1932 static ssize_t firmware_version_show(struct device *dev,
1933 struct device_attribute *attr, char *buf)
1935 TP_DEBUG("*** firmware_version_show fw_version = %s***\n", fw_version);
1936 return sprintf(buf, "%s\n", fw_version);
1939 static ssize_t firmware_version_store(struct device *dev,
1940 struct device_attribute *attr, const char *buf, size_t size)
1942 unsigned char dbbus_tx_data[3];
1943 unsigned char dbbus_rx_data[4] ;
1944 unsigned short major=0, minor=0;
1946 dbbusDWIICEnterSerialDebugMode();
1947 dbbusDWIICStopMCU();
1948 dbbusDWIICIICUseBus();
1949 dbbusDWIICIICReshape();
1952 if(NULL==fw_version)
1954 fw_version = kzalloc(sizeof(char), GFP_KERNEL);
1957 //Get_Chip_Version();
1958 dbbus_tx_data[0] = 0x53;
1959 dbbus_tx_data[1] = 0x00;
1960 dbbus_tx_data[2] = 0x2a;
1961 HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX_TP, &dbbus_tx_data[0], 3);
1962 HalTscrCReadI2CSeq(FW_ADDR_MSG21XX_TP, &dbbus_rx_data[0], 4);
1964 major = (dbbus_rx_data[1]<<8)+dbbus_rx_data[0];
1965 minor = (dbbus_rx_data[3]<<8)+dbbus_rx_data[2];
1967 TP_DEBUG("***major = %d ***\n", major);
1968 TP_DEBUG("***minor = %d ***\n", minor);
1969 sprintf(fw_version,"%03d%03d", major, minor);
1970 //TP_DEBUG(printk("***fw_version = %s ***\n", fw_version);)
1974 static DEVICE_ATTR(version, 0664, firmware_version_show, firmware_version_store);
1976 static ssize_t firmware_data_show(struct device *dev,
1977 struct device_attribute *attr, char *buf)
1982 static ssize_t firmware_data_store(struct device *dev,
1983 struct device_attribute *attr, const char *buf, size_t size)
1986 TP_DEBUG("***FwDataCnt = %d ***\n", FwDataCnt);
1987 for (i = 0; i < 1024; i++)
1989 memcpy(temp[FwDataCnt], buf, 1024);
1994 static DEVICE_ATTR(data, 0664, firmware_data_show, firmware_data_store);
1995 #endif //__FIRMWARE_UPDATE__
1997 static int pixcir_i2c_txdata(char *txdata, int length)
2000 struct i2c_msg msg[] = {
2002 .addr = msg21xx_i2c_client->addr,
2009 ret = i2c_transfer(msg21xx_i2c_client->adapter, msg, 1);
2011 pr_err("%s i2c write error: %d\n", __func__, ret);
2016 static int pixcir_i2c_write_data(unsigned char addr, unsigned char data)
2018 unsigned char buf[2];
2021 return pixcir_i2c_txdata(buf, 2);
2024 static bool msg2138_i2c_read(char *pbt_buf, int dw_lenth)
2027 // pr_ch("The msg_i2c_client->addr=0x%x\n",i2c_client->addr);
2028 ret = i2c_master_recv(msg21xx_i2c_client, pbt_buf, dw_lenth);
2032 //pr_tp("msg_i2c_read_interface error\n");
2039 static bool msg2138_i2c_write(char *pbt_buf, int dw_lenth)
2042 // pr_ch("The msg_i2c_client->addr=0x%x\n",i2c_client->addr);
2043 ret = i2c_master_send(msg21xx_i2c_client, pbt_buf, dw_lenth);
2047 //pr_tp("msg_i2c_read_interface error\n");
2054 static DEVICE_ATTR(calibrate, S_IRUGO | S_IWUSR, NULL, pixcir_set_calibrate);
2055 static DEVICE_ATTR(suspend, S_IRUGO | S_IWUSR, pixcir_show_suspend, pixcir_store_suspend);
2057 static ssize_t pixcir_set_calibrate(struct device* cd, struct device_attribute *attr,
2058 const char* buf, size_t len)
2060 unsigned long on_off = simple_strtoul(buf, NULL, 10);
2064 printk("%s: PIXCIR calibrate\n",__func__);
2065 pixcir_i2c_write_data(0x3a , 0x03);
2072 static ssize_t pixcir_show_suspend(struct device* cd,
2073 struct device_attribute *attr, char* buf)
2078 sprintf(buf, "Pixcir Suspend\n");
2080 sprintf(buf, "Pixcir Resume\n");
2082 ret = strlen(buf) + 1;
2087 static ssize_t pixcir_store_suspend(struct device* cd, struct device_attribute *attr,
2088 const char* buf, size_t len)
2090 unsigned long on_off = simple_strtoul(buf, NULL, 10);
2091 suspend_flag = on_off;
2095 printk("Pixcir Entry Suspend\n");
2096 pixcir_ts_suspend(NULL);
2100 printk("Pixcir Entry Resume\n");
2101 pixcir_ts_resume(NULL);
2108 static void pixcir_reset(void)
2110 struct msg2138_ts_platform_data *pdata = msg21xx_i2c_ts_data->platform_data;
2112 PIXCIR_DBG("%s\n",__func__);
2113 gpio_set_value(pdata->reset_gpio_number, 1);
2115 gpio_set_value(pdata->reset_gpio_number, 0);
2117 gpio_set_value(pdata->reset_gpio_number, 1);
2123 static void cg_tpfwver_readfwver()
2125 unsigned char dbbus_tx_data[3];
2126 unsigned char dbbus_rx_data[4] ;
2127 unsigned short major=0, minor=0;
2131 for(count=0;count<5;count++)
2135 if(NULL == cg_fw_version)
2137 cg_fw_version = kzalloc(sizeof(char), GFP_KERNEL);
2140 //Get_Chip_Version();
2141 dbbus_tx_data[0] = 0x53;
2142 dbbus_tx_data[1] = 0x00;
2143 dbbus_tx_data[2] = 0x2a;
2144 ret = HalTscrCDevWriteI2CSeq(FW_ADDR_MSG21XX_TP, &dbbus_tx_data[0], 3);
2147 printk("*** write fail ret = %d ***\n", ret);
2151 ret = HalTscrCReadI2CSeq(FW_ADDR_MSG21XX_TP, &dbbus_rx_data[0], 4);
2154 printk("*** read fail ret = %d ***\n", ret);
2157 major =(dbbus_rx_data[1]<<8)+dbbus_rx_data[0];
2160 printk("*** major fail = %d ***\n", major);
2163 minor =(dbbus_rx_data[3]<<8)+dbbus_rx_data[2];
2164 printk("***major = %d ***\n", major);
2165 printk("***minor = %d ***\n", minor);
2167 sprintf(cg_fw_version,"%03d%03d", major, minor);
2168 printk("***tp_fw_version = %s ***\n", cg_fw_version);
2171 printk("*** count = %d ***\n", count);
2174 static ssize_t cg_tpfwver_show(struct device *dev,
2175 struct device_attribute *attr, char *buf)
2177 cg_tpfwver_readfwver();
2178 return sprintf(buf, "%s\n", cg_fw_version);
2182 static ssize_t cg_tpfwver_store(struct device *dev,
2183 struct device_attribute *attr, const char *buf, size_t size)
2188 static DEVICE_ATTR(fwversion, S_IRUGO, cg_tpfwver_show,NULL);
2193 static int pixcir_create_sysfs(struct i2c_client *client)
2196 struct device *dev = &(client->dev);
2198 PIXCIR_DBG("%s\n", __func__);
2200 err = device_create_file(dev, &dev_attr_calibrate);
2201 err = device_create_file(dev, &dev_attr_suspend);
2203 err = device_create_file(dev, &dev_attr_fwversion); //cg,20130929
2208 #ifdef CONFIG_HAS_EARLYSUSPEND
2209 static void pixcir_ts_suspend(struct early_suspend *handler)
2211 struct msg2138_ts_platform_data *pdata = msg21xx_i2c_ts_data->platform_data;
2212 printk("==%s==\n", __func__);
2213 disable_irq_nosync(global_irq);
2215 gpio_set_value(pdata->reset_gpio_number, 0);
2218 static void pixcir_ts_resume(struct early_suspend *handler)
2220 //unsigned char rdbuf[27];
2222 //disable_irq_nosync(global_irq);
2225 struct pixcir_i2c_ts_data *pixcir_ts = (struct pixcir_i2c_ts_data *)i2c_get_clientdata(msg21xx_i2c_client);
2226 queue_work(pixcir_ts->ts_resume_workqueue, &pixcir_ts->resume_work);
2228 printk("==%s==start==\n", __func__);
2230 enable_irq(global_irq);
2231 printk("==%s==end==\n", __func__);
2236 #ifdef TOUCH_VIRTUAL_KEYS
2237 /*static ssize_t virtual_keys_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
2240 __stringify(EV_KEY) ":" __stringify(KEY_HOMEPAGE) ":192:1000:64:60"
2241 ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":256:1000:64:60"
2242 ":" __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":128:1000:64:60"
2243 ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":64:1000:64:60"
2246 static ssize_t virtual_keys_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
2248 struct pixcir_i2c_ts_data *data = i2c_get_clientdata(msg21xx_i2c_client);
2249 struct msg2138_ts_platform_data *pdata = data->platform_data;
2250 return sprintf(buf,"%s:%s:%d:%d:%d:%d:%s:%s:%d:%d:%d:%d:%s:%s:%d:%d:%d:%d\n"
2251 ,__stringify(EV_KEY), __stringify(KEY_MENU),pdata ->virtualkeys[0],pdata ->virtualkeys[1],pdata ->virtualkeys[2],pdata ->virtualkeys[3]
2252 ,__stringify(EV_KEY), __stringify(KEY_HOMEPAGE),pdata ->virtualkeys[4],pdata ->virtualkeys[5],pdata ->virtualkeys[6],pdata ->virtualkeys[7]
2253 ,__stringify(EV_KEY), __stringify(KEY_BACK),pdata ->virtualkeys[8],pdata ->virtualkeys[9],pdata ->virtualkeys[10],pdata ->virtualkeys[11]);
2256 static struct kobj_attribute virtual_keys_attr = {
2258 .name = "virtualkeys.msg2138_ts",
2261 .show = &virtual_keys_show,
2264 static struct attribute *properties_attrs[] = {
2265 &virtual_keys_attr.attr,
2269 static struct attribute_group properties_attr_group = {
2270 .attrs = properties_attrs,
2273 static void pixcir_ts_virtual_keys_init(void)
2276 struct kobject *properties_kobj;
2278 PIXCIR_DBG("%s\n",__func__);
2280 properties_kobj = kobject_create_and_add("board_properties", NULL);
2281 if (properties_kobj)
2282 ret = sysfs_create_group(properties_kobj,
2283 &properties_attr_group);
2284 if (!properties_kobj || ret)
2285 pr_err("failed to create board_properties\n");
2289 static int getchipType(void)
2291 int curr_ic_type = 0;
2292 u8 dbbus_tx_data[4];
2293 unsigned char dbbus_rx_data[2] = {0};
2297 dbbus_tx_data[0] = 0x10;
2298 dbbus_tx_data[1] = 0x1E;
2299 dbbus_tx_data[2] = 0xCC;
2300 error = HalTscrCDevWriteI2CSeq ( FW_ADDR_MSG21XX, dbbus_tx_data, 3 );
2302 pr_err("[MSG2138A] getchipType() write i2c error %d\n",error);
2305 error = HalTscrCReadI2CSeq ( FW_ADDR_MSG21XX, &dbbus_rx_data[0], 2 );
2307 pr_err("[MSG2138A] getchipType() read i2c error %d\n",error);
2310 if ( dbbus_rx_data[0] == 2 ) {
2311 curr_ic_type = CTP_ID_MSG21XXA;
2313 curr_ic_type = CTP_ID_MSG21XX;
2316 return curr_ic_type;
2320 static void pixcir_ts_hw_init(struct pixcir_i2c_ts_data *tsdata)
2322 struct regulator *g_cg_reg_vdd;
2323 struct msg2138_ts_platform_data *pdata = tsdata->platform_data;
2324 struct i2c_client *client = tsdata->client;
2326 gpio_request(pdata->reset_gpio_number, "gpio_tp_rst");
2327 gpio_request(pdata->irq_gpio_number, "gpio_tp_irq");
2328 gpio_direction_output(pdata->reset_gpio_number,1);
2329 gpio_direction_input(pdata->irq_gpio_number);
2330 g_cg_reg_vdd = regulator_get(&client->dev, pdata->vdd_name);
2331 if (!WARN(IS_ERR(g_cg_reg_vdd), "[MSG2138] pixcir_ts_hw_init regulator: failed to get %s.\n", pdata->vdd_name)) {
2332 regulator_set_voltage(g_cg_reg_vdd, 2800000, 2800000);
2333 err = regulator_enable(g_cg_reg_vdd);
2339 /*static int attb_read_val(void)
2341 struct msg2138_ts_platform_data *pdata = msg21xx_i2c_ts_data->platform_data;
2342 return gpio_get_value(pdata->irq_gpio_number);
2345 unsigned char tpd_check_sum(unsigned char *pval)
2349 for(i = 0; i < 7; i++)
2354 return (unsigned char)((-sum) & 0xFF);
2357 static void return_i2c_dev(struct i2c_dev *i2c_dev)
2359 spin_lock(&i2c_dev_list_lock);
2360 list_del(&i2c_dev->list);
2361 spin_unlock(&i2c_dev_list_lock);
2365 static struct i2c_dev *i2c_dev_get_by_minor(unsigned index)
2367 struct i2c_dev *i2c_dev;
2370 spin_lock(&i2c_dev_list_lock);
2371 list_for_each_entry(i2c_dev, &i2c_dev_list, list)
2373 if (i2c_dev->adap->nr == index)
2377 found: spin_unlock(&i2c_dev_list_lock);
2381 static struct i2c_dev *get_free_i2c_dev(struct i2c_adapter *adap)
2383 struct i2c_dev *i2c_dev;
2385 if (adap->nr >= I2C_MINORS) {
2386 printk(KERN_ERR "i2c-dev: Out of device minors (%d)\n",
2388 return ERR_PTR(-ENODEV);
2391 i2c_dev = kzalloc(sizeof(*i2c_dev), GFP_KERNEL);
2393 return ERR_PTR(-ENOMEM);
2395 i2c_dev->adap = adap;
2397 spin_lock(&i2c_dev_list_lock);
2398 list_add_tail(&i2c_dev->list, &i2c_dev_list);
2399 spin_unlock(&i2c_dev_list_lock);
2402 /*********************************Bee-0928-bottom**************************************/
2404 struct point_node_t{
2405 unsigned char active ;
2406 unsigned char finger_id;
2411 static struct point_node_t point_slot[MAX_FINGER_NUM*2];
2413 static int sy_rxdata(struct touch_info *cinfo, struct touch_info *pinfo)
2416 //static unsigned char tt_mode;
2417 //pinfo->count = cinfo->count;
2418 unsigned char reg_val[8] = {0};
2419 int dst_x=0,dst_y=0;
2420 unsigned int temp_checksum;
2421 struct TouchScreenInfo_t touchData;
2422 //unsigned char touchkeycode = 0;
2423 //static int preKeyStatus;
2425 //TPD_DEBUG("pinfo->count =%d\n",pinfo->count);
2426 cinfo->count = 0; //touch end
2427 msg2138_i2c_read(reg_val, 8);
2429 //retval = i2c_smbus_read_i2c_block_data(msg21xx_i2c_client, TPD_REG_BASE, 8, (unsigned char *)&g_operation_data);
2430 //retval += i2c_smbus_read_i2c_block_data(msg21xx_i2c_client, TPD_REG_BASE + 8, 8, (((unsigned char *)(&g_operation_data)) + 8));
2432 cinfo->x1 = ((reg_val[1] & 0xF0) << 4) | reg_val[2];
2433 cinfo->y1 = ((reg_val[1] & 0x0F) << 8) | reg_val[3];
2434 dst_x = ((reg_val[4] & 0xF0) << 4) | reg_val[5];
2435 dst_y = ((reg_val[4] & 0x0F) << 8) | reg_val[6];
2438 temp_checksum = tpd_check_sum(reg_val);
2440 if((temp_checksum==reg_val[7])&&(reg_val[0] == 0x52))
2443 if ((reg_val[1] == 0xFF) && (reg_val[2] == 0xFF) && (reg_val[3] == 0xFF) && (reg_val[4] == 0xFF) && (reg_val[6] == 0xFF))
2445 cinfo->x1 = 0; // final X coordinate
2446 cinfo->y1 = 0; // final Y coordinate
2448 if((reg_val[5]==0x0)||(reg_val[5]==0xFF))
2450 cinfo->count = 0; //touch end
2451 touchData.nTouchKeyCode = 0; //TouchKeyMode
2452 touchData.nTouchKeyMode = 0; //TouchKeyMode
2457 touchData.nTouchKeyMode = 1; //TouchKeyMode
2458 touchData.nTouchKeyCode = reg_val[5]; //TouchKeyCode
2459 keycode= reg_val[5];
2463 cinfo->x1 = 256; // final X coordinate
2464 cinfo->y1 = 1000; // final Y coordinate
2469 cinfo->x1 = 192; // final X coordinate
2470 cinfo->y1 = 1000; // final Y coordinate
2473 else if (keycode==4)
2475 cinfo->x1 = 128; // final X coordinate
2476 cinfo->y1 = 1000; // final Y coordinate
2485 touchData.nTouchKeyMode = 0; //Touch on screen...
2487 if ((dst_x == 0) && (dst_y == 0))
2489 cinfo->count = 1; //one touch
2491 xysawp_temp=cinfo->x1;
2492 //cinfo->x1=2047-cinfo->y1;
2493 cinfo->x1=cinfo->y1;
2494 cinfo->y1=xysawp_temp;
2498 cinfo->x1 = 2047 - cinfo->x1;
2501 cinfo->x1 = (cinfo->x1 * MS_TS_MSG21XX_X_MAX) / 2048;
2502 cinfo->y1 = (cinfo->y1 * MS_TS_MSG21XX_Y_MAX) / 2048;
2507 cinfo->count = 2; //two touch
2510 if (dst_x > 2048) //transform the unsigh value to sign value
2519 cinfo->x2 = (cinfo->x1 + dst_x);
2520 cinfo->y2 = (cinfo->y1 + dst_y);
2523 xysawp_temp=cinfo->x1;
2524 //cinfo->x1=2047-cinfo->y1;
2525 cinfo->x1=cinfo->y1;
2526 cinfo->y1=xysawp_temp;
2528 xysawp_temp=cinfo->x2;
2529 cinfo->x2=2047-cinfo->y2;
2530 cinfo->y2=xysawp_temp;
2534 cinfo->x1 = 2047 - cinfo->x1;
2535 cinfo->x2 = 2047 - cinfo->x2;
2538 cinfo->x1 = (cinfo->x1 * MS_TS_MSG21XX_X_MAX) / 2048;
2539 cinfo->y1 = (cinfo->y1 * MS_TS_MSG21XX_Y_MAX) / 2048;
2541 cinfo->x2 = (cinfo->x2 * MS_TS_MSG21XX_X_MAX) / 2048;
2542 cinfo->y2 = (cinfo->y2 * MS_TS_MSG21XX_Y_MAX) / 2048;
2551 static void pixcir_ts_poscheck(struct pixcir_i2c_ts_data *data)
2553 struct pixcir_i2c_ts_data *tsdata = data;
2554 struct touch_info cinfo, pinfo;
2556 unsigned char touch;
2557 unsigned char rdbuf[27];
2559 //static int lastkey=0;
2560 // printk("===%s===\n",__func__);
2562 //pixcir_i2c_rxdata(rdbuf, 27);
2564 //touch = rdbuf[0]&0x07;
2565 sy_rxdata(&cinfo, &pinfo);
2566 touch = cinfo.count;
2567 //button = rdbuf[1];
2570 // printk("===touch:%d===",touch);
2571 for (i=0; i<touch; i++) {
2572 //pix_id = (*(p+4));
2573 //slot_id = ((pix_id & 7)<<1) | ((pix_id & 8)>>3);
2574 point_slot[i].active = 1;
2575 point_slot[i].finger_id = i;
2576 point_slot[i].posx = *(p+i*2);
2577 point_slot[i].posy = *(p+i*2+1);
2582 //input_report_key(tsdata->input, BTN_TOUCH, 1);
2583 //input_report_abs(tsdata->input, ABS_MT_TOUCH_MAJOR, 15);
2584 for (i=0; i<touch; i++) {
2585 if (point_slot[i].active == 1) {
2586 if(point_slot[i].posy<0) {
2588 if(point_slot[i].posx<0) {
2589 point_slot[i].posx = 0;
2590 } else if (point_slot[i].posx>(MS_TS_MSG21XX_X_MAX -2)) {
2591 point_slot[i].posx = (MS_TS_MSG21XX_X_MAX -2);
2593 input_report_abs(tsdata->input, ABS_MT_POSITION_X, point_slot[i].posx);
2594 input_report_abs(tsdata->input, ABS_MT_POSITION_Y, point_slot[i].posy);
2595 //input_report_abs(tsdata->input, ABS_MT_TOUCH_MAJOR, 15);
2596 //input_report_abs(tsdata->input, ABS_MT_WIDTH_MAJOR, 1);
2597 input_report_key(tsdata->input, BTN_TOUCH, 1);
2598 input_mt_sync(tsdata->input);
2599 PIXCIR_DBG("%s: slot=%d,x%d=%d,y%d=%d\n",__func__, i, i/2,point_slot[i].posx, i/2, point_slot[i].posy);
2604 PIXCIR_DBG("%s: release\n",__func__);
2606 //input_report_key(tsdata->input, BTN_TOUCH, 0);
2607 input_report_abs(tsdata->input, ABS_MT_TOUCH_MAJOR, 0);
2608 input_report_abs(tsdata->input, ABS_MT_WIDTH_MAJOR, 0);
2609 input_mt_sync(tsdata->input);
2611 input_report_key(tsdata->input, BTN_TOUCH, 0);
2612 input_mt_sync(tsdata->input);
2614 PIXCIR_DBG("%s: keycode =%x\n",__func__,keycode);
2616 if(lastkey!=keycode)
2620 input_report_key(tsdata->input, keymap[i], (keycode)&(1<<i));
2624 input_sync(tsdata->input);
2625 for (i=0; i<MAX_FINGER_NUM*2; i++) {
2626 if (point_slot[i].active == 0) {
2627 point_slot[i].posx = 0;
2628 point_slot[i].posy = 0;
2630 point_slot[i].active = 0;
2635 static int touch_event_handler(void *unused)
2637 struct sched_param param = { .sched_priority = 5 };
2639 struct pixcir_i2c_ts_data *tsdata = i2c_get_clientdata(msg21xx_i2c_client);
2640 sched_setscheduler(current, SCHED_RR, ¶m);
2643 set_current_state(TASK_INTERRUPTIBLE);
2644 wait_event_interruptible(waiter, (0 != tpd_flag));
2646 set_current_state(TASK_RUNNING);
2648 pixcir_ts_poscheck(tsdata);
2650 } while (!kthread_should_stop());
2656 static irqreturn_t pixcir_ts_isr(int irq, void *dev_id)
2660 wake_up_interruptible(&waiter);
2665 struct pixcir_i2c_ts_data *tsdata = dev_id;
2667 disable_irq_nosync(irq);
2669 // while (!tsdata->exiting) {
2670 pixcir_ts_poscheck(tsdata);
2671 #endif //cg,20140402
2673 if (attb_read_val()) {
2674 PIXCIR_DBG("%s: release\n",__func__);
2675 //input_report_key(tsdata->input, BTN_TOUCH, 0);
2676 input_report_abs(tsdata->input, ABS_MT_TOUCH_MAJOR, 0);
2677 input_sync(tsdata->input);
2690 #ifdef CONFIG_PM_SLEEP
2691 static int pixcir_i2c_ts_suspend(struct device *dev)
2693 struct i2c_client *client = to_i2c_client(dev);
2694 unsigned char wrbuf[2] = { 0 };
2698 wrbuf[1] = 0x03; //enter into freeze mode;
2699 /**************************************************************
2700 wrbuf[1]: 0x00: Active mode
2702 0xA4: Sleep mode automatically switch
2704 More details see application note 710 power manangement section
2705 ****************************************************************/
2706 ret = i2c_master_send(client, wrbuf, 2);
2708 dev_err(&client->dev,
2709 "%s: i2c_master_send failed(), ret=%d\n",
2713 if (device_may_wakeup(&client->dev))
2714 enable_irq_wake(client->irq);
2719 static int pixcir_i2c_ts_resume(struct device *dev)
2721 struct i2c_client *client = to_i2c_client(dev);
2722 ///if suspend enter into freeze mode please reset TP
2726 unsigned char wrbuf[2] = { 0 };
2731 ret = i2c_master_send(client, wrbuf, 2);
2733 dev_err(&client->dev,
2734 "%s: i2c_master_send failed(), ret=%d\n",
2738 if (device_may_wakeup(&client->dev))
2739 disable_irq_wake(client->irq);
2745 static SIMPLE_DEV_PM_OPS(pixcir_dev_pm_ops,
2746 pixcir_i2c_ts_suspend, pixcir_i2c_ts_resume);
2748 static int tpd_get_bl_info (int show)
2750 int retval = TPD_OK;
2752 retval = i2c_smbus_read_i2c_block_data(msg21xx_i2c_client, TPD_REG_BASE, 8, (unsigned char *)&g_bootloader_data);
2753 retval += i2c_smbus_read_i2c_block_data(msg21xx_i2c_client, TPD_REG_BASE + 8, 8, (((unsigned char *)&g_bootloader_data) + 8));
2754 TPD_DEBUG("ret=%d,first=0x%02x\n",retval,(unsigned char )(*((unsigned char *)&g_bootloader_data)));
2758 TPD_DEBUG("BL: bl_file = %02X, bl_status = %02X, bl_error = %02X, blver = %02X%02X, bld_blver = %02X%02X\n", \
2759 g_bootloader_data.bl_file, \
2760 g_bootloader_data.bl_status, \
2761 g_bootloader_data.bl_error, \
2762 g_bootloader_data.blver_hi, g_bootloader_data.blver_lo, \
2763 g_bootloader_data.bld_blver_hi, g_bootloader_data.bld_blver_lo);
2765 TPD_DEBUG("BL: ttspver = 0x%02X%02X, appid=0x%02X%02X, appver=0x%02X%02X\n", \
2766 g_bootloader_data.ttspver_hi, g_bootloader_data.ttspver_lo, \
2767 g_bootloader_data.appid_hi, g_bootloader_data.appid_lo, \
2768 g_bootloader_data.appver_hi, g_bootloader_data.appver_lo);
2770 TPD_DEBUG("BL: cid = 0x%02X%02X%02X\n", \
2771 g_bootloader_data.cid_0, \
2772 g_bootloader_data.cid_1, \
2773 g_bootloader_data.cid_2);
2782 static int sy_init(void)
2784 int retval = TPD_OK;
2786 unsigned char host_reg;
2787 host_reg = TPD_SOFT_RESET_MODE;
2788 // printk("==sy_init==0==");
2789 retval = i2c_smbus_write_i2c_block_data(msg21xx_i2c_client,TPD_REG_BASE,sizeof(host_reg),&host_reg);
2790 // printk("==sy_init==1==retval:%d==",retval);
2796 retval = tpd_get_bl_info(1);
2797 }while(!(retval < TPD_OK) && !GET_BOOTLOADERMODE(g_bootloader_data.bl_status)&&
2798 !(g_bootloader_data.bl_file == TPD_OP_MODE + TPD_LOW_PWR_MODE) && tries++ < 10);
2799 if(g_bootloader_data.bl_status != (unsigned char )0x11)
2803 host_reg = TPD_OP_MODE;
2804 retval = i2c_smbus_write_i2c_block_data(msg21xx_i2c_client,TPD_REG_BASE,sizeof(host_reg),&host_reg);
2809 TPD_DEBUG("Switch to sysinfo mode \n");
2810 host_reg = TPD_SYSINFO_MODE;
2811 retval = i2c_smbus_write_i2c_block_data(msg21xx_i2c_client,TPD_REG_BASE,sizeof(host_reg),&host_reg);
2814 if(!(retval < TPD_OK))
2816 retval = i2c_smbus_read_i2c_block_data(msg21xx_i2c_client,TPD_REG_BASE, 8, (unsigned char *)&g_sysinfo_data);
2817 retval += i2c_smbus_read_i2c_block_data(msg21xx_i2c_client,TPD_REG_BASE + 8, 8, (((unsigned char *)(&g_sysinfo_data)) + 8));
2818 retval += i2c_smbus_read_i2c_block_data(msg21xx_i2c_client,TPD_REG_BASE + 16, 8, (((unsigned char *)(&g_sysinfo_data)) + 16));
2819 retval += i2c_smbus_read_i2c_block_data (msg21xx_i2c_client,TPD_REG_BASE + 24, 8, (((unsigned char *)(&g_sysinfo_data)) + 24));
2821 TPD_DEBUG("SI: hst_mode = 0x%02X, mfg_cmd = 0x%02X, mfg_stat = 0x%02X\n", \
2822 g_sysinfo_data.hst_mode, \
2823 g_sysinfo_data.mfg_cmd, \
2824 g_sysinfo_data.mfg_stat);
2825 TPD_DEBUG("SI: bl_ver = 0x%02X%02X\n", \
2826 g_sysinfo_data.bl_verh, \
2827 g_sysinfo_data.bl_verl);
2828 TPD_DEBUG("SI: act_int = 0x%02X, tch_tmout = 0x%02X, lp_int = 0x%02X\n", \
2829 g_sysinfo_data.act_intrvl, \
2830 g_sysinfo_data.tch_tmout, \
2831 g_sysinfo_data.lp_intrvl);
2832 TPD_DEBUG("SI: tver = %02X%02X, a_id = %02X%02X, aver = %02X%02X\n", \
2833 g_sysinfo_data.tts_verh, \
2834 g_sysinfo_data.tts_verl, \
2835 g_sysinfo_data.app_idh, \
2836 g_sysinfo_data.app_idl, \
2837 g_sysinfo_data.app_verh, \
2838 g_sysinfo_data.app_verl);
2839 TPD_DEBUG("SI: c_id = %02X%02X%02X\n", \
2840 g_sysinfo_data.cid[0], \
2841 g_sysinfo_data.cid[1], \
2842 g_sysinfo_data.cid[2]);
2845 TPD_DEBUG("Switch back to operational mode \n");
2846 if (!(retval < TPD_OK))
2848 host_reg = TPD_OP_MODE;
2849 retval = i2c_smbus_write_i2c_block_data(msg21xx_i2c_client, TPD_REG_BASE, sizeof(host_reg), &host_reg);
2856 //update_support = 1;
2857 TPD_DEBUG("Switch back to operational mode \n");
2859 if (!(retval < TPD_OK))
2861 unsigned char op_cmds[] = {0x00, 0x00, 0xFF, 0xA5, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07};
2862 //retval = i2c_master_send_ext(i2c_client, op_cmds, sizeof(op_cmds));
2863 retval = i2c_master_send(msg21xx_i2c_client,op_cmds, sizeof(op_cmds));
2876 static void ito_test_create_entry(void);
2880 static struct msg2138_ts_platform_data *pixcir_ts_parse_dt(struct device *dev)
2882 struct msg2138_ts_platform_data *pdata = NULL;
2883 struct device_node *np = dev->of_node;
2886 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
2888 dev_err(dev, "Could not allocate struct msg2138_ts_platform_data");
2891 pdata->reset_gpio_number = of_get_gpio(np, 0);
2892 if(pdata->reset_gpio_number < 0){
2893 dev_err(dev, "fail to get reset_gpio_number\n");
2896 pdata->irq_gpio_number = of_get_gpio(np, 1);
2897 if(pdata->irq_gpio_number < 0){
2898 dev_err(dev, "fail to get irq_gpio_number\n");
2901 ret = of_property_read_string(np, "vdd_name", &pdata->vdd_name);
2903 dev_err(dev, "fail to get vdd_name\n");
2906 ret = of_property_read_u32_array(np, "virtualkeys", &pdata->virtualkeys,12);
2908 dev_err(dev, "fail to get virtualkeys\n");
2911 ret = of_property_read_u32(np, "TP_MAX_X", &pdata->TP_MAX_X);
2913 dev_err(dev, "fail to get TP_MAX_X\n");
2916 ret = of_property_read_u32(np, "TP_MAX_Y", &pdata->TP_MAX_Y);
2918 dev_err(dev, "fail to get TP_MAX_Y\n");
2929 static int pixcir_i2c_ts_probe(struct i2c_client *client,const struct i2c_device_id *id)
2931 struct msg2138_ts_platform_data *pdata = client->dev.platform_data;
2932 struct pixcir_i2c_ts_data *tsdata = NULL;
2933 struct input_dev *input = NULL;
2934 struct device *dev = NULL;
2935 struct i2c_dev *i2c_dev = NULL;
2938 printk("msg2138 probe in! \n");
2941 struct device_node *np = client->dev.of_node;
2943 pdata = pixcir_ts_parse_dt(&client->dev);
2945 client->dev.platform_data = pdata;
2949 goto exit_alloc_platform_data_failed;
2954 tsdata = kzalloc(sizeof(*tsdata), GFP_KERNEL);
2957 dev_err(&client->dev, "Failed to allocate tsdata!\n");
2958 goto exit_alloc_tsdata_failed;
2961 msg21xx_i2c_client = client;
2962 tsdata->client = client;
2963 msg21xx_i2c_ts_data = tsdata;
2964 tsdata->platform_data = pdata;
2965 MS_TS_MSG21XX_X_MAX = pdata->TP_MAX_X;
2966 MS_TS_MSG21XX_Y_MAX = pdata->TP_MAX_Y;
2967 //client->addr = 0x26;
2968 pixcir_ts_hw_init(tsdata);
2969 client->irq = gpio_to_irq(pdata->irq_gpio_number);
2970 i2c_set_clientdata(client, tsdata);
2972 #if defined(CONFIG_I2C_SPRD) || defined(CONFIG_I2C_SPRD_V1)
2973 sprd_i2c_ctl_chg_clk(client->adapter->nr, 400000);
2976 error = getchipType();
2978 pr_err("[MSG2138A] read chip id failed\n");
2980 goto exit_chip_check_failed;
2982 printk("[MSG2138A] the chip id is %d\n",error);
2985 for(i=0; i<MAX_FINGER_NUM*2; i++) {
2986 point_slot[i].active = 0;
2991 input = input_allocate_device();
2993 dev_err(&client->dev, "Failed to allocate input device!\n");
2995 goto exit_input_alloc_failed;
2998 #ifdef TOUCH_VIRTUAL_KEYS
2999 pixcir_ts_virtual_keys_init();
3002 tsdata->input = input;
3003 global_irq = client->irq;
3004 input->name = MSG2138_TS_NAME;
3005 input->id.bustype = BUS_I2C;
3006 input->dev.parent = &client->dev;
3008 __set_bit(EV_KEY, input->evbit);
3009 __set_bit(EV_ABS, input->evbit);
3010 __set_bit(EV_SYN, input->evbit);
3011 //__set_bit(BTN_TOUCH, input->keybit);
3012 __set_bit(ABS_MT_TOUCH_MAJOR, input->absbit);
3013 __set_bit(ABS_MT_POSITION_X, input->absbit);
3014 __set_bit(ABS_MT_POSITION_Y, input->absbit);
3015 __set_bit(ABS_MT_WIDTH_MAJOR, input->absbit);
3017 __set_bit(KEY_MENU, input->keybit);
3018 __set_bit(KEY_BACK, input->keybit);
3019 __set_bit(KEY_HOME, input->keybit);
3020 __set_bit(KEY_SEARCH, input->keybit);
3022 input_set_abs_params(input, ABS_MT_POSITION_X, 0, pdata->TP_MAX_X, 0, 0);
3023 input_set_abs_params(input, ABS_MT_POSITION_Y, 0, pdata->TP_MAX_Y, 0, 0);
3024 input_set_abs_params(input, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
3025 input_set_abs_params(input, ABS_MT_WIDTH_MAJOR, 0, 255, 0, 0);
3026 input_set_drvdata(input, tsdata);
3028 error = request_irq(client->irq, pixcir_ts_isr,
3029 IRQF_TRIGGER_FALLING, client->name, tsdata);
3031 dev_err(&client->dev, "Unable to request touchscreen IRQ.\n");
3032 goto exit_requst_irq_failed;
3034 disable_irq_nosync(client->irq);
3036 error = input_register_device(input);
3038 goto exit_input_register_failed;
3039 device_init_wakeup(&client->dev, 1);
3041 /*********************************Bee-0928-TOP****************************************/
3042 i2c_dev = get_free_i2c_dev(client->adapter);
3043 if (IS_ERR(i2c_dev)) {
3044 error = PTR_ERR(i2c_dev);
3045 goto exit_get_i2c_dev_failed;
3048 dev = device_create(i2c_dev_class, &client->adapter->dev, MKDEV(I2C_MAJOR,
3049 client->adapter->nr), NULL, "pixcir_i2c_ts%d", 0);
3051 error = PTR_ERR(dev);
3052 goto exit_device_create_failed;
3054 /*********************************Bee-0928-BOTTOM****************************************/
3055 #ifdef CONFIG_HAS_EARLYSUSPEND
3056 pixcir_early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1;
3057 pixcir_early_suspend.suspend = pixcir_ts_suspend;
3058 pixcir_early_suspend.resume = pixcir_ts_resume;
3059 register_early_suspend(&pixcir_early_suspend);
3062 /********* frameware upgrade *********/
3063 #ifdef __FIRMWARE_UPDATE__
3064 firmware_class = class_create(THIS_MODULE, "ms-touchscreen-msg20xx");
3065 if (IS_ERR(firmware_class))
3066 pr_err("Failed to create class(firmware)!\n");
3067 firmware_cmd_dev = device_create(firmware_class,
3068 NULL, 0, NULL, "device");
3069 if (IS_ERR(firmware_cmd_dev))
3070 pr_err("Failed to create device(firmware_cmd_dev)!\n");
3073 if (device_create_file(firmware_cmd_dev, &dev_attr_version) < 0)
3074 pr_err("Failed to create device file(%s)!\n", dev_attr_version.attr.name);
3076 if (device_create_file(firmware_cmd_dev, &dev_attr_update) < 0)
3077 pr_err("Failed to create device file(%s)!\n", dev_attr_update.attr.name);
3079 if (device_create_file(firmware_cmd_dev, &dev_attr_data) < 0)
3080 pr_err("Failed to create device file(%s)!\n", dev_attr_data.attr.name);
3082 // if (device_create_file(firmware_cmd_dev, &dev_attr_clear) < 0)
3083 // pr_err("Failed to create device file(%s)!\n", dev_attr_clear.attr.name);
3085 dev_set_drvdata(firmware_cmd_dev, NULL);
3086 #endif //__FIRMWARE_UPDATE__
3088 ito_test_create_entry();
3091 error = pixcir_create_sysfs(client);
3093 dev_err(&client->dev, "insmod successfully!\n");
3094 goto exit_create_sysfs_failed;
3098 cg_tpfwver_readfwver();
3099 #endif //cg,20130929
3102 thread = kthread_run(touch_event_handler, 0, "pixcir-wait-queue");
3105 error = PTR_ERR(thread);
3106 dev_err(&client->dev, "failed to create kernel thread\n");
3107 goto exit_kthread_run_failed;
3111 enable_irq(client->irq);
3113 printk("[MSG2138A]pixcir_i2c probe success\n");
3116 exit_kthread_run_failed:
3117 exit_create_sysfs_failed:
3118 exit_device_create_failed:
3119 exit_get_i2c_dev_failed:
3120 input_unregister_device(input);
3121 exit_input_register_failed:
3122 free_irq(client->irq, tsdata);
3123 exit_requst_irq_failed:
3124 input_free_device(input);
3125 exit_input_alloc_failed:
3126 exit_chip_check_failed:
3127 gpio_free(pdata->irq_gpio_number);
3128 gpio_free(pdata->reset_gpio_number);
3130 exit_alloc_tsdata_failed:
3133 exit_alloc_platform_data_failed:
3137 static int pixcir_i2c_ts_remove(struct i2c_client *client)
3140 struct i2c_dev *i2c_dev;
3141 struct pixcir_i2c_ts_data *tsdata = i2c_get_clientdata(client);
3143 device_init_wakeup(&client->dev, 0);
3145 tsdata->exiting = true;
3147 free_irq(client->irq, tsdata);
3149 /*********************************Bee-0928-TOP****************************************/
3150 i2c_dev = get_free_i2c_dev(client->adapter);
3151 if (IS_ERR(i2c_dev)) {
3152 error = PTR_ERR(i2c_dev);
3156 return_i2c_dev(i2c_dev);
3157 device_destroy(i2c_dev_class, MKDEV(I2C_MAJOR, client->adapter->nr));
3158 /*********************************Bee-0928-BOTTOM****************************************/
3159 unregister_early_suspend(&pixcir_early_suspend);
3160 input_unregister_device(tsdata->input);
3166 /*************************************Bee-0928****************************************/
3168 /*************************************Bee-0928****************************************/
3169 static int pixcir_open(struct inode *inode, struct file *file)
3172 struct i2c_client *client;
3173 struct i2c_adapter *adapter;
3174 struct i2c_dev *i2c_dev;
3176 PIXCIR_DBG("enter pixcir_open function\n");
3178 subminor = iminor(inode);
3181 i2c_dev = i2c_dev_get_by_minor(subminor);
3183 //printk("error i2c_dev\n");
3187 adapter = i2c_get_adapter(i2c_dev->adap->nr);
3192 client = kzalloc(sizeof(*client), GFP_KERNEL);
3194 i2c_put_adapter(adapter);
3198 snprintf(client->name, I2C_NAME_SIZE, "pixcir_i2c_ts%d", adapter->nr);
3199 client->driver = &pixcir_i2c_ts_driver;
3200 client->adapter = adapter;
3202 file->private_data = client;
3207 /*************************************Bee-0928****************************************/
3209 /*************************************Bee-0928****************************************/
3210 static long pixcir_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
3212 //struct i2c_client *client = (struct i2c_client *) file->private_data;
3214 PIXCIR_DBG("pixcir_ioctl(),cmd = %d,arg = %ld\n", cmd, arg);
3219 case CALIBRATION_FLAG: //CALIBRATION_FLAG = 1
3220 client->addr = SLAVE_ADDR;
3221 status_reg = CALIBRATION_FLAG;
3224 case BOOTLOADER: //BOOTLOADER = 7
3225 client->addr = BOOTLOADER_ADDR;
3226 status_reg = BOOTLOADER;
3232 case RESET_TP: //RESET_TP = 9
3236 case ENABLE_IRQ: //ENABLE_IRQ = 10
3238 enable_irq(global_irq);
3241 case DISABLE_IRQ: //DISABLE_IRQ = 11
3242 disable_irq_nosync(global_irq);
3245 case BOOTLOADER_STU: //BOOTLOADER_STU = 12
3246 client->addr = BOOTLOADER_ADDR;
3247 status_reg = BOOTLOADER_STU;
3252 case ATTB_VALUE: //ATTB_VALUE = 13
3253 client->addr = SLAVE_ADDR;
3254 status_reg = ATTB_VALUE;
3258 client->addr = SLAVE_ADDR;
3266 /***********************************Bee-0928****************************************/
3268 /***********************************Bee-0928****************************************/
3269 static ssize_t pixcir_read (struct file *file, char __user *buf, size_t count,loff_t *offset)
3271 //struct i2c_client *client = (struct i2c_client *)file->private_data;
3272 //unsigned char *tmp, bootloader_stu[4], attb_value[1];
3277 case BOOTLOADER_STU:
3278 i2c_master_recv(client, bootloader_stu, sizeof(bootloader_stu));
3279 if (ret!=sizeof(bootloader_stu)) {
3280 dev_err(&client->dev,
3281 "%s: BOOTLOADER_STU: i2c_master_recv() failed, ret=%d\n",
3286 ret = copy_to_user(buf, bootloader_stu, sizeof(bootloader_stu));
3288 dev_err(&client->dev,
3289 "%s: BOOTLOADER_STU: copy_to_user() failed.\n", __func__);
3297 attb_value[0] = attb_read_val();
3298 if(copy_to_user(buf, attb_value, sizeof(attb_value))) {
3299 dev_err(&client->dev,
3300 "%s: ATTB_VALUE: copy_to_user() failed.\n", __func__);
3308 tmp = kmalloc(count,GFP_KERNEL);
3312 ret = i2c_master_recv(client, tmp, count);
3314 dev_err(&client->dev,
3315 "%s: default: i2c_master_recv() failed, ret=%d\n",
3320 if(copy_to_user(buf, tmp, count)) {
3321 dev_err(&client->dev,
3322 "%s: default: copy_to_user() failed.\n", __func__);
3333 /***********************************Bee-0928****************************************/
3335 /***********************************Bee-0928****************************************/
3336 static ssize_t pixcir_write(struct file *file,const char __user *buf,size_t count, loff_t *ppos)
3338 //struct i2c_client *client;
3339 //unsigned char *tmp, bootload_data[143];
3342 client = file->private_data;
3346 case CALIBRATION_FLAG: //CALIBRATION_FLAG=1
3347 tmp = kmalloc(count,GFP_KERNEL);
3351 if (copy_from_user(tmp,buf,count)) {
3352 dev_err(&client->dev,
3353 "%s: CALIBRATION_FLAG: copy_from_user() failed.\n", __func__);
3358 ret = i2c_master_send(client,tmp,count);
3360 dev_err(&client->dev,
3361 "%s: CALIBRATION: i2c_master_send() failed, ret=%d\n",
3367 while(!attb_read_val()) {
3371 break; //10s no high aatb break
3372 } //waiting to finish the calibration.(pixcir application_note_710_v3 p43)
3378 memset(bootload_data, 0, sizeof(bootload_data));
3380 if (copy_from_user(bootload_data, buf, count)) {
3381 dev_err(&client->dev,
3382 "%s: BOOTLOADER: copy_from_user() failed.\n", __func__);
3386 ret = i2c_master_send(client, bootload_data, count);
3388 dev_err(&client->dev,
3389 "%s: BOOTLOADER: i2c_master_send() failed, ret = %d\n",
3396 tmp = kmalloc(count,GFP_KERNEL);
3400 if (copy_from_user(tmp,buf,count)) {
3401 dev_err(&client->dev,
3402 "%s: default: copy_from_user() failed.\n", __func__);
3407 ret = i2c_master_send(client,tmp,count);
3409 dev_err(&client->dev,
3410 "%s: default: i2c_master_send() failed, ret=%d\n",
3422 /***********************************Bee-0928****************************************/
3423 /* pixcir_release */
3424 /***********************************Bee-0928****************************************/
3425 static int pixcir_release(struct inode *inode, struct file *file)
3427 struct i2c_client *client = file->private_data;
3429 PIXCIR_DBG("enter pixcir_release funtion\n");
3431 i2c_put_adapter(client->adapter);
3433 file->private_data = NULL;
3438 /*********************************Bee-0928-TOP****************************************/
3439 static const struct file_operations pixcir_i2c_ts_fops =
3440 { .owner = THIS_MODULE,
3441 .read = pixcir_read,
3442 .write = pixcir_write,
3443 .open = pixcir_open,
3444 .unlocked_ioctl = pixcir_ioctl,
3445 .release = pixcir_release,
3447 /*********************************Bee-0928-BOTTOM****************************************/
3449 static const struct i2c_device_id pixcir_i2c_ts_id[] = {
3450 { MSG2138_TS_NAME, MSG2138_TS_ADDR },//0
3453 MODULE_DEVICE_TABLE(i2c, pixcir_i2c_ts_id);
3456 static unsigned short force[] = {0,0x4c,I2C_CLIENT_END,I2C_CLIENT_END};
3457 static const unsigned short * const forces[] = { force, NULL };
3458 static struct i2c_client_address_data addr_data = { .forces = forces, };
3460 static const struct of_device_id msg2138_of_match[] = {
3461 { .compatible = "Mstar,msg2138_ts", },
3464 MODULE_DEVICE_TABLE(of, msg2138_of_match);
3466 static struct i2c_driver pixcir_i2c_ts_driver = {
3468 .owner = THIS_MODULE,
3469 .name = MSG2138_TS_NAME,
3470 .of_match_table = msg2138_of_match,
3472 .probe = pixcir_i2c_ts_probe,
3473 .remove = pixcir_i2c_ts_remove,
3474 .id_table = pixcir_i2c_ts_id,
3477 static int __init pixcir_i2c_ts_init(void)
3481 /*if (0 != tp_cg_flag)
3485 /*********************************Bee-0928-TOP****************************************/
3486 TPD_DEBUG("msg2138 init111!\n");
3487 ret = register_chrdev(I2C_MAJOR,"pixcir_i2c_ts",&pixcir_i2c_ts_fops);
3489 //printk(KERN_ERR "%s:register chrdev failed\n",__FILE__);
3492 TPD_DEBUG("msg2138 init222!\n");
3493 i2c_dev_class = class_create(THIS_MODULE, "pixcir_i2c_dev");
3494 if (IS_ERR(i2c_dev_class)) {
3495 ret = PTR_ERR(i2c_dev_class);
3496 class_destroy(i2c_dev_class);
3498 /********************************Bee-0928-BOTTOM******************************************/
3500 return i2c_add_driver(&pixcir_i2c_ts_driver);
3503 static void pixcir_i2c_ts_exit(void)
3505 i2c_del_driver(&pixcir_i2c_ts_driver);
3506 /********************************Bee-0928-TOP******************************************/
3507 class_destroy(i2c_dev_class);
3508 unregister_chrdev(I2C_MAJOR,"pixcir_i2c_ts");
3509 /********************************Bee-0928-BOTTOM******************************************/
3512 module_init(pixcir_i2c_ts_init);
3513 module_exit(pixcir_i2c_ts_exit);
3517 #include "./ito_test/open_test_ANA1_8861A_lianchuang.h"
3518 #include "./ito_test/open_test_ANA2_8861A_lianchuang.h"
3519 #include "./ito_test/open_test_ANA1_B_8861A_lianchuang.h"
3520 #include "./ito_test/open_test_ANA2_B_8861A_lianchuang.h"
3521 #include "./ito_test/open_test_ANA3_8861A_lianchuang.h"
3522 ///////////////////////////////////////////////////////////////////////////
3523 u8 bItoTestDebug = 0;
3524 #define ITO_TEST_DEBUG(format, ...) \
3528 printk(KERN_ERR "ito_test ***" format "\n", ## __VA_ARGS__); \
3532 #define ITO_TEST_DEBUG_MUST(format, ...) printk(KERN_ERR "ito_test ***" format "\n", ## __VA_ARGS__);mdelay(5)
3536 s16 s16_raw_data_1[48] = {0};
3537 s16 s16_raw_data_2[48] = {0};
3538 s16 s16_raw_data_3[48] = {0};
3539 u8 ito_test_keynum = 0;
3540 u8 ito_test_dummynum = 0;
3541 u8 ito_test_trianglenum = 0;
3544 uint16_t *open_1 = NULL;
3545 uint16_t *open_1B = NULL;
3546 uint16_t *open_2 = NULL;
3547 uint16_t *open_2B = NULL;
3548 uint16_t *open_3 = NULL;
3562 #define ITO_TEST_ADDR_TP (0x4C>>1)
3563 #define ITO_TEST_ADDR_REG (0xC4>>1)
3564 #define REG_INTR_FIQ_MASK 0x04
3565 #define FIQ_E_FRAME_READY_MASK ( 1 << 8 )
3566 #define MAX_CHNL_NUM (48)
3570 #define BIT11 (1<<11)
3571 #define BIT15 (1<<15)
3574 static int ito_test_i2c_read(u8 addr, u8* read_data, u16 size)
3577 u8 addr_before = msg21xx_i2c_client->addr;
3578 msg21xx_i2c_client->addr = addr;
3581 if(size>8&&NULL!=I2CDMABuf_va)
3584 msg21xx_i2c_client->ext_flag = msg21xx_i2c_client->ext_flag | I2C_DMA_FLAG ;
3585 rc = i2c_master_recv(msg21xx_i2c_client, (unsigned char *)I2CDMABuf_pa, size);
3586 for(i = 0; i < size; i++)
3588 read_data[i] = I2CDMABuf_va[i];
3593 rc = i2c_master_recv(msg21xx_i2c_client, read_data, size);
3595 msg21xx_i2c_client->ext_flag = msg21xx_i2c_client->ext_flag & (~I2C_DMA_FLAG);
3597 rc = i2c_master_recv(msg21xx_i2c_client, read_data, size);
3600 msg21xx_i2c_client->addr = addr_before;
3603 ITO_TEST_DEBUG_MUST("ito_test_i2c_read error %d,addr=%d\n", rc,addr);
3608 static int ito_test_i2c_write(u8 addr, u8* data, u16 size)
3611 u8 addr_before = msg21xx_i2c_client->addr;
3612 msg21xx_i2c_client->addr = addr;
3615 if(size>8&&NULL!=I2CDMABuf_va)
3620 I2CDMABuf_va[i]=data[i];
3622 msg21xx_i2c_client->ext_flag = msg21xx_i2c_client->ext_flag | I2C_DMA_FLAG ;
3623 rc = i2c_master_send(msg21xx_i2c_client, (unsigned char *)I2CDMABuf_pa, size);
3627 rc = i2c_master_send(msg21xx_i2c_client, data, size);
3629 msg21xx_i2c_client->ext_flag = msg21xx_i2c_client->ext_flag & (~I2C_DMA_FLAG);
3631 rc = i2c_master_send(msg21xx_i2c_client, data, size);
3634 msg21xx_i2c_client->addr = addr_before;
3637 ITO_TEST_DEBUG_MUST("ito_test_i2c_write error %d,addr = %d,data[0]=%d\n", rc, addr,data[0]);
3642 static void ito_test_reset(void)
3644 struct msg2138_ts_platform_data *pdata = msg21xx_i2c_ts_data->platform_data;
3645 gpio_direction_output(pdata->reset_gpio_number, 1);
3646 gpio_set_value(pdata->reset_gpio_number, 1);
3647 gpio_set_value(pdata->reset_gpio_number, 0);
3649 ITO_TEST_DEBUG("reset tp\n");
3650 gpio_set_value(pdata->reset_gpio_number, 1);
3653 static void ito_test_disable_irq(void)
3655 disable_irq_nosync(global_irq);
3657 static void ito_test_enable_irq(void)
3659 enable_irq(global_irq);
3662 static void ito_test_set_iic_rate(u32 iicRate)
3664 #ifdef CONFIG_I2C_SPRD
3665 sprd_i2c_ctl_chg_clk(msg21xx_i2c_client->adapter->nr, iicRate);
3669 msg21xx_i2c_client->timing = iicRate/1000;
3673 static void ito_test_WriteReg( u8 bank, u8 addr, u16 data )
3675 u8 tx_data[5] = {0x10, bank, addr, data & 0xFF, data >> 8};
3676 ito_test_i2c_write( ITO_TEST_ADDR_REG, &tx_data[0], 5 );
3678 static void ito_test_WriteReg8Bit( u8 bank, u8 addr, u8 data )
3680 u8 tx_data[4] = {0x10, bank, addr, data};
3681 ito_test_i2c_write ( ITO_TEST_ADDR_REG, &tx_data[0], 4 );
3683 static unsigned short ito_test_ReadReg( u8 bank, u8 addr )
3685 u8 tx_data[3] = {0x10, bank, addr};
3686 u8 rx_data[2] = {0};
3688 ito_test_i2c_write( ITO_TEST_ADDR_REG, &tx_data[0], 3 );
3689 ito_test_i2c_read ( ITO_TEST_ADDR_REG, &rx_data[0], 2 );
3690 return ( rx_data[1] << 8 | rx_data[0] );
3692 static u32 ito_test_get_TpType(void)
3694 u8 tx_data[3] = {0};
3695 u8 rx_data[4] = {0};
3696 u32 Major = 0, Minor = 0;
3698 ITO_TEST_DEBUG("GetTpType\n");
3703 ito_test_i2c_write(ITO_TEST_ADDR_TP, &tx_data[0], 3);
3705 ito_test_i2c_read(ITO_TEST_ADDR_TP, &rx_data[0], 4);
3706 Major = (rx_data[1]<<8) + rx_data[0];
3707 Minor = (rx_data[3]<<8) + rx_data[2];
3709 ITO_TEST_DEBUG("***TpTypeMajor = %d ***\n", Major);
3710 ITO_TEST_DEBUG("***TpTypeMinor = %d ***\n", Minor);
3716 #define TP_OF_LIANCHUANG (2)
3717 static u32 ito_test_choose_TpType(void)
3737 ito_test_keynum = 0;
3738 ito_test_dummynum = 0;
3739 ito_test_trianglenum = 0;
3744 tpType = ito_test_get_TpType();
3745 ITO_TEST_DEBUG("tpType=%d;i=%d;\n",tpType,i);
3746 if(TP_OF_LIANCHUANG==tpType)
3760 if(TP_OF_LIANCHUANG==tpType)
3762 open_1 = open_1_lianchuang;
3763 open_1B = open_1B_lianchuang;
3764 open_2 = open_2_lianchuang;
3765 open_2B = open_2B_lianchuang;
3766 open_3 = open_3_lianchuang;
3767 MAP1 = MAP1_lianchuang;
3768 MAP2 = MAP2_lianchuang;
3769 MAP3 = MAP3_lianchuang;
3770 MAP40_1 = MAP40_1_lianchuang;
3771 MAP40_2 = MAP40_2_lianchuang;
3772 MAP40_3 = MAP40_3_lianchuang;
3773 MAP40_4 = MAP40_4_lianchuang;
3774 MAP41_1 = MAP41_1_lianchuang;
3775 MAP41_2 = MAP41_2_lianchuang;
3776 MAP41_3 = MAP41_3_lianchuang;
3777 MAP41_4 = MAP41_4_lianchuang;
3778 ito_test_keynum = NUM_KEY_LIANCHUANG;
3779 ito_test_dummynum = NUM_DUMMY_LIANCHUANG;
3780 ito_test_trianglenum = NUM_SENSOR_LIANCHUANG;
3781 ito_test_2r = ENABLE_2R_LIANCHUANG;
3789 static void ito_test_EnterSerialDebugMode(void)
3798 ito_test_i2c_write(ITO_TEST_ADDR_REG, &data[0], 5);
3801 ito_test_i2c_write(ITO_TEST_ADDR_REG, &data[0], 1);
3804 ito_test_i2c_write(ITO_TEST_ADDR_REG, &data[0], 1);
3807 ito_test_i2c_write(ITO_TEST_ADDR_REG, &data[0], 1);
3809 static uint16_t ito_test_get_num( void )
3811 uint16_t num_of_sensor,i;
3812 uint16_t RegValue1,RegValue2;
3816 RegValue1 = ito_test_ReadReg( 0x11, 0x4A);
3817 ITO_TEST_DEBUG("ito_test_get_num,RegValue1=%d\n",RegValue1);
3818 if ( ( RegValue1 & BIT1) == BIT1 )
3820 RegValue1 = ito_test_ReadReg( 0x12, 0x0A);
3821 RegValue1 = RegValue1 & 0x0F;
3823 RegValue2 = ito_test_ReadReg( 0x12, 0x16);
3824 RegValue2 = (( RegValue2 >> 1 ) & 0x0F) + 1;
3826 num_of_sensor = RegValue1 * RegValue2;
3832 num_of_sensor+=(ito_test_ReadReg( 0x12, 0x0A)>>(4*i))&0x0F;
3835 ITO_TEST_DEBUG("ito_test_get_num,num_of_sensor=%d\n",num_of_sensor);
3836 return num_of_sensor;
3838 static void ito_test_polling( void )
3840 uint16_t reg_int = 0x0000;
3841 uint8_t dbbus_tx_data[5];
3842 uint8_t dbbus_rx_data[4];
3848 ito_test_WriteReg( 0x13, 0x0C, BIT15 );
3849 ito_test_WriteReg( 0x12, 0x14, (ito_test_ReadReg(0x12,0x14) | BIT0) );
3851 ITO_TEST_DEBUG("polling start\n");
3852 while( ( reg_int & BIT0 ) == 0x0000 )
3854 dbbus_tx_data[0] = 0x10;
3855 dbbus_tx_data[1] = 0x3D;
3856 dbbus_tx_data[2] = 0x18;
3857 ito_test_i2c_write(ITO_TEST_ADDR_REG, dbbus_tx_data, 3);
3858 ito_test_i2c_read(ITO_TEST_ADDR_REG, dbbus_rx_data, 2);
3859 reg_int = dbbus_rx_data[1];
3861 ITO_TEST_DEBUG("polling end\n");
3862 reg_value = ito_test_ReadReg( 0x3D, 0x18 );
3863 ito_test_WriteReg( 0x3D, 0x18, reg_value & (~BIT0) );
3865 static uint16_t ito_test_get_data_out( int16_t* s16_raw_data )
3867 uint8_t i,dbbus_tx_data[8];
3868 uint16_t raw_data[48]={0};
3869 uint16_t num_of_sensor;
3871 uint8_t dbbus_rx_data[96]={0};
3873 num_of_sensor = ito_test_get_num();
3874 if(num_of_sensor*2>96)
3876 ITO_TEST_DEBUG("danger,num_of_sensor=%d\n",num_of_sensor);
3877 return num_of_sensor;
3880 reg_int = ito_test_ReadReg( 0x3d, REG_INTR_FIQ_MASK<<1 );
3881 ito_test_WriteReg( 0x3d, REG_INTR_FIQ_MASK<<1, (reg_int & (uint16_t)(~FIQ_E_FRAME_READY_MASK) ) );
3883 dbbus_tx_data[0] = 0x10;
3884 dbbus_tx_data[1] = 0x13;
3885 dbbus_tx_data[2] = 0x40;
3886 ito_test_i2c_write(ITO_TEST_ADDR_REG, dbbus_tx_data, 3);
3888 ito_test_i2c_read(ITO_TEST_ADDR_REG, &dbbus_rx_data[0], (num_of_sensor * 2));
3890 for(i=0;i<num_of_sensor * 2;i++)
3892 ITO_TEST_DEBUG("dbbus_rx_data[%d]=%d\n",i,dbbus_rx_data[i]);
3895 reg_int = ito_test_ReadReg( 0x3d, REG_INTR_FIQ_MASK<<1 );
3896 ito_test_WriteReg( 0x3d, REG_INTR_FIQ_MASK<<1, (reg_int | (uint16_t)FIQ_E_FRAME_READY_MASK ) );
3899 for( i = 0; i < num_of_sensor; i++ )
3901 raw_data[i] = ( dbbus_rx_data[ 2 * i + 1] << 8 ) | ( dbbus_rx_data[2 * i] );
3902 s16_raw_data[i] = ( int16_t )raw_data[i];
3905 return(num_of_sensor);
3909 static void ito_test_send_data_in( uint8_t step )
3912 uint8_t dbbus_tx_data[512];
3913 uint16_t *Type1=NULL;
3915 ITO_TEST_DEBUG("ito_test_send_data_in step=%d\n",step);
3920 else if( step == 5 )
3924 else if( step == 6 )
3928 else if( step == 9 )
3930 Type1 = &open_1B[0];
3932 else if( step == 10 )
3934 Type1 = &open_2B[0];
3937 dbbus_tx_data[0] = 0x10;
3938 dbbus_tx_data[1] = 0x11;
3939 dbbus_tx_data[2] = 0x00;
3940 for( i = 0; i <= 0x3E ; i++ )
3942 dbbus_tx_data[3+2*i] = Type1[i] & 0xFF;
3943 dbbus_tx_data[4+2*i] = ( Type1[i] >> 8 ) & 0xFF;
3945 ito_test_i2c_write(ITO_TEST_ADDR_REG, dbbus_tx_data, 3+0x3F*2);
3947 dbbus_tx_data[2] = 0x7A * 2;
3948 for( i = 0x7A; i <= 0x7D ; i++ )
3950 dbbus_tx_data[3+2*(i-0x7A)] = 0;
3951 dbbus_tx_data[4+2*(i-0x7A)] = 0;
3953 ito_test_i2c_write(ITO_TEST_ADDR_REG, dbbus_tx_data, 3+8);
3955 dbbus_tx_data[0] = 0x10;
3956 dbbus_tx_data[1] = 0x12;
3958 dbbus_tx_data[2] = 5 * 2;
3959 dbbus_tx_data[3] = Type1[128+5] & 0xFF;
3960 dbbus_tx_data[4] = ( Type1[128+5] >> 8 ) & 0xFF;
3961 ito_test_i2c_write(ITO_TEST_ADDR_REG, dbbus_tx_data, 5);
3963 dbbus_tx_data[2] = 0x0B * 2;
3964 dbbus_tx_data[3] = Type1[128+0x0B] & 0xFF;
3965 dbbus_tx_data[4] = ( Type1[128+0x0B] >> 8 ) & 0xFF;
3966 ito_test_i2c_write(ITO_TEST_ADDR_REG, dbbus_tx_data, 5);
3968 dbbus_tx_data[2] = 0x12 * 2;
3969 dbbus_tx_data[3] = Type1[128+0x12] & 0xFF;
3970 dbbus_tx_data[4] = ( Type1[128+0x12] >> 8 ) & 0xFF;
3971 ito_test_i2c_write(ITO_TEST_ADDR_REG, dbbus_tx_data, 5);
3973 dbbus_tx_data[2] = 0x15 * 2;
3974 dbbus_tx_data[3] = Type1[128+0x15] & 0xFF;
3975 dbbus_tx_data[4] = ( Type1[128+0x15] >> 8 ) & 0xFF;
3976 ito_test_i2c_write(ITO_TEST_ADDR_REG, dbbus_tx_data, 5);
3979 static void ito_test_set_v( uint8_t Enable, uint8_t Prs)
3981 uint16_t u16RegValue;
3984 u16RegValue = ito_test_ReadReg( 0x12, 0x08);
3985 u16RegValue = u16RegValue & 0xF1;
3988 ito_test_WriteReg( 0x12, 0x08, u16RegValue| 0x0C);
3990 else if ( Prs == 1 )
3992 ito_test_WriteReg( 0x12, 0x08, u16RegValue| 0x0E);
3996 ito_test_WriteReg( 0x12, 0x08, u16RegValue| 0x02);
4001 u16RegValue = ito_test_ReadReg( 0x11, 0x06);
4002 ito_test_WriteReg( 0x11, 0x06, u16RegValue| 0x03);
4006 u16RegValue = ito_test_ReadReg( 0x11, 0x06);
4007 u16RegValue = u16RegValue & 0xFC;
4008 ito_test_WriteReg( 0x11, 0x06, u16RegValue);
4013 static void ito_test_set_c( uint8_t Csub_Step )
4016 uint8_t dbbus_tx_data[MAX_CHNL_NUM+3];
4017 uint8_t HighLevel_Csub = false;
4020 dbbus_tx_data[0] = 0x10;
4021 dbbus_tx_data[1] = 0x11;
4022 dbbus_tx_data[2] = 0x84;
4023 for( i = 0; i < MAX_CHNL_NUM; i++ )
4025 Csub_new = Csub_Step;
4026 HighLevel_Csub = false;
4027 if( Csub_new > 0x1F )
4029 Csub_new = Csub_new - 0x14;
4030 HighLevel_Csub = true;
4033 dbbus_tx_data[3+i] = Csub_new & 0x1F;
4034 if( HighLevel_Csub == true )
4036 dbbus_tx_data[3+i] |= BIT5;
4039 ito_test_i2c_write(ITO_TEST_ADDR_REG, dbbus_tx_data, MAX_CHNL_NUM+3);
4041 dbbus_tx_data[2] = 0xB4;
4042 ito_test_i2c_write(ITO_TEST_ADDR_REG, dbbus_tx_data, MAX_CHNL_NUM+3);
4045 static void ito_test_sw( void )
4047 ito_test_WriteReg( 0x11, 0x00, 0xFFFF );
4048 ito_test_WriteReg( 0x11, 0x00, 0x0000 );
4054 static void ito_test_first( uint8_t item_id , int16_t* s16_raw_data)
4056 uint8_t result = 0,loop;
4057 uint8_t dbbus_tx_data[9];
4059 int16_t s16_raw_data_tmp[48]={0};
4060 uint8_t num_of_sensor, num_of_sensor2,total_sensor;
4061 uint16_t u16RegValue;
4062 uint8_t *pMapping=NULL;
4068 ITO_TEST_DEBUG("ito_test_first item_id=%d\n",item_id);
4069 ito_test_WriteReg( 0x0F, 0xE6, 0x01 );
4071 ito_test_WriteReg( 0x1E, 0x24, 0x0500 );
4072 ito_test_WriteReg( 0x1E, 0x2A, 0x0000 );
4073 ito_test_WriteReg( 0x1E, 0xE6, 0x6E00 );
4074 ito_test_WriteReg( 0x1E, 0xE8, 0x0071 );
4076 if ( item_id == 40 )
4078 pMapping = &MAP1[0];
4081 total_sensor = ito_test_trianglenum/2;
4085 total_sensor = ito_test_trianglenum/2 + ito_test_keynum + ito_test_dummynum;
4088 else if( item_id == 41 )
4090 pMapping = &MAP2[0];
4093 total_sensor = ito_test_trianglenum/2;
4097 total_sensor = ito_test_trianglenum/2 + ito_test_keynum + ito_test_dummynum;
4100 else if( item_id == 42 )
4102 pMapping = &MAP3[0];
4103 total_sensor = ito_test_trianglenum + ito_test_keynum+ ito_test_dummynum;
4108 if ( item_id != 42 )
4115 ITO_TEST_DEBUG("loop=%d\n",loop);
4116 for ( i = 0; i < loop; i++ )
4120 ito_test_send_data_in( item_id - 36 );
4124 if ( item_id == 40 )
4125 ito_test_send_data_in( 9 );
4127 ito_test_send_data_in( 10 );
4130 ito_test_set_v(1,0);
4131 u16RegValue = ito_test_ReadReg( 0x11, 0x0E);
4132 ito_test_WriteReg( 0x11, 0x0E, u16RegValue | BIT11 );
4135 ito_test_set_c( 32 );
4137 ito_test_set_c( 0 );
4143 num_of_sensor=ito_test_get_data_out( s16_raw_data_tmp );
4144 ITO_TEST_DEBUG("num_of_sensor=%d;\n",num_of_sensor);
4148 num_of_sensor2=ito_test_get_data_out( &s16_raw_data_tmp[num_of_sensor] );
4149 ITO_TEST_DEBUG("num_of_sensor=%d;num_of_sensor2=%d\n",num_of_sensor,num_of_sensor2);
4152 for ( j = 0; j < total_sensor ; j ++ )
4155 s16_raw_data[pMapping[j]] = s16_raw_data_tmp[j] + 4096;
4157 s16_raw_data[pMapping[j]] = s16_raw_data_tmp[j];
4167 ITO_TEST_GET_TP_TYPE_ERROR,
4170 ITO_TEST_RET ito_test_second (u8 item_id)
4174 s32 s16_raw_data_jg_tmp1 = 0;
4175 s32 s16_raw_data_jg_tmp2 = 0;
4176 s32 jg_tmp1_avg_Th_max =0;
4177 s32 jg_tmp1_avg_Th_min =0;
4178 s32 jg_tmp2_avg_Th_max =0;
4179 s32 jg_tmp2_avg_Th_min =0;
4184 if ( item_id == 40 )
4186 for (i=0; i<(ito_test_trianglenum/2)-2; i++)
4188 s16_raw_data_jg_tmp1 += s16_raw_data_1[MAP40_1[i]];
4192 s16_raw_data_jg_tmp2 += s16_raw_data_1[MAP40_2[i]];
4195 else if( item_id == 41 )
4197 for (i=0; i<(ito_test_trianglenum/2)-2; i++)
4199 s16_raw_data_jg_tmp1 += s16_raw_data_2[MAP41_1[i]];
4203 s16_raw_data_jg_tmp2 += s16_raw_data_2[MAP41_2[i]];
4207 jg_tmp1_avg_Th_max = (s16_raw_data_jg_tmp1 / ((ito_test_trianglenum/2)-2)) * ( 100 + Th_Tri) / 100 ;
4208 jg_tmp1_avg_Th_min = (s16_raw_data_jg_tmp1 / ((ito_test_trianglenum/2)-2)) * ( 100 - Th_Tri) / 100 ;
4209 jg_tmp2_avg_Th_max = (s16_raw_data_jg_tmp2 / 2) * ( 100 + Th_bor) / 100 ;
4210 jg_tmp2_avg_Th_min = (s16_raw_data_jg_tmp2 / 2 ) * ( 100 - Th_bor) / 100 ;
4212 ITO_TEST_DEBUG("item_id=%d;sum1=%d;max1=%d;min1=%d;sum2=%d;max2=%d;min2=%d\n",item_id,s16_raw_data_jg_tmp1,jg_tmp1_avg_Th_max,jg_tmp1_avg_Th_min,s16_raw_data_jg_tmp2,jg_tmp2_avg_Th_max,jg_tmp2_avg_Th_min);
4214 if ( item_id == 40 )
4216 for (i=0; i<(ito_test_trianglenum/2)-2; i++)
4218 if (s16_raw_data_1[MAP40_1[i]] > jg_tmp1_avg_Th_max || s16_raw_data_1[MAP40_1[i]] < jg_tmp1_avg_Th_min)
4219 return ITO_TEST_FAIL;
4221 for (i=0; i<(ito_test_trianglenum/2)-3; i++)
4223 if (s16_raw_data_1[MAP40_1[i]] > s16_raw_data_1[MAP40_1[i+1]] )
4224 return ITO_TEST_FAIL;
4228 if (s16_raw_data_1[MAP40_2[i]] > jg_tmp2_avg_Th_max || s16_raw_data_1[MAP40_2[i]] < jg_tmp2_avg_Th_min)
4229 return ITO_TEST_FAIL;
4233 if ( item_id == 41 )
4235 for (i=0; i<(ito_test_trianglenum/2)-2; i++)
4237 if (s16_raw_data_2[MAP41_1[i]] > jg_tmp1_avg_Th_max || s16_raw_data_2[MAP41_1[i]] < jg_tmp1_avg_Th_min)
4238 return ITO_TEST_FAIL;
4240 for (i=0; i<(ito_test_trianglenum/2)-3; i++)
4242 if (s16_raw_data_2[MAP41_1[i]] < s16_raw_data_2[MAP41_1[i+1]] )
4243 return ITO_TEST_FAIL;
4248 if (s16_raw_data_2[MAP41_2[i]] > jg_tmp2_avg_Th_max || s16_raw_data_2[MAP41_2[i]] < jg_tmp2_avg_Th_min)
4249 return ITO_TEST_FAIL;
4256 ITO_TEST_RET ito_test_second_2r (u8 item_id)
4260 s32 s16_raw_data_jg_tmp1 = 0;
4261 s32 s16_raw_data_jg_tmp2 = 0;
4262 s32 s16_raw_data_jg_tmp3 = 0;
4263 s32 s16_raw_data_jg_tmp4 = 0;
4265 s32 jg_tmp1_avg_Th_max =0;
4266 s32 jg_tmp1_avg_Th_min =0;
4267 s32 jg_tmp2_avg_Th_max =0;
4268 s32 jg_tmp2_avg_Th_min =0;
4269 s32 jg_tmp3_avg_Th_max =0;
4270 s32 jg_tmp3_avg_Th_min =0;
4271 s32 jg_tmp4_avg_Th_max =0;
4272 s32 jg_tmp4_avg_Th_min =0;
4274 u8 Th_Tri = 25; // non-border threshold
4275 u8 Th_bor = 25; // border threshold
4277 if ( item_id == 40 )
4279 for (i=0; i<(ito_test_trianglenum/4)-2; i++)
4281 s16_raw_data_jg_tmp1 += s16_raw_data_1[MAP40_1[i]]; //first region: non-border
4285 s16_raw_data_jg_tmp2 += s16_raw_data_1[MAP40_2[i]]; //first region: border
4288 for (i=0; i<(ito_test_trianglenum/4)-2; i++)
4290 s16_raw_data_jg_tmp3 += s16_raw_data_1[MAP40_3[i]]; //second region: non-border
4294 s16_raw_data_jg_tmp4 += s16_raw_data_1[MAP40_4[i]]; //second region: border
4301 else if( item_id == 41 )
4303 for (i=0; i<(ito_test_trianglenum/4)-2; i++)
4305 s16_raw_data_jg_tmp1 += s16_raw_data_2[MAP41_1[i]]; //first region: non-border
4309 s16_raw_data_jg_tmp2 += s16_raw_data_2[MAP41_2[i]]; //first region: border
4311 for (i=0; i<(ito_test_trianglenum/4)-2; i++)
4313 s16_raw_data_jg_tmp3 += s16_raw_data_2[MAP41_3[i]]; //second region: non-border
4317 s16_raw_data_jg_tmp4 += s16_raw_data_2[MAP41_4[i]]; //second region: border
4321 jg_tmp1_avg_Th_max = (s16_raw_data_jg_tmp1 / ((ito_test_trianglenum/4)-2)) * ( 100 + Th_Tri) / 100 ;
4322 jg_tmp1_avg_Th_min = (s16_raw_data_jg_tmp1 / ((ito_test_trianglenum/4)-2)) * ( 100 - Th_Tri) / 100 ;
4323 jg_tmp2_avg_Th_max = (s16_raw_data_jg_tmp2 / 2) * ( 100 + Th_bor) / 100 ;
4324 jg_tmp2_avg_Th_min = (s16_raw_data_jg_tmp2 / 2) * ( 100 - Th_bor) / 100 ;
4325 jg_tmp3_avg_Th_max = (s16_raw_data_jg_tmp3 / ((ito_test_trianglenum/4)-2)) * ( 100 + Th_Tri) / 100 ;
4326 jg_tmp3_avg_Th_min = (s16_raw_data_jg_tmp3 / ((ito_test_trianglenum/4)-2)) * ( 100 - Th_Tri) / 100 ;
4327 jg_tmp4_avg_Th_max = (s16_raw_data_jg_tmp4 / 2) * ( 100 + Th_bor) / 100 ;
4328 jg_tmp4_avg_Th_min = (s16_raw_data_jg_tmp4 / 2) * ( 100 - Th_bor) / 100 ;
4331 ITO_TEST_DEBUG("item_id=%d;sum1=%d;max1=%d;min1=%d;sum2=%d;max2=%d;min2=%d;sum3=%d;max3=%d;min3=%d;sum4=%d;max4=%d;min4=%d;\n",item_id,s16_raw_data_jg_tmp1,jg_tmp1_avg_Th_max,jg_tmp1_avg_Th_min,s16_raw_data_jg_tmp2,jg_tmp2_avg_Th_max,jg_tmp2_avg_Th_min,s16_raw_data_jg_tmp3,jg_tmp3_avg_Th_max,jg_tmp3_avg_Th_min,s16_raw_data_jg_tmp4,jg_tmp4_avg_Th_max,jg_tmp4_avg_Th_min);
4336 if ( item_id == 40 )
4338 for (i=0; i<(ito_test_trianglenum/4)-2; i++)
4340 if (s16_raw_data_1[MAP40_1[i]] > jg_tmp1_avg_Th_max || s16_raw_data_1[MAP40_1[i]] < jg_tmp1_avg_Th_min)
4341 return ITO_TEST_FAIL;
4346 if (s16_raw_data_1[MAP40_2[i]] > jg_tmp2_avg_Th_max || s16_raw_data_1[MAP40_2[i]] < jg_tmp2_avg_Th_min)
4347 return ITO_TEST_FAIL;
4350 for (i=0; i<(ito_test_trianglenum/4)-2; i++)
4352 if (s16_raw_data_1[MAP40_3[i]] > jg_tmp3_avg_Th_max || s16_raw_data_1[MAP40_3[i]] < jg_tmp3_avg_Th_min)
4353 return ITO_TEST_FAIL;
4358 if (s16_raw_data_1[MAP40_4[i]] > jg_tmp4_avg_Th_max || s16_raw_data_1[MAP40_4[i]] < jg_tmp4_avg_Th_min)
4359 return ITO_TEST_FAIL;
4363 if ( item_id == 41 )
4365 for (i=0; i<(ito_test_trianglenum/4)-2; i++)
4367 if (s16_raw_data_2[MAP41_1[i]] > jg_tmp1_avg_Th_max || s16_raw_data_2[MAP41_1[i]] < jg_tmp1_avg_Th_min)
4368 return ITO_TEST_FAIL;
4373 if (s16_raw_data_2[MAP41_2[i]] > jg_tmp2_avg_Th_max || s16_raw_data_2[MAP41_2[i]] < jg_tmp2_avg_Th_min)
4374 return ITO_TEST_FAIL;
4377 for (i=0; i<(ito_test_trianglenum/4)-2; i++)
4379 if (s16_raw_data_2[MAP41_3[i]] > jg_tmp3_avg_Th_max || s16_raw_data_2[MAP41_3[i]] < jg_tmp3_avg_Th_min)
4380 return ITO_TEST_FAIL;
4385 if (s16_raw_data_2[MAP41_4[i]] > jg_tmp4_avg_Th_max || s16_raw_data_2[MAP41_4[i]] < jg_tmp4_avg_Th_min)
4386 return ITO_TEST_FAIL;
4395 static ITO_TEST_RET ito_test_interface(void)
4397 ITO_TEST_RET ret = ITO_TEST_OK;
4402 ito_test_set_iic_rate(50000);
4403 ITO_TEST_DEBUG("start\n");
4404 ito_test_disable_irq();
4406 if(!ito_test_choose_TpType())
4408 ITO_TEST_DEBUG("choose tpType fail\n");
4409 ret = ITO_TEST_GET_TP_TYPE_ERROR;
4412 ito_test_EnterSerialDebugMode();
4414 ITO_TEST_DEBUG("EnterSerialDebugMode\n");
4415 ito_test_WriteReg8Bit ( 0x0F, 0xE6, 0x01 );
4416 ito_test_WriteReg ( 0x3C, 0x60, 0xAA55 );
4417 ITO_TEST_DEBUG("stop mcu and disable watchdog V.005\n");
4420 for(i = 0;i < 48;i++)
4422 s16_raw_data_1[i] = 0;
4423 s16_raw_data_2[i] = 0;
4424 s16_raw_data_3[i] = 0;
4427 ito_test_first(40, s16_raw_data_1);
4428 ITO_TEST_DEBUG("40 get s16_raw_data_1\n");
4431 ret=ito_test_second_2r(40);
4435 ret=ito_test_second(40);
4437 if(ITO_TEST_FAIL==ret)
4442 ito_test_first(41, s16_raw_data_2);
4443 ITO_TEST_DEBUG("41 get s16_raw_data_2\n");
4446 ret=ito_test_second_2r(41);
4450 ret=ito_test_second(41);
4452 if(ITO_TEST_FAIL==ret)
4457 ito_test_first(42, s16_raw_data_3);
4458 ITO_TEST_DEBUG("42 get s16_raw_data_3\n");
4464 ito_test_set_iic_rate(100000);
4466 ito_test_enable_irq();
4467 ITO_TEST_DEBUG("end\n");
4471 #include <linux/proc_fs.h>
4472 #define ITO_TEST_AUTHORITY 0777
4473 static struct proc_dir_entry *msg_ito_test = NULL;
4474 static struct proc_dir_entry *debug = NULL;
4475 static struct proc_dir_entry *debug_on_off = NULL;
4476 #define PROC_MSG_ITO_TESE "msg-ito-test"
4477 #define PROC_ITO_TEST_DEBUG "debug"
4478 #define PROC_ITO_TEST_DEBUG_ON_OFF "debug-on-off"
4479 ITO_TEST_RET g_ito_test_ret = ITO_TEST_OK;
4480 static int ito_test_proc_read_debug(char *page, char **start, off_t off, int count, int *eof, void *data)
4484 g_ito_test_ret = ito_test_interface();
4485 if(ITO_TEST_OK==g_ito_test_ret)
4487 ITO_TEST_DEBUG_MUST("ITO_TEST_OK");
4489 else if(ITO_TEST_FAIL==g_ito_test_ret)
4491 ITO_TEST_DEBUG_MUST("ITO_TEST_FAIL");
4493 else if(ITO_TEST_GET_TP_TYPE_ERROR==g_ito_test_ret)
4495 ITO_TEST_DEBUG_MUST("ITO_TEST_GET_TP_TYPE_ERROR");
4502 static int ito_test_proc_write_debug(struct file *file, const char *buffer, unsigned long count, void *data)
4506 ITO_TEST_DEBUG_MUST("ito_test_ret = %d",g_ito_test_ret);
4510 ITO_TEST_DEBUG_MUST("data_1[%d]=%d;\n",i,s16_raw_data_1[i]);
4515 ITO_TEST_DEBUG_MUST("data_2[%d]=%d;\n",i,s16_raw_data_2[i]);
4520 ITO_TEST_DEBUG_MUST("data_3[%d]=%d;\n",i,s16_raw_data_3[i]);
4525 static int ito_test_proc_read_debug_on_off(char *page, char **start, off_t off, int count, int *eof, void *data)
4530 ITO_TEST_DEBUG_MUST("on debug bItoTestDebug = %d",bItoTestDebug);
4536 static int ito_test_proc_write_debug_on_off(struct file *file, const char *buffer, unsigned long count, void *data)
4539 ITO_TEST_DEBUG_MUST("off debug bItoTestDebug = %d",bItoTestDebug);
4543 static void ito_test_create_entry(void)
4546 static const struct file_operations debug_ops = {
4547 .owner = THIS_MODULE,
4548 .read = ito_test_proc_read_debug,
4549 .write = ito_test_proc_write_debug,
4552 static const struct file_operations debug_on_off_ops = {
4553 .owner = THIS_MODULE,
4554 .read = ito_test_proc_read_debug_on_off,
4555 .write = ito_test_proc_write_debug_on_off,
4558 msg_ito_test = proc_mkdir(PROC_MSG_ITO_TESE, NULL);
4559 debug = proc_create(PROC_ITO_TEST_DEBUG,ITO_TEST_AUTHORITY,msg_ito_test,&debug_ops);
4560 debug_on_off = proc_create(PROC_ITO_TEST_DEBUG_ON_OFF,ITO_TEST_AUTHORITY,msg_ito_test,&debug_on_off_ops);
4563 ITO_TEST_DEBUG_MUST("create_proc_entry ITO TEST DEBUG failed\n");
4567 ITO_TEST_DEBUG_MUST("create_proc_entry ITO TEST DEBUG OK\n");
4569 if (NULL==debug_on_off)
4571 ITO_TEST_DEBUG_MUST("create_proc_entry ITO TEST ON OFF failed\n");
4575 ITO_TEST_DEBUG_MUST("create_proc_entry ITO TEST ON OFF OK\n");
4579 MODULE_AUTHOR("Jianchun Bian <jcbian@pixcir.com.cn>");
4580 MODULE_DESCRIPTION("Pixcir I2C Touchscreen Driver");
4581 MODULE_LICENSE("GPL");