1 /***********************************************************************
4 * DENX Software Engineering
5 * Wolfgang Denk, wd@denx.de
8 * Simple 16550A serial driver
10 * Originally from linux source (drivers/char/ps2ser.c)
12 * Used by the PS/2 multiplexer driver (ps2mult.c)
14 ***********************************************************************/
18 #ifdef CONFIG_PS2SERIAL
21 #include <asm/atomic.h>
23 #if defined(CFG_NS16550) || defined(CONFIG_MPC85xx)
27 DECLARE_GLOBAL_DATA_PTR;
31 #define PS2SER_BAUD 57600
34 #if CONFIG_PS2SERIAL == 1
35 #define PSC_BASE MPC5XXX_PSC1
36 #elif CONFIG_PS2SERIAL == 2
37 #define PSC_BASE MPC5XXX_PSC2
38 #elif CONFIG_PS2SERIAL == 3
39 #define PSC_BASE MPC5XXX_PSC3
40 #elif defined(CONFIG_MGT5100)
41 #error CONFIG_PS2SERIAL must be in 1, 2 or 3
42 #elif CONFIG_PS2SERIAL == 4
43 #define PSC_BASE MPC5XXX_PSC4
44 #elif CONFIG_PS2SERIAL == 5
45 #define PSC_BASE MPC5XXX_PSC5
46 #elif CONFIG_PS2SERIAL == 6
47 #define PSC_BASE MPC5XXX_PSC6
49 #error CONFIG_PS2SERIAL must be in 1 ... 6
52 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
53 defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
55 #if CONFIG_PS2SERIAL == 1
56 #define COM_BASE (CFG_CCSRBAR+0x4500)
57 #elif CONFIG_PS2SERIAL == 2
58 #define COM_BASE (CFG_CCSRBAR+0x4600)
60 #error CONFIG_PS2SERIAL must be in 1 ... 2
63 #endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
65 static int ps2ser_getc_hw(void);
66 static void ps2ser_interrupt(void *dev_id);
68 extern struct serial_state rs_table[]; /* in serial.c */
69 #if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && \
70 !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8548) && \
71 !defined(CONFIG_MPC8555)
72 static struct serial_state *state;
75 static u_char ps2buf[PS2BUF_SIZE];
76 static atomic_t ps2buf_cnt;
77 static int ps2buf_in_idx;
78 static int ps2buf_out_idx;
83 volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
84 unsigned long baseclk;
88 psc->command = PSC_SEL_MODE_REG_1;
90 /* select clock sources */
91 #if defined(CONFIG_MGT5100)
92 psc->psc_clock_select = 0xdd00;
93 baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32;
94 #elif defined(CONFIG_MPC5200)
95 psc->psc_clock_select = 0;
96 baseclk = (gd->ipb_clk + 16) / 32;
99 /* switch to UART mode */
102 /* configure parity, bit length and so on */
103 #if defined(CONFIG_MGT5100)
104 psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE;
105 #elif defined(CONFIG_MPC5200)
106 psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
108 psc->mode = PSC_MODE_ONE_STOP;
110 /* set up UART divisor */
111 div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD;
112 psc->ctur = (div >> 8) & 0xff;
113 psc->ctlr = div & 0xff;
115 /* disable all interrupts */
118 /* reset and enable Rx/Tx */
119 psc->command = PSC_RST_RX;
120 psc->command = PSC_RST_TX;
121 psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
126 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
127 defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
128 int ps2ser_init(void)
130 NS16550_t com_port = (NS16550_t)COM_BASE;
132 com_port->ier = 0x00;
133 com_port->lcr = LCR_BKSE | LCR_8N1;
134 com_port->dll = (CFG_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
135 com_port->dlm = ((CFG_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
136 com_port->lcr = LCR_8N1;
137 com_port->mcr = (MCR_DTR | MCR_RTS);
138 com_port->fcr = (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR);
143 #else /* !CONFIG_MPC5xxx && !CONFIG_MPC8540 / other */
145 static inline unsigned int ps2ser_in(int offset)
147 return readb((unsigned long) state->iomem_base + offset);
150 static inline void ps2ser_out(int offset, int value)
152 writeb(value, (unsigned long) state->iomem_base + offset);
155 int ps2ser_init(void)
160 state = rs_table + CONFIG_PS2SERIAL;
162 quot = state->baud_base / PS2SER_BAUD;
163 cval = 0x3; /* 8N1 - 8 data bits, no parity bits, 1 stop bit */
165 /* Set speed, enable interrupts, enable FIFO
167 ps2ser_out(UART_LCR, cval | UART_LCR_DLAB);
168 ps2ser_out(UART_DLL, quot & 0xff);
169 ps2ser_out(UART_DLM, quot >> 8);
170 ps2ser_out(UART_LCR, cval);
171 ps2ser_out(UART_IER, UART_IER_RDI);
172 ps2ser_out(UART_MCR, UART_MCR_OUT2 | UART_MCR_DTR | UART_MCR_RTS);
174 UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
176 /* If we read 0xff from the LSR, there is no UART here
178 if (ps2ser_in(UART_LSR) == 0xff) {
179 printf ("ps2ser.c: no UART found\n");
183 irq_install_handler(state->irq, ps2ser_interrupt, NULL);
187 #endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
189 void ps2ser_putc(int chr)
191 #ifdef CONFIG_MPC5xxx
192 volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
193 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
194 defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
195 NS16550_t com_port = (NS16550_t)COM_BASE;
198 printf(">>>> 0x%02x\n", chr);
201 #ifdef CONFIG_MPC5xxx
202 while (!(psc->psc_status & PSC_SR_TXRDY));
204 psc->psc_buffer_8 = chr;
205 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
206 defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
207 while ((com_port->lsr & LSR_THRE) == 0);
210 while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));
212 ps2ser_out(UART_TX, chr);
216 static int ps2ser_getc_hw(void)
218 #ifdef CONFIG_MPC5xxx
219 volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
220 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
221 defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
222 NS16550_t com_port = (NS16550_t)COM_BASE;
226 #ifdef CONFIG_MPC5xxx
227 if (psc->psc_status & PSC_SR_RXRDY) {
228 res = (psc->psc_buffer_8);
230 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
231 defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
232 if (com_port->lsr & LSR_DR) {
236 if (ps2ser_in(UART_LSR) & UART_LSR_DR) {
237 res = (ps2ser_in(UART_RX));
244 int ps2ser_getc(void)
253 flags = disable_interrupts();
256 if (atomic_read(&ps2buf_cnt) != 0) {
257 chr = ps2buf[ps2buf_out_idx++];
258 ps2buf_out_idx &= (PS2BUF_SIZE - 1);
259 atomic_dec(&ps2buf_cnt);
261 chr = ps2ser_getc_hw();
266 if (flags) enable_interrupts();
269 printf("0x%02x\n", chr);
275 int ps2ser_check(void)
279 flags = disable_interrupts();
280 ps2ser_interrupt(NULL);
281 if (flags) enable_interrupts();
283 return atomic_read(&ps2buf_cnt);
286 static void ps2ser_interrupt(void *dev_id)
288 #ifdef CONFIG_MPC5xxx
289 volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
290 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
291 defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
292 NS16550_t com_port = (NS16550_t)COM_BASE;
298 chr = ps2ser_getc_hw();
299 #ifdef CONFIG_MPC5xxx
300 status = psc->psc_status;
301 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
302 defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
303 status = com_port->lsr;
305 status = ps2ser_in(UART_IIR);
307 if (chr < 0) continue;
309 if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) {
310 ps2buf[ps2buf_in_idx++] = chr;
311 ps2buf_in_idx &= (PS2BUF_SIZE - 1);
312 atomic_inc(&ps2buf_cnt);
314 printf ("ps2ser.c: buffer overflow\n");
316 #ifdef CONFIG_MPC5xxx
317 } while (status & PSC_SR_RXRDY);
318 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
319 defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
320 } while (status & LSR_DR);
322 } while (status & UART_IIR_RDI);
325 if (atomic_read(&ps2buf_cnt)) {
326 ps2mult_callback(atomic_read(&ps2buf_cnt));
330 #endif /* CONFIG_PS2SERIAL */