drivers/infiniband/hw/qib/qib_verbs.c

   1 /*
   2  * Copyright (c) 2012, 2013 Intel Corporation.  All rights reserved.
   3  * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
   4  * Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <rdma/ib_mad.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <linux/io.h>
  38 #include <linux/module.h>
  39 #include <linux/utsname.h>
  40 #include <linux/rculist.h>
  41 #include <linux/mm.h>
  42 #include <linux/random.h>
  43 #include <linux/vmalloc.h>
  44 #include <rdma/rdma_vt.h>
  45
  46 #include "qib.h"
  47 #include "qib_common.h"
  48
  49 static unsigned int ib_qib_qp_table_size = 256;
  50 module_param_named(qp_table_size, ib_qib_qp_table_size, uint, S_IRUGO);
  51 MODULE_PARM_DESC(qp_table_size, "QP table size");
  52
  53 unsigned int ib_qib_lkey_table_size = 16;
  54 module_param_named(lkey_table_size, ib_qib_lkey_table_size, uint,
  55                    S_IRUGO);
  56 MODULE_PARM_DESC(lkey_table_size,
  57                  "LKEY table size in bits (2^n, 1 <= n <= 23)");
  58
  59 static unsigned int ib_qib_max_pds = 0xFFFF;
  60 module_param_named(max_pds, ib_qib_max_pds, uint, S_IRUGO);
  61 MODULE_PARM_DESC(max_pds,
  62                  "Maximum number of protection domains to support");
  63
  64 static unsigned int ib_qib_max_ahs = 0xFFFF;
  65 module_param_named(max_ahs, ib_qib_max_ahs, uint, S_IRUGO);
  66 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
  67
  68 unsigned int ib_qib_max_cqes = 0x2FFFF;
  69 module_param_named(max_cqes, ib_qib_max_cqes, uint, S_IRUGO);
  70 MODULE_PARM_DESC(max_cqes,
  71                  "Maximum number of completion queue entries to support");
  72
  73 unsigned int ib_qib_max_cqs = 0x1FFFF;
  74 module_param_named(max_cqs, ib_qib_max_cqs, uint, S_IRUGO);
  75 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
  76
  77 unsigned int ib_qib_max_qp_wrs = 0x3FFF;
  78 module_param_named(max_qp_wrs, ib_qib_max_qp_wrs, uint, S_IRUGO);
  79 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
  80
  81 unsigned int ib_qib_max_qps = 16384;
  82 module_param_named(max_qps, ib_qib_max_qps, uint, S_IRUGO);
  83 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
  84
  85 unsigned int ib_qib_max_sges = 0x60;
  86 module_param_named(max_sges, ib_qib_max_sges, uint, S_IRUGO);
  87 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
  88
  89 unsigned int ib_qib_max_mcast_grps = 16384;
  90 module_param_named(max_mcast_grps, ib_qib_max_mcast_grps, uint, S_IRUGO);
  91 MODULE_PARM_DESC(max_mcast_grps,
  92                  "Maximum number of multicast groups to support");
  93
  94 unsigned int ib_qib_max_mcast_qp_attached = 16;
  95 module_param_named(max_mcast_qp_attached, ib_qib_max_mcast_qp_attached,
  96                    uint, S_IRUGO);
  97 MODULE_PARM_DESC(max_mcast_qp_attached,
  98                  "Maximum number of attached QPs to support");
  99
 100 unsigned int ib_qib_max_srqs = 1024;
 101 module_param_named(max_srqs, ib_qib_max_srqs, uint, S_IRUGO);
 102 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
 103
 104 unsigned int ib_qib_max_srq_sges = 128;
 105 module_param_named(max_srq_sges, ib_qib_max_srq_sges, uint, S_IRUGO);
 106 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
 107
 108 unsigned int ib_qib_max_srq_wrs = 0x1FFFF;
 109 module_param_named(max_srq_wrs, ib_qib_max_srq_wrs, uint, S_IRUGO);
 110 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
 111
 112 static unsigned int ib_qib_disable_sma;
 113 module_param_named(disable_sma, ib_qib_disable_sma, uint, S_IWUSR | S_IRUGO);
 114 MODULE_PARM_DESC(disable_sma, "Disable the SMA");
 115
 116 /*
 117  * Note that it is OK to post send work requests in the SQE and ERR
 118  * states; qib_do_send() will process them and generate error
 119  * completions as per IB 1.2 C10-96.
 120  */
 121 const int ib_qib_state_ops[IB_QPS_ERR + 1] = {
 122         [IB_QPS_RESET] = 0,
 123         [IB_QPS_INIT] = QIB_POST_RECV_OK,
 124         [IB_QPS_RTR] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK,
 125         [IB_QPS_RTS] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
 126             QIB_POST_SEND_OK | QIB_PROCESS_SEND_OK |
 127             QIB_PROCESS_NEXT_SEND_OK,
 128         [IB_QPS_SQD] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
 129             QIB_POST_SEND_OK | QIB_PROCESS_SEND_OK,
 130         [IB_QPS_SQE] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
 131             QIB_POST_SEND_OK | QIB_FLUSH_SEND,
 132         [IB_QPS_ERR] = QIB_POST_RECV_OK | QIB_FLUSH_RECV |
 133             QIB_POST_SEND_OK | QIB_FLUSH_SEND,
 134 };
 135
 136 struct qib_ucontext {
 137         struct ib_ucontext ibucontext;
 138 };
 139
 140 static inline struct qib_ucontext *to_iucontext(struct ib_ucontext
 141                                                   *ibucontext)
 142 {
 143         return container_of(ibucontext, struct qib_ucontext, ibucontext);
 144 }
 145
 146 /*
 147  * Translate ib_wr_opcode into ib_wc_opcode.
 148  */
 149 const enum ib_wc_opcode ib_qib_wc_opcode[] = {
 150         [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
 151         [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
 152         [IB_WR_SEND] = IB_WC_SEND,
 153         [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
 154         [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
 155         [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
 156         [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD
 157 };
 158
 159 /*
 160  * System image GUID.
 161  */
 162 __be64 ib_qib_sys_image_guid;
 163
 164 /**
 165  * qib_copy_sge - copy data to SGE memory
 166  * @ss: the SGE state
 167  * @data: the data to copy
 168  * @length: the length of the data
 169  */
 170 void qib_copy_sge(struct qib_sge_state *ss, void *data, u32 length, int release)
 171 {
 172         struct qib_sge *sge = &ss->sge;
 173
 174         while (length) {
 175                 u32 len = sge->length;
 176
 177                 if (len > length)
 178                         len = length;
 179                 if (len > sge->sge_length)
 180                         len = sge->sge_length;
 181                 BUG_ON(len == 0);
 182                 memcpy(sge->vaddr, data, len);
 183                 sge->vaddr += len;
 184                 sge->length -= len;
 185                 sge->sge_length -= len;
 186                 if (sge->sge_length == 0) {
 187                         if (release)
 188                                 qib_put_mr(sge->mr);
 189                         if (--ss->num_sge)
 190                                 *sge = *ss->sg_list++;
 191                 } else if (sge->length == 0 && sge->mr->lkey) {
 192                         if (++sge->n >= QIB_SEGSZ) {
 193                                 if (++sge->m >= sge->mr->mapsz)
 194                                         break;
 195                                 sge->n = 0;
 196                         }
 197                         sge->vaddr =
 198                                 sge->mr->map[sge->m]->segs[sge->n].vaddr;
 199                         sge->length =
 200                                 sge->mr->map[sge->m]->segs[sge->n].length;
 201                 }
 202                 data += len;
 203                 length -= len;
 204         }
 205 }
 206
 207 /**
 208  * qib_skip_sge - skip over SGE memory - XXX almost dup of prev func
 209  * @ss: the SGE state
 210  * @length: the number of bytes to skip
 211  */
 212 void qib_skip_sge(struct qib_sge_state *ss, u32 length, int release)
 213 {
 214         struct qib_sge *sge = &ss->sge;
 215
 216         while (length) {
 217                 u32 len = sge->length;
 218
 219                 if (len > length)
 220                         len = length;
 221                 if (len > sge->sge_length)
 222                         len = sge->sge_length;
 223                 BUG_ON(len == 0);
 224                 sge->vaddr += len;
 225                 sge->length -= len;
 226                 sge->sge_length -= len;
 227                 if (sge->sge_length == 0) {
 228                         if (release)
 229                                 qib_put_mr(sge->mr);
 230                         if (--ss->num_sge)
 231                                 *sge = *ss->sg_list++;
 232                 } else if (sge->length == 0 && sge->mr->lkey) {
 233                         if (++sge->n >= QIB_SEGSZ) {
 234                                 if (++sge->m >= sge->mr->mapsz)
 235                                         break;
 236                                 sge->n = 0;
 237                         }
 238                         sge->vaddr =
 239                                 sge->mr->map[sge->m]->segs[sge->n].vaddr;
 240                         sge->length =
 241                                 sge->mr->map[sge->m]->segs[sge->n].length;
 242                 }
 243                 length -= len;
 244         }
 245 }
 246
 247 /*
 248  * Count the number of DMA descriptors needed to send length bytes of data.
 249  * Don't modify the qib_sge_state to get the count.
 250  * Return zero if any of the segments is not aligned.
 251  */
 252 static u32 qib_count_sge(struct qib_sge_state *ss, u32 length)
 253 {
 254         struct qib_sge *sg_list = ss->sg_list;
 255         struct qib_sge sge = ss->sge;
 256         u8 num_sge = ss->num_sge;
 257         u32 ndesc = 1;  /* count the header */
 258
 259         while (length) {
 260                 u32 len = sge.length;
 261
 262                 if (len > length)
 263                         len = length;
 264                 if (len > sge.sge_length)
 265                         len = sge.sge_length;
 266                 BUG_ON(len == 0);
 267                 if (((long) sge.vaddr & (sizeof(u32) - 1)) ||
 268                     (len != length && (len & (sizeof(u32) - 1)))) {
 269                         ndesc = 0;
 270                         break;
 271                 }
 272                 ndesc++;
 273                 sge.vaddr += len;
 274                 sge.length -= len;
 275                 sge.sge_length -= len;
 276                 if (sge.sge_length == 0) {
 277                         if (--num_sge)
 278                                 sge = *sg_list++;
 279                 } else if (sge.length == 0 && sge.mr->lkey) {
 280                         if (++sge.n >= QIB_SEGSZ) {
 281                                 if (++sge.m >= sge.mr->mapsz)
 282                                         break;
 283                                 sge.n = 0;
 284                         }
 285                         sge.vaddr =
 286                                 sge.mr->map[sge.m]->segs[sge.n].vaddr;
 287                         sge.length =
 288                                 sge.mr->map[sge.m]->segs[sge.n].length;
 289                 }
 290                 length -= len;
 291         }
 292         return ndesc;
 293 }
 294
 295 /*
 296  * Copy from the SGEs to the data buffer.
 297  */
 298 static void qib_copy_from_sge(void *data, struct qib_sge_state *ss, u32 length)
 299 {
 300         struct qib_sge *sge = &ss->sge;
 301
 302         while (length) {
 303                 u32 len = sge->length;
 304
 305                 if (len > length)
 306                         len = length;
 307                 if (len > sge->sge_length)
 308                         len = sge->sge_length;
 309                 BUG_ON(len == 0);
 310                 memcpy(data, sge->vaddr, len);
 311                 sge->vaddr += len;
 312                 sge->length -= len;
 313                 sge->sge_length -= len;
 314                 if (sge->sge_length == 0) {
 315                         if (--ss->num_sge)
 316                                 *sge = *ss->sg_list++;
 317                 } else if (sge->length == 0 && sge->mr->lkey) {
 318                         if (++sge->n >= QIB_SEGSZ) {
 319                                 if (++sge->m >= sge->mr->mapsz)
 320                                         break;
 321                                 sge->n = 0;
 322                         }
 323                         sge->vaddr =
 324                                 sge->mr->map[sge->m]->segs[sge->n].vaddr;
 325                         sge->length =
 326                                 sge->mr->map[sge->m]->segs[sge->n].length;
 327                 }
 328                 data += len;
 329                 length -= len;
 330         }
 331 }
 332
 333 /**
 334  * qib_post_one_send - post one RC, UC, or UD send work request
 335  * @qp: the QP to post on
 336  * @wr: the work request to send
 337  */
 338 static int qib_post_one_send(struct qib_qp *qp, struct ib_send_wr *wr,
 339         int *scheduled)
 340 {
 341         struct qib_swqe *wqe;
 342         u32 next;
 343         int i;
 344         int j;
 345         int acc;
 346         int ret;
 347         unsigned long flags;
 348         struct qib_lkey_table *rkt;
 349         struct rvt_pd *pd;
 350         int avoid_schedule = 0;
 351
 352         spin_lock_irqsave(&qp->s_lock, flags);
 353
 354         /* Check that state is OK to post send. */
 355         if (unlikely(!(ib_qib_state_ops[qp->state] & QIB_POST_SEND_OK)))
 356                 goto bail_inval;
 357
 358         /* IB spec says that num_sge == 0 is OK. */
 359         if (wr->num_sge > qp->s_max_sge)
 360                 goto bail_inval;
 361
 362         /*
 363          * Don't allow RDMA reads or atomic operations on UC or
 364          * undefined operations.
 365          * Make sure buffer is large enough to hold the result for atomics.
 366          */
 367         if (wr->opcode == IB_WR_REG_MR) {
 368                 if (qib_reg_mr(qp, reg_wr(wr)))
 369                         goto bail_inval;
 370         } else if (qp->ibqp.qp_type == IB_QPT_UC) {
 371                 if ((unsigned) wr->opcode >= IB_WR_RDMA_READ)
 372                         goto bail_inval;
 373         } else if (qp->ibqp.qp_type != IB_QPT_RC) {
 374                 /* Check IB_QPT_SMI, IB_QPT_GSI, IB_QPT_UD opcode */
 375                 if (wr->opcode != IB_WR_SEND &&
 376                     wr->opcode != IB_WR_SEND_WITH_IMM)
 377                         goto bail_inval;
 378                 /* Check UD destination address PD */
 379                 if (qp->ibqp.pd != ud_wr(wr)->ah->pd)
 380                         goto bail_inval;
 381         } else if ((unsigned) wr->opcode > IB_WR_ATOMIC_FETCH_AND_ADD)
 382                 goto bail_inval;
 383         else if (wr->opcode >= IB_WR_ATOMIC_CMP_AND_SWP &&
 384                    (wr->num_sge == 0 ||
 385                     wr->sg_list[0].length < sizeof(u64) ||
 386                     wr->sg_list[0].addr & (sizeof(u64) - 1)))
 387                 goto bail_inval;
 388         else if (wr->opcode >= IB_WR_RDMA_READ && !qp->s_max_rd_atomic)
 389                 goto bail_inval;
 390
 391         next = qp->s_head + 1;
 392         if (next >= qp->s_size)
 393                 next = 0;
 394         if (next == qp->s_last) {
 395                 ret = -ENOMEM;
 396                 goto bail;
 397         }
 398
 399         rkt = &to_idev(qp->ibqp.device)->lk_table;
 400         pd = ibpd_to_rvtpd(qp->ibqp.pd);
 401         wqe = get_swqe_ptr(qp, qp->s_head);
 402
 403         if (qp->ibqp.qp_type != IB_QPT_UC &&
 404             qp->ibqp.qp_type != IB_QPT_RC)
 405                 memcpy(&wqe->ud_wr, ud_wr(wr), sizeof(wqe->ud_wr));
 406         else if (wr->opcode == IB_WR_REG_MR)
 407                 memcpy(&wqe->reg_wr, reg_wr(wr),
 408                         sizeof(wqe->reg_wr));
 409         else if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM ||
 410                  wr->opcode == IB_WR_RDMA_WRITE ||
 411                  wr->opcode == IB_WR_RDMA_READ)
 412                 memcpy(&wqe->rdma_wr, rdma_wr(wr), sizeof(wqe->rdma_wr));
 413         else if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
 414                  wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
 415                 memcpy(&wqe->atomic_wr, atomic_wr(wr), sizeof(wqe->atomic_wr));
 416         else
 417                 memcpy(&wqe->wr, wr, sizeof(wqe->wr));
 418
 419         wqe->length = 0;
 420         j = 0;
 421         if (wr->num_sge) {
 422                 acc = wr->opcode >= IB_WR_RDMA_READ ?
 423                         IB_ACCESS_LOCAL_WRITE : 0;
 424                 for (i = 0; i < wr->num_sge; i++) {
 425                         u32 length = wr->sg_list[i].length;
 426                         int ok;
 427
 428                         if (length == 0)
 429                                 continue;
 430                         ok = qib_lkey_ok(rkt, pd, &wqe->sg_list[j],
 431                                          &wr->sg_list[i], acc);
 432                         if (!ok)
 433                                 goto bail_inval_free;
 434                         wqe->length += length;
 435                         j++;
 436                 }
 437                 wqe->wr.num_sge = j;
 438         }
 439         if (qp->ibqp.qp_type == IB_QPT_UC ||
 440             qp->ibqp.qp_type == IB_QPT_RC) {
 441                 if (wqe->length > 0x80000000U)
 442                         goto bail_inval_free;
 443                 if (wqe->length <= qp->pmtu)
 444                         avoid_schedule = 1;
 445         } else if (wqe->length > (dd_from_ibdev(qp->ibqp.device)->pport +
 446                                   qp->port_num - 1)->ibmtu) {
 447                 goto bail_inval_free;
 448         } else {
 449                 atomic_inc(&to_iah(ud_wr(wr)->ah)->refcount);
 450                 avoid_schedule = 1;
 451         }
 452         wqe->ssn = qp->s_ssn++;
 453         qp->s_head = next;
 454
 455         ret = 0;
 456         goto bail;
 457
 458 bail_inval_free:
 459         while (j) {
 460                 struct qib_sge *sge = &wqe->sg_list[--j];
 461
 462                 qib_put_mr(sge->mr);
 463         }
 464 bail_inval:
 465         ret = -EINVAL;
 466 bail:
 467         if (!ret && !wr->next && !avoid_schedule &&
 468          !qib_sdma_empty(
 469            dd_from_ibdev(qp->ibqp.device)->pport + qp->port_num - 1)) {
 470                 qib_schedule_send(qp);
 471                 *scheduled = 1;
 472         }
 473         spin_unlock_irqrestore(&qp->s_lock, flags);
 474         return ret;
 475 }
 476
 477 /**
 478  * qib_post_send - post a send on a QP
 479  * @ibqp: the QP to post the send on
 480  * @wr: the list of work requests to post
 481  * @bad_wr: the first bad WR is put here
 482  *
 483  * This may be called from interrupt context.
 484  */
 485 static int qib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 486                          struct ib_send_wr **bad_wr)
 487 {
 488         struct qib_qp *qp = to_iqp(ibqp);
 489         struct qib_qp_priv *priv = qp->priv;
 490         int err = 0;
 491         int scheduled = 0;
 492
 493         for (; wr; wr = wr->next) {
 494                 err = qib_post_one_send(qp, wr, &scheduled);
 495                 if (err) {
 496                         *bad_wr = wr;
 497                         goto bail;
 498                 }
 499         }
 500
 501         /* Try to do the send work in the caller's context. */
 502         if (!scheduled)
 503                 qib_do_send(&priv->s_work);
 504
 505 bail:
 506         return err;
 507 }
 508
 509 /**
 510  * qib_post_receive - post a receive on a QP
 511  * @ibqp: the QP to post the receive on
 512  * @wr: the WR to post
 513  * @bad_wr: the first bad WR is put here
 514  *
 515  * This may be called from interrupt context.
 516  */
 517 static int qib_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 518                             struct ib_recv_wr **bad_wr)
 519 {
 520         struct qib_qp *qp = to_iqp(ibqp);
 521         struct qib_rwq *wq = qp->r_rq.wq;
 522         unsigned long flags;
 523         int ret;
 524
 525         /* Check that state is OK to post receive. */
 526         if (!(ib_qib_state_ops[qp->state] & QIB_POST_RECV_OK) || !wq) {
 527                 *bad_wr = wr;
 528                 ret = -EINVAL;
 529                 goto bail;
 530         }
 531
 532         for (; wr; wr = wr->next) {
 533                 struct qib_rwqe *wqe;
 534                 u32 next;
 535                 int i;
 536
 537                 if ((unsigned) wr->num_sge > qp->r_rq.max_sge) {
 538                         *bad_wr = wr;
 539                         ret = -EINVAL;
 540                         goto bail;
 541                 }
 542
 543                 spin_lock_irqsave(&qp->r_rq.lock, flags);
 544                 next = wq->head + 1;
 545                 if (next >= qp->r_rq.size)
 546                         next = 0;
 547                 if (next == wq->tail) {
 548                         spin_unlock_irqrestore(&qp->r_rq.lock, flags);
 549                         *bad_wr = wr;
 550                         ret = -ENOMEM;
 551                         goto bail;
 552                 }
 553
 554                 wqe = get_rwqe_ptr(&qp->r_rq, wq->head);
 555                 wqe->wr_id = wr->wr_id;
 556                 wqe->num_sge = wr->num_sge;
 557                 for (i = 0; i < wr->num_sge; i++)
 558                         wqe->sg_list[i] = wr->sg_list[i];
 559                 /* Make sure queue entry is written before the head index. */
 560                 smp_wmb();
 561                 wq->head = next;
 562                 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
 563         }
 564         ret = 0;
 565
 566 bail:
 567         return ret;
 568 }
 569
 570 /**
 571  * qib_qp_rcv - processing an incoming packet on a QP
 572  * @rcd: the context pointer
 573  * @hdr: the packet header
 574  * @has_grh: true if the packet has a GRH
 575  * @data: the packet data
 576  * @tlen: the packet length
 577  * @qp: the QP the packet came on
 578  *
 579  * This is called from qib_ib_rcv() to process an incoming packet
 580  * for the given QP.
 581  * Called at interrupt level.
 582  */
 583 static void qib_qp_rcv(struct qib_ctxtdata *rcd, struct qib_ib_header *hdr,
 584                        int has_grh, void *data, u32 tlen, struct qib_qp *qp)
 585 {
 586         struct qib_ibport *ibp = &rcd->ppd->ibport_data;
 587
 588         spin_lock(&qp->r_lock);
 589
 590         /* Check for valid receive state. */
 591         if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK)) {
 592                 ibp->n_pkt_drops++;
 593                 goto unlock;
 594         }
 595
 596         switch (qp->ibqp.qp_type) {
 597         case IB_QPT_SMI:
 598         case IB_QPT_GSI:
 599                 if (ib_qib_disable_sma)
 600                         break;
 601                 /* FALLTHROUGH */
 602         case IB_QPT_UD:
 603                 qib_ud_rcv(ibp, hdr, has_grh, data, tlen, qp);
 604                 break;
 605
 606         case IB_QPT_RC:
 607                 qib_rc_rcv(rcd, hdr, has_grh, data, tlen, qp);
 608                 break;
 609
 610         case IB_QPT_UC:
 611                 qib_uc_rcv(ibp, hdr, has_grh, data, tlen, qp);
 612                 break;
 613
 614         default:
 615                 break;
 616         }
 617
 618 unlock:
 619         spin_unlock(&qp->r_lock);
 620 }
 621
 622 /**
 623  * qib_ib_rcv - process an incoming packet
 624  * @rcd: the context pointer
 625  * @rhdr: the header of the packet
 626  * @data: the packet payload
 627  * @tlen: the packet length
 628  *
 629  * This is called from qib_kreceive() to process an incoming packet at
 630  * interrupt level. Tlen is the length of the header + data + CRC in bytes.
 631  */
 632 void qib_ib_rcv(struct qib_ctxtdata *rcd, void *rhdr, void *data, u32 tlen)
 633 {
 634         struct qib_pportdata *ppd = rcd->ppd;
 635         struct qib_ibport *ibp = &ppd->ibport_data;
 636         struct qib_ib_header *hdr = rhdr;
 637         struct qib_other_headers *ohdr;
 638         struct qib_qp *qp;
 639         u32 qp_num;
 640         int lnh;
 641         u8 opcode;
 642         u16 lid;
 643
 644         /* 24 == LRH+BTH+CRC */
 645         if (unlikely(tlen < 24))
 646                 goto drop;
 647
 648         /* Check for a valid destination LID (see ch. 7.11.1). */
 649         lid = be16_to_cpu(hdr->lrh[1]);
 650         if (lid < be16_to_cpu(IB_MULTICAST_LID_BASE)) {
 651                 lid &= ~((1 << ppd->lmc) - 1);
 652                 if (unlikely(lid != ppd->lid))
 653                         goto drop;
 654         }
 655
 656         /* Check for GRH */
 657         lnh = be16_to_cpu(hdr->lrh[0]) & 3;
 658         if (lnh == QIB_LRH_BTH)
 659                 ohdr = &hdr->u.oth;
 660         else if (lnh == QIB_LRH_GRH) {
 661                 u32 vtf;
 662
 663                 ohdr = &hdr->u.l.oth;
 664                 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
 665                         goto drop;
 666                 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
 667                 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
 668                         goto drop;
 669         } else
 670                 goto drop;
 671
 672         opcode = (be32_to_cpu(ohdr->bth[0]) >> 24) & 0x7f;
 673 #ifdef CONFIG_DEBUG_FS
 674         rcd->opstats->stats[opcode].n_bytes += tlen;
 675         rcd->opstats->stats[opcode].n_packets++;
 676 #endif
 677
 678         /* Get the destination QP number. */
 679         qp_num = be32_to_cpu(ohdr->bth[1]) & QIB_QPN_MASK;
 680         if (qp_num == QIB_MULTICAST_QPN) {
 681                 struct qib_mcast *mcast;
 682                 struct qib_mcast_qp *p;
 683
 684                 if (lnh != QIB_LRH_GRH)
 685                         goto drop;
 686                 mcast = qib_mcast_find(ibp, &hdr->u.l.grh.dgid);
 687                 if (mcast == NULL)
 688                         goto drop;
 689                 this_cpu_inc(ibp->pmastats->n_multicast_rcv);
 690                 list_for_each_entry_rcu(p, &mcast->qp_list, list)
 691                         qib_qp_rcv(rcd, hdr, 1, data, tlen, p->qp);
 692                 /*
 693                  * Notify qib_multicast_detach() if it is waiting for us
 694                  * to finish.
 695                  */
 696                 if (atomic_dec_return(&mcast->refcount) <= 1)
 697                         wake_up(&mcast->wait);
 698         } else {
 699                 if (rcd->lookaside_qp) {
 700                         if (rcd->lookaside_qpn != qp_num) {
 701                                 if (atomic_dec_and_test(
 702                                         &rcd->lookaside_qp->refcount))
 703                                         wake_up(
 704                                          &rcd->lookaside_qp->wait);
 705                                 rcd->lookaside_qp = NULL;
 706                         }
 707                 }
 708                 if (!rcd->lookaside_qp) {
 709                         qp = qib_lookup_qpn(ibp, qp_num);
 710                         if (!qp)
 711                                 goto drop;
 712                         rcd->lookaside_qp = qp;
 713                         rcd->lookaside_qpn = qp_num;
 714                 } else
 715                         qp = rcd->lookaside_qp;
 716                 this_cpu_inc(ibp->pmastats->n_unicast_rcv);
 717                 qib_qp_rcv(rcd, hdr, lnh == QIB_LRH_GRH, data, tlen, qp);
 718         }
 719         return;
 720
 721 drop:
 722         ibp->n_pkt_drops++;
 723 }
 724
 725 /*
 726  * This is called from a timer to check for QPs
 727  * which need kernel memory in order to send a packet.
 728  */
 729 static void mem_timer(unsigned long data)
 730 {
 731         struct qib_ibdev *dev = (struct qib_ibdev *) data;
 732         struct list_head *list = &dev->memwait;
 733         struct qib_qp *qp = NULL;
 734         struct qib_qp_priv *priv = NULL;
 735         unsigned long flags;
 736
 737         spin_lock_irqsave(&dev->pending_lock, flags);
 738         if (!list_empty(list)) {
 739                 priv = list_entry(list->next, struct qib_qp_priv, iowait);
 740                 qp = priv->owner;
 741                 list_del_init(&priv->iowait);
 742                 atomic_inc(&qp->refcount);
 743                 if (!list_empty(list))
 744                         mod_timer(&dev->mem_timer, jiffies + 1);
 745         }
 746         spin_unlock_irqrestore(&dev->pending_lock, flags);
 747
 748         if (qp) {
 749                 spin_lock_irqsave(&qp->s_lock, flags);
 750                 if (qp->s_flags & QIB_S_WAIT_KMEM) {
 751                         qp->s_flags &= ~QIB_S_WAIT_KMEM;
 752                         qib_schedule_send(qp);
 753                 }
 754                 spin_unlock_irqrestore(&qp->s_lock, flags);
 755                 if (atomic_dec_and_test(&qp->refcount))
 756                         wake_up(&qp->wait);
 757         }
 758 }
 759
 760 static void update_sge(struct qib_sge_state *ss, u32 length)
 761 {
 762         struct qib_sge *sge = &ss->sge;
 763
 764         sge->vaddr += length;
 765         sge->length -= length;
 766         sge->sge_length -= length;
 767         if (sge->sge_length == 0) {
 768                 if (--ss->num_sge)
 769                         *sge = *ss->sg_list++;
 770         } else if (sge->length == 0 && sge->mr->lkey) {
 771                 if (++sge->n >= QIB_SEGSZ) {
 772                         if (++sge->m >= sge->mr->mapsz)
 773                                 return;
 774                         sge->n = 0;
 775                 }
 776                 sge->vaddr = sge->mr->map[sge->m]->segs[sge->n].vaddr;
 777                 sge->length = sge->mr->map[sge->m]->segs[sge->n].length;
 778         }
 779 }
 780
 781 #ifdef __LITTLE_ENDIAN
 782 static inline u32 get_upper_bits(u32 data, u32 shift)
 783 {
 784         return data >> shift;
 785 }
 786
 787 static inline u32 set_upper_bits(u32 data, u32 shift)
 788 {
 789         return data << shift;
 790 }
 791
 792 static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
 793 {
 794         data <<= ((sizeof(u32) - n) * BITS_PER_BYTE);
 795         data >>= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
 796         return data;
 797 }
 798 #else
 799 static inline u32 get_upper_bits(u32 data, u32 shift)
 800 {
 801         return data << shift;
 802 }
 803
 804 static inline u32 set_upper_bits(u32 data, u32 shift)
 805 {
 806         return data >> shift;
 807 }
 808
 809 static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
 810 {
 811         data >>= ((sizeof(u32) - n) * BITS_PER_BYTE);
 812         data <<= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
 813         return data;
 814 }
 815 #endif
 816
 817 static void copy_io(u32 __iomem *piobuf, struct qib_sge_state *ss,
 818                     u32 length, unsigned flush_wc)
 819 {
 820         u32 extra = 0;
 821         u32 data = 0;
 822         u32 last;
 823
 824         while (1) {
 825                 u32 len = ss->sge.length;
 826                 u32 off;
 827
 828                 if (len > length)
 829                         len = length;
 830                 if (len > ss->sge.sge_length)
 831                         len = ss->sge.sge_length;
 832                 BUG_ON(len == 0);
 833                 /* If the source address is not aligned, try to align it. */
 834                 off = (unsigned long)ss->sge.vaddr & (sizeof(u32) - 1);
 835                 if (off) {
 836                         u32 *addr = (u32 *)((unsigned long)ss->sge.vaddr &
 837                                             ~(sizeof(u32) - 1));
 838                         u32 v = get_upper_bits(*addr, off * BITS_PER_BYTE);
 839                         u32 y;
 840
 841                         y = sizeof(u32) - off;
 842                         if (len > y)
 843                                 len = y;
 844                         if (len + extra >= sizeof(u32)) {
 845                                 data |= set_upper_bits(v, extra *
 846                                                        BITS_PER_BYTE);
 847                                 len = sizeof(u32) - extra;
 848                                 if (len == length) {
 849                                         last = data;
 850                                         break;
 851                                 }
 852                                 __raw_writel(data, piobuf);
 853                                 piobuf++;
 854                                 extra = 0;
 855                                 data = 0;
 856                         } else {
 857                                 /* Clear unused upper bytes */
 858                                 data |= clear_upper_bytes(v, len, extra);
 859                                 if (len == length) {
 860                                         last = data;
 861                                         break;
 862                                 }
 863                                 extra += len;
 864                         }
 865                 } else if (extra) {
 866                         /* Source address is aligned. */
 867                         u32 *addr = (u32 *) ss->sge.vaddr;
 868                         int shift = extra * BITS_PER_BYTE;
 869                         int ushift = 32 - shift;
 870                         u32 l = len;
 871
 872                         while (l >= sizeof(u32)) {
 873                                 u32 v = *addr;
 874
 875                                 data |= set_upper_bits(v, shift);
 876                                 __raw_writel(data, piobuf);
 877                                 data = get_upper_bits(v, ushift);
 878                                 piobuf++;
 879                                 addr++;
 880                                 l -= sizeof(u32);
 881                         }
 882                         /*
 883                          * We still have 'extra' number of bytes leftover.
 884                          */
 885                         if (l) {
 886                                 u32 v = *addr;
 887
 888                                 if (l + extra >= sizeof(u32)) {
 889                                         data |= set_upper_bits(v, shift);
 890                                         len -= l + extra - sizeof(u32);
 891                                         if (len == length) {
 892                                                 last = data;
 893                                                 break;
 894                                         }
 895                                         __raw_writel(data, piobuf);
 896                                         piobuf++;
 897                                         extra = 0;
 898                                         data = 0;
 899                                 } else {
 900                                         /* Clear unused upper bytes */
 901                                         data |= clear_upper_bytes(v, l, extra);
 902                                         if (len == length) {
 903                                                 last = data;
 904                                                 break;
 905                                         }
 906                                         extra += l;
 907                                 }
 908                         } else if (len == length) {
 909                                 last = data;
 910                                 break;
 911                         }
 912                 } else if (len == length) {
 913                         u32 w;
 914
 915                         /*
 916                          * Need to round up for the last dword in the
 917                          * packet.
 918                          */
 919                         w = (len + 3) >> 2;
 920                         qib_pio_copy(piobuf, ss->sge.vaddr, w - 1);
 921                         piobuf += w - 1;
 922                         last = ((u32 *) ss->sge.vaddr)[w - 1];
 923                         break;
 924                 } else {
 925                         u32 w = len >> 2;
 926
 927                         qib_pio_copy(piobuf, ss->sge.vaddr, w);
 928                         piobuf += w;
 929
 930                         extra = len & (sizeof(u32) - 1);
 931                         if (extra) {
 932                                 u32 v = ((u32 *) ss->sge.vaddr)[w];
 933
 934                                 /* Clear unused upper bytes */
 935                                 data = clear_upper_bytes(v, extra, 0);
 936                         }
 937                 }
 938                 update_sge(ss, len);
 939                 length -= len;
 940         }
 941         /* Update address before sending packet. */
 942         update_sge(ss, length);
 943         if (flush_wc) {
 944                 /* must flush early everything before trigger word */
 945                 qib_flush_wc();
 946                 __raw_writel(last, piobuf);
 947                 /* be sure trigger word is written */
 948                 qib_flush_wc();
 949         } else
 950                 __raw_writel(last, piobuf);
 951 }
 952
 953 static noinline struct qib_verbs_txreq *__get_txreq(struct qib_ibdev *dev,
 954                                            struct qib_qp *qp)
 955 {
 956         struct qib_qp_priv *priv = qp->priv;
 957         struct qib_verbs_txreq *tx;
 958         unsigned long flags;
 959
 960         spin_lock_irqsave(&qp->s_lock, flags);
 961         spin_lock(&dev->pending_lock);
 962
 963         if (!list_empty(&dev->txreq_free)) {
 964                 struct list_head *l = dev->txreq_free.next;
 965
 966                 list_del(l);
 967                 spin_unlock(&dev->pending_lock);
 968                 spin_unlock_irqrestore(&qp->s_lock, flags);
 969                 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
 970         } else {
 971                 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK &&
 972                     list_empty(&priv->iowait)) {
 973                         dev->n_txwait++;
 974                         qp->s_flags |= QIB_S_WAIT_TX;
 975                         list_add_tail(&priv->iowait, &dev->txwait);
 976                 }
 977                 qp->s_flags &= ~QIB_S_BUSY;
 978                 spin_unlock(&dev->pending_lock);
 979                 spin_unlock_irqrestore(&qp->s_lock, flags);
 980                 tx = ERR_PTR(-EBUSY);
 981         }
 982         return tx;
 983 }
 984
 985 static inline struct qib_verbs_txreq *get_txreq(struct qib_ibdev *dev,
 986                                          struct qib_qp *qp)
 987 {
 988         struct qib_verbs_txreq *tx;
 989         unsigned long flags;
 990
 991         spin_lock_irqsave(&dev->pending_lock, flags);
 992         /* assume the list non empty */
 993         if (likely(!list_empty(&dev->txreq_free))) {
 994                 struct list_head *l = dev->txreq_free.next;
 995
 996                 list_del(l);
 997                 spin_unlock_irqrestore(&dev->pending_lock, flags);
 998                 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
 999         } else {
1000                 /* call slow path to get the extra lock */
1001                 spin_unlock_irqrestore(&dev->pending_lock, flags);
1002                 tx =  __get_txreq(dev, qp);
1003         }
1004         return tx;
1005 }
1006
1007 void qib_put_txreq(struct qib_verbs_txreq *tx)
1008 {
1009         struct qib_ibdev *dev;
1010         struct qib_qp *qp;
1011         struct qib_qp_priv *priv;
1012         unsigned long flags;
1013
1014         qp = tx->qp;
1015         dev = to_idev(qp->ibqp.device);
1016
1017         if (atomic_dec_and_test(&qp->refcount))
1018                 wake_up(&qp->wait);
1019         if (tx->mr) {
1020                 qib_put_mr(tx->mr);
1021                 tx->mr = NULL;
1022         }
1023         if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF) {
1024                 tx->txreq.flags &= ~QIB_SDMA_TXREQ_F_FREEBUF;
1025                 dma_unmap_single(&dd_from_dev(dev)->pcidev->dev,
1026                                  tx->txreq.addr, tx->hdr_dwords << 2,
1027                                  DMA_TO_DEVICE);
1028                 kfree(tx->align_buf);
1029         }
1030
1031         spin_lock_irqsave(&dev->pending_lock, flags);
1032
1033         /* Put struct back on free list */
1034         list_add(&tx->txreq.list, &dev->txreq_free);
1035
1036         if (!list_empty(&dev->txwait)) {
1037                 /* Wake up first QP wanting a free struct */
1038                 priv = list_entry(dev->txwait.next, struct qib_qp_priv,
1039                                   iowait);
1040                 qp = priv->owner;
1041                 list_del_init(&priv->iowait);
1042                 atomic_inc(&qp->refcount);
1043                 spin_unlock_irqrestore(&dev->pending_lock, flags);
1044
1045                 spin_lock_irqsave(&qp->s_lock, flags);
1046                 if (qp->s_flags & QIB_S_WAIT_TX) {
1047                         qp->s_flags &= ~QIB_S_WAIT_TX;
1048                         qib_schedule_send(qp);
1049                 }
1050                 spin_unlock_irqrestore(&qp->s_lock, flags);
1051
1052                 if (atomic_dec_and_test(&qp->refcount))
1053                         wake_up(&qp->wait);
1054         } else
1055                 spin_unlock_irqrestore(&dev->pending_lock, flags);
1056 }
1057
1058 /*
1059  * This is called when there are send DMA descriptors that might be
1060  * available.
1061  *
1062  * This is called with ppd->sdma_lock held.
1063  */
1064 void qib_verbs_sdma_desc_avail(struct qib_pportdata *ppd, unsigned avail)
1065 {
1066         struct qib_qp *qp, *nqp;
1067         struct qib_qp_priv *qpp, *nqpp;
1068         struct qib_qp *qps[20];
1069         struct qib_ibdev *dev;
1070         unsigned i, n;
1071
1072         n = 0;
1073         dev = &ppd->dd->verbs_dev;
1074         spin_lock(&dev->pending_lock);
1075
1076         /* Search wait list for first QP wanting DMA descriptors. */
1077         list_for_each_entry_safe(qpp, nqpp, &dev->dmawait, iowait) {
1078                 qp = qpp->owner;
1079                 nqp = nqpp->owner;
1080                 if (qp->port_num != ppd->port)
1081                         continue;
1082                 if (n == ARRAY_SIZE(qps))
1083                         break;
1084                 if (qpp->s_tx->txreq.sg_count > avail)
1085                         break;
1086                 avail -= qpp->s_tx->txreq.sg_count;
1087                 list_del_init(&qpp->iowait);
1088                 atomic_inc(&qp->refcount);
1089                 qps[n++] = qp;
1090         }
1091
1092         spin_unlock(&dev->pending_lock);
1093
1094         for (i = 0; i < n; i++) {
1095                 qp = qps[i];
1096                 spin_lock(&qp->s_lock);
1097                 if (qp->s_flags & QIB_S_WAIT_DMA_DESC) {
1098                         qp->s_flags &= ~QIB_S_WAIT_DMA_DESC;
1099                         qib_schedule_send(qp);
1100                 }
1101                 spin_unlock(&qp->s_lock);
1102                 if (atomic_dec_and_test(&qp->refcount))
1103                         wake_up(&qp->wait);
1104         }
1105 }
1106
1107 /*
1108  * This is called with ppd->sdma_lock held.
1109  */
1110 static void sdma_complete(struct qib_sdma_txreq *cookie, int status)
1111 {
1112         struct qib_verbs_txreq *tx =
1113                 container_of(cookie, struct qib_verbs_txreq, txreq);
1114         struct qib_qp *qp = tx->qp;
1115         struct qib_qp_priv *priv = qp->priv;
1116
1117         spin_lock(&qp->s_lock);
1118         if (tx->wqe)
1119                 qib_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
1120         else if (qp->ibqp.qp_type == IB_QPT_RC) {
1121                 struct qib_ib_header *hdr;
1122
1123                 if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF)
1124                         hdr = &tx->align_buf->hdr;
1125                 else {
1126                         struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1127
1128                         hdr = &dev->pio_hdrs[tx->hdr_inx].hdr;
1129                 }
1130                 qib_rc_send_complete(qp, hdr);
1131         }
1132         if (atomic_dec_and_test(&priv->s_dma_busy)) {
1133                 if (qp->state == IB_QPS_RESET)
1134                         wake_up(&priv->wait_dma);
1135                 else if (qp->s_flags & QIB_S_WAIT_DMA) {
1136                         qp->s_flags &= ~QIB_S_WAIT_DMA;
1137                         qib_schedule_send(qp);
1138                 }
1139         }
1140         spin_unlock(&qp->s_lock);
1141
1142         qib_put_txreq(tx);
1143 }
1144
1145 static int wait_kmem(struct qib_ibdev *dev, struct qib_qp *qp)
1146 {
1147         struct qib_qp_priv *priv = qp->priv;
1148         unsigned long flags;
1149         int ret = 0;
1150
1151         spin_lock_irqsave(&qp->s_lock, flags);
1152         if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK) {
1153                 spin_lock(&dev->pending_lock);
1154                 if (list_empty(&priv->iowait)) {
1155                         if (list_empty(&dev->memwait))
1156                                 mod_timer(&dev->mem_timer, jiffies + 1);
1157                         qp->s_flags |= QIB_S_WAIT_KMEM;
1158                         list_add_tail(&priv->iowait, &dev->memwait);
1159                 }
1160                 spin_unlock(&dev->pending_lock);
1161                 qp->s_flags &= ~QIB_S_BUSY;
1162                 ret = -EBUSY;
1163         }
1164         spin_unlock_irqrestore(&qp->s_lock, flags);
1165
1166         return ret;
1167 }
1168
1169 static int qib_verbs_send_dma(struct qib_qp *qp, struct qib_ib_header *hdr,
1170                               u32 hdrwords, struct qib_sge_state *ss, u32 len,
1171                               u32 plen, u32 dwords)
1172 {
1173         struct qib_qp_priv *priv = qp->priv;
1174         struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1175         struct qib_devdata *dd = dd_from_dev(dev);
1176         struct qib_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
1177         struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1178         struct qib_verbs_txreq *tx;
1179         struct qib_pio_header *phdr;
1180         u32 control;
1181         u32 ndesc;
1182         int ret;
1183
1184         tx = priv->s_tx;
1185         if (tx) {
1186                 priv->s_tx = NULL;
1187                 /* resend previously constructed packet */
1188                 ret = qib_sdma_verbs_send(ppd, tx->ss, tx->dwords, tx);
1189                 goto bail;
1190         }
1191
1192         tx = get_txreq(dev, qp);
1193         if (IS_ERR(tx))
1194                 goto bail_tx;
1195
1196         control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
1197                                        be16_to_cpu(hdr->lrh[0]) >> 12);
1198         tx->qp = qp;
1199         atomic_inc(&qp->refcount);
1200         tx->wqe = qp->s_wqe;
1201         tx->mr = qp->s_rdma_mr;
1202         if (qp->s_rdma_mr)
1203                 qp->s_rdma_mr = NULL;
1204         tx->txreq.callback = sdma_complete;
1205         if (dd->flags & QIB_HAS_SDMA_TIMEOUT)
1206                 tx->txreq.flags = QIB_SDMA_TXREQ_F_HEADTOHOST;
1207         else
1208                 tx->txreq.flags = QIB_SDMA_TXREQ_F_INTREQ;
1209         if (plen + 1 > dd->piosize2kmax_dwords)
1210                 tx->txreq.flags |= QIB_SDMA_TXREQ_F_USELARGEBUF;
1211
1212         if (len) {
1213                 /*
1214                  * Don't try to DMA if it takes more descriptors than
1215                  * the queue holds.
1216                  */
1217                 ndesc = qib_count_sge(ss, len);
1218                 if (ndesc >= ppd->sdma_descq_cnt)
1219                         ndesc = 0;
1220         } else
1221                 ndesc = 1;
1222         if (ndesc) {
1223                 phdr = &dev->pio_hdrs[tx->hdr_inx];
1224                 phdr->pbc[0] = cpu_to_le32(plen);
1225                 phdr->pbc[1] = cpu_to_le32(control);
1226                 memcpy(&phdr->hdr, hdr, hdrwords << 2);
1227                 tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEDESC;
1228                 tx->txreq.sg_count = ndesc;
1229                 tx->txreq.addr = dev->pio_hdrs_phys +
1230                         tx->hdr_inx * sizeof(struct qib_pio_header);
1231                 tx->hdr_dwords = hdrwords + 2; /* add PBC length */
1232                 ret = qib_sdma_verbs_send(ppd, ss, dwords, tx);
1233                 goto bail;
1234         }
1235
1236         /* Allocate a buffer and copy the header and payload to it. */
1237         tx->hdr_dwords = plen + 1;
1238         phdr = kmalloc(tx->hdr_dwords << 2, GFP_ATOMIC);
1239         if (!phdr)
1240                 goto err_tx;
1241         phdr->pbc[0] = cpu_to_le32(plen);
1242         phdr->pbc[1] = cpu_to_le32(control);
1243         memcpy(&phdr->hdr, hdr, hdrwords << 2);
1244         qib_copy_from_sge((u32 *) &phdr->hdr + hdrwords, ss, len);
1245
1246         tx->txreq.addr = dma_map_single(&dd->pcidev->dev, phdr,
1247                                         tx->hdr_dwords << 2, DMA_TO_DEVICE);
1248         if (dma_mapping_error(&dd->pcidev->dev, tx->txreq.addr))
1249                 goto map_err;
1250         tx->align_buf = phdr;
1251         tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEBUF;
1252         tx->txreq.sg_count = 1;
1253         ret = qib_sdma_verbs_send(ppd, NULL, 0, tx);
1254         goto unaligned;
1255
1256 map_err:
1257         kfree(phdr);
1258 err_tx:
1259         qib_put_txreq(tx);
1260         ret = wait_kmem(dev, qp);
1261 unaligned:
1262         ibp->n_unaligned++;
1263 bail:
1264         return ret;
1265 bail_tx:
1266         ret = PTR_ERR(tx);
1267         goto bail;
1268 }
1269
1270 /*
1271  * If we are now in the error state, return zero to flush the
1272  * send work request.
1273  */
1274 static int no_bufs_available(struct qib_qp *qp)
1275 {
1276         struct qib_qp_priv *priv = qp->priv;
1277         struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1278         struct qib_devdata *dd;
1279         unsigned long flags;
1280         int ret = 0;
1281
1282         /*
1283          * Note that as soon as want_buffer() is called and
1284          * possibly before it returns, qib_ib_piobufavail()
1285          * could be called. Therefore, put QP on the I/O wait list before
1286          * enabling the PIO avail interrupt.
1287          */
1288         spin_lock_irqsave(&qp->s_lock, flags);
1289         if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK) {
1290                 spin_lock(&dev->pending_lock);
1291                 if (list_empty(&priv->iowait)) {
1292                         dev->n_piowait++;
1293                         qp->s_flags |= QIB_S_WAIT_PIO;
1294                         list_add_tail(&priv->iowait, &dev->piowait);
1295                         dd = dd_from_dev(dev);
1296                         dd->f_wantpiobuf_intr(dd, 1);
1297                 }
1298                 spin_unlock(&dev->pending_lock);
1299                 qp->s_flags &= ~QIB_S_BUSY;
1300                 ret = -EBUSY;
1301         }
1302         spin_unlock_irqrestore(&qp->s_lock, flags);
1303         return ret;
1304 }
1305
1306 static int qib_verbs_send_pio(struct qib_qp *qp, struct qib_ib_header *ibhdr,
1307                               u32 hdrwords, struct qib_sge_state *ss, u32 len,
1308                               u32 plen, u32 dwords)
1309 {
1310         struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1311         struct qib_pportdata *ppd = dd->pport + qp->port_num - 1;
1312         u32 *hdr = (u32 *) ibhdr;
1313         u32 __iomem *piobuf_orig;
1314         u32 __iomem *piobuf;
1315         u64 pbc;
1316         unsigned long flags;
1317         unsigned flush_wc;
1318         u32 control;
1319         u32 pbufn;
1320
1321         control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
1322                 be16_to_cpu(ibhdr->lrh[0]) >> 12);
1323         pbc = ((u64) control << 32) | plen;
1324         piobuf = dd->f_getsendbuf(ppd, pbc, &pbufn);
1325         if (unlikely(piobuf == NULL))
1326                 return no_bufs_available(qp);
1327
1328         /*
1329          * Write the pbc.
1330          * We have to flush after the PBC for correctness on some cpus
1331          * or WC buffer can be written out of order.
1332          */
1333         writeq(pbc, piobuf);
1334         piobuf_orig = piobuf;
1335         piobuf += 2;
1336
1337         flush_wc = dd->flags & QIB_PIO_FLUSH_WC;
1338         if (len == 0) {
1339                 /*
1340                  * If there is just the header portion, must flush before
1341                  * writing last word of header for correctness, and after
1342                  * the last header word (trigger word).
1343                  */
1344                 if (flush_wc) {
1345                         qib_flush_wc();
1346                         qib_pio_copy(piobuf, hdr, hdrwords - 1);
1347                         qib_flush_wc();
1348                         __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords - 1);
1349                         qib_flush_wc();
1350                 } else
1351                         qib_pio_copy(piobuf, hdr, hdrwords);
1352                 goto done;
1353         }
1354
1355         if (flush_wc)
1356                 qib_flush_wc();
1357         qib_pio_copy(piobuf, hdr, hdrwords);
1358         piobuf += hdrwords;
1359
1360         /* The common case is aligned and contained in one segment. */
1361         if (likely(ss->num_sge == 1 && len <= ss->sge.length &&
1362                    !((unsigned long)ss->sge.vaddr & (sizeof(u32) - 1)))) {
1363                 u32 *addr = (u32 *) ss->sge.vaddr;
1364
1365                 /* Update address before sending packet. */
1366                 update_sge(ss, len);
1367                 if (flush_wc) {
1368                         qib_pio_copy(piobuf, addr, dwords - 1);
1369                         /* must flush early everything before trigger word */
1370                         qib_flush_wc();
1371                         __raw_writel(addr[dwords - 1], piobuf + dwords - 1);
1372                         /* be sure trigger word is written */
1373                         qib_flush_wc();
1374                 } else
1375                         qib_pio_copy(piobuf, addr, dwords);
1376                 goto done;
1377         }
1378         copy_io(piobuf, ss, len, flush_wc);
1379 done:
1380         if (dd->flags & QIB_USE_SPCL_TRIG) {
1381                 u32 spcl_off = (pbufn >= dd->piobcnt2k) ? 2047 : 1023;
1382
1383                 qib_flush_wc();
1384                 __raw_writel(0xaebecede, piobuf_orig + spcl_off);
1385         }
1386         qib_sendbuf_done(dd, pbufn);
1387         if (qp->s_rdma_mr) {
1388                 qib_put_mr(qp->s_rdma_mr);
1389                 qp->s_rdma_mr = NULL;
1390         }
1391         if (qp->s_wqe) {
1392                 spin_lock_irqsave(&qp->s_lock, flags);
1393                 qib_send_complete(qp, qp->s_wqe, IB_WC_SUCCESS);
1394                 spin_unlock_irqrestore(&qp->s_lock, flags);
1395         } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1396                 spin_lock_irqsave(&qp->s_lock, flags);
1397                 qib_rc_send_complete(qp, ibhdr);
1398                 spin_unlock_irqrestore(&qp->s_lock, flags);
1399         }
1400         return 0;
1401 }
1402
1403 /**
1404  * qib_verbs_send - send a packet
1405  * @qp: the QP to send on
1406  * @hdr: the packet header
1407  * @hdrwords: the number of 32-bit words in the header
1408  * @ss: the SGE to send
1409  * @len: the length of the packet in bytes
1410  *
1411  * Return zero if packet is sent or queued OK.
1412  * Return non-zero and clear qp->s_flags QIB_S_BUSY otherwise.
1413  */
1414 int qib_verbs_send(struct qib_qp *qp, struct qib_ib_header *hdr,
1415                    u32 hdrwords, struct qib_sge_state *ss, u32 len)
1416 {
1417         struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1418         u32 plen;
1419         int ret;
1420         u32 dwords = (len + 3) >> 2;
1421
1422         /*
1423          * Calculate the send buffer trigger address.
1424          * The +1 counts for the pbc control dword following the pbc length.
1425          */
1426         plen = hdrwords + dwords + 1;
1427
1428         /*
1429          * VL15 packets (IB_QPT_SMI) will always use PIO, so we
1430          * can defer SDMA restart until link goes ACTIVE without
1431          * worrying about just how we got there.
1432          */
1433         if (qp->ibqp.qp_type == IB_QPT_SMI ||
1434             !(dd->flags & QIB_HAS_SEND_DMA))
1435                 ret = qib_verbs_send_pio(qp, hdr, hdrwords, ss, len,
1436                                          plen, dwords);
1437         else
1438                 ret = qib_verbs_send_dma(qp, hdr, hdrwords, ss, len,
1439                                          plen, dwords);
1440
1441         return ret;
1442 }
1443
1444 int qib_snapshot_counters(struct qib_pportdata *ppd, u64 *swords,
1445                           u64 *rwords, u64 *spkts, u64 *rpkts,
1446                           u64 *xmit_wait)
1447 {
1448         int ret;
1449         struct qib_devdata *dd = ppd->dd;
1450
1451         if (!(dd->flags & QIB_PRESENT)) {
1452                 /* no hardware, freeze, etc. */
1453                 ret = -EINVAL;
1454                 goto bail;
1455         }
1456         *swords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDSEND);
1457         *rwords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDRCV);
1458         *spkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTSEND);
1459         *rpkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTRCV);
1460         *xmit_wait = dd->f_portcntr(ppd, QIBPORTCNTR_SENDSTALL);
1461
1462         ret = 0;
1463
1464 bail:
1465         return ret;
1466 }
1467
1468 /**
1469  * qib_get_counters - get various chip counters
1470  * @dd: the qlogic_ib device
1471  * @cntrs: counters are placed here
1472  *
1473  * Return the counters needed by recv_pma_get_portcounters().
1474  */
1475 int qib_get_counters(struct qib_pportdata *ppd,
1476                      struct qib_verbs_counters *cntrs)
1477 {
1478         int ret;
1479
1480         if (!(ppd->dd->flags & QIB_PRESENT)) {
1481                 /* no hardware, freeze, etc. */
1482                 ret = -EINVAL;
1483                 goto bail;
1484         }
1485         cntrs->symbol_error_counter =
1486                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBSYMBOLERR);
1487         cntrs->link_error_recovery_counter =
1488                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKERRRECOV);
1489         /*
1490          * The link downed counter counts when the other side downs the
1491          * connection.  We add in the number of times we downed the link
1492          * due to local link integrity errors to compensate.
1493          */
1494         cntrs->link_downed_counter =
1495                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKDOWN);
1496         cntrs->port_rcv_errors =
1497                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXDROPPKT) +
1498                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVOVFL) +
1499                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERR_RLEN) +
1500                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_INVALIDRLEN) +
1501                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLINK) +
1502                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRICRC) +
1503                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRVCRC) +
1504                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLPCRC) +
1505                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_BADFORMAT);
1506         cntrs->port_rcv_errors +=
1507                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXLOCALPHYERR);
1508         cntrs->port_rcv_errors +=
1509                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXVLERR);
1510         cntrs->port_rcv_remphys_errors =
1511                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVEBP);
1512         cntrs->port_xmit_discards =
1513                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_UNSUPVL);
1514         cntrs->port_xmit_data = ppd->dd->f_portcntr(ppd,
1515                         QIBPORTCNTR_WORDSEND);
1516         cntrs->port_rcv_data = ppd->dd->f_portcntr(ppd,
1517                         QIBPORTCNTR_WORDRCV);
1518         cntrs->port_xmit_packets = ppd->dd->f_portcntr(ppd,
1519                         QIBPORTCNTR_PKTSEND);
1520         cntrs->port_rcv_packets = ppd->dd->f_portcntr(ppd,
1521                         QIBPORTCNTR_PKTRCV);
1522         cntrs->local_link_integrity_errors =
1523                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_LLI);
1524         cntrs->excessive_buffer_overrun_errors =
1525                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_EXCESSBUFOVFL);
1526         cntrs->vl15_dropped =
1527                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_VL15PKTDROP);
1528
1529         ret = 0;
1530
1531 bail:
1532         return ret;
1533 }
1534
1535 /**
1536  * qib_ib_piobufavail - callback when a PIO buffer is available
1537  * @dd: the device pointer
1538  *
1539  * This is called from qib_intr() at interrupt level when a PIO buffer is
1540  * available after qib_verbs_send() returned an error that no buffers were
1541  * available. Disable the interrupt if there are no more QPs waiting.
1542  */
1543 void qib_ib_piobufavail(struct qib_devdata *dd)
1544 {
1545         struct qib_ibdev *dev = &dd->verbs_dev;
1546         struct list_head *list;
1547         struct qib_qp *qps[5];
1548         struct qib_qp *qp;
1549         unsigned long flags;
1550         unsigned i, n;
1551         struct qib_qp_priv *priv;
1552
1553         list = &dev->piowait;
1554         n = 0;
1555
1556         /*
1557          * Note: checking that the piowait list is empty and clearing
1558          * the buffer available interrupt needs to be atomic or we
1559          * could end up with QPs on the wait list with the interrupt
1560          * disabled.
1561          */
1562         spin_lock_irqsave(&dev->pending_lock, flags);
1563         while (!list_empty(list)) {
1564                 if (n == ARRAY_SIZE(qps))
1565                         goto full;
1566                 priv = list_entry(list->next, struct qib_qp_priv, iowait);
1567                 qp = priv->owner;
1568                 list_del_init(&priv->iowait);
1569                 atomic_inc(&qp->refcount);
1570                 qps[n++] = qp;
1571         }
1572         dd->f_wantpiobuf_intr(dd, 0);
1573 full:
1574         spin_unlock_irqrestore(&dev->pending_lock, flags);
1575
1576         for (i = 0; i < n; i++) {
1577                 qp = qps[i];
1578
1579                 spin_lock_irqsave(&qp->s_lock, flags);
1580                 if (qp->s_flags & QIB_S_WAIT_PIO) {
1581                         qp->s_flags &= ~QIB_S_WAIT_PIO;
1582                         qib_schedule_send(qp);
1583                 }
1584                 spin_unlock_irqrestore(&qp->s_lock, flags);
1585
1586                 /* Notify qib_destroy_qp() if it is waiting. */
1587                 if (atomic_dec_and_test(&qp->refcount))
1588                         wake_up(&qp->wait);
1589         }
1590 }
1591
1592 static int qib_query_device(struct ib_device *ibdev, struct ib_device_attr *props,
1593                             struct ib_udata *uhw)
1594 {
1595         struct qib_devdata *dd = dd_from_ibdev(ibdev);
1596         struct qib_ibdev *dev = to_idev(ibdev);
1597
1598         if (uhw->inlen || uhw->outlen)
1599                 return -EINVAL;
1600         memset(props, 0, sizeof(*props));
1601
1602         props->device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1603                 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1604                 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1605                 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE;
1606         props->page_size_cap = PAGE_SIZE;
1607         props->vendor_id =
1608                 QIB_SRC_OUI_1 << 16 | QIB_SRC_OUI_2 << 8 | QIB_SRC_OUI_3;
1609         props->vendor_part_id = dd->deviceid;
1610         props->hw_ver = dd->minrev;
1611         props->sys_image_guid = ib_qib_sys_image_guid;
1612         props->max_mr_size = ~0ULL;
1613         props->max_qp = ib_qib_max_qps;
1614         props->max_qp_wr = ib_qib_max_qp_wrs;
1615         props->max_sge = ib_qib_max_sges;
1616         props->max_sge_rd = ib_qib_max_sges;
1617         props->max_cq = ib_qib_max_cqs;
1618         props->max_ah = ib_qib_max_ahs;
1619         props->max_cqe = ib_qib_max_cqes;
1620         props->max_mr = dev->lk_table.max;
1621         props->max_fmr = dev->lk_table.max;
1622         props->max_map_per_fmr = 32767;
1623         props->max_pd = dev->rdi.dparms.props.max_pd;
1624         props->max_qp_rd_atom = QIB_MAX_RDMA_ATOMIC;
1625         props->max_qp_init_rd_atom = 255;
1626         /* props->max_res_rd_atom */
1627         props->max_srq = ib_qib_max_srqs;
1628         props->max_srq_wr = ib_qib_max_srq_wrs;
1629         props->max_srq_sge = ib_qib_max_srq_sges;
1630         /* props->local_ca_ack_delay */
1631         props->atomic_cap = IB_ATOMIC_GLOB;
1632         props->max_pkeys = qib_get_npkeys(dd);
1633         props->max_mcast_grp = ib_qib_max_mcast_grps;
1634         props->max_mcast_qp_attach = ib_qib_max_mcast_qp_attached;
1635         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1636                 props->max_mcast_grp;
1637
1638         return 0;
1639 }
1640
1641 static int qib_query_port(struct ib_device *ibdev, u8 port,
1642                           struct ib_port_attr *props)
1643 {
1644         struct qib_devdata *dd = dd_from_ibdev(ibdev);
1645         struct qib_ibport *ibp = to_iport(ibdev, port);
1646         struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1647         enum ib_mtu mtu;
1648         u16 lid = ppd->lid;
1649
1650         memset(props, 0, sizeof(*props));
1651         props->lid = lid ? lid : be16_to_cpu(IB_LID_PERMISSIVE);
1652         props->lmc = ppd->lmc;
1653         props->sm_lid = ibp->sm_lid;
1654         props->sm_sl = ibp->sm_sl;
1655         props->state = dd->f_iblink_state(ppd->lastibcstat);
1656         props->phys_state = dd->f_ibphys_portstate(ppd->lastibcstat);
1657         props->port_cap_flags = ibp->port_cap_flags;
1658         props->gid_tbl_len = QIB_GUIDS_PER_PORT;
1659         props->max_msg_sz = 0x80000000;
1660         props->pkey_tbl_len = qib_get_npkeys(dd);
1661         props->bad_pkey_cntr = ibp->pkey_violations;
1662         props->qkey_viol_cntr = ibp->qkey_violations;
1663         props->active_width = ppd->link_width_active;
1664         /* See rate_show() */
1665         props->active_speed = ppd->link_speed_active;
1666         props->max_vl_num = qib_num_vls(ppd->vls_supported);
1667         props->init_type_reply = 0;
1668
1669         props->max_mtu = qib_ibmtu ? qib_ibmtu : IB_MTU_4096;
1670         switch (ppd->ibmtu) {
1671         case 4096:
1672                 mtu = IB_MTU_4096;
1673                 break;
1674         case 2048:
1675                 mtu = IB_MTU_2048;
1676                 break;
1677         case 1024:
1678                 mtu = IB_MTU_1024;
1679                 break;
1680         case 512:
1681                 mtu = IB_MTU_512;
1682                 break;
1683         case 256:
1684                 mtu = IB_MTU_256;
1685                 break;
1686         default:
1687                 mtu = IB_MTU_2048;
1688         }
1689         props->active_mtu = mtu;
1690         props->subnet_timeout = ibp->subnet_timeout;
1691
1692         return 0;
1693 }
1694
1695 static int qib_modify_device(struct ib_device *device,
1696                              int device_modify_mask,
1697                              struct ib_device_modify *device_modify)
1698 {
1699         struct qib_devdata *dd = dd_from_ibdev(device);
1700         unsigned i;
1701         int ret;
1702
1703         if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1704                                    IB_DEVICE_MODIFY_NODE_DESC)) {
1705                 ret = -EOPNOTSUPP;
1706                 goto bail;
1707         }
1708
1709         if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1710                 memcpy(device->node_desc, device_modify->node_desc, 64);
1711                 for (i = 0; i < dd->num_pports; i++) {
1712                         struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1713
1714                         qib_node_desc_chg(ibp);
1715                 }
1716         }
1717
1718         if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1719                 ib_qib_sys_image_guid =
1720                         cpu_to_be64(device_modify->sys_image_guid);
1721                 for (i = 0; i < dd->num_pports; i++) {
1722                         struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1723
1724                         qib_sys_guid_chg(ibp);
1725                 }
1726         }
1727
1728         ret = 0;
1729
1730 bail:
1731         return ret;
1732 }
1733
1734 static int qib_modify_port(struct ib_device *ibdev, u8 port,
1735                            int port_modify_mask, struct ib_port_modify *props)
1736 {
1737         struct qib_ibport *ibp = to_iport(ibdev, port);
1738         struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1739
1740         ibp->port_cap_flags |= props->set_port_cap_mask;
1741         ibp->port_cap_flags &= ~props->clr_port_cap_mask;
1742         if (props->set_port_cap_mask || props->clr_port_cap_mask)
1743                 qib_cap_mask_chg(ibp);
1744         if (port_modify_mask & IB_PORT_SHUTDOWN)
1745                 qib_set_linkstate(ppd, QIB_IB_LINKDOWN);
1746         if (port_modify_mask & IB_PORT_RESET_QKEY_CNTR)
1747                 ibp->qkey_violations = 0;
1748         return 0;
1749 }
1750
1751 static int qib_query_gid(struct ib_device *ibdev, u8 port,
1752                          int index, union ib_gid *gid)
1753 {
1754         struct qib_devdata *dd = dd_from_ibdev(ibdev);
1755         int ret = 0;
1756
1757         if (!port || port > dd->num_pports)
1758                 ret = -EINVAL;
1759         else {
1760                 struct qib_ibport *ibp = to_iport(ibdev, port);
1761                 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1762
1763                 gid->global.subnet_prefix = ibp->gid_prefix;
1764                 if (index == 0)
1765                         gid->global.interface_id = ppd->guid;
1766                 else if (index < QIB_GUIDS_PER_PORT)
1767                         gid->global.interface_id = ibp->guids[index - 1];
1768                 else
1769                         ret = -EINVAL;
1770         }
1771
1772         return ret;
1773 }
1774
1775 int qib_check_ah(struct ib_device *ibdev, struct ib_ah_attr *ah_attr)
1776 {
1777         /* A multicast address requires a GRH (see ch. 8.4.1). */
1778         if (ah_attr->dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE) &&
1779             ah_attr->dlid != be16_to_cpu(IB_LID_PERMISSIVE) &&
1780             !(ah_attr->ah_flags & IB_AH_GRH))
1781                 goto bail;
1782         if ((ah_attr->ah_flags & IB_AH_GRH) &&
1783             ah_attr->grh.sgid_index >= QIB_GUIDS_PER_PORT)
1784                 goto bail;
1785         if (ah_attr->dlid == 0)
1786                 goto bail;
1787         if (ah_attr->port_num < 1 ||
1788             ah_attr->port_num > ibdev->phys_port_cnt)
1789                 goto bail;
1790         if (ah_attr->static_rate != IB_RATE_PORT_CURRENT &&
1791             ib_rate_to_mult(ah_attr->static_rate) < 0)
1792                 goto bail;
1793         if (ah_attr->sl > 15)
1794                 goto bail;
1795         return 0;
1796 bail:
1797         return -EINVAL;
1798 }
1799
1800 /**
1801  * qib_create_ah - create an address handle
1802  * @pd: the protection domain
1803  * @ah_attr: the attributes of the AH
1804  *
1805  * This may be called from interrupt context.
1806  */
1807 static struct ib_ah *qib_create_ah(struct ib_pd *pd,
1808                                    struct ib_ah_attr *ah_attr)
1809 {
1810         struct qib_ah *ah;
1811         struct ib_ah *ret;
1812         struct qib_ibdev *dev = to_idev(pd->device);
1813         unsigned long flags;
1814
1815         if (qib_check_ah(pd->device, ah_attr)) {
1816                 ret = ERR_PTR(-EINVAL);
1817                 goto bail;
1818         }
1819
1820         ah = kmalloc(sizeof(*ah), GFP_ATOMIC);
1821         if (!ah) {
1822                 ret = ERR_PTR(-ENOMEM);
1823                 goto bail;
1824         }
1825
1826         spin_lock_irqsave(&dev->n_ahs_lock, flags);
1827         if (dev->n_ahs_allocated == ib_qib_max_ahs) {
1828                 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1829                 kfree(ah);
1830                 ret = ERR_PTR(-ENOMEM);
1831                 goto bail;
1832         }
1833
1834         dev->n_ahs_allocated++;
1835         spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1836
1837         /* ib_create_ah() will initialize ah->ibah. */
1838         ah->attr = *ah_attr;
1839         atomic_set(&ah->refcount, 0);
1840
1841         ret = &ah->ibah;
1842
1843 bail:
1844         return ret;
1845 }
1846
1847 struct ib_ah *qib_create_qp0_ah(struct qib_ibport *ibp, u16 dlid)
1848 {
1849         struct ib_ah_attr attr;
1850         struct ib_ah *ah = ERR_PTR(-EINVAL);
1851         struct qib_qp *qp0;
1852
1853         memset(&attr, 0, sizeof(attr));
1854         attr.dlid = dlid;
1855         attr.port_num = ppd_from_ibp(ibp)->port;
1856         rcu_read_lock();
1857         qp0 = rcu_dereference(ibp->qp0);
1858         if (qp0)
1859                 ah = ib_create_ah(qp0->ibqp.pd, &attr);
1860         rcu_read_unlock();
1861         return ah;
1862 }
1863
1864 /**
1865  * qib_destroy_ah - destroy an address handle
1866  * @ibah: the AH to destroy
1867  *
1868  * This may be called from interrupt context.
1869  */
1870 static int qib_destroy_ah(struct ib_ah *ibah)
1871 {
1872         struct qib_ibdev *dev = to_idev(ibah->device);
1873         struct qib_ah *ah = to_iah(ibah);
1874         unsigned long flags;
1875
1876         if (atomic_read(&ah->refcount) != 0)
1877                 return -EBUSY;
1878
1879         spin_lock_irqsave(&dev->n_ahs_lock, flags);
1880         dev->n_ahs_allocated--;
1881         spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1882
1883         kfree(ah);
1884
1885         return 0;
1886 }
1887
1888 static int qib_modify_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1889 {
1890         struct qib_ah *ah = to_iah(ibah);
1891
1892         if (qib_check_ah(ibah->device, ah_attr))
1893                 return -EINVAL;
1894
1895         ah->attr = *ah_attr;
1896
1897         return 0;
1898 }
1899
1900 static int qib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1901 {
1902         struct qib_ah *ah = to_iah(ibah);
1903
1904         *ah_attr = ah->attr;
1905
1906         return 0;
1907 }
1908
1909 /**
1910  * qib_get_npkeys - return the size of the PKEY table for context 0
1911  * @dd: the qlogic_ib device
1912  */
1913 unsigned qib_get_npkeys(struct qib_devdata *dd)
1914 {
1915         return ARRAY_SIZE(dd->rcd[0]->pkeys);
1916 }
1917
1918 /*
1919  * Return the indexed PKEY from the port PKEY table.
1920  * No need to validate rcd[ctxt]; the port is setup if we are here.
1921  */
1922 unsigned qib_get_pkey(struct qib_ibport *ibp, unsigned index)
1923 {
1924         struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1925         struct qib_devdata *dd = ppd->dd;
1926         unsigned ctxt = ppd->hw_pidx;
1927         unsigned ret;
1928
1929         /* dd->rcd null if mini_init or some init failures */
1930         if (!dd->rcd || index >= ARRAY_SIZE(dd->rcd[ctxt]->pkeys))
1931                 ret = 0;
1932         else
1933                 ret = dd->rcd[ctxt]->pkeys[index];
1934
1935         return ret;
1936 }
1937
1938 static int qib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1939                           u16 *pkey)
1940 {
1941         struct qib_devdata *dd = dd_from_ibdev(ibdev);
1942         int ret;
1943
1944         if (index >= qib_get_npkeys(dd)) {
1945                 ret = -EINVAL;
1946                 goto bail;
1947         }
1948
1949         *pkey = qib_get_pkey(to_iport(ibdev, port), index);
1950         ret = 0;
1951
1952 bail:
1953         return ret;
1954 }
1955
1956 /**
1957  * qib_alloc_ucontext - allocate a ucontest
1958  * @ibdev: the infiniband device
1959  * @udata: not used by the QLogic_IB driver
1960  */
1961
1962 static struct ib_ucontext *qib_alloc_ucontext(struct ib_device *ibdev,
1963                                               struct ib_udata *udata)
1964 {
1965         struct qib_ucontext *context;
1966         struct ib_ucontext *ret;
1967
1968         context = kmalloc(sizeof(*context), GFP_KERNEL);
1969         if (!context) {
1970                 ret = ERR_PTR(-ENOMEM);
1971                 goto bail;
1972         }
1973
1974         ret = &context->ibucontext;
1975
1976 bail:
1977         return ret;
1978 }
1979
1980 static int qib_dealloc_ucontext(struct ib_ucontext *context)
1981 {
1982         kfree(to_iucontext(context));
1983         return 0;
1984 }
1985
1986 static void init_ibport(struct qib_pportdata *ppd)
1987 {
1988         struct qib_verbs_counters cntrs;
1989         struct qib_ibport *ibp = &ppd->ibport_data;
1990
1991         spin_lock_init(&ibp->lock);
1992         /* Set the prefix to the default value (see ch. 4.1.1) */
1993         ibp->gid_prefix = IB_DEFAULT_GID_PREFIX;
1994         ibp->sm_lid = be16_to_cpu(IB_LID_PERMISSIVE);
1995         ibp->port_cap_flags = IB_PORT_SYS_IMAGE_GUID_SUP |
1996                 IB_PORT_CLIENT_REG_SUP | IB_PORT_SL_MAP_SUP |
1997                 IB_PORT_TRAP_SUP | IB_PORT_AUTO_MIGR_SUP |
1998                 IB_PORT_DR_NOTICE_SUP | IB_PORT_CAP_MASK_NOTICE_SUP |
1999                 IB_PORT_OTHER_LOCAL_CHANGES_SUP;
2000         if (ppd->dd->flags & QIB_HAS_LINK_LATENCY)
2001                 ibp->port_cap_flags |= IB_PORT_LINK_LATENCY_SUP;
2002         ibp->pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
2003         ibp->pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
2004         ibp->pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
2005         ibp->pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
2006         ibp->pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
2007
2008         /* Snapshot current HW counters to "clear" them. */
2009         qib_get_counters(ppd, &cntrs);
2010         ibp->z_symbol_error_counter = cntrs.symbol_error_counter;
2011         ibp->z_link_error_recovery_counter =
2012                 cntrs.link_error_recovery_counter;
2013         ibp->z_link_downed_counter = cntrs.link_downed_counter;
2014         ibp->z_port_rcv_errors = cntrs.port_rcv_errors;
2015         ibp->z_port_rcv_remphys_errors = cntrs.port_rcv_remphys_errors;
2016         ibp->z_port_xmit_discards = cntrs.port_xmit_discards;
2017         ibp->z_port_xmit_data = cntrs.port_xmit_data;
2018         ibp->z_port_rcv_data = cntrs.port_rcv_data;
2019         ibp->z_port_xmit_packets = cntrs.port_xmit_packets;
2020         ibp->z_port_rcv_packets = cntrs.port_rcv_packets;
2021         ibp->z_local_link_integrity_errors =
2022                 cntrs.local_link_integrity_errors;
2023         ibp->z_excessive_buffer_overrun_errors =
2024                 cntrs.excessive_buffer_overrun_errors;
2025         ibp->z_vl15_dropped = cntrs.vl15_dropped;
2026         RCU_INIT_POINTER(ibp->qp0, NULL);
2027         RCU_INIT_POINTER(ibp->qp1, NULL);
2028 }
2029
2030 static int qib_port_immutable(struct ib_device *ibdev, u8 port_num,
2031                               struct ib_port_immutable *immutable)
2032 {
2033         struct ib_port_attr attr;
2034         int err;
2035
2036         err = qib_query_port(ibdev, port_num, &attr);
2037         if (err)
2038                 return err;
2039
2040         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2041         immutable->gid_tbl_len = attr.gid_tbl_len;
2042         immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
2043         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2044
2045         return 0;
2046 }
2047
2048 /**
2049  * qib_register_ib_device - register our device with the infiniband core
2050  * @dd: the device data structure
2051  * Return the allocated qib_ibdev pointer or NULL on error.
2052  */
2053 int qib_register_ib_device(struct qib_devdata *dd)
2054 {
2055         struct qib_ibdev *dev = &dd->verbs_dev;
2056         struct ib_device *ibdev = &dev->rdi.ibdev;
2057         struct qib_pportdata *ppd = dd->pport;
2058         unsigned i, lk_tab_size;
2059         int ret;
2060
2061         dev->qp_table_size = ib_qib_qp_table_size;
2062         get_random_bytes(&dev->qp_rnd, sizeof(dev->qp_rnd));
2063         dev->qp_table = kmalloc_array(
2064                                 dev->qp_table_size,
2065                                 sizeof(*dev->qp_table),
2066                                 GFP_KERNEL);
2067         if (!dev->qp_table) {
2068                 ret = -ENOMEM;
2069                 goto err_qpt;
2070         }
2071         for (i = 0; i < dev->qp_table_size; i++)
2072                 RCU_INIT_POINTER(dev->qp_table[i], NULL);
2073
2074         for (i = 0; i < dd->num_pports; i++)
2075                 init_ibport(ppd + i);
2076
2077         /* Only need to initialize non-zero fields. */
2078         spin_lock_init(&dev->qpt_lock);
2079         spin_lock_init(&dev->n_ahs_lock);
2080         spin_lock_init(&dev->n_cqs_lock);
2081         spin_lock_init(&dev->n_qps_lock);
2082         spin_lock_init(&dev->n_srqs_lock);
2083         spin_lock_init(&dev->n_mcast_grps_lock);
2084         init_timer(&dev->mem_timer);
2085         dev->mem_timer.function = mem_timer;
2086         dev->mem_timer.data = (unsigned long) dev;
2087
2088         qib_init_qpn_table(dd, &dev->qpn_table);
2089
2090         /*
2091          * The top ib_qib_lkey_table_size bits are used to index the
2092          * table.  The lower 8 bits can be owned by the user (copied from
2093          * the LKEY).  The remaining bits act as a generation number or tag.
2094          */
2095         spin_lock_init(&dev->lk_table.lock);
2096         /* insure generation is at least 4 bits see keys.c */
2097         if (ib_qib_lkey_table_size > MAX_LKEY_TABLE_BITS) {
2098                 qib_dev_warn(dd, "lkey bits %u too large, reduced to %u\n",
2099                         ib_qib_lkey_table_size, MAX_LKEY_TABLE_BITS);
2100                 ib_qib_lkey_table_size = MAX_LKEY_TABLE_BITS;
2101         }
2102         dev->lk_table.max = 1 << ib_qib_lkey_table_size;
2103         lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
2104         dev->lk_table.table = (struct qib_mregion __rcu **)
2105                 vmalloc(lk_tab_size);
2106         if (dev->lk_table.table == NULL) {
2107                 ret = -ENOMEM;
2108                 goto err_lk;
2109         }
2110         RCU_INIT_POINTER(dev->dma_mr, NULL);
2111         for (i = 0; i < dev->lk_table.max; i++)
2112                 RCU_INIT_POINTER(dev->lk_table.table[i], NULL);
2113         INIT_LIST_HEAD(&dev->pending_mmaps);
2114         spin_lock_init(&dev->pending_lock);
2115         dev->mmap_offset = PAGE_SIZE;
2116         spin_lock_init(&dev->mmap_offset_lock);
2117         INIT_LIST_HEAD(&dev->piowait);
2118         INIT_LIST_HEAD(&dev->dmawait);
2119         INIT_LIST_HEAD(&dev->txwait);
2120         INIT_LIST_HEAD(&dev->memwait);
2121         INIT_LIST_HEAD(&dev->txreq_free);
2122
2123         if (ppd->sdma_descq_cnt) {
2124                 dev->pio_hdrs = dma_alloc_coherent(&dd->pcidev->dev,
2125                                                 ppd->sdma_descq_cnt *
2126                                                 sizeof(struct qib_pio_header),
2127                                                 &dev->pio_hdrs_phys,
2128                                                 GFP_KERNEL);
2129                 if (!dev->pio_hdrs) {
2130                         ret = -ENOMEM;
2131                         goto err_hdrs;
2132                 }
2133         }
2134
2135         for (i = 0; i < ppd->sdma_descq_cnt; i++) {
2136                 struct qib_verbs_txreq *tx;
2137
2138                 tx = kzalloc(sizeof(*tx), GFP_KERNEL);
2139                 if (!tx) {
2140                         ret = -ENOMEM;
2141                         goto err_tx;
2142                 }
2143                 tx->hdr_inx = i;
2144                 list_add(&tx->txreq.list, &dev->txreq_free);
2145         }
2146
2147         /*
2148          * The system image GUID is supposed to be the same for all
2149          * IB HCAs in a single system but since there can be other
2150          * device types in the system, we can't be sure this is unique.
2151          */
2152         if (!ib_qib_sys_image_guid)
2153                 ib_qib_sys_image_guid = ppd->guid;
2154
2155         strlcpy(ibdev->name, "qib%d", IB_DEVICE_NAME_MAX);
2156         ibdev->owner = THIS_MODULE;
2157         ibdev->node_guid = ppd->guid;
2158         ibdev->uverbs_abi_ver = QIB_UVERBS_ABI_VERSION;
2159         ibdev->uverbs_cmd_mask =
2160                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
2161                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
2162                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
2163                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
2164                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
2165                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
2166                 (1ull << IB_USER_VERBS_CMD_MODIFY_AH)           |
2167                 (1ull << IB_USER_VERBS_CMD_QUERY_AH)            |
2168                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
2169                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
2170                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
2171                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2172                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
2173                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
2174                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
2175                 (1ull << IB_USER_VERBS_CMD_POLL_CQ)             |
2176                 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ)       |
2177                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
2178                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
2179                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
2180                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
2181                 (1ull << IB_USER_VERBS_CMD_POST_SEND)           |
2182                 (1ull << IB_USER_VERBS_CMD_POST_RECV)           |
2183                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
2184                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
2185                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
2186                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
2187                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
2188                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
2189                 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
2190         ibdev->node_type = RDMA_NODE_IB_CA;
2191         ibdev->phys_port_cnt = dd->num_pports;
2192         ibdev->num_comp_vectors = 1;
2193         ibdev->dma_device = &dd->pcidev->dev;
2194         ibdev->query_device = qib_query_device;
2195         ibdev->modify_device = qib_modify_device;
2196         ibdev->query_port = qib_query_port;
2197         ibdev->modify_port = qib_modify_port;
2198         ibdev->query_pkey = qib_query_pkey;
2199         ibdev->query_gid = qib_query_gid;
2200         ibdev->alloc_ucontext = qib_alloc_ucontext;
2201         ibdev->dealloc_ucontext = qib_dealloc_ucontext;
2202         ibdev->alloc_pd = NULL;
2203         ibdev->dealloc_pd = NULL;
2204         ibdev->create_ah = qib_create_ah;
2205         ibdev->destroy_ah = qib_destroy_ah;
2206         ibdev->modify_ah = qib_modify_ah;
2207         ibdev->query_ah = qib_query_ah;
2208         ibdev->create_srq = qib_create_srq;
2209         ibdev->modify_srq = qib_modify_srq;
2210         ibdev->query_srq = qib_query_srq;
2211         ibdev->destroy_srq = qib_destroy_srq;
2212         ibdev->create_qp = qib_create_qp;
2213         ibdev->modify_qp = qib_modify_qp;
2214         ibdev->query_qp = qib_query_qp;
2215         ibdev->destroy_qp = qib_destroy_qp;
2216         ibdev->post_send = qib_post_send;
2217         ibdev->post_recv = qib_post_receive;
2218         ibdev->post_srq_recv = qib_post_srq_receive;
2219         ibdev->create_cq = qib_create_cq;
2220         ibdev->destroy_cq = qib_destroy_cq;
2221         ibdev->resize_cq = qib_resize_cq;
2222         ibdev->poll_cq = qib_poll_cq;
2223         ibdev->req_notify_cq = qib_req_notify_cq;
2224         ibdev->get_dma_mr = qib_get_dma_mr;
2225         ibdev->reg_user_mr = qib_reg_user_mr;
2226         ibdev->dereg_mr = qib_dereg_mr;
2227         ibdev->alloc_mr = qib_alloc_mr;
2228         ibdev->map_mr_sg = qib_map_mr_sg;
2229         ibdev->alloc_fmr = qib_alloc_fmr;
2230         ibdev->map_phys_fmr = qib_map_phys_fmr;
2231         ibdev->unmap_fmr = qib_unmap_fmr;
2232         ibdev->dealloc_fmr = qib_dealloc_fmr;
2233         ibdev->attach_mcast = qib_multicast_attach;
2234         ibdev->detach_mcast = qib_multicast_detach;
2235         ibdev->process_mad = qib_process_mad;
2236         ibdev->mmap = qib_mmap;
2237         ibdev->dma_ops = NULL;
2238         ibdev->get_port_immutable = qib_port_immutable;
2239
2240         snprintf(ibdev->node_desc, sizeof(ibdev->node_desc),
2241                  "Intel Infiniband HCA %s", init_utsname()->nodename);
2242
2243         /*
2244          * Fill in rvt info object.
2245          */
2246         dd->verbs_dev.rdi.driver_f.port_callback = qib_create_port_files;
2247         dd->verbs_dev.rdi.driver_f.get_card_name = qib_get_card_name;
2248         dd->verbs_dev.rdi.driver_f.get_pci_dev = qib_get_pci_dev;
2249         dd->verbs_dev.rdi.dparms.props.max_pd = ib_qib_max_pds;
2250         dd->verbs_dev.rdi.flags = (RVT_FLAG_MR_INIT_DRIVER |
2251                                    RVT_FLAG_QP_INIT_DRIVER |
2252                                    RVT_FLAG_CQ_INIT_DRIVER);
2253
2254
2255         ret = rvt_register_device(&dd->verbs_dev.rdi);
2256         if (ret)
2257                 goto err_reg;
2258
2259         ret = qib_create_agents(dev);
2260         if (ret)
2261                 goto err_agents;
2262
2263         ret = qib_verbs_register_sysfs(dd);
2264         if (ret)
2265                 goto err_class;
2266
2267         goto bail;
2268
2269 err_class:
2270         qib_free_agents(dev);
2271 err_agents:
2272         rvt_unregister_device(&dd->verbs_dev.rdi);
2273 err_reg:
2274 err_tx:
2275         while (!list_empty(&dev->txreq_free)) {
2276                 struct list_head *l = dev->txreq_free.next;
2277                 struct qib_verbs_txreq *tx;
2278
2279                 list_del(l);
2280                 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
2281                 kfree(tx);
2282         }
2283         if (ppd->sdma_descq_cnt)
2284                 dma_free_coherent(&dd->pcidev->dev,
2285                                   ppd->sdma_descq_cnt *
2286                                         sizeof(struct qib_pio_header),
2287                                   dev->pio_hdrs, dev->pio_hdrs_phys);
2288 err_hdrs:
2289         vfree(dev->lk_table.table);
2290 err_lk:
2291         kfree(dev->qp_table);
2292 err_qpt:
2293         qib_dev_err(dd, "cannot register verbs: %d!\n", -ret);
2294 bail:
2295         return ret;
2296 }
2297
2298 void qib_unregister_ib_device(struct qib_devdata *dd)
2299 {
2300         struct qib_ibdev *dev = &dd->verbs_dev;
2301         u32 qps_inuse;
2302         unsigned lk_tab_size;
2303
2304         qib_verbs_unregister_sysfs(dd);
2305
2306         qib_free_agents(dev);
2307
2308         rvt_unregister_device(&dd->verbs_dev.rdi);
2309
2310         if (!list_empty(&dev->piowait))
2311                 qib_dev_err(dd, "piowait list not empty!\n");
2312         if (!list_empty(&dev->dmawait))
2313                 qib_dev_err(dd, "dmawait list not empty!\n");
2314         if (!list_empty(&dev->txwait))
2315                 qib_dev_err(dd, "txwait list not empty!\n");
2316         if (!list_empty(&dev->memwait))
2317                 qib_dev_err(dd, "memwait list not empty!\n");
2318         if (dev->dma_mr)
2319                 qib_dev_err(dd, "DMA MR not NULL!\n");
2320
2321         qps_inuse = qib_free_all_qps(dd);
2322         if (qps_inuse)
2323                 qib_dev_err(dd, "QP memory leak! %u still in use\n",
2324                             qps_inuse);
2325
2326         del_timer_sync(&dev->mem_timer);
2327         qib_free_qpn_table(&dev->qpn_table);
2328         while (!list_empty(&dev->txreq_free)) {
2329                 struct list_head *l = dev->txreq_free.next;
2330                 struct qib_verbs_txreq *tx;
2331
2332                 list_del(l);
2333                 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
2334                 kfree(tx);
2335         }
2336         if (dd->pport->sdma_descq_cnt)
2337                 dma_free_coherent(&dd->pcidev->dev,
2338                                   dd->pport->sdma_descq_cnt *
2339                                         sizeof(struct qib_pio_header),
2340                                   dev->pio_hdrs, dev->pio_hdrs_phys);
2341         lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
2342         vfree(dev->lk_table.table);
2343         kfree(dev->qp_table);
2344 }
2345
2346 /*
2347  * This must be called with s_lock held.
2348  */
2349 void qib_schedule_send(struct qib_qp *qp)
2350 {
2351         struct qib_qp_priv *priv = qp->priv;
2352         if (qib_send_ok(qp)) {
2353                 struct qib_ibport *ibp =
2354                         to_iport(qp->ibqp.device, qp->port_num);
2355                 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
2356
2357                 queue_work(ppd->qib_wq, &priv->s_work);
2358         }
2359 }