2 * Copyright (c) 2012 Intel Corporation. All rights reserved.
3 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
36 #include <linux/pci.h>
37 #include <linux/vmalloc.h>
42 * QLogic_IB "Two Wire Serial Interface" driver.
43 * Originally written for a not-quite-i2c serial eeprom, which is
44 * still used on some supported boards. Later boards have added a
45 * variety of other uses, most board-specific, so the bit-boffing
46 * part has been split off to this file, while the other parts
47 * have been moved to chip-specific files.
49 * We have also dropped all pretense of fully generic (e.g. pretend
50 * we don't know whether '1' is the higher voltage) interface, as
51 * the restrictions of the generic i2c interface (e.g. no access from
52 * driver itself) make it unsuitable for this use.
59 * i2c_wait_for_writes - wait for a write
60 * @dd: the qlogic_ib device
62 * We use this instead of udelay directly, so we can make sure
63 * that previous register writes have been flushed all the way
64 * to the chip. Since we are delaying anyway, the cost doesn't
65 * hurt, and makes the bit twiddling more regular
67 static void i2c_wait_for_writes(struct qib_devdata *dd)
70 * implicit read of EXTStatus is as good as explicit
71 * read of scratch, if all we want to do is flush
74 dd->f_gpio_mod(dd, 0, 0, 0);
75 rmb(); /* inlined, so prevent compiler reordering */
79 * QSFP modules are allowed to hold SCL low for 500uSec. Allow twice that
80 * for "almost compliant" modules
82 #define SCL_WAIT_USEC 1000
84 /* BUF_WAIT is time bus must be free between STOP or ACK and to next START.
85 * Should be 20, but some chips need more.
87 #define TWSI_BUF_WAIT_USEC 60
89 static void scl_out(struct qib_devdata *dd, u8 bit)
95 mask = 1UL << dd->gpio_scl_num;
97 /* SCL is meant to be bare-drain, so never set "OUT", just DIR */
98 dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);
101 * Allow for slow slaves by simple
102 * delay for falling edge, sampling on rise.
108 for (rise_usec = SCL_WAIT_USEC; rise_usec > 0; rise_usec -= 2) {
109 if (mask & dd->f_gpio_mod(dd, 0, 0, 0))
114 qib_dev_err(dd, "SCL interface stuck low > %d uSec\n",
117 i2c_wait_for_writes(dd);
120 static void sda_out(struct qib_devdata *dd, u8 bit)
124 mask = 1UL << dd->gpio_sda_num;
126 /* SDA is meant to be bare-drain, so never set "OUT", just DIR */
127 dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);
129 i2c_wait_for_writes(dd);
133 static u8 sda_in(struct qib_devdata *dd, int wait)
138 bnum = dd->gpio_sda_num;
139 mask = (1UL << bnum);
140 /* SDA is meant to be bare-drain, so never set "OUT", just DIR */
141 dd->f_gpio_mod(dd, 0, 0, mask);
142 read_val = dd->f_gpio_mod(dd, 0, 0, 0);
144 i2c_wait_for_writes(dd);
145 return (read_val & mask) >> bnum;
149 * i2c_ackrcv - see if ack following write is true
150 * @dd: the qlogic_ib device
152 static int i2c_ackrcv(struct qib_devdata *dd)
156 /* AT ENTRY SCL = LOW */
157 /* change direction, ignore data */
158 ack_received = sda_in(dd, 1);
160 ack_received = sda_in(dd, 1) == 0;
165 static void stop_cmd(struct qib_devdata *dd);
168 * rd_byte - read a byte, sending STOP on last, else ACK
169 * @dd: the qlogic_ib device
171 * Returns byte shifted out of device
173 static int rd_byte(struct qib_devdata *dd, int last)
179 for (bit_cntr = 7; bit_cntr >= 0; --bit_cntr) {
182 data |= sda_in(dd, 0);
198 * wr_byte - write a byte, one bit at a time
199 * @dd: the qlogic_ib device
200 * @data: the byte to write
202 * Returns 0 if we got the following ack, otherwise 1
204 static int wr_byte(struct qib_devdata *dd, u8 data)
209 for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) {
210 bit = (data >> bit_cntr) & 1;
215 return (!i2c_ackrcv(dd)) ? 1 : 0;
219 * issue TWSI start sequence:
220 * (both clock/data high, clock high, data low while clock is high)
222 static void start_seq(struct qib_devdata *dd)
232 * stop_seq - transmit the stop sequence
233 * @dd: the qlogic_ib device
235 * (both clock/data low, clock high, data high while clock is high)
237 static void stop_seq(struct qib_devdata *dd)
246 * stop_cmd - transmit the stop condition
247 * @dd: the qlogic_ib device
249 * (both clock/data low, clock high, data high while clock is high)
251 static void stop_cmd(struct qib_devdata *dd)
254 udelay(TWSI_BUF_WAIT_USEC);
258 * qib_twsi_reset - reset I2C communication
259 * @dd: the qlogic_ib device
262 int qib_twsi_reset(struct qib_devdata *dd)
264 int clock_cycles_left = 9;
268 /* Both SCL and SDA should be high. If not, there
269 * is something wrong.
271 mask = (1UL << dd->gpio_scl_num) | (1UL << dd->gpio_sda_num);
274 * Force pins to desired innocuous state.
275 * This is the default power-on state with out=0 and dir=0,
276 * So tri-stated and should be floating high (barring HW problems)
278 dd->f_gpio_mod(dd, 0, 0, mask);
281 * Clock nine times to get all listeners into a sane state.
282 * If SDA does not go high at any point, we are wedged.
283 * One vendor recommends then issuing START followed by STOP.
284 * we cannot use our "normal" functions to do that, because
285 * if SCL drops between them, another vendor's part will
286 * wedge, dropping SDA and keeping it low forever, at the end of
287 * the next transaction (even if it was not the device addressed).
288 * So our START and STOP take place with SCL held high.
290 while (clock_cycles_left--) {
293 /* Note if SDA is high, but keep clocking to sync slave */
294 was_high |= sda_in(dd, 0);
299 * We saw a high, which we hope means the slave is sync'd.
300 * Issue START, STOP, pause for T_BUF.
303 pins = dd->f_gpio_mod(dd, 0, 0, 0);
304 if ((pins & mask) != mask)
305 qib_dev_err(dd, "GPIO pins not at rest: %d\n",
307 /* Drop SDA to issue START */
308 udelay(1); /* Guarantee .6 uSec setup */
310 udelay(1); /* Guarantee .6 uSec hold */
311 /* At this point, SCL is high, SDA low. Raise SDA for STOP */
313 udelay(TWSI_BUF_WAIT_USEC);
319 #define QIB_TWSI_START 0x100
320 #define QIB_TWSI_STOP 0x200
322 /* Write byte to TWSI, optionally prefixed with START or suffixed with
324 * returns 0 if OK (ACK received), else != 0
326 static int qib_twsi_wr(struct qib_devdata *dd, int data, int flags)
329 if (flags & QIB_TWSI_START)
332 ret = wr_byte(dd, data); /* Leaves SCL low (from i2c_ackrcv()) */
334 if (flags & QIB_TWSI_STOP)
339 /* Added functionality for IBA7220-based cards */
340 #define QIB_TEMP_DEV 0x98
344 * Formerly called qib_eeprom_internal_read, and only used for eeprom,
345 * but now the general interface for data transfer from twsi devices.
346 * One vestige of its former role is that it recognizes a device
347 * QIB_TWSI_NO_DEV and does the correct operation for the legacy part,
348 * which responded to all TWSI device codes, interpreting them as
349 * address within device. On all other devices found on board handled by
350 * this driver, the device is followed by a one-byte "address" which selects
351 * the "register" or "offset" within the device from which data should
354 int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr,
355 void *buffer, int len)
362 if (dev == QIB_TWSI_NO_DEV) {
363 /* legacy not-really-I2C */
364 addr = (addr << 1) | READ_CMD;
365 ret = qib_twsi_wr(dd, addr, QIB_TWSI_START);
368 ret = qib_twsi_wr(dd, dev | WRITE_CMD, QIB_TWSI_START);
375 * SFF spec claims we do _not_ stop after the addr
376 * but simply issue a start with the "read" dev-addr.
377 * Since we are implicitely waiting for ACK here,
378 * we need t_buf (nominally 20uSec) before that start,
379 * and cannot rely on the delay built in to the STOP
381 ret = qib_twsi_wr(dd, addr, 0);
382 udelay(TWSI_BUF_WAIT_USEC);
386 "Failed to write interface read addr %02X\n",
391 ret = qib_twsi_wr(dd, dev | READ_CMD, QIB_TWSI_START);
400 * block devices keeps clocking data out as long as we ack,
401 * automatically incrementing the address. Some have "pages"
402 * whose boundaries will not be crossed, but the handling
403 * of these is left to the caller, who is in a better
408 * Get and store data, sending ACK if length remaining,
411 *bp++ = rd_byte(dd, !len);
422 * Formerly called qib_eeprom_internal_write, and only used for eeprom,
423 * but now the general interface for data transfer to twsi devices.
424 * One vestige of its former role is that it recognizes a device
425 * QIB_TWSI_NO_DEV and does the correct operation for the legacy part,
426 * which responded to all TWSI device codes, interpreting them as
427 * address within device. On all other devices found on board handled by
428 * this driver, the device is followed by a one-byte "address" which selects
429 * the "register" or "offset" within the device to which data should
432 int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,
433 const void *buffer, int len)
436 const u8 *bp = buffer;
437 int max_wait_time, i;
442 if (dev == QIB_TWSI_NO_DEV) {
443 if (qib_twsi_wr(dd, (addr << 1) | WRITE_CMD,
449 if (qib_twsi_wr(dd, dev | WRITE_CMD, QIB_TWSI_START))
451 ret = qib_twsi_wr(dd, addr, 0);
454 "Failed to write interface write addr %02X\n",
460 sub_len = min(len, 4);
464 for (i = 0; i < sub_len; i++)
465 if (qib_twsi_wr(dd, *bp++, 0))
471 * Wait for write complete by waiting for a successful
472 * read (the chip replies with a zero after the write
473 * cmd completes, and before it writes to the eeprom.
474 * The startcmd for the read will fail the ack until
475 * the writes have completed. We do this inline to avoid
476 * the debug prints that are in the real read routine
477 * if the startcmd fails.
478 * We also use the proper device address, so it doesn't matter
479 * whether we have real eeprom_dev. Legacy likes any address.
482 while (qib_twsi_wr(dd, dev | READ_CMD, QIB_TWSI_START)) {
484 if (!--max_wait_time)
487 /* now read (and ignore) the resulting byte */