2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/mlx5/fs.h>
40 /* not supported currently */
41 static int wq_signature;
44 MLX5_IB_ACK_REQ_FREQ = 8,
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
55 MLX5_IB_SQ_STRIDE = 6,
58 static const u32 mlx5_ib_opcode[] = {
59 [IB_WR_SEND] = MLX5_OPCODE_SEND,
60 [IB_WR_LSO] = MLX5_OPCODE_LSO,
61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
75 struct mlx5_wqe_eth_pad {
79 enum raw_qp_set_mask_map {
80 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
81 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
84 struct mlx5_modify_raw_qp_param {
87 u32 set_mask; /* raw_qp_set_mask_map */
92 static void get_cqs(enum ib_qp_type qp_type,
93 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
94 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
96 static int is_qp0(enum ib_qp_type qp_type)
98 return qp_type == IB_QPT_SMI;
101 static int is_sqp(enum ib_qp_type qp_type)
103 return is_qp0(qp_type) || is_qp1(qp_type);
106 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
108 return mlx5_buf_offset(&qp->buf, offset);
111 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
113 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
116 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
118 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
122 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
124 * @qp: QP to copy from.
125 * @send: copy from the send queue when non-zero, use the receive queue
127 * @wqe_index: index to start copying from. For send work queues, the
128 * wqe_index is in units of MLX5_SEND_WQE_BB.
129 * For receive work queue, it is the number of work queue
130 * element in the queue.
131 * @buffer: destination buffer.
132 * @length: maximum number of bytes to copy.
134 * Copies at least a single WQE, but may copy more data.
136 * Return: the number of bytes copied, or an error code.
138 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
139 void *buffer, u32 length,
140 struct mlx5_ib_qp_base *base)
142 struct ib_device *ibdev = qp->ibqp.device;
143 struct mlx5_ib_dev *dev = to_mdev(ibdev);
144 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
147 struct ib_umem *umem = base->ubuffer.umem;
148 u32 first_copy_length;
152 if (wq->wqe_cnt == 0) {
153 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
158 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
159 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
161 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
164 if (offset > umem->length ||
165 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
168 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
169 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
174 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
175 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
177 wqe_length = ds * MLX5_WQE_DS_UNITS;
179 wqe_length = 1 << wq->wqe_shift;
182 if (wqe_length <= first_copy_length)
183 return first_copy_length;
185 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
186 wqe_length - first_copy_length);
193 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
195 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
196 struct ib_event event;
198 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
199 /* This event is only valid for trans_qps */
200 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
203 if (ibqp->event_handler) {
204 event.device = ibqp->device;
205 event.element.qp = ibqp;
207 case MLX5_EVENT_TYPE_PATH_MIG:
208 event.event = IB_EVENT_PATH_MIG;
210 case MLX5_EVENT_TYPE_COMM_EST:
211 event.event = IB_EVENT_COMM_EST;
213 case MLX5_EVENT_TYPE_SQ_DRAINED:
214 event.event = IB_EVENT_SQ_DRAINED;
216 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
217 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
219 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
220 event.event = IB_EVENT_QP_FATAL;
222 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
223 event.event = IB_EVENT_PATH_MIG_ERR;
225 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
226 event.event = IB_EVENT_QP_REQ_ERR;
228 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
229 event.event = IB_EVENT_QP_ACCESS_ERR;
232 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
236 ibqp->event_handler(&event, ibqp->qp_context);
240 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
241 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
246 /* Sanity check RQ size before proceeding */
247 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
253 qp->rq.wqe_shift = 0;
254 cap->max_recv_wr = 0;
255 cap->max_recv_sge = 0;
258 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
259 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
260 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
261 qp->rq.max_post = qp->rq.wqe_cnt;
263 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
264 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
265 wqe_size = roundup_pow_of_two(wqe_size);
266 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
267 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
268 qp->rq.wqe_cnt = wq_size / wqe_size;
269 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
270 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
272 MLX5_CAP_GEN(dev->mdev,
276 qp->rq.wqe_shift = ilog2(wqe_size);
277 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
278 qp->rq.max_post = qp->rq.wqe_cnt;
285 static int sq_overhead(struct ib_qp_init_attr *attr)
289 switch (attr->qp_type) {
291 size += sizeof(struct mlx5_wqe_xrc_seg);
294 size += sizeof(struct mlx5_wqe_ctrl_seg) +
295 max(sizeof(struct mlx5_wqe_atomic_seg) +
296 sizeof(struct mlx5_wqe_raddr_seg),
297 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
298 sizeof(struct mlx5_mkey_seg));
305 size += sizeof(struct mlx5_wqe_ctrl_seg) +
306 max(sizeof(struct mlx5_wqe_raddr_seg),
307 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
308 sizeof(struct mlx5_mkey_seg));
312 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
313 size += sizeof(struct mlx5_wqe_eth_pad) +
314 sizeof(struct mlx5_wqe_eth_seg);
317 case MLX5_IB_QPT_HW_GSI:
318 size += sizeof(struct mlx5_wqe_ctrl_seg) +
319 sizeof(struct mlx5_wqe_datagram_seg);
322 case MLX5_IB_QPT_REG_UMR:
323 size += sizeof(struct mlx5_wqe_ctrl_seg) +
324 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
325 sizeof(struct mlx5_mkey_seg);
335 static int calc_send_wqe(struct ib_qp_init_attr *attr)
340 size = sq_overhead(attr);
344 if (attr->cap.max_inline_data) {
345 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
346 attr->cap.max_inline_data;
349 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
350 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
351 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
352 return MLX5_SIG_WQE_SIZE;
354 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
357 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
361 if (attr->qp_type == IB_QPT_RC)
362 max_sge = (min_t(int, wqe_size, 512) -
363 sizeof(struct mlx5_wqe_ctrl_seg) -
364 sizeof(struct mlx5_wqe_raddr_seg)) /
365 sizeof(struct mlx5_wqe_data_seg);
366 else if (attr->qp_type == IB_QPT_XRC_INI)
367 max_sge = (min_t(int, wqe_size, 512) -
368 sizeof(struct mlx5_wqe_ctrl_seg) -
369 sizeof(struct mlx5_wqe_xrc_seg) -
370 sizeof(struct mlx5_wqe_raddr_seg)) /
371 sizeof(struct mlx5_wqe_data_seg);
373 max_sge = (wqe_size - sq_overhead(attr)) /
374 sizeof(struct mlx5_wqe_data_seg);
376 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
377 sizeof(struct mlx5_wqe_data_seg));
380 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
381 struct mlx5_ib_qp *qp)
386 if (!attr->cap.max_send_wr)
389 wqe_size = calc_send_wqe(attr);
390 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
394 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
395 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
396 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
400 qp->max_inline_data = wqe_size - sq_overhead(attr) -
401 sizeof(struct mlx5_wqe_inline_seg);
402 attr->cap.max_inline_data = qp->max_inline_data;
404 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
405 qp->signature_en = true;
407 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
408 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
409 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
410 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
411 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
416 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
417 qp->sq.max_gs = get_send_sge(attr, wqe_size);
418 if (qp->sq.max_gs < attr->cap.max_send_sge)
421 attr->cap.max_send_sge = qp->sq.max_gs;
422 qp->sq.max_post = wq_size / wqe_size;
423 attr->cap.max_send_wr = qp->sq.max_post;
428 static int set_user_buf_size(struct mlx5_ib_dev *dev,
429 struct mlx5_ib_qp *qp,
430 struct mlx5_ib_create_qp *ucmd,
431 struct mlx5_ib_qp_base *base,
432 struct ib_qp_init_attr *attr)
434 int desc_sz = 1 << qp->sq.wqe_shift;
436 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
437 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
438 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
442 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
443 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
444 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
448 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
450 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
451 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
453 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
457 if (attr->qp_type == IB_QPT_RAW_PACKET ||
458 qp->flags & MLX5_IB_QP_UNDERLAY) {
459 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
460 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
462 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
463 (qp->sq.wqe_cnt << 6);
469 static int qp_has_rq(struct ib_qp_init_attr *attr)
471 if (attr->qp_type == IB_QPT_XRC_INI ||
472 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
473 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
474 !attr->cap.max_recv_wr)
480 static int first_med_bfreg(void)
486 /* this is the first blue flame register in the array of bfregs assigned
487 * to a processes. Since we do not use it for blue flame but rather
488 * regular 64 bit doorbells, we do not need a lock for maintaiing
491 NUM_NON_BLUE_FLAME_BFREGS = 1,
494 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
496 return get_num_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
499 static int num_med_bfreg(struct mlx5_ib_dev *dev,
500 struct mlx5_bfreg_info *bfregi)
504 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
505 NUM_NON_BLUE_FLAME_BFREGS;
507 return n >= 0 ? n : 0;
510 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
511 struct mlx5_bfreg_info *bfregi)
515 med = num_med_bfreg(dev, bfregi);
519 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
520 struct mlx5_bfreg_info *bfregi)
524 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
525 if (!bfregi->count[i]) {
534 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
535 struct mlx5_bfreg_info *bfregi)
537 int minidx = first_med_bfreg();
540 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
541 if (bfregi->count[i] < bfregi->count[minidx])
543 if (!bfregi->count[minidx])
547 bfregi->count[minidx]++;
551 static int alloc_bfreg(struct mlx5_ib_dev *dev,
552 struct mlx5_bfreg_info *bfregi,
553 enum mlx5_ib_latency_class lat)
555 int bfregn = -EINVAL;
557 mutex_lock(&bfregi->lock);
559 case MLX5_IB_LATENCY_CLASS_LOW:
560 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
562 bfregi->count[bfregn]++;
565 case MLX5_IB_LATENCY_CLASS_MEDIUM:
569 bfregn = alloc_med_class_bfreg(dev, bfregi);
572 case MLX5_IB_LATENCY_CLASS_HIGH:
576 bfregn = alloc_high_class_bfreg(dev, bfregi);
579 mutex_unlock(&bfregi->lock);
584 static void free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
586 mutex_lock(&bfregi->lock);
587 bfregi->count[bfregn]--;
588 mutex_unlock(&bfregi->lock);
591 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
594 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
595 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
596 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
597 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
598 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
599 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
600 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
605 static int to_mlx5_st(enum ib_qp_type type)
608 case IB_QPT_RC: return MLX5_QP_ST_RC;
609 case IB_QPT_UC: return MLX5_QP_ST_UC;
610 case IB_QPT_UD: return MLX5_QP_ST_UD;
611 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
613 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
614 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
615 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
616 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
617 case IB_QPT_RAW_PACKET:
618 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
620 default: return -EINVAL;
624 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
625 struct mlx5_ib_cq *recv_cq);
626 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
627 struct mlx5_ib_cq *recv_cq);
629 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
630 struct mlx5_bfreg_info *bfregi, int bfregn)
632 int bfregs_per_sys_page;
633 int index_of_sys_page;
636 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
637 MLX5_NON_FP_BFREGS_PER_UAR;
638 index_of_sys_page = bfregn / bfregs_per_sys_page;
640 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
642 return bfregi->sys_pages[index_of_sys_page] + offset;
645 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
647 unsigned long addr, size_t size,
648 struct ib_umem **umem,
649 int *npages, int *page_shift, int *ncont,
654 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
656 mlx5_ib_dbg(dev, "umem_get failed\n");
657 return PTR_ERR(*umem);
660 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
662 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
664 mlx5_ib_warn(dev, "bad offset\n");
668 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
669 addr, size, *npages, *page_shift, *ncont, *offset);
674 ib_umem_release(*umem);
680 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
681 struct mlx5_ib_rwq *rwq)
683 struct mlx5_ib_ucontext *context;
685 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
686 atomic_dec(&dev->delay_drop.rqs_cnt);
688 context = to_mucontext(pd->uobject->context);
689 mlx5_ib_db_unmap_user(context, &rwq->db);
691 ib_umem_release(rwq->umem);
694 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
695 struct mlx5_ib_rwq *rwq,
696 struct mlx5_ib_create_wq *ucmd)
698 struct mlx5_ib_ucontext *context;
708 context = to_mucontext(pd->uobject->context);
709 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
710 rwq->buf_size, 0, 0);
711 if (IS_ERR(rwq->umem)) {
712 mlx5_ib_dbg(dev, "umem_get failed\n");
713 err = PTR_ERR(rwq->umem);
717 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
719 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
720 &rwq->rq_page_offset);
722 mlx5_ib_warn(dev, "bad offset\n");
726 rwq->rq_num_pas = ncont;
727 rwq->page_shift = page_shift;
728 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
729 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
731 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
732 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
733 npages, page_shift, ncont, offset);
735 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
737 mlx5_ib_dbg(dev, "map failed\n");
741 rwq->create_type = MLX5_WQ_USER;
745 ib_umem_release(rwq->umem);
749 static int adjust_bfregn(struct mlx5_ib_dev *dev,
750 struct mlx5_bfreg_info *bfregi, int bfregn)
752 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
753 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
756 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
757 struct mlx5_ib_qp *qp, struct ib_udata *udata,
758 struct ib_qp_init_attr *attr,
760 struct mlx5_ib_create_qp_resp *resp, int *inlen,
761 struct mlx5_ib_qp_base *base)
763 struct mlx5_ib_ucontext *context;
764 struct mlx5_ib_create_qp ucmd;
765 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
776 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
778 mlx5_ib_dbg(dev, "copy failed\n");
782 context = to_mucontext(pd->uobject->context);
784 * TBD: should come from the verbs when we have the API
786 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
787 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
788 bfregn = MLX5_CROSS_CHANNEL_BFREG;
790 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
792 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
793 mlx5_ib_dbg(dev, "reverting to medium latency\n");
794 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
796 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
797 mlx5_ib_dbg(dev, "reverting to high latency\n");
798 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
800 mlx5_ib_warn(dev, "bfreg allocation failed\n");
807 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn);
808 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
811 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
812 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
814 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
818 if (ucmd.buf_addr && ubuffer->buf_size) {
819 ubuffer->buf_addr = ucmd.buf_addr;
820 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
822 &ubuffer->umem, &npages, &page_shift,
827 ubuffer->umem = NULL;
830 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
831 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
832 *in = kvzalloc(*inlen, GFP_KERNEL);
838 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
840 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
842 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
844 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
845 MLX5_SET(qpc, qpc, page_offset, offset);
847 MLX5_SET(qpc, qpc, uar_page, uar_index);
848 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
851 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
853 mlx5_ib_dbg(dev, "map failed\n");
857 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
859 mlx5_ib_dbg(dev, "copy failed\n");
862 qp->create_type = MLX5_QP_USER;
867 mlx5_ib_db_unmap_user(context, &qp->db);
874 ib_umem_release(ubuffer->umem);
877 free_bfreg(dev, &context->bfregi, bfregn);
881 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
882 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
884 struct mlx5_ib_ucontext *context;
886 context = to_mucontext(pd->uobject->context);
887 mlx5_ib_db_unmap_user(context, &qp->db);
888 if (base->ubuffer.umem)
889 ib_umem_release(base->ubuffer.umem);
890 free_bfreg(dev, &context->bfregi, qp->bfregn);
893 static int create_kernel_qp(struct mlx5_ib_dev *dev,
894 struct ib_qp_init_attr *init_attr,
895 struct mlx5_ib_qp *qp,
896 u32 **in, int *inlen,
897 struct mlx5_ib_qp_base *base)
903 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
904 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
905 IB_QP_CREATE_IPOIB_UD_LSO |
906 IB_QP_CREATE_NETIF_QP |
907 mlx5_ib_create_qp_sqpn_qp1()))
910 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
911 qp->bf.bfreg = &dev->fp_bfreg;
913 qp->bf.bfreg = &dev->bfreg;
915 /* We need to divide by two since each register is comprised of
916 * two buffers of identical size, namely odd and even
918 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
919 uar_index = qp->bf.bfreg->index;
921 err = calc_sq_size(dev, init_attr, qp);
923 mlx5_ib_dbg(dev, "err %d\n", err);
928 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
929 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
931 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
933 mlx5_ib_dbg(dev, "err %d\n", err);
937 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
938 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
939 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
940 *in = kvzalloc(*inlen, GFP_KERNEL);
946 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
947 MLX5_SET(qpc, qpc, uar_page, uar_index);
948 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
950 /* Set "fast registration enabled" for all kernel QPs */
951 MLX5_SET(qpc, qpc, fre, 1);
952 MLX5_SET(qpc, qpc, rlky, 1);
954 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
955 MLX5_SET(qpc, qpc, deth_sqpn, 1);
956 qp->flags |= MLX5_IB_QP_SQPN_QP1;
959 mlx5_fill_page_array(&qp->buf,
960 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
962 err = mlx5_db_alloc(dev->mdev, &qp->db);
964 mlx5_ib_dbg(dev, "err %d\n", err);
968 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
969 sizeof(*qp->sq.wrid), GFP_KERNEL);
970 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
971 sizeof(*qp->sq.wr_data), GFP_KERNEL);
972 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
973 sizeof(*qp->rq.wrid), GFP_KERNEL);
974 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
975 sizeof(*qp->sq.w_list), GFP_KERNEL);
976 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
977 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
979 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
980 !qp->sq.w_list || !qp->sq.wqe_head) {
984 qp->create_type = MLX5_QP_KERNEL;
989 kvfree(qp->sq.wqe_head);
990 kvfree(qp->sq.w_list);
992 kvfree(qp->sq.wr_data);
994 mlx5_db_free(dev->mdev, &qp->db);
1000 mlx5_buf_free(dev->mdev, &qp->buf);
1004 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1006 kvfree(qp->sq.wqe_head);
1007 kvfree(qp->sq.w_list);
1008 kvfree(qp->sq.wrid);
1009 kvfree(qp->sq.wr_data);
1010 kvfree(qp->rq.wrid);
1011 mlx5_db_free(dev->mdev, &qp->db);
1012 mlx5_buf_free(dev->mdev, &qp->buf);
1015 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1017 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1018 (attr->qp_type == IB_QPT_XRC_INI))
1020 else if (!qp->has_rq)
1021 return MLX5_ZERO_LEN_RQ;
1023 return MLX5_NON_ZERO_RQ;
1026 static int is_connected(enum ib_qp_type qp_type)
1028 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1034 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1035 struct mlx5_ib_qp *qp,
1036 struct mlx5_ib_sq *sq, u32 tdn)
1038 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1039 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1041 MLX5_SET(tisc, tisc, transport_domain, tdn);
1042 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1043 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1045 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1048 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1049 struct mlx5_ib_sq *sq)
1051 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1054 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1055 struct mlx5_ib_sq *sq, void *qpin,
1058 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1062 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1071 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1072 &sq->ubuffer.umem, &npages, &page_shift,
1077 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1078 in = kvzalloc(inlen, GFP_KERNEL);
1084 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1085 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1086 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1087 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1088 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1089 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1090 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1091 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1092 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1093 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1094 MLX5_CAP_ETH(dev->mdev, swp))
1095 MLX5_SET(sqc, sqc, allow_swp, 1);
1097 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1098 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1099 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1100 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1101 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1102 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1103 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1104 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1105 MLX5_SET(wq, wq, page_offset, offset);
1107 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1108 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1110 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1120 ib_umem_release(sq->ubuffer.umem);
1121 sq->ubuffer.umem = NULL;
1126 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1127 struct mlx5_ib_sq *sq)
1129 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1130 ib_umem_release(sq->ubuffer.umem);
1133 static int get_rq_pas_size(void *qpc)
1135 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1136 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1137 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1138 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1139 u32 po_quanta = 1 << (log_page_size - 6);
1140 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1141 u32 page_size = 1 << log_page_size;
1142 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1143 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1145 return rq_num_pas * sizeof(u64);
1148 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1149 struct mlx5_ib_rq *rq, void *qpin)
1151 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1157 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1160 u32 rq_pas_size = get_rq_pas_size(qpc);
1162 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1163 in = kvzalloc(inlen, GFP_KERNEL);
1167 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1168 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1169 MLX5_SET(rqc, rqc, vsd, 1);
1170 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1171 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1172 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1173 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1174 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1176 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1177 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1179 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1180 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1181 MLX5_SET(wq, wq, end_padding_mode,
1182 MLX5_GET(qpc, qpc, end_padding_mode));
1183 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1184 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1185 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1186 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1187 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1188 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1190 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1191 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1192 memcpy(pas, qp_pas, rq_pas_size);
1194 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1201 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1202 struct mlx5_ib_rq *rq)
1204 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1207 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1208 struct mlx5_ib_rq *rq, u32 tdn)
1215 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1216 in = kvzalloc(inlen, GFP_KERNEL);
1220 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1221 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1222 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1223 MLX5_SET(tirc, tirc, transport_domain, tdn);
1225 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1232 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1233 struct mlx5_ib_rq *rq)
1235 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1238 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1242 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1243 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1244 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1245 struct ib_uobject *uobj = pd->uobject;
1246 struct ib_ucontext *ucontext = uobj->context;
1247 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1249 u32 tdn = mucontext->tdn;
1251 if (qp->sq.wqe_cnt) {
1252 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
1256 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1258 goto err_destroy_tis;
1260 sq->base.container_mibqp = qp;
1261 sq->base.mqp.event = mlx5_ib_qp_event;
1264 if (qp->rq.wqe_cnt) {
1265 rq->base.container_mibqp = qp;
1267 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1268 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1269 err = create_raw_packet_qp_rq(dev, rq, in);
1271 goto err_destroy_sq;
1274 err = create_raw_packet_qp_tir(dev, rq, tdn);
1276 goto err_destroy_rq;
1279 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1285 destroy_raw_packet_qp_rq(dev, rq);
1287 if (!qp->sq.wqe_cnt)
1289 destroy_raw_packet_qp_sq(dev, sq);
1291 destroy_raw_packet_qp_tis(dev, sq);
1296 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1297 struct mlx5_ib_qp *qp)
1299 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1300 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1301 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1303 if (qp->rq.wqe_cnt) {
1304 destroy_raw_packet_qp_tir(dev, rq);
1305 destroy_raw_packet_qp_rq(dev, rq);
1308 if (qp->sq.wqe_cnt) {
1309 destroy_raw_packet_qp_sq(dev, sq);
1310 destroy_raw_packet_qp_tis(dev, sq);
1314 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1315 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1317 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1318 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1322 sq->doorbell = &qp->db;
1323 rq->doorbell = &qp->db;
1326 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1328 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1331 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1333 struct ib_qp_init_attr *init_attr,
1334 struct ib_udata *udata)
1336 struct ib_uobject *uobj = pd->uobject;
1337 struct ib_ucontext *ucontext = uobj->context;
1338 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1339 struct mlx5_ib_create_qp_resp resp = {};
1345 u32 selected_fields = 0;
1346 size_t min_resp_len;
1347 u32 tdn = mucontext->tdn;
1348 struct mlx5_ib_create_qp_rss ucmd = {};
1349 size_t required_cmd_sz;
1351 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1354 if (init_attr->create_flags || init_attr->send_cq)
1357 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1358 if (udata->outlen < min_resp_len)
1361 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1362 if (udata->inlen < required_cmd_sz) {
1363 mlx5_ib_dbg(dev, "invalid inlen\n");
1367 if (udata->inlen > sizeof(ucmd) &&
1368 !ib_is_udata_cleared(udata, sizeof(ucmd),
1369 udata->inlen - sizeof(ucmd))) {
1370 mlx5_ib_dbg(dev, "inlen is not supported\n");
1374 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1375 mlx5_ib_dbg(dev, "copy failed\n");
1379 if (ucmd.comp_mask) {
1380 mlx5_ib_dbg(dev, "invalid comp mask\n");
1384 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1385 mlx5_ib_dbg(dev, "invalid reserved\n");
1389 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1391 mlx5_ib_dbg(dev, "copy failed\n");
1395 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1396 in = kvzalloc(inlen, GFP_KERNEL);
1400 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1401 MLX5_SET(tirc, tirc, disp_type,
1402 MLX5_TIRC_DISP_TYPE_INDIRECT);
1403 MLX5_SET(tirc, tirc, indirect_table,
1404 init_attr->rwq_ind_tbl->ind_tbl_num);
1405 MLX5_SET(tirc, tirc, transport_domain, tdn);
1407 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1408 switch (ucmd.rx_hash_function) {
1409 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1411 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1412 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1414 if (len != ucmd.rx_key_len) {
1419 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1420 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1421 memcpy(rss_key, ucmd.rx_hash_key, len);
1429 if (!ucmd.rx_hash_fields_mask) {
1430 /* special case when this TIR serves as steering entry without hashing */
1431 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1437 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1438 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1439 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1440 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1445 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1446 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1447 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1448 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1449 MLX5_L3_PROT_TYPE_IPV4);
1450 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1451 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1452 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1453 MLX5_L3_PROT_TYPE_IPV6);
1455 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1456 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1457 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1458 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1463 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1464 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1465 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1466 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1467 MLX5_L4_PROT_TYPE_TCP);
1468 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1469 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1470 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1471 MLX5_L4_PROT_TYPE_UDP);
1473 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1474 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1475 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1477 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1478 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1479 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1481 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1482 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1483 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1485 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1486 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1487 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1489 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1492 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1498 /* qpn is reserved for that QP */
1499 qp->trans_qp.base.mqp.qpn = 0;
1500 qp->flags |= MLX5_IB_QP_RSS;
1508 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1509 struct ib_qp_init_attr *init_attr,
1510 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1512 struct mlx5_ib_resources *devr = &dev->devr;
1513 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1514 struct mlx5_core_dev *mdev = dev->mdev;
1515 struct mlx5_ib_create_qp_resp resp;
1516 struct mlx5_ib_cq *send_cq;
1517 struct mlx5_ib_cq *recv_cq;
1518 unsigned long flags;
1519 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1520 struct mlx5_ib_create_qp ucmd;
1521 struct mlx5_ib_qp_base *base;
1526 mutex_init(&qp->mutex);
1527 spin_lock_init(&qp->sq.lock);
1528 spin_lock_init(&qp->rq.lock);
1530 if (init_attr->rwq_ind_tbl) {
1534 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1538 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1539 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1540 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1543 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1547 if (init_attr->create_flags &
1548 (IB_QP_CREATE_CROSS_CHANNEL |
1549 IB_QP_CREATE_MANAGED_SEND |
1550 IB_QP_CREATE_MANAGED_RECV)) {
1551 if (!MLX5_CAP_GEN(mdev, cd)) {
1552 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1555 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1556 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1557 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1558 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1559 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1560 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1563 if (init_attr->qp_type == IB_QPT_UD &&
1564 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1565 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1566 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1570 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1571 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1572 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1575 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1576 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1577 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1580 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1583 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1584 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1586 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1587 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1588 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1589 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1591 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1594 if (pd && pd->uobject) {
1595 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1596 mlx5_ib_dbg(dev, "copy failed\n");
1600 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1601 &ucmd, udata->inlen, &uidx);
1605 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1606 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1608 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1609 if (init_attr->qp_type != IB_QPT_UD ||
1610 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1611 MLX5_CAP_PORT_TYPE_IB) ||
1612 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1613 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1617 qp->flags |= MLX5_IB_QP_UNDERLAY;
1618 qp->underlay_qpn = init_attr->source_qpn;
1621 qp->wq_sig = !!wq_signature;
1624 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1625 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1626 &qp->raw_packet_qp.rq.base :
1629 qp->has_rq = qp_has_rq(init_attr);
1630 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1631 qp, (pd && pd->uobject) ? &ucmd : NULL);
1633 mlx5_ib_dbg(dev, "err %d\n", err);
1640 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1641 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1642 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1643 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1644 mlx5_ib_dbg(dev, "invalid rq params\n");
1647 if (ucmd.sq_wqe_count > max_wqes) {
1648 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1649 ucmd.sq_wqe_count, max_wqes);
1652 if (init_attr->create_flags &
1653 mlx5_ib_create_qp_sqpn_qp1()) {
1654 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1657 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1658 &resp, &inlen, base);
1660 mlx5_ib_dbg(dev, "err %d\n", err);
1662 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1665 mlx5_ib_dbg(dev, "err %d\n", err);
1671 in = kvzalloc(inlen, GFP_KERNEL);
1675 qp->create_type = MLX5_QP_EMPTY;
1678 if (is_sqp(init_attr->qp_type))
1679 qp->port = init_attr->port_num;
1681 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1683 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1684 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1686 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1687 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1689 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1693 MLX5_SET(qpc, qpc, wq_signature, 1);
1695 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1696 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1698 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1699 MLX5_SET(qpc, qpc, cd_master, 1);
1700 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1701 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1702 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1703 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1705 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1709 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1710 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1713 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1715 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1717 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1719 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1721 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1725 if (qp->rq.wqe_cnt) {
1726 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1727 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1730 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1732 if (qp->sq.wqe_cnt) {
1733 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1735 MLX5_SET(qpc, qpc, no_sq, 1);
1736 if (init_attr->srq &&
1737 init_attr->srq->srq_type == IB_SRQT_TM)
1738 MLX5_SET(qpc, qpc, offload_type,
1739 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1742 /* Set default resources */
1743 switch (init_attr->qp_type) {
1744 case IB_QPT_XRC_TGT:
1745 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1746 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1747 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1748 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1750 case IB_QPT_XRC_INI:
1751 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1752 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1753 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1756 if (init_attr->srq) {
1757 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1758 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1760 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1761 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1765 if (init_attr->send_cq)
1766 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1768 if (init_attr->recv_cq)
1769 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1771 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1773 /* 0xffffff means we ask to work with cqe version 0 */
1774 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1775 MLX5_SET(qpc, qpc, user_index, uidx);
1777 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1778 if (init_attr->qp_type == IB_QPT_UD &&
1779 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1780 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1781 qp->flags |= MLX5_IB_QP_LSO;
1784 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1785 qp->flags & MLX5_IB_QP_UNDERLAY) {
1786 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1787 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1788 err = create_raw_packet_qp(dev, qp, in, pd);
1790 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1794 mlx5_ib_dbg(dev, "create qp failed\n");
1800 base->container_mibqp = qp;
1801 base->mqp.event = mlx5_ib_qp_event;
1803 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1804 &send_cq, &recv_cq);
1805 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1806 mlx5_ib_lock_cqs(send_cq, recv_cq);
1807 /* Maintain device to QPs access, needed for further handling via reset
1810 list_add_tail(&qp->qps_list, &dev->qp_list);
1811 /* Maintain CQ to QPs access, needed for further handling via reset flow
1814 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1816 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1817 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1818 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1823 if (qp->create_type == MLX5_QP_USER)
1824 destroy_qp_user(dev, pd, qp, base);
1825 else if (qp->create_type == MLX5_QP_KERNEL)
1826 destroy_qp_kernel(dev, qp);
1832 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1833 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1837 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1838 spin_lock(&send_cq->lock);
1839 spin_lock_nested(&recv_cq->lock,
1840 SINGLE_DEPTH_NESTING);
1841 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1842 spin_lock(&send_cq->lock);
1843 __acquire(&recv_cq->lock);
1845 spin_lock(&recv_cq->lock);
1846 spin_lock_nested(&send_cq->lock,
1847 SINGLE_DEPTH_NESTING);
1850 spin_lock(&send_cq->lock);
1851 __acquire(&recv_cq->lock);
1853 } else if (recv_cq) {
1854 spin_lock(&recv_cq->lock);
1855 __acquire(&send_cq->lock);
1857 __acquire(&send_cq->lock);
1858 __acquire(&recv_cq->lock);
1862 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1863 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1867 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1868 spin_unlock(&recv_cq->lock);
1869 spin_unlock(&send_cq->lock);
1870 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1871 __release(&recv_cq->lock);
1872 spin_unlock(&send_cq->lock);
1874 spin_unlock(&send_cq->lock);
1875 spin_unlock(&recv_cq->lock);
1878 __release(&recv_cq->lock);
1879 spin_unlock(&send_cq->lock);
1881 } else if (recv_cq) {
1882 __release(&send_cq->lock);
1883 spin_unlock(&recv_cq->lock);
1885 __release(&recv_cq->lock);
1886 __release(&send_cq->lock);
1890 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1892 return to_mpd(qp->ibqp.pd);
1895 static void get_cqs(enum ib_qp_type qp_type,
1896 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1897 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1900 case IB_QPT_XRC_TGT:
1904 case MLX5_IB_QPT_REG_UMR:
1905 case IB_QPT_XRC_INI:
1906 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1911 case MLX5_IB_QPT_HW_GSI:
1915 case IB_QPT_RAW_IPV6:
1916 case IB_QPT_RAW_ETHERTYPE:
1917 case IB_QPT_RAW_PACKET:
1918 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1919 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1930 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1931 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1932 u8 lag_tx_affinity);
1934 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1936 struct mlx5_ib_cq *send_cq, *recv_cq;
1937 struct mlx5_ib_qp_base *base;
1938 unsigned long flags;
1941 if (qp->ibqp.rwq_ind_tbl) {
1942 destroy_rss_raw_qp_tir(dev, qp);
1946 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
1947 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1948 &qp->raw_packet_qp.rq.base :
1951 if (qp->state != IB_QPS_RESET) {
1952 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
1953 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
1954 err = mlx5_core_qp_modify(dev->mdev,
1955 MLX5_CMD_OP_2RST_QP, 0,
1958 struct mlx5_modify_raw_qp_param raw_qp_param = {
1959 .operation = MLX5_CMD_OP_2RST_QP
1962 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
1965 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1969 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1970 &send_cq, &recv_cq);
1972 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1973 mlx5_ib_lock_cqs(send_cq, recv_cq);
1974 /* del from lists under both locks above to protect reset flow paths */
1975 list_del(&qp->qps_list);
1977 list_del(&qp->cq_send_list);
1980 list_del(&qp->cq_recv_list);
1982 if (qp->create_type == MLX5_QP_KERNEL) {
1983 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1984 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1985 if (send_cq != recv_cq)
1986 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1989 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1990 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1992 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
1993 qp->flags & MLX5_IB_QP_UNDERLAY) {
1994 destroy_raw_packet_qp(dev, qp);
1996 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1998 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2002 if (qp->create_type == MLX5_QP_KERNEL)
2003 destroy_qp_kernel(dev, qp);
2004 else if (qp->create_type == MLX5_QP_USER)
2005 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2008 static const char *ib_qp_type_str(enum ib_qp_type type)
2012 return "IB_QPT_SMI";
2014 return "IB_QPT_GSI";
2021 case IB_QPT_RAW_IPV6:
2022 return "IB_QPT_RAW_IPV6";
2023 case IB_QPT_RAW_ETHERTYPE:
2024 return "IB_QPT_RAW_ETHERTYPE";
2025 case IB_QPT_XRC_INI:
2026 return "IB_QPT_XRC_INI";
2027 case IB_QPT_XRC_TGT:
2028 return "IB_QPT_XRC_TGT";
2029 case IB_QPT_RAW_PACKET:
2030 return "IB_QPT_RAW_PACKET";
2031 case MLX5_IB_QPT_REG_UMR:
2032 return "MLX5_IB_QPT_REG_UMR";
2035 return "Invalid QP type";
2039 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2040 struct ib_qp_init_attr *init_attr,
2041 struct ib_udata *udata)
2043 struct mlx5_ib_dev *dev;
2044 struct mlx5_ib_qp *qp;
2049 dev = to_mdev(pd->device);
2051 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2053 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2054 return ERR_PTR(-EINVAL);
2055 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2056 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2057 return ERR_PTR(-EINVAL);
2061 /* being cautious here */
2062 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2063 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2064 pr_warn("%s: no PD for transport %s\n", __func__,
2065 ib_qp_type_str(init_attr->qp_type));
2066 return ERR_PTR(-EINVAL);
2068 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2071 switch (init_attr->qp_type) {
2072 case IB_QPT_XRC_TGT:
2073 case IB_QPT_XRC_INI:
2074 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2075 mlx5_ib_dbg(dev, "XRC not supported\n");
2076 return ERR_PTR(-ENOSYS);
2078 init_attr->recv_cq = NULL;
2079 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2080 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2081 init_attr->send_cq = NULL;
2085 case IB_QPT_RAW_PACKET:
2090 case MLX5_IB_QPT_HW_GSI:
2091 case MLX5_IB_QPT_REG_UMR:
2092 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2094 return ERR_PTR(-ENOMEM);
2096 err = create_qp_common(dev, pd, init_attr, udata, qp);
2098 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2100 return ERR_PTR(err);
2103 if (is_qp0(init_attr->qp_type))
2104 qp->ibqp.qp_num = 0;
2105 else if (is_qp1(init_attr->qp_type))
2106 qp->ibqp.qp_num = 1;
2108 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2110 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2111 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2112 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2113 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2115 qp->trans_qp.xrcdn = xrcdn;
2120 return mlx5_ib_gsi_create_qp(pd, init_attr);
2122 case IB_QPT_RAW_IPV6:
2123 case IB_QPT_RAW_ETHERTYPE:
2126 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2127 init_attr->qp_type);
2128 /* Don't support raw QPs */
2129 return ERR_PTR(-EINVAL);
2135 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2137 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2138 struct mlx5_ib_qp *mqp = to_mqp(qp);
2140 if (unlikely(qp->qp_type == IB_QPT_GSI))
2141 return mlx5_ib_gsi_destroy_qp(qp);
2143 destroy_qp_common(dev, mqp);
2150 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2153 u32 hw_access_flags = 0;
2157 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2158 dest_rd_atomic = attr->max_dest_rd_atomic;
2160 dest_rd_atomic = qp->trans_qp.resp_depth;
2162 if (attr_mask & IB_QP_ACCESS_FLAGS)
2163 access_flags = attr->qp_access_flags;
2165 access_flags = qp->trans_qp.atomic_rd_en;
2167 if (!dest_rd_atomic)
2168 access_flags &= IB_ACCESS_REMOTE_WRITE;
2170 if (access_flags & IB_ACCESS_REMOTE_READ)
2171 hw_access_flags |= MLX5_QP_BIT_RRE;
2172 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2173 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2174 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2175 hw_access_flags |= MLX5_QP_BIT_RWE;
2177 return cpu_to_be32(hw_access_flags);
2181 MLX5_PATH_FLAG_FL = 1 << 0,
2182 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2183 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2186 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2188 if (rate == IB_RATE_PORT_CURRENT) {
2190 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2193 while (rate != IB_RATE_2_5_GBPS &&
2194 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2195 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2199 return rate + MLX5_STAT_RATE_OFFSET;
2202 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2203 struct mlx5_ib_sq *sq, u8 sl)
2210 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2211 in = kvzalloc(inlen, GFP_KERNEL);
2215 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2217 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2218 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2220 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2227 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2228 struct mlx5_ib_sq *sq, u8 tx_affinity)
2235 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2236 in = kvzalloc(inlen, GFP_KERNEL);
2240 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2242 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2243 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2245 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2252 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2253 const struct rdma_ah_attr *ah,
2254 struct mlx5_qp_path *path, u8 port, int attr_mask,
2255 u32 path_flags, const struct ib_qp_attr *attr,
2258 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2260 enum ib_gid_type gid_type;
2261 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2262 u8 sl = rdma_ah_get_sl(ah);
2264 if (attr_mask & IB_QP_PKEY_INDEX)
2265 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2268 if (ah_flags & IB_AH_GRH) {
2269 if (grh->sgid_index >=
2270 dev->mdev->port_caps[port - 1].gid_table_len) {
2271 pr_err("sgid_index (%u) too large. max is %d\n",
2273 dev->mdev->port_caps[port - 1].gid_table_len);
2278 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2279 if (!(ah_flags & IB_AH_GRH))
2281 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index,
2285 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2286 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2288 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2289 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2290 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2292 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2294 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2295 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2296 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2297 if (ah_flags & IB_AH_GRH)
2298 path->grh_mlid |= 1 << 7;
2299 path->dci_cfi_prio_sl = sl & 0xf;
2302 if (ah_flags & IB_AH_GRH) {
2303 path->mgid_index = grh->sgid_index;
2304 path->hop_limit = grh->hop_limit;
2305 path->tclass_flowlabel =
2306 cpu_to_be32((grh->traffic_class << 20) |
2308 memcpy(path->rgid, grh->dgid.raw, 16);
2311 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2314 path->static_rate = err;
2317 if (attr_mask & IB_QP_TIMEOUT)
2318 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2320 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2321 return modify_raw_packet_eth_prio(dev->mdev,
2322 &qp->raw_packet_qp.sq,
2328 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2329 [MLX5_QP_STATE_INIT] = {
2330 [MLX5_QP_STATE_INIT] = {
2331 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2332 MLX5_QP_OPTPAR_RAE |
2333 MLX5_QP_OPTPAR_RWE |
2334 MLX5_QP_OPTPAR_PKEY_INDEX |
2335 MLX5_QP_OPTPAR_PRI_PORT,
2336 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2337 MLX5_QP_OPTPAR_PKEY_INDEX |
2338 MLX5_QP_OPTPAR_PRI_PORT,
2339 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2340 MLX5_QP_OPTPAR_Q_KEY |
2341 MLX5_QP_OPTPAR_PRI_PORT,
2343 [MLX5_QP_STATE_RTR] = {
2344 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2345 MLX5_QP_OPTPAR_RRE |
2346 MLX5_QP_OPTPAR_RAE |
2347 MLX5_QP_OPTPAR_RWE |
2348 MLX5_QP_OPTPAR_PKEY_INDEX,
2349 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2350 MLX5_QP_OPTPAR_RWE |
2351 MLX5_QP_OPTPAR_PKEY_INDEX,
2352 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2353 MLX5_QP_OPTPAR_Q_KEY,
2354 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2355 MLX5_QP_OPTPAR_Q_KEY,
2356 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2357 MLX5_QP_OPTPAR_RRE |
2358 MLX5_QP_OPTPAR_RAE |
2359 MLX5_QP_OPTPAR_RWE |
2360 MLX5_QP_OPTPAR_PKEY_INDEX,
2363 [MLX5_QP_STATE_RTR] = {
2364 [MLX5_QP_STATE_RTS] = {
2365 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2366 MLX5_QP_OPTPAR_RRE |
2367 MLX5_QP_OPTPAR_RAE |
2368 MLX5_QP_OPTPAR_RWE |
2369 MLX5_QP_OPTPAR_PM_STATE |
2370 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2371 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2372 MLX5_QP_OPTPAR_RWE |
2373 MLX5_QP_OPTPAR_PM_STATE,
2374 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2377 [MLX5_QP_STATE_RTS] = {
2378 [MLX5_QP_STATE_RTS] = {
2379 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2380 MLX5_QP_OPTPAR_RAE |
2381 MLX5_QP_OPTPAR_RWE |
2382 MLX5_QP_OPTPAR_RNR_TIMEOUT |
2383 MLX5_QP_OPTPAR_PM_STATE |
2384 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2385 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2386 MLX5_QP_OPTPAR_PM_STATE |
2387 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2388 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2389 MLX5_QP_OPTPAR_SRQN |
2390 MLX5_QP_OPTPAR_CQN_RCV,
2393 [MLX5_QP_STATE_SQER] = {
2394 [MLX5_QP_STATE_RTS] = {
2395 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2396 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2397 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
2398 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2399 MLX5_QP_OPTPAR_RWE |
2400 MLX5_QP_OPTPAR_RAE |
2406 static int ib_nr_to_mlx5_nr(int ib_mask)
2411 case IB_QP_CUR_STATE:
2413 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2415 case IB_QP_ACCESS_FLAGS:
2416 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2418 case IB_QP_PKEY_INDEX:
2419 return MLX5_QP_OPTPAR_PKEY_INDEX;
2421 return MLX5_QP_OPTPAR_PRI_PORT;
2423 return MLX5_QP_OPTPAR_Q_KEY;
2425 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2426 MLX5_QP_OPTPAR_PRI_PORT;
2427 case IB_QP_PATH_MTU:
2430 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2431 case IB_QP_RETRY_CNT:
2432 return MLX5_QP_OPTPAR_RETRY_COUNT;
2433 case IB_QP_RNR_RETRY:
2434 return MLX5_QP_OPTPAR_RNR_RETRY;
2437 case IB_QP_MAX_QP_RD_ATOMIC:
2438 return MLX5_QP_OPTPAR_SRA_MAX;
2439 case IB_QP_ALT_PATH:
2440 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2441 case IB_QP_MIN_RNR_TIMER:
2442 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2445 case IB_QP_MAX_DEST_RD_ATOMIC:
2446 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2447 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2448 case IB_QP_PATH_MIG_STATE:
2449 return MLX5_QP_OPTPAR_PM_STATE;
2452 case IB_QP_DEST_QPN:
2458 static int ib_mask_to_mlx5_opt(int ib_mask)
2463 for (i = 0; i < 8 * sizeof(int); i++) {
2464 if ((1 << i) & ib_mask)
2465 result |= ib_nr_to_mlx5_nr(1 << i);
2471 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2472 struct mlx5_ib_rq *rq, int new_state,
2473 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2480 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2481 in = kvzalloc(inlen, GFP_KERNEL);
2485 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2487 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2488 MLX5_SET(rqc, rqc, state, new_state);
2490 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2491 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2492 MLX5_SET64(modify_rq_in, in, modify_bitmask,
2493 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2494 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2496 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2500 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2504 rq->state = new_state;
2511 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2512 struct mlx5_ib_sq *sq,
2514 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2516 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2517 u32 old_rate = ibqp->rate_limit;
2518 u32 new_rate = old_rate;
2525 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2526 in = kvzalloc(inlen, GFP_KERNEL);
2530 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2532 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2533 MLX5_SET(sqc, sqc, state, new_state);
2535 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2536 if (new_state != MLX5_SQC_STATE_RDY)
2537 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2540 new_rate = raw_qp_param->rate_limit;
2543 if (old_rate != new_rate) {
2545 err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2547 pr_err("Failed configuring rate %u: %d\n",
2553 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2554 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2557 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2559 /* Remove new rate from table if failed */
2561 old_rate != new_rate)
2562 mlx5_rl_remove_rate(dev, new_rate);
2566 /* Only remove the old rate after new rate was set */
2568 (old_rate != new_rate)) ||
2569 (new_state != MLX5_SQC_STATE_RDY))
2570 mlx5_rl_remove_rate(dev, old_rate);
2572 ibqp->rate_limit = new_rate;
2573 sq->state = new_state;
2580 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2581 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2584 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2585 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2586 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2587 int modify_rq = !!qp->rq.wqe_cnt;
2588 int modify_sq = !!qp->sq.wqe_cnt;
2593 switch (raw_qp_param->operation) {
2594 case MLX5_CMD_OP_RST2INIT_QP:
2595 rq_state = MLX5_RQC_STATE_RDY;
2596 sq_state = MLX5_SQC_STATE_RDY;
2598 case MLX5_CMD_OP_2ERR_QP:
2599 rq_state = MLX5_RQC_STATE_ERR;
2600 sq_state = MLX5_SQC_STATE_ERR;
2602 case MLX5_CMD_OP_2RST_QP:
2603 rq_state = MLX5_RQC_STATE_RST;
2604 sq_state = MLX5_SQC_STATE_RST;
2606 case MLX5_CMD_OP_RTR2RTS_QP:
2607 case MLX5_CMD_OP_RTS2RTS_QP:
2608 if (raw_qp_param->set_mask ==
2609 MLX5_RAW_QP_RATE_LIMIT) {
2611 sq_state = sq->state;
2613 return raw_qp_param->set_mask ? -EINVAL : 0;
2616 case MLX5_CMD_OP_INIT2INIT_QP:
2617 case MLX5_CMD_OP_INIT2RTR_QP:
2618 if (raw_qp_param->set_mask)
2628 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2635 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2641 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2647 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2648 const struct ib_qp_attr *attr, int attr_mask,
2649 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2651 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2652 [MLX5_QP_STATE_RST] = {
2653 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2654 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2655 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2657 [MLX5_QP_STATE_INIT] = {
2658 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2659 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2660 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2661 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2663 [MLX5_QP_STATE_RTR] = {
2664 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2665 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2666 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2668 [MLX5_QP_STATE_RTS] = {
2669 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2670 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2671 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2673 [MLX5_QP_STATE_SQD] = {
2674 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2675 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2677 [MLX5_QP_STATE_SQER] = {
2678 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2679 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2680 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2682 [MLX5_QP_STATE_ERR] = {
2683 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2684 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2688 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2689 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2690 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2691 struct mlx5_ib_cq *send_cq, *recv_cq;
2692 struct mlx5_qp_context *context;
2693 struct mlx5_ib_pd *pd;
2694 struct mlx5_ib_port *mibport = NULL;
2695 enum mlx5_qp_state mlx5_cur, mlx5_new;
2696 enum mlx5_qp_optpar optpar;
2702 context = kzalloc(sizeof(*context), GFP_KERNEL);
2706 err = to_mlx5_st(ibqp->qp_type);
2708 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2712 context->flags = cpu_to_be32(err << 16);
2714 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2715 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2717 switch (attr->path_mig_state) {
2718 case IB_MIG_MIGRATED:
2719 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2722 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2725 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2730 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2731 if ((ibqp->qp_type == IB_QPT_RC) ||
2732 (ibqp->qp_type == IB_QPT_UD &&
2733 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2734 (ibqp->qp_type == IB_QPT_UC) ||
2735 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2736 (ibqp->qp_type == IB_QPT_XRC_INI) ||
2737 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2738 if (mlx5_lag_is_active(dev->mdev)) {
2739 tx_affinity = (unsigned int)atomic_add_return(1,
2740 &dev->roce.next_port) %
2742 context->flags |= cpu_to_be32(tx_affinity << 24);
2747 if (is_sqp(ibqp->qp_type)) {
2748 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2749 } else if ((ibqp->qp_type == IB_QPT_UD &&
2750 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
2751 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2752 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2753 } else if (attr_mask & IB_QP_PATH_MTU) {
2754 if (attr->path_mtu < IB_MTU_256 ||
2755 attr->path_mtu > IB_MTU_4096) {
2756 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2760 context->mtu_msgmax = (attr->path_mtu << 5) |
2761 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2764 if (attr_mask & IB_QP_DEST_QPN)
2765 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2767 if (attr_mask & IB_QP_PKEY_INDEX)
2768 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2770 /* todo implement counter_index functionality */
2772 if (is_sqp(ibqp->qp_type))
2773 context->pri_path.port = qp->port;
2775 if (attr_mask & IB_QP_PORT)
2776 context->pri_path.port = attr->port_num;
2778 if (attr_mask & IB_QP_AV) {
2779 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2780 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2781 attr_mask, 0, attr, false);
2786 if (attr_mask & IB_QP_TIMEOUT)
2787 context->pri_path.ackto_lt |= attr->timeout << 3;
2789 if (attr_mask & IB_QP_ALT_PATH) {
2790 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2793 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2800 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2801 &send_cq, &recv_cq);
2803 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2804 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2805 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2806 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2808 if (attr_mask & IB_QP_RNR_RETRY)
2809 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2811 if (attr_mask & IB_QP_RETRY_CNT)
2812 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2814 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2815 if (attr->max_rd_atomic)
2817 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2820 if (attr_mask & IB_QP_SQ_PSN)
2821 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2823 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2824 if (attr->max_dest_rd_atomic)
2826 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2829 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2830 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2832 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2833 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2835 if (attr_mask & IB_QP_RQ_PSN)
2836 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2838 if (attr_mask & IB_QP_QKEY)
2839 context->qkey = cpu_to_be32(attr->qkey);
2841 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2842 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2844 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2845 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2848 /* Underlay port should be used - index 0 function per port */
2849 if (qp->flags & MLX5_IB_QP_UNDERLAY)
2852 mibport = &dev->port[port_num];
2853 context->qp_counter_set_usr_page |=
2854 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
2857 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2858 context->sq_crq_size |= cpu_to_be16(1 << 4);
2860 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2861 context->deth_sqpn = cpu_to_be32(1);
2863 mlx5_cur = to_mlx5_state(cur_state);
2864 mlx5_new = to_mlx5_state(new_state);
2865 mlx5_st = to_mlx5_st(ibqp->qp_type);
2869 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2870 !optab[mlx5_cur][mlx5_new])
2873 op = optab[mlx5_cur][mlx5_new];
2874 optpar = ib_mask_to_mlx5_opt(attr_mask);
2875 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2877 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2878 qp->flags & MLX5_IB_QP_UNDERLAY) {
2879 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2881 raw_qp_param.operation = op;
2882 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2883 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
2884 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2887 if (attr_mask & IB_QP_RATE_LIMIT) {
2888 raw_qp_param.rate_limit = attr->rate_limit;
2889 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2892 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
2894 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2901 qp->state = new_state;
2903 if (attr_mask & IB_QP_ACCESS_FLAGS)
2904 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2905 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2906 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2907 if (attr_mask & IB_QP_PORT)
2908 qp->port = attr->port_num;
2909 if (attr_mask & IB_QP_ALT_PATH)
2910 qp->trans_qp.alt_port = attr->alt_port_num;
2913 * If we moved a kernel QP to RESET, clean up all old CQ
2914 * entries and reinitialize the QP.
2916 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2917 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2918 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2919 if (send_cq != recv_cq)
2920 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2926 qp->sq.cur_post = 0;
2927 qp->sq.last_poll = 0;
2928 qp->db.db[MLX5_RCV_DBR] = 0;
2929 qp->db.db[MLX5_SND_DBR] = 0;
2937 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2938 int attr_mask, struct ib_udata *udata)
2940 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2941 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2942 enum ib_qp_type qp_type;
2943 enum ib_qp_state cur_state, new_state;
2946 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2948 if (ibqp->rwq_ind_tbl)
2951 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2952 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2954 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2955 IB_QPT_GSI : ibqp->qp_type;
2957 mutex_lock(&qp->mutex);
2959 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2960 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2962 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2963 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2964 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2967 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
2968 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
2969 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
2973 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
2974 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2975 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2976 cur_state, new_state, ibqp->qp_type, attr_mask);
2980 if ((attr_mask & IB_QP_PORT) &&
2981 (attr->port_num == 0 ||
2982 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2983 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2984 attr->port_num, dev->num_ports);
2988 if (attr_mask & IB_QP_PKEY_INDEX) {
2989 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2990 if (attr->pkey_index >=
2991 dev->mdev->port_caps[port - 1].pkey_table_len) {
2992 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2998 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2999 attr->max_rd_atomic >
3000 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3001 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3002 attr->max_rd_atomic);
3006 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3007 attr->max_dest_rd_atomic >
3008 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3009 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3010 attr->max_dest_rd_atomic);
3014 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3019 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
3022 mutex_unlock(&qp->mutex);
3026 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3028 struct mlx5_ib_cq *cq;
3031 cur = wq->head - wq->tail;
3032 if (likely(cur + nreq < wq->max_post))
3036 spin_lock(&cq->lock);
3037 cur = wq->head - wq->tail;
3038 spin_unlock(&cq->lock);
3040 return cur + nreq >= wq->max_post;
3043 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3044 u64 remote_addr, u32 rkey)
3046 rseg->raddr = cpu_to_be64(remote_addr);
3047 rseg->rkey = cpu_to_be32(rkey);
3051 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3052 struct ib_send_wr *wr, void *qend,
3053 struct mlx5_ib_qp *qp, int *size)
3057 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3059 if (wr->send_flags & IB_SEND_IP_CSUM)
3060 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3061 MLX5_ETH_WQE_L4_CSUM;
3063 seg += sizeof(struct mlx5_wqe_eth_seg);
3064 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3066 if (wr->opcode == IB_WR_LSO) {
3067 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3068 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3069 u64 left, leftlen, copysz;
3070 void *pdata = ud_wr->header;
3073 eseg->mss = cpu_to_be16(ud_wr->mss);
3074 eseg->inline_hdr.sz = cpu_to_be16(left);
3077 * check if there is space till the end of queue, if yes,
3078 * copy all in one shot, otherwise copy till the end of queue,
3079 * rollback and than the copy the left
3081 leftlen = qend - (void *)eseg->inline_hdr.start;
3082 copysz = min_t(u64, leftlen, left);
3084 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3086 if (likely(copysz > size_of_inl_hdr_start)) {
3087 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3088 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3091 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3092 seg = mlx5_get_send_wqe(qp, 0);
3095 memcpy(seg, pdata, left);
3096 seg += ALIGN(left, 16);
3097 *size += ALIGN(left, 16) / 16;
3104 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3105 struct ib_send_wr *wr)
3107 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3108 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3109 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3112 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3114 dseg->byte_count = cpu_to_be32(sg->length);
3115 dseg->lkey = cpu_to_be32(sg->lkey);
3116 dseg->addr = cpu_to_be64(sg->addr);
3119 static u64 get_xlt_octo(u64 bytes)
3121 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3122 MLX5_IB_UMR_OCTOWORD;
3125 static __be64 frwr_mkey_mask(void)
3129 result = MLX5_MKEY_MASK_LEN |
3130 MLX5_MKEY_MASK_PAGE_SIZE |
3131 MLX5_MKEY_MASK_START_ADDR |
3132 MLX5_MKEY_MASK_EN_RINVAL |
3133 MLX5_MKEY_MASK_KEY |
3139 MLX5_MKEY_MASK_SMALL_FENCE |
3140 MLX5_MKEY_MASK_FREE;
3142 return cpu_to_be64(result);
3145 static __be64 sig_mkey_mask(void)
3149 result = MLX5_MKEY_MASK_LEN |
3150 MLX5_MKEY_MASK_PAGE_SIZE |
3151 MLX5_MKEY_MASK_START_ADDR |
3152 MLX5_MKEY_MASK_EN_SIGERR |
3153 MLX5_MKEY_MASK_EN_RINVAL |
3154 MLX5_MKEY_MASK_KEY |
3159 MLX5_MKEY_MASK_SMALL_FENCE |
3160 MLX5_MKEY_MASK_FREE |
3161 MLX5_MKEY_MASK_BSF_EN;
3163 return cpu_to_be64(result);
3166 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3167 struct mlx5_ib_mr *mr)
3169 int size = mr->ndescs * mr->desc_size;
3171 memset(umr, 0, sizeof(*umr));
3173 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3174 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3175 umr->mkey_mask = frwr_mkey_mask();
3178 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3180 memset(umr, 0, sizeof(*umr));
3181 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3182 umr->flags = MLX5_UMR_INLINE;
3185 static __be64 get_umr_enable_mr_mask(void)
3189 result = MLX5_MKEY_MASK_KEY |
3190 MLX5_MKEY_MASK_FREE;
3192 return cpu_to_be64(result);
3195 static __be64 get_umr_disable_mr_mask(void)
3199 result = MLX5_MKEY_MASK_FREE;
3201 return cpu_to_be64(result);
3204 static __be64 get_umr_update_translation_mask(void)
3208 result = MLX5_MKEY_MASK_LEN |
3209 MLX5_MKEY_MASK_PAGE_SIZE |
3210 MLX5_MKEY_MASK_START_ADDR;
3212 return cpu_to_be64(result);
3215 static __be64 get_umr_update_access_mask(int atomic)
3219 result = MLX5_MKEY_MASK_LR |
3225 result |= MLX5_MKEY_MASK_A;
3227 return cpu_to_be64(result);
3230 static __be64 get_umr_update_pd_mask(void)
3234 result = MLX5_MKEY_MASK_PD;
3236 return cpu_to_be64(result);
3239 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3240 struct ib_send_wr *wr, int atomic)
3242 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3244 memset(umr, 0, sizeof(*umr));
3246 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3247 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3249 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3251 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3252 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3253 u64 offset = get_xlt_octo(umrwr->offset);
3255 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3256 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3257 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3259 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3260 umr->mkey_mask |= get_umr_update_translation_mask();
3261 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3262 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3263 umr->mkey_mask |= get_umr_update_pd_mask();
3265 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3266 umr->mkey_mask |= get_umr_enable_mr_mask();
3267 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3268 umr->mkey_mask |= get_umr_disable_mr_mask();
3271 umr->flags |= MLX5_UMR_INLINE;
3274 static u8 get_umr_flags(int acc)
3276 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3277 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3278 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3279 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
3280 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3283 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3284 struct mlx5_ib_mr *mr,
3285 u32 key, int access)
3287 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3289 memset(seg, 0, sizeof(*seg));
3291 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3292 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3293 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3294 /* KLMs take twice the size of MTTs */
3297 seg->flags = get_umr_flags(access) | mr->access_mode;
3298 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3299 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3300 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3301 seg->len = cpu_to_be64(mr->ibmr.length);
3302 seg->xlt_oct_size = cpu_to_be32(ndescs);
3305 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3307 memset(seg, 0, sizeof(*seg));
3308 seg->status = MLX5_MKEY_STATUS_FREE;
3311 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3313 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3315 memset(seg, 0, sizeof(*seg));
3316 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3317 seg->status = MLX5_MKEY_STATUS_FREE;
3319 seg->flags = convert_access(umrwr->access_flags);
3321 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3322 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3324 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3326 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3327 seg->len = cpu_to_be64(umrwr->length);
3328 seg->log2_page_size = umrwr->page_shift;
3329 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3330 mlx5_mkey_variant(umrwr->mkey));
3333 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3334 struct mlx5_ib_mr *mr,
3335 struct mlx5_ib_pd *pd)
3337 int bcount = mr->desc_size * mr->ndescs;
3339 dseg->addr = cpu_to_be64(mr->desc_map);
3340 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3341 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3344 static __be32 send_ieth(struct ib_send_wr *wr)
3346 switch (wr->opcode) {
3347 case IB_WR_SEND_WITH_IMM:
3348 case IB_WR_RDMA_WRITE_WITH_IMM:
3349 return wr->ex.imm_data;
3351 case IB_WR_SEND_WITH_INV:
3352 return cpu_to_be32(wr->ex.invalidate_rkey);
3359 static u8 calc_sig(void *wqe, int size)
3365 for (i = 0; i < size; i++)
3371 static u8 wq_sig(void *wqe)
3373 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3376 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3379 struct mlx5_wqe_inline_seg *seg;
3380 void *qend = qp->sq.qend;
3388 wqe += sizeof(*seg);
3389 for (i = 0; i < wr->num_sge; i++) {
3390 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3391 len = wr->sg_list[i].length;
3394 if (unlikely(inl > qp->max_inline_data))
3397 if (unlikely(wqe + len > qend)) {
3399 memcpy(wqe, addr, copy);
3402 wqe = mlx5_get_send_wqe(qp, 0);
3404 memcpy(wqe, addr, len);
3408 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3410 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3415 static u16 prot_field_size(enum ib_signature_type type)
3418 case IB_SIG_TYPE_T10_DIF:
3419 return MLX5_DIF_SIZE;
3425 static u8 bs_selector(int block_size)
3427 switch (block_size) {
3428 case 512: return 0x1;
3429 case 520: return 0x2;
3430 case 4096: return 0x3;
3431 case 4160: return 0x4;
3432 case 1073741824: return 0x5;
3437 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3438 struct mlx5_bsf_inl *inl)
3440 /* Valid inline section and allow BSF refresh */
3441 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3442 MLX5_BSF_REFRESH_DIF);
3443 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3444 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3445 /* repeating block */
3446 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3447 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3448 MLX5_DIF_CRC : MLX5_DIF_IPCS;
3450 if (domain->sig.dif.ref_remap)
3451 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3453 if (domain->sig.dif.app_escape) {
3454 if (domain->sig.dif.ref_escape)
3455 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3457 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3460 inl->dif_app_bitmask_check =
3461 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3464 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3465 struct ib_sig_attrs *sig_attrs,
3466 struct mlx5_bsf *bsf, u32 data_size)
3468 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3469 struct mlx5_bsf_basic *basic = &bsf->basic;
3470 struct ib_sig_domain *mem = &sig_attrs->mem;
3471 struct ib_sig_domain *wire = &sig_attrs->wire;
3473 memset(bsf, 0, sizeof(*bsf));
3475 /* Basic + Extended + Inline */
3476 basic->bsf_size_sbs = 1 << 7;
3477 /* Input domain check byte mask */
3478 basic->check_byte_mask = sig_attrs->check_mask;
3479 basic->raw_data_size = cpu_to_be32(data_size);
3482 switch (sig_attrs->mem.sig_type) {
3483 case IB_SIG_TYPE_NONE:
3485 case IB_SIG_TYPE_T10_DIF:
3486 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3487 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3488 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3495 switch (sig_attrs->wire.sig_type) {
3496 case IB_SIG_TYPE_NONE:
3498 case IB_SIG_TYPE_T10_DIF:
3499 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3500 mem->sig_type == wire->sig_type) {
3501 /* Same block structure */
3502 basic->bsf_size_sbs |= 1 << 4;
3503 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3504 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3505 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3506 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3507 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3508 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3510 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3512 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3513 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3522 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3523 struct mlx5_ib_qp *qp, void **seg, int *size)
3525 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3526 struct ib_mr *sig_mr = wr->sig_mr;
3527 struct mlx5_bsf *bsf;
3528 u32 data_len = wr->wr.sg_list->length;
3529 u32 data_key = wr->wr.sg_list->lkey;
3530 u64 data_va = wr->wr.sg_list->addr;
3535 (data_key == wr->prot->lkey &&
3536 data_va == wr->prot->addr &&
3537 data_len == wr->prot->length)) {
3539 * Source domain doesn't contain signature information
3540 * or data and protection are interleaved in memory.
3541 * So need construct:
3542 * ------------------
3544 * ------------------
3546 * ------------------
3548 struct mlx5_klm *data_klm = *seg;
3550 data_klm->bcount = cpu_to_be32(data_len);
3551 data_klm->key = cpu_to_be32(data_key);
3552 data_klm->va = cpu_to_be64(data_va);
3553 wqe_size = ALIGN(sizeof(*data_klm), 64);
3556 * Source domain contains signature information
3557 * So need construct a strided block format:
3558 * ---------------------------
3559 * | stride_block_ctrl |
3560 * ---------------------------
3562 * ---------------------------
3564 * ---------------------------
3566 * ---------------------------
3568 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3569 struct mlx5_stride_block_entry *data_sentry;
3570 struct mlx5_stride_block_entry *prot_sentry;
3571 u32 prot_key = wr->prot->lkey;
3572 u64 prot_va = wr->prot->addr;
3573 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3577 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3578 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3580 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3582 pr_err("Bad block size given: %u\n", block_size);
3585 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3587 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3588 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3589 sblock_ctrl->num_entries = cpu_to_be16(2);
3591 data_sentry->bcount = cpu_to_be16(block_size);
3592 data_sentry->key = cpu_to_be32(data_key);
3593 data_sentry->va = cpu_to_be64(data_va);
3594 data_sentry->stride = cpu_to_be16(block_size);
3596 prot_sentry->bcount = cpu_to_be16(prot_size);
3597 prot_sentry->key = cpu_to_be32(prot_key);
3598 prot_sentry->va = cpu_to_be64(prot_va);
3599 prot_sentry->stride = cpu_to_be16(prot_size);
3601 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3602 sizeof(*prot_sentry), 64);
3606 *size += wqe_size / 16;
3607 if (unlikely((*seg == qp->sq.qend)))
3608 *seg = mlx5_get_send_wqe(qp, 0);
3611 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3615 *seg += sizeof(*bsf);
3616 *size += sizeof(*bsf) / 16;
3617 if (unlikely((*seg == qp->sq.qend)))
3618 *seg = mlx5_get_send_wqe(qp, 0);
3623 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3624 struct ib_sig_handover_wr *wr, u32 size,
3625 u32 length, u32 pdn)
3627 struct ib_mr *sig_mr = wr->sig_mr;
3628 u32 sig_key = sig_mr->rkey;
3629 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3631 memset(seg, 0, sizeof(*seg));
3633 seg->flags = get_umr_flags(wr->access_flags) |
3634 MLX5_MKC_ACCESS_MODE_KLMS;
3635 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3636 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3637 MLX5_MKEY_BSF_EN | pdn);
3638 seg->len = cpu_to_be64(length);
3639 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
3640 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3643 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3646 memset(umr, 0, sizeof(*umr));
3648 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3649 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3650 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3651 umr->mkey_mask = sig_mkey_mask();
3655 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3656 void **seg, int *size)
3658 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3659 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3660 u32 pdn = get_pd(qp)->pdn;
3662 int region_len, ret;
3664 if (unlikely(wr->wr.num_sge != 1) ||
3665 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3666 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3667 unlikely(!sig_mr->sig->sig_status_checked))
3670 /* length of the protected region, data + protection */
3671 region_len = wr->wr.sg_list->length;
3673 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3674 wr->prot->addr != wr->wr.sg_list->addr ||
3675 wr->prot->length != wr->wr.sg_list->length))
3676 region_len += wr->prot->length;
3679 * KLM octoword size - if protection was provided
3680 * then we use strided block format (3 octowords),
3681 * else we use single KLM (1 octoword)
3683 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
3685 set_sig_umr_segment(*seg, xlt_size);
3686 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3687 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3688 if (unlikely((*seg == qp->sq.qend)))
3689 *seg = mlx5_get_send_wqe(qp, 0);
3691 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
3692 *seg += sizeof(struct mlx5_mkey_seg);
3693 *size += sizeof(struct mlx5_mkey_seg) / 16;
3694 if (unlikely((*seg == qp->sq.qend)))
3695 *seg = mlx5_get_send_wqe(qp, 0);
3697 ret = set_sig_data_segment(wr, qp, seg, size);
3701 sig_mr->sig->sig_status_checked = false;
3705 static int set_psv_wr(struct ib_sig_domain *domain,
3706 u32 psv_idx, void **seg, int *size)
3708 struct mlx5_seg_set_psv *psv_seg = *seg;
3710 memset(psv_seg, 0, sizeof(*psv_seg));
3711 psv_seg->psv_num = cpu_to_be32(psv_idx);
3712 switch (domain->sig_type) {
3713 case IB_SIG_TYPE_NONE:
3715 case IB_SIG_TYPE_T10_DIF:
3716 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3717 domain->sig.dif.app_tag);
3718 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3721 pr_err("Bad signature type (%d) is given.\n",
3726 *seg += sizeof(*psv_seg);
3727 *size += sizeof(*psv_seg) / 16;
3732 static int set_reg_wr(struct mlx5_ib_qp *qp,
3733 struct ib_reg_wr *wr,
3734 void **seg, int *size)
3736 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3737 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3739 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3740 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3741 "Invalid IB_SEND_INLINE send flag\n");
3745 set_reg_umr_seg(*seg, mr);
3746 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3747 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3748 if (unlikely((*seg == qp->sq.qend)))
3749 *seg = mlx5_get_send_wqe(qp, 0);
3751 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3752 *seg += sizeof(struct mlx5_mkey_seg);
3753 *size += sizeof(struct mlx5_mkey_seg) / 16;
3754 if (unlikely((*seg == qp->sq.qend)))
3755 *seg = mlx5_get_send_wqe(qp, 0);
3757 set_reg_data_seg(*seg, mr, pd);
3758 *seg += sizeof(struct mlx5_wqe_data_seg);
3759 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3764 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3766 set_linv_umr_seg(*seg);
3767 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3768 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3769 if (unlikely((*seg == qp->sq.qend)))
3770 *seg = mlx5_get_send_wqe(qp, 0);
3771 set_linv_mkey_seg(*seg);
3772 *seg += sizeof(struct mlx5_mkey_seg);
3773 *size += sizeof(struct mlx5_mkey_seg) / 16;
3774 if (unlikely((*seg == qp->sq.qend)))
3775 *seg = mlx5_get_send_wqe(qp, 0);
3778 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3784 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3785 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3786 if ((i & 0xf) == 0) {
3787 void *buf = mlx5_get_send_wqe(qp, tidx);
3788 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3792 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3793 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3794 be32_to_cpu(p[j + 3]));
3798 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3799 struct mlx5_wqe_ctrl_seg **ctrl,
3800 struct ib_send_wr *wr, unsigned *idx,
3801 int *size, int nreq)
3803 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3806 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3807 *seg = mlx5_get_send_wqe(qp, *idx);
3809 *(uint32_t *)(*seg + 8) = 0;
3810 (*ctrl)->imm = send_ieth(wr);
3811 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3812 (wr->send_flags & IB_SEND_SIGNALED ?
3813 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3814 (wr->send_flags & IB_SEND_SOLICITED ?
3815 MLX5_WQE_CTRL_SOLICITED : 0);
3817 *seg += sizeof(**ctrl);
3818 *size = sizeof(**ctrl) / 16;
3823 static void finish_wqe(struct mlx5_ib_qp *qp,
3824 struct mlx5_wqe_ctrl_seg *ctrl,
3825 u8 size, unsigned idx, u64 wr_id,
3826 int nreq, u8 fence, u32 mlx5_opcode)
3830 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3831 mlx5_opcode | ((u32)opmod << 24));
3832 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3833 ctrl->fm_ce_se |= fence;
3834 if (unlikely(qp->wq_sig))
3835 ctrl->signature = wq_sig(ctrl);
3837 qp->sq.wrid[idx] = wr_id;
3838 qp->sq.w_list[idx].opcode = mlx5_opcode;
3839 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3840 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3841 qp->sq.w_list[idx].next = qp->sq.cur_post;
3845 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3846 struct ib_send_wr **bad_wr)
3848 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3849 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3850 struct mlx5_core_dev *mdev = dev->mdev;
3851 struct mlx5_ib_qp *qp;
3852 struct mlx5_ib_mr *mr;
3853 struct mlx5_wqe_data_seg *dpseg;
3854 struct mlx5_wqe_xrc_seg *xrc;
3856 int uninitialized_var(size);
3858 unsigned long flags;
3869 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3870 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3876 spin_lock_irqsave(&qp->sq.lock, flags);
3878 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3885 for (nreq = 0; wr; nreq++, wr = wr->next) {
3886 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3887 mlx5_ib_warn(dev, "\n");
3893 num_sge = wr->num_sge;
3894 if (unlikely(num_sge > qp->sq.max_gs)) {
3895 mlx5_ib_warn(dev, "\n");
3901 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3903 mlx5_ib_warn(dev, "\n");
3909 if (wr->opcode == IB_WR_LOCAL_INV ||
3910 wr->opcode == IB_WR_REG_MR) {
3911 fence = dev->umr_fence;
3912 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3913 } else if (wr->send_flags & IB_SEND_FENCE) {
3915 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
3917 fence = MLX5_FENCE_MODE_FENCE;
3919 fence = qp->next_fence;
3922 switch (ibqp->qp_type) {
3923 case IB_QPT_XRC_INI:
3925 seg += sizeof(*xrc);
3926 size += sizeof(*xrc) / 16;
3929 switch (wr->opcode) {
3930 case IB_WR_RDMA_READ:
3931 case IB_WR_RDMA_WRITE:
3932 case IB_WR_RDMA_WRITE_WITH_IMM:
3933 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3935 seg += sizeof(struct mlx5_wqe_raddr_seg);
3936 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3939 case IB_WR_ATOMIC_CMP_AND_SWP:
3940 case IB_WR_ATOMIC_FETCH_AND_ADD:
3941 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3942 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3947 case IB_WR_LOCAL_INV:
3948 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3949 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3950 set_linv_wr(qp, &seg, &size);
3955 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3956 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3957 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3965 case IB_WR_REG_SIG_MR:
3966 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3967 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3969 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3970 err = set_sig_umr_wr(wr, qp, &seg, &size);
3972 mlx5_ib_warn(dev, "\n");
3977 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3978 fence, MLX5_OPCODE_UMR);
3980 * SET_PSV WQEs are not signaled and solicited
3983 wr->send_flags &= ~IB_SEND_SIGNALED;
3984 wr->send_flags |= IB_SEND_SOLICITED;
3985 err = begin_wqe(qp, &seg, &ctrl, wr,
3988 mlx5_ib_warn(dev, "\n");
3994 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
3995 mr->sig->psv_memory.psv_idx, &seg,
3998 mlx5_ib_warn(dev, "\n");
4003 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4004 fence, MLX5_OPCODE_SET_PSV);
4005 err = begin_wqe(qp, &seg, &ctrl, wr,
4008 mlx5_ib_warn(dev, "\n");
4014 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4015 mr->sig->psv_wire.psv_idx, &seg,
4018 mlx5_ib_warn(dev, "\n");
4023 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4024 fence, MLX5_OPCODE_SET_PSV);
4025 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4035 switch (wr->opcode) {
4036 case IB_WR_RDMA_WRITE:
4037 case IB_WR_RDMA_WRITE_WITH_IMM:
4038 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4040 seg += sizeof(struct mlx5_wqe_raddr_seg);
4041 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4050 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4051 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4056 case MLX5_IB_QPT_HW_GSI:
4057 set_datagram_seg(seg, wr);
4058 seg += sizeof(struct mlx5_wqe_datagram_seg);
4059 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4060 if (unlikely((seg == qend)))
4061 seg = mlx5_get_send_wqe(qp, 0);
4064 set_datagram_seg(seg, wr);
4065 seg += sizeof(struct mlx5_wqe_datagram_seg);
4066 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4068 if (unlikely((seg == qend)))
4069 seg = mlx5_get_send_wqe(qp, 0);
4071 /* handle qp that supports ud offload */
4072 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4073 struct mlx5_wqe_eth_pad *pad;
4076 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4077 seg += sizeof(struct mlx5_wqe_eth_pad);
4078 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4080 seg = set_eth_seg(seg, wr, qend, qp, &size);
4082 if (unlikely((seg == qend)))
4083 seg = mlx5_get_send_wqe(qp, 0);
4086 case MLX5_IB_QPT_REG_UMR:
4087 if (wr->opcode != MLX5_IB_WR_UMR) {
4089 mlx5_ib_warn(dev, "bad opcode\n");
4092 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4093 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4094 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4095 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4096 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4097 if (unlikely((seg == qend)))
4098 seg = mlx5_get_send_wqe(qp, 0);
4099 set_reg_mkey_segment(seg, wr);
4100 seg += sizeof(struct mlx5_mkey_seg);
4101 size += sizeof(struct mlx5_mkey_seg) / 16;
4102 if (unlikely((seg == qend)))
4103 seg = mlx5_get_send_wqe(qp, 0);
4110 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4111 int uninitialized_var(sz);
4113 err = set_data_inl_seg(qp, wr, seg, &sz);
4114 if (unlikely(err)) {
4115 mlx5_ib_warn(dev, "\n");
4123 for (i = 0; i < num_sge; i++) {
4124 if (unlikely(dpseg == qend)) {
4125 seg = mlx5_get_send_wqe(qp, 0);
4128 if (likely(wr->sg_list[i].length)) {
4129 set_data_ptr_seg(dpseg, wr->sg_list + i);
4130 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4136 qp->next_fence = next_fence;
4137 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4138 mlx5_ib_opcode[wr->opcode]);
4141 dump_wqe(qp, idx, size);
4146 qp->sq.head += nreq;
4148 /* Make sure that descriptors are written before
4149 * updating doorbell record and ringing the doorbell
4153 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4155 /* Make sure doorbell record is visible to the HCA before
4156 * we hit doorbell */
4159 /* currently we support only regular doorbells */
4160 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4161 /* Make sure doorbells don't leak out of SQ spinlock
4162 * and reach the HCA out of order.
4165 bf->offset ^= bf->buf_size;
4168 spin_unlock_irqrestore(&qp->sq.lock, flags);
4173 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4175 sig->signature = calc_sig(sig, size);
4178 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4179 struct ib_recv_wr **bad_wr)
4181 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4182 struct mlx5_wqe_data_seg *scat;
4183 struct mlx5_rwqe_sig *sig;
4184 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4185 struct mlx5_core_dev *mdev = dev->mdev;
4186 unsigned long flags;
4192 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4193 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4195 spin_lock_irqsave(&qp->rq.lock, flags);
4197 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4204 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4206 for (nreq = 0; wr; nreq++, wr = wr->next) {
4207 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4213 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4219 scat = get_recv_wqe(qp, ind);
4223 for (i = 0; i < wr->num_sge; i++)
4224 set_data_ptr_seg(scat + i, wr->sg_list + i);
4226 if (i < qp->rq.max_gs) {
4227 scat[i].byte_count = 0;
4228 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4233 sig = (struct mlx5_rwqe_sig *)scat;
4234 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4237 qp->rq.wrid[ind] = wr->wr_id;
4239 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4244 qp->rq.head += nreq;
4246 /* Make sure that descriptors are written before
4251 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4254 spin_unlock_irqrestore(&qp->rq.lock, flags);
4259 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4261 switch (mlx5_state) {
4262 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4263 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4264 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4265 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4266 case MLX5_QP_STATE_SQ_DRAINING:
4267 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4268 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4269 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4274 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4276 switch (mlx5_mig_state) {
4277 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4278 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4279 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4284 static int to_ib_qp_access_flags(int mlx5_flags)
4288 if (mlx5_flags & MLX5_QP_BIT_RRE)
4289 ib_flags |= IB_ACCESS_REMOTE_READ;
4290 if (mlx5_flags & MLX5_QP_BIT_RWE)
4291 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4292 if (mlx5_flags & MLX5_QP_BIT_RAE)
4293 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4298 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4299 struct rdma_ah_attr *ah_attr,
4300 struct mlx5_qp_path *path)
4302 struct mlx5_core_dev *dev = ibdev->mdev;
4304 memset(ah_attr, 0, sizeof(*ah_attr));
4306 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4307 rdma_ah_set_port_num(ah_attr, path->port);
4308 if (rdma_ah_get_port_num(ah_attr) == 0 ||
4309 rdma_ah_get_port_num(ah_attr) > MLX5_CAP_GEN(dev, num_ports))
4312 rdma_ah_set_port_num(ah_attr, path->port);
4313 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4315 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4316 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4317 rdma_ah_set_static_rate(ah_attr,
4318 path->static_rate ? path->static_rate - 5 : 0);
4319 if (path->grh_mlid & (1 << 7)) {
4320 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4322 rdma_ah_set_grh(ah_attr, NULL,
4326 (tc_fl >> 20) & 0xff);
4327 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4331 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4332 struct mlx5_ib_sq *sq,
4340 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4341 out = kvzalloc(inlen, GFP_KERNEL);
4345 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4349 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4350 *sq_state = MLX5_GET(sqc, sqc, state);
4351 sq->state = *sq_state;
4358 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4359 struct mlx5_ib_rq *rq,
4367 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4368 out = kvzalloc(inlen, GFP_KERNEL);
4372 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4376 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4377 *rq_state = MLX5_GET(rqc, rqc, state);
4378 rq->state = *rq_state;
4385 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4386 struct mlx5_ib_qp *qp, u8 *qp_state)
4388 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4389 [MLX5_RQC_STATE_RST] = {
4390 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4391 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4392 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4393 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4395 [MLX5_RQC_STATE_RDY] = {
4396 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4397 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4398 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4399 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4401 [MLX5_RQC_STATE_ERR] = {
4402 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4403 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4404 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4405 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4407 [MLX5_RQ_STATE_NA] = {
4408 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4409 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4410 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4411 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4415 *qp_state = sqrq_trans[rq_state][sq_state];
4417 if (*qp_state == MLX5_QP_STATE_BAD) {
4418 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4419 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4420 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4424 if (*qp_state == MLX5_QP_STATE)
4425 *qp_state = qp->state;
4430 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4431 struct mlx5_ib_qp *qp,
4432 u8 *raw_packet_qp_state)
4434 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4435 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4436 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4438 u8 sq_state = MLX5_SQ_STATE_NA;
4439 u8 rq_state = MLX5_RQ_STATE_NA;
4441 if (qp->sq.wqe_cnt) {
4442 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4447 if (qp->rq.wqe_cnt) {
4448 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4453 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4454 raw_packet_qp_state);
4457 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4458 struct ib_qp_attr *qp_attr)
4460 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4461 struct mlx5_qp_context *context;
4466 outb = kzalloc(outlen, GFP_KERNEL);
4470 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4475 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4476 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4478 mlx5_state = be32_to_cpu(context->flags) >> 28;
4480 qp->state = to_ib_qp_state(mlx5_state);
4481 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4482 qp_attr->path_mig_state =
4483 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4484 qp_attr->qkey = be32_to_cpu(context->qkey);
4485 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4486 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4487 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4488 qp_attr->qp_access_flags =
4489 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4491 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4492 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4493 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4494 qp_attr->alt_pkey_index =
4495 be16_to_cpu(context->alt_path.pkey_index);
4496 qp_attr->alt_port_num =
4497 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
4500 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4501 qp_attr->port_num = context->pri_path.port;
4503 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4504 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4506 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4508 qp_attr->max_dest_rd_atomic =
4509 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4510 qp_attr->min_rnr_timer =
4511 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4512 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4513 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4514 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4515 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
4522 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4523 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4525 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4526 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4528 u8 raw_packet_qp_state;
4530 if (ibqp->rwq_ind_tbl)
4533 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4534 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4537 /* Not all of output fields are applicable, make sure to zero them */
4538 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4539 memset(qp_attr, 0, sizeof(*qp_attr));
4541 mutex_lock(&qp->mutex);
4543 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
4544 qp->flags & MLX5_IB_QP_UNDERLAY) {
4545 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4548 qp->state = raw_packet_qp_state;
4549 qp_attr->port_num = 1;
4551 err = query_qp_attr(dev, qp, qp_attr);
4556 qp_attr->qp_state = qp->state;
4557 qp_attr->cur_qp_state = qp_attr->qp_state;
4558 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4559 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4561 if (!ibqp->uobject) {
4562 qp_attr->cap.max_send_wr = qp->sq.max_post;
4563 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4564 qp_init_attr->qp_context = ibqp->qp_context;
4566 qp_attr->cap.max_send_wr = 0;
4567 qp_attr->cap.max_send_sge = 0;
4570 qp_init_attr->qp_type = ibqp->qp_type;
4571 qp_init_attr->recv_cq = ibqp->recv_cq;
4572 qp_init_attr->send_cq = ibqp->send_cq;
4573 qp_init_attr->srq = ibqp->srq;
4574 qp_attr->cap.max_inline_data = qp->max_inline_data;
4576 qp_init_attr->cap = qp_attr->cap;
4578 qp_init_attr->create_flags = 0;
4579 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4580 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4582 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4583 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4584 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4585 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4586 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4587 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4588 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4589 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4591 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4592 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4595 mutex_unlock(&qp->mutex);
4599 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4600 struct ib_ucontext *context,
4601 struct ib_udata *udata)
4603 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4604 struct mlx5_ib_xrcd *xrcd;
4607 if (!MLX5_CAP_GEN(dev->mdev, xrc))
4608 return ERR_PTR(-ENOSYS);
4610 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4612 return ERR_PTR(-ENOMEM);
4614 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4617 return ERR_PTR(-ENOMEM);
4620 return &xrcd->ibxrcd;
4623 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4625 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4626 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4629 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4631 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4640 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4642 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4643 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4644 struct ib_event event;
4646 if (rwq->ibwq.event_handler) {
4647 event.device = rwq->ibwq.device;
4648 event.element.wq = &rwq->ibwq;
4650 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4651 event.event = IB_EVENT_WQ_FATAL;
4654 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4658 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4662 static int set_delay_drop(struct mlx5_ib_dev *dev)
4666 mutex_lock(&dev->delay_drop.lock);
4667 if (dev->delay_drop.activate)
4670 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
4674 dev->delay_drop.activate = true;
4676 mutex_unlock(&dev->delay_drop.lock);
4679 atomic_inc(&dev->delay_drop.rqs_cnt);
4683 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4684 struct ib_wq_init_attr *init_attr)
4686 struct mlx5_ib_dev *dev;
4687 int has_net_offloads;
4695 dev = to_mdev(pd->device);
4697 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4698 in = kvzalloc(inlen, GFP_KERNEL);
4702 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4703 MLX5_SET(rqc, rqc, mem_rq_type,
4704 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4705 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4706 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4707 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4708 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4709 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4710 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4711 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4712 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4713 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4714 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4715 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4716 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4717 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4718 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4719 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
4720 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4721 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4722 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4727 MLX5_SET(rqc, rqc, vsd, 1);
4729 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4730 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4731 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4735 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4737 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4738 if (!(dev->ib_dev.attrs.raw_packet_caps &
4739 IB_RAW_PACKET_CAP_DELAY_DROP)) {
4740 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
4744 MLX5_SET(rqc, rqc, delay_drop_en, 1);
4746 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4747 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4748 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
4749 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4750 err = set_delay_drop(dev);
4752 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
4754 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4756 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
4764 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4765 struct ib_wq_init_attr *wq_init_attr,
4766 struct mlx5_ib_create_wq *ucmd,
4767 struct mlx5_ib_rwq *rwq)
4769 /* Sanity check RQ size before proceeding */
4770 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4773 if (!ucmd->rq_wqe_count)
4776 rwq->wqe_count = ucmd->rq_wqe_count;
4777 rwq->wqe_shift = ucmd->rq_wqe_shift;
4778 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4779 rwq->log_rq_stride = rwq->wqe_shift;
4780 rwq->log_rq_size = ilog2(rwq->wqe_count);
4784 static int prepare_user_rq(struct ib_pd *pd,
4785 struct ib_wq_init_attr *init_attr,
4786 struct ib_udata *udata,
4787 struct mlx5_ib_rwq *rwq)
4789 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4790 struct mlx5_ib_create_wq ucmd = {};
4792 size_t required_cmd_sz;
4794 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4795 if (udata->inlen < required_cmd_sz) {
4796 mlx5_ib_dbg(dev, "invalid inlen\n");
4800 if (udata->inlen > sizeof(ucmd) &&
4801 !ib_is_udata_cleared(udata, sizeof(ucmd),
4802 udata->inlen - sizeof(ucmd))) {
4803 mlx5_ib_dbg(dev, "inlen is not supported\n");
4807 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4808 mlx5_ib_dbg(dev, "copy failed\n");
4812 if (ucmd.comp_mask) {
4813 mlx5_ib_dbg(dev, "invalid comp mask\n");
4817 if (ucmd.reserved) {
4818 mlx5_ib_dbg(dev, "invalid reserved\n");
4822 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4824 mlx5_ib_dbg(dev, "err %d\n", err);
4828 err = create_user_rq(dev, pd, rwq, &ucmd);
4830 mlx5_ib_dbg(dev, "err %d\n", err);
4835 rwq->user_index = ucmd.user_index;
4839 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4840 struct ib_wq_init_attr *init_attr,
4841 struct ib_udata *udata)
4843 struct mlx5_ib_dev *dev;
4844 struct mlx5_ib_rwq *rwq;
4845 struct mlx5_ib_create_wq_resp resp = {};
4846 size_t min_resp_len;
4850 return ERR_PTR(-ENOSYS);
4852 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4853 if (udata->outlen && udata->outlen < min_resp_len)
4854 return ERR_PTR(-EINVAL);
4856 dev = to_mdev(pd->device);
4857 switch (init_attr->wq_type) {
4859 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4861 return ERR_PTR(-ENOMEM);
4862 err = prepare_user_rq(pd, init_attr, udata, rwq);
4865 err = create_rq(rwq, pd, init_attr);
4870 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4871 init_attr->wq_type);
4872 return ERR_PTR(-EINVAL);
4875 rwq->ibwq.wq_num = rwq->core_qp.qpn;
4876 rwq->ibwq.state = IB_WQS_RESET;
4877 if (udata->outlen) {
4878 resp.response_length = offsetof(typeof(resp), response_length) +
4879 sizeof(resp.response_length);
4880 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4885 rwq->core_qp.event = mlx5_ib_wq_event;
4886 rwq->ibwq.event_handler = init_attr->event_handler;
4890 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4892 destroy_user_rq(dev, pd, rwq);
4895 return ERR_PTR(err);
4898 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4900 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4901 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4903 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4904 destroy_user_rq(dev, wq->pd, rwq);
4910 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4911 struct ib_rwq_ind_table_init_attr *init_attr,
4912 struct ib_udata *udata)
4914 struct mlx5_ib_dev *dev = to_mdev(device);
4915 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4916 int sz = 1 << init_attr->log_ind_tbl_size;
4917 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4918 size_t min_resp_len;
4925 if (udata->inlen > 0 &&
4926 !ib_is_udata_cleared(udata, 0,
4928 return ERR_PTR(-EOPNOTSUPP);
4930 if (init_attr->log_ind_tbl_size >
4931 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4932 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4933 init_attr->log_ind_tbl_size,
4934 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4935 return ERR_PTR(-EINVAL);
4938 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4939 if (udata->outlen && udata->outlen < min_resp_len)
4940 return ERR_PTR(-EINVAL);
4942 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4944 return ERR_PTR(-ENOMEM);
4946 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4947 in = kvzalloc(inlen, GFP_KERNEL);
4953 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4955 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4956 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4958 for (i = 0; i < sz; i++)
4959 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4961 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4967 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4968 if (udata->outlen) {
4969 resp.response_length = offsetof(typeof(resp), response_length) +
4970 sizeof(resp.response_length);
4971 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4976 return &rwq_ind_tbl->ib_rwq_ind_tbl;
4979 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4982 return ERR_PTR(err);
4985 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4987 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4988 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4990 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4996 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4997 u32 wq_attr_mask, struct ib_udata *udata)
4999 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5000 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5001 struct mlx5_ib_modify_wq ucmd = {};
5002 size_t required_cmd_sz;
5010 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5011 if (udata->inlen < required_cmd_sz)
5014 if (udata->inlen > sizeof(ucmd) &&
5015 !ib_is_udata_cleared(udata, sizeof(ucmd),
5016 udata->inlen - sizeof(ucmd)))
5019 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5022 if (ucmd.comp_mask || ucmd.reserved)
5025 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5026 in = kvzalloc(inlen, GFP_KERNEL);
5030 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5032 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5033 wq_attr->curr_wq_state : wq->state;
5034 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5035 wq_attr->wq_state : curr_wq_state;
5036 if (curr_wq_state == IB_WQS_ERR)
5037 curr_wq_state = MLX5_RQC_STATE_ERR;
5038 if (wq_state == IB_WQS_ERR)
5039 wq_state = MLX5_RQC_STATE_ERR;
5040 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5041 MLX5_SET(rqc, rqc, state, wq_state);
5043 if (wq_attr_mask & IB_WQ_FLAGS) {
5044 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5045 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5046 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5047 mlx5_ib_dbg(dev, "VLAN offloads are not "
5052 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5053 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5054 MLX5_SET(rqc, rqc, vsd,
5055 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5059 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5060 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5061 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5062 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5063 MLX5_SET(rqc, rqc, counter_set_id,
5064 dev->port->cnts.set_id);
5066 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5070 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
5072 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;