2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2020, Intel Corporation. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/kref.h>
36 #include <linux/random.h>
37 #include <linux/debugfs.h>
38 #include <linux/export.h>
39 #include <linux/delay.h>
40 #include <linux/dma-buf.h>
41 #include <linux/dma-resv.h>
42 #include <rdma/ib_umem_odp.h>
48 MAX_PENDING_REG_MR = 8,
51 #define MLX5_UMR_ALIGN 2048
54 create_mkey_callback(int status, struct mlx5_async_work *context);
55 static struct mlx5_ib_mr *reg_create(struct ib_pd *pd, struct ib_umem *umem,
56 u64 iova, int access_flags,
57 unsigned int page_size, bool populate);
59 static void set_mkc_access_pd_addr_fields(void *mkc, int acc, u64 start_addr,
62 struct mlx5_ib_dev *dev = to_mdev(pd->device);
64 MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC));
65 MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE));
66 MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ));
67 MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE));
68 MLX5_SET(mkc, mkc, lr, 1);
70 if (acc & IB_ACCESS_RELAXED_ORDERING) {
71 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write))
72 MLX5_SET(mkc, mkc, relaxed_ordering_write, 1);
74 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) ||
75 (MLX5_CAP_GEN(dev->mdev,
76 relaxed_ordering_read_pci_enabled) &&
77 pcie_relaxed_ordering_enabled(dev->mdev->pdev)))
78 MLX5_SET(mkc, mkc, relaxed_ordering_read, 1);
81 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
82 MLX5_SET(mkc, mkc, qpn, 0xffffff);
83 MLX5_SET64(mkc, mkc, start_addr, start_addr);
86 static void assign_mkey_variant(struct mlx5_ib_dev *dev, u32 *mkey, u32 *in)
88 u8 key = atomic_inc_return(&dev->mkey_var);
91 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
92 MLX5_SET(mkc, mkc, mkey_7_0, key);
96 static int mlx5_ib_create_mkey(struct mlx5_ib_dev *dev,
97 struct mlx5_ib_mkey *mkey, u32 *in, int inlen)
101 assign_mkey_variant(dev, &mkey->key, in);
102 ret = mlx5_core_create_mkey(dev->mdev, &mkey->key, in, inlen);
104 init_waitqueue_head(&mkey->wait);
109 static int mlx5_ib_create_mkey_cb(struct mlx5r_async_create_mkey *async_create)
111 struct mlx5_ib_dev *dev = async_create->ent->dev;
112 size_t inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
113 size_t outlen = MLX5_ST_SZ_BYTES(create_mkey_out);
115 MLX5_SET(create_mkey_in, async_create->in, opcode,
116 MLX5_CMD_OP_CREATE_MKEY);
117 assign_mkey_variant(dev, &async_create->mkey, async_create->in);
118 return mlx5_cmd_exec_cb(&dev->async_ctx, async_create->in, inlen,
119 async_create->out, outlen, create_mkey_callback,
120 &async_create->cb_work);
123 static int mkey_cache_max_order(struct mlx5_ib_dev *dev);
124 static void queue_adjust_cache_locked(struct mlx5_cache_ent *ent);
126 static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
128 WARN_ON(xa_load(&dev->odp_mkeys, mlx5_base_mkey(mr->mmkey.key)));
130 return mlx5_core_destroy_mkey(dev->mdev, mr->mmkey.key);
133 static void create_mkey_warn(struct mlx5_ib_dev *dev, int status, void *out)
135 if (status == -ENXIO) /* core driver is not available */
138 mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status);
139 if (status != -EREMOTEIO) /* driver specific failure */
142 /* Failed in FW, print cmd out failure details */
143 mlx5_cmd_out_err(dev->mdev, MLX5_CMD_OP_CREATE_MKEY, 0, out);
146 static int push_mkey_locked(struct mlx5_cache_ent *ent, bool limit_pendings,
149 XA_STATE(xas, &ent->mkeys, 0);
152 if (limit_pendings &&
153 (ent->reserved - ent->stored) > MAX_PENDING_REG_MR)
158 * This is cmpxchg (NULL, XA_ZERO_ENTRY) however this version
159 * doesn't transparently unlock. Instead we set the xas index to
160 * the current value of reserved every iteration.
162 xas_set(&xas, ent->reserved);
163 curr = xas_load(&xas);
165 if (to_store && ent->stored == ent->reserved)
166 xas_store(&xas, to_store);
168 xas_store(&xas, XA_ZERO_ENTRY);
169 if (xas_valid(&xas)) {
172 if (ent->stored != ent->reserved)
173 __xa_store(&ent->mkeys,
178 queue_adjust_cache_locked(ent);
179 WRITE_ONCE(ent->dev->cache.last_add,
184 xa_unlock_irq(&ent->mkeys);
187 * Notice xas_nomem() must always be called as it cleans
188 * up any cached allocation.
190 if (!xas_nomem(&xas, GFP_KERNEL))
192 xa_lock_irq(&ent->mkeys);
194 xa_lock_irq(&ent->mkeys);
196 return xas_error(&xas);
202 static int push_mkey(struct mlx5_cache_ent *ent, bool limit_pendings,
207 xa_lock_irq(&ent->mkeys);
208 ret = push_mkey_locked(ent, limit_pendings, to_store);
209 xa_unlock_irq(&ent->mkeys);
213 static void undo_push_reserve_mkey(struct mlx5_cache_ent *ent)
218 old = __xa_erase(&ent->mkeys, ent->reserved);
222 static void push_to_reserved(struct mlx5_cache_ent *ent, u32 mkey)
226 old = __xa_store(&ent->mkeys, ent->stored, xa_mk_value(mkey), 0);
231 static u32 pop_stored_mkey(struct mlx5_cache_ent *ent)
238 if (ent->stored == ent->reserved) {
239 xa_mkey = __xa_erase(&ent->mkeys, ent->stored);
241 return (u32)xa_to_value(xa_mkey);
244 xa_mkey = __xa_store(&ent->mkeys, ent->stored, XA_ZERO_ENTRY,
246 WARN_ON(!xa_mkey || xa_is_err(xa_mkey));
247 old = __xa_erase(&ent->mkeys, ent->reserved);
249 return (u32)xa_to_value(xa_mkey);
252 static void create_mkey_callback(int status, struct mlx5_async_work *context)
254 struct mlx5r_async_create_mkey *mkey_out =
255 container_of(context, struct mlx5r_async_create_mkey, cb_work);
256 struct mlx5_cache_ent *ent = mkey_out->ent;
257 struct mlx5_ib_dev *dev = ent->dev;
261 create_mkey_warn(dev, status, mkey_out->out);
263 xa_lock_irqsave(&ent->mkeys, flags);
264 undo_push_reserve_mkey(ent);
265 WRITE_ONCE(dev->fill_delay, 1);
266 xa_unlock_irqrestore(&ent->mkeys, flags);
267 mod_timer(&dev->delay_timer, jiffies + HZ);
271 mkey_out->mkey |= mlx5_idx_to_mkey(
272 MLX5_GET(create_mkey_out, mkey_out->out, mkey_index));
273 WRITE_ONCE(dev->cache.last_add, jiffies);
275 xa_lock_irqsave(&ent->mkeys, flags);
276 push_to_reserved(ent, mkey_out->mkey);
277 /* If we are doing fill_to_high_water then keep going. */
278 queue_adjust_cache_locked(ent);
279 xa_unlock_irqrestore(&ent->mkeys, flags);
283 static int get_mkc_octo_size(unsigned int access_mode, unsigned int ndescs)
287 switch (access_mode) {
288 case MLX5_MKC_ACCESS_MODE_MTT:
289 ret = DIV_ROUND_UP(ndescs, MLX5_IB_UMR_OCTOWORD /
290 sizeof(struct mlx5_mtt));
292 case MLX5_MKC_ACCESS_MODE_KSM:
293 ret = DIV_ROUND_UP(ndescs, MLX5_IB_UMR_OCTOWORD /
294 sizeof(struct mlx5_klm));
302 static void set_cache_mkc(struct mlx5_cache_ent *ent, void *mkc)
304 set_mkc_access_pd_addr_fields(mkc, ent->rb_key.access_flags, 0,
306 MLX5_SET(mkc, mkc, free, 1);
307 MLX5_SET(mkc, mkc, umr_en, 1);
308 MLX5_SET(mkc, mkc, access_mode_1_0, ent->rb_key.access_mode & 0x3);
309 MLX5_SET(mkc, mkc, access_mode_4_2,
310 (ent->rb_key.access_mode >> 2) & 0x7);
312 MLX5_SET(mkc, mkc, translations_octword_size,
313 get_mkc_octo_size(ent->rb_key.access_mode,
314 ent->rb_key.ndescs));
315 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
318 /* Asynchronously schedule new MRs to be populated in the cache. */
319 static int add_keys(struct mlx5_cache_ent *ent, unsigned int num)
321 struct mlx5r_async_create_mkey *async_create;
326 for (i = 0; i < num; i++) {
327 async_create = kzalloc(sizeof(struct mlx5r_async_create_mkey),
331 mkc = MLX5_ADDR_OF(create_mkey_in, async_create->in,
332 memory_key_mkey_entry);
333 set_cache_mkc(ent, mkc);
334 async_create->ent = ent;
336 err = push_mkey(ent, true, NULL);
338 goto free_async_create;
340 err = mlx5_ib_create_mkey_cb(async_create);
342 mlx5_ib_warn(ent->dev, "create mkey failed %d\n", err);
343 goto err_undo_reserve;
350 xa_lock_irq(&ent->mkeys);
351 undo_push_reserve_mkey(ent);
352 xa_unlock_irq(&ent->mkeys);
358 /* Synchronously create a MR in the cache */
359 static int create_cache_mkey(struct mlx5_cache_ent *ent, u32 *mkey)
361 size_t inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
366 in = kzalloc(inlen, GFP_KERNEL);
369 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
370 set_cache_mkc(ent, mkc);
372 err = mlx5_core_create_mkey(ent->dev->mdev, mkey, in, inlen);
376 WRITE_ONCE(ent->dev->cache.last_add, jiffies);
382 static void remove_cache_mr_locked(struct mlx5_cache_ent *ent)
386 lockdep_assert_held(&ent->mkeys.xa_lock);
389 mkey = pop_stored_mkey(ent);
390 xa_unlock_irq(&ent->mkeys);
391 mlx5_core_destroy_mkey(ent->dev->mdev, mkey);
392 xa_lock_irq(&ent->mkeys);
395 static int resize_available_mrs(struct mlx5_cache_ent *ent, unsigned int target,
397 __acquires(&ent->mkeys) __releases(&ent->mkeys)
401 lockdep_assert_held(&ent->mkeys.xa_lock);
405 target = ent->limit * 2;
406 if (target == ent->reserved)
408 if (target > ent->reserved) {
409 u32 todo = target - ent->reserved;
411 xa_unlock_irq(&ent->mkeys);
412 err = add_keys(ent, todo);
414 usleep_range(3000, 5000);
415 xa_lock_irq(&ent->mkeys);
422 remove_cache_mr_locked(ent);
427 static ssize_t size_write(struct file *filp, const char __user *buf,
428 size_t count, loff_t *pos)
430 struct mlx5_cache_ent *ent = filp->private_data;
434 err = kstrtou32_from_user(buf, count, 0, &target);
439 * Target is the new value of total_mrs the user requests, however we
440 * cannot free MRs that are in use. Compute the target value for stored
443 xa_lock_irq(&ent->mkeys);
444 if (target < ent->in_use) {
448 target = target - ent->in_use;
449 if (target < ent->limit || target > ent->limit*2) {
453 err = resize_available_mrs(ent, target, false);
456 xa_unlock_irq(&ent->mkeys);
461 xa_unlock_irq(&ent->mkeys);
465 static ssize_t size_read(struct file *filp, char __user *buf, size_t count,
468 struct mlx5_cache_ent *ent = filp->private_data;
472 err = snprintf(lbuf, sizeof(lbuf), "%ld\n", ent->stored + ent->in_use);
476 return simple_read_from_buffer(buf, count, pos, lbuf, err);
479 static const struct file_operations size_fops = {
480 .owner = THIS_MODULE,
486 static ssize_t limit_write(struct file *filp, const char __user *buf,
487 size_t count, loff_t *pos)
489 struct mlx5_cache_ent *ent = filp->private_data;
493 err = kstrtou32_from_user(buf, count, 0, &var);
498 * Upon set we immediately fill the cache to high water mark implied by
501 xa_lock_irq(&ent->mkeys);
503 err = resize_available_mrs(ent, 0, true);
504 xa_unlock_irq(&ent->mkeys);
510 static ssize_t limit_read(struct file *filp, char __user *buf, size_t count,
513 struct mlx5_cache_ent *ent = filp->private_data;
517 err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit);
521 return simple_read_from_buffer(buf, count, pos, lbuf, err);
524 static const struct file_operations limit_fops = {
525 .owner = THIS_MODULE,
527 .write = limit_write,
531 static bool someone_adding(struct mlx5_mkey_cache *cache)
533 struct mlx5_cache_ent *ent;
534 struct rb_node *node;
537 mutex_lock(&cache->rb_lock);
538 for (node = rb_first(&cache->rb_root); node; node = rb_next(node)) {
539 ent = rb_entry(node, struct mlx5_cache_ent, node);
540 xa_lock_irq(&ent->mkeys);
541 ret = ent->stored < ent->limit;
542 xa_unlock_irq(&ent->mkeys);
544 mutex_unlock(&cache->rb_lock);
548 mutex_unlock(&cache->rb_lock);
553 * Check if the bucket is outside the high/low water mark and schedule an async
554 * update. The cache refill has hysteresis, once the low water mark is hit it is
555 * refilled up to the high mark.
557 static void queue_adjust_cache_locked(struct mlx5_cache_ent *ent)
559 lockdep_assert_held(&ent->mkeys.xa_lock);
561 if (ent->disabled || READ_ONCE(ent->dev->fill_delay) || ent->is_tmp)
563 if (ent->stored < ent->limit) {
564 ent->fill_to_high_water = true;
565 mod_delayed_work(ent->dev->cache.wq, &ent->dwork, 0);
566 } else if (ent->fill_to_high_water &&
567 ent->reserved < 2 * ent->limit) {
569 * Once we start populating due to hitting a low water mark
570 * continue until we pass the high water mark.
572 mod_delayed_work(ent->dev->cache.wq, &ent->dwork, 0);
573 } else if (ent->stored == 2 * ent->limit) {
574 ent->fill_to_high_water = false;
575 } else if (ent->stored > 2 * ent->limit) {
576 /* Queue deletion of excess entries */
577 ent->fill_to_high_water = false;
578 if (ent->stored != ent->reserved)
579 queue_delayed_work(ent->dev->cache.wq, &ent->dwork,
580 msecs_to_jiffies(1000));
582 mod_delayed_work(ent->dev->cache.wq, &ent->dwork, 0);
586 static void __cache_work_func(struct mlx5_cache_ent *ent)
588 struct mlx5_ib_dev *dev = ent->dev;
589 struct mlx5_mkey_cache *cache = &dev->cache;
592 xa_lock_irq(&ent->mkeys);
596 if (ent->fill_to_high_water && ent->reserved < 2 * ent->limit &&
597 !READ_ONCE(dev->fill_delay)) {
598 xa_unlock_irq(&ent->mkeys);
599 err = add_keys(ent, 1);
600 xa_lock_irq(&ent->mkeys);
605 * EAGAIN only happens if there are pending MRs, so we
606 * will be rescheduled when storing them. The only
607 * failure path here is ENOMEM.
609 if (err != -EAGAIN) {
612 "add keys command failed, err %d\n",
614 queue_delayed_work(cache->wq, &ent->dwork,
615 msecs_to_jiffies(1000));
618 } else if (ent->stored > 2 * ent->limit) {
622 * The remove_cache_mr() logic is performed as garbage
623 * collection task. Such task is intended to be run when no
624 * other active processes are running.
626 * The need_resched() will return TRUE if there are user tasks
627 * to be activated in near future.
629 * In such case, we don't execute remove_cache_mr() and postpone
630 * the garbage collection work to try to run in next cycle, in
631 * order to free CPU resources to other tasks.
633 xa_unlock_irq(&ent->mkeys);
634 need_delay = need_resched() || someone_adding(cache) ||
636 READ_ONCE(cache->last_add) + 300 * HZ);
637 xa_lock_irq(&ent->mkeys);
641 queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ);
644 remove_cache_mr_locked(ent);
645 queue_adjust_cache_locked(ent);
648 xa_unlock_irq(&ent->mkeys);
651 static void delayed_cache_work_func(struct work_struct *work)
653 struct mlx5_cache_ent *ent;
655 ent = container_of(work, struct mlx5_cache_ent, dwork.work);
656 __cache_work_func(ent);
659 static int cache_ent_key_cmp(struct mlx5r_cache_rb_key key1,
660 struct mlx5r_cache_rb_key key2)
664 res = key1.ats - key2.ats;
668 res = key1.access_mode - key2.access_mode;
672 res = key1.access_flags - key2.access_flags;
677 * keep ndescs the last in the compare table since the find function
678 * searches for an exact match on all properties and only closest
681 return key1.ndescs - key2.ndescs;
684 static int mlx5_cache_ent_insert(struct mlx5_mkey_cache *cache,
685 struct mlx5_cache_ent *ent)
687 struct rb_node **new = &cache->rb_root.rb_node, *parent = NULL;
688 struct mlx5_cache_ent *cur;
691 /* Figure out where to put new node */
693 cur = rb_entry(*new, struct mlx5_cache_ent, node);
695 cmp = cache_ent_key_cmp(cur->rb_key, ent->rb_key);
697 new = &((*new)->rb_left);
699 new = &((*new)->rb_right);
701 mutex_unlock(&cache->rb_lock);
706 /* Add new node and rebalance tree. */
707 rb_link_node(&ent->node, parent, new);
708 rb_insert_color(&ent->node, &cache->rb_root);
713 static struct mlx5_cache_ent *
714 mkey_cache_ent_from_rb_key(struct mlx5_ib_dev *dev,
715 struct mlx5r_cache_rb_key rb_key)
717 struct rb_node *node = dev->cache.rb_root.rb_node;
718 struct mlx5_cache_ent *cur, *smallest = NULL;
722 * Find the smallest ent with order >= requested_order.
725 cur = rb_entry(node, struct mlx5_cache_ent, node);
726 cmp = cache_ent_key_cmp(cur->rb_key, rb_key);
729 node = node->rb_left;
732 node = node->rb_right;
738 smallest->rb_key.access_mode == rb_key.access_mode &&
739 smallest->rb_key.access_flags == rb_key.access_flags &&
740 smallest->rb_key.ats == rb_key.ats) ?
745 static struct mlx5_ib_mr *_mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev,
746 struct mlx5_cache_ent *ent,
749 struct mlx5_ib_mr *mr;
752 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
754 return ERR_PTR(-ENOMEM);
756 xa_lock_irq(&ent->mkeys);
760 queue_adjust_cache_locked(ent);
762 xa_unlock_irq(&ent->mkeys);
763 err = create_cache_mkey(ent, &mr->mmkey.key);
765 xa_lock_irq(&ent->mkeys);
767 xa_unlock_irq(&ent->mkeys);
772 mr->mmkey.key = pop_stored_mkey(ent);
773 queue_adjust_cache_locked(ent);
774 xa_unlock_irq(&ent->mkeys);
776 mr->mmkey.cache_ent = ent;
777 mr->mmkey.type = MLX5_MKEY_MR;
778 init_waitqueue_head(&mr->mmkey.wait);
782 static int get_unchangeable_access_flags(struct mlx5_ib_dev *dev,
787 if ((access_flags & IB_ACCESS_REMOTE_ATOMIC) &&
788 MLX5_CAP_GEN(dev->mdev, atomic) &&
789 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))
790 ret |= IB_ACCESS_REMOTE_ATOMIC;
792 if ((access_flags & IB_ACCESS_RELAXED_ORDERING) &&
793 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) &&
794 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr))
795 ret |= IB_ACCESS_RELAXED_ORDERING;
797 if ((access_flags & IB_ACCESS_RELAXED_ORDERING) &&
798 (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) ||
799 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_pci_enabled)) &&
800 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr))
801 ret |= IB_ACCESS_RELAXED_ORDERING;
806 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev,
807 int access_flags, int access_mode,
810 struct mlx5r_cache_rb_key rb_key = {
812 .access_mode = access_mode,
813 .access_flags = get_unchangeable_access_flags(dev, access_flags)
815 struct mlx5_cache_ent *ent = mkey_cache_ent_from_rb_key(dev, rb_key);
818 return ERR_PTR(-EOPNOTSUPP);
820 return _mlx5_mr_cache_alloc(dev, ent, access_flags);
823 static void clean_keys(struct mlx5_ib_dev *dev, struct mlx5_cache_ent *ent)
827 cancel_delayed_work(&ent->dwork);
828 xa_lock_irq(&ent->mkeys);
829 while (ent->stored) {
830 mkey = pop_stored_mkey(ent);
831 xa_unlock_irq(&ent->mkeys);
832 mlx5_core_destroy_mkey(dev->mdev, mkey);
833 xa_lock_irq(&ent->mkeys);
835 xa_unlock_irq(&ent->mkeys);
838 static void mlx5_mkey_cache_debugfs_cleanup(struct mlx5_ib_dev *dev)
840 if (!mlx5_debugfs_root || dev->is_rep)
843 debugfs_remove_recursive(dev->cache.fs_root);
844 dev->cache.fs_root = NULL;
847 static void mlx5_mkey_cache_debugfs_add_ent(struct mlx5_ib_dev *dev,
848 struct mlx5_cache_ent *ent)
850 int order = order_base_2(ent->rb_key.ndescs);
853 if (!mlx5_debugfs_root || dev->is_rep)
856 if (ent->rb_key.access_mode == MLX5_MKC_ACCESS_MODE_KSM)
857 order = MLX5_IMR_KSM_CACHE_ENTRY + 2;
859 sprintf(ent->name, "%d", order);
860 dir = debugfs_create_dir(ent->name, dev->cache.fs_root);
861 debugfs_create_file("size", 0600, dir, ent, &size_fops);
862 debugfs_create_file("limit", 0600, dir, ent, &limit_fops);
863 debugfs_create_ulong("cur", 0400, dir, &ent->stored);
864 debugfs_create_u32("miss", 0600, dir, &ent->miss);
867 static void mlx5_mkey_cache_debugfs_init(struct mlx5_ib_dev *dev)
869 struct dentry *dbg_root = mlx5_debugfs_get_dev_root(dev->mdev);
870 struct mlx5_mkey_cache *cache = &dev->cache;
872 if (!mlx5_debugfs_root || dev->is_rep)
875 cache->fs_root = debugfs_create_dir("mr_cache", dbg_root);
878 static void delay_time_func(struct timer_list *t)
880 struct mlx5_ib_dev *dev = from_timer(dev, t, delay_timer);
882 WRITE_ONCE(dev->fill_delay, 0);
885 struct mlx5_cache_ent *
886 mlx5r_cache_create_ent_locked(struct mlx5_ib_dev *dev,
887 struct mlx5r_cache_rb_key rb_key,
888 bool persistent_entry)
890 struct mlx5_cache_ent *ent;
894 ent = kzalloc(sizeof(*ent), GFP_KERNEL);
896 return ERR_PTR(-ENOMEM);
898 xa_init_flags(&ent->mkeys, XA_FLAGS_LOCK_IRQ);
899 ent->rb_key = rb_key;
901 ent->is_tmp = !persistent_entry;
903 INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func);
905 ret = mlx5_cache_ent_insert(&dev->cache, ent);
911 if (persistent_entry) {
912 if (rb_key.access_mode == MLX5_MKC_ACCESS_MODE_KSM)
913 order = MLX5_IMR_KSM_CACHE_ENTRY;
915 order = order_base_2(rb_key.ndescs) - 2;
917 if ((dev->mdev->profile.mask & MLX5_PROF_MASK_MR_CACHE) &&
918 !dev->is_rep && mlx5_core_is_pf(dev->mdev) &&
919 mlx5r_umr_can_load_pas(dev, 0))
920 ent->limit = dev->mdev->profile.mr_cache[order].limit;
924 mlx5_mkey_cache_debugfs_add_ent(dev, ent);
926 mod_delayed_work(ent->dev->cache.wq,
927 &ent->dev->cache.remove_ent_dwork,
928 msecs_to_jiffies(30 * 1000));
934 static void remove_ent_work_func(struct work_struct *work)
936 struct mlx5_mkey_cache *cache;
937 struct mlx5_cache_ent *ent;
940 cache = container_of(work, struct mlx5_mkey_cache,
941 remove_ent_dwork.work);
942 mutex_lock(&cache->rb_lock);
943 cur = rb_last(&cache->rb_root);
945 ent = rb_entry(cur, struct mlx5_cache_ent, node);
947 mutex_unlock(&cache->rb_lock);
949 xa_lock_irq(&ent->mkeys);
951 xa_unlock_irq(&ent->mkeys);
952 mutex_lock(&cache->rb_lock);
955 xa_unlock_irq(&ent->mkeys);
957 clean_keys(ent->dev, ent);
958 mutex_lock(&cache->rb_lock);
960 mutex_unlock(&cache->rb_lock);
963 int mlx5_mkey_cache_init(struct mlx5_ib_dev *dev)
965 struct mlx5_mkey_cache *cache = &dev->cache;
966 struct rb_root *root = &dev->cache.rb_root;
967 struct mlx5r_cache_rb_key rb_key = {
968 .access_mode = MLX5_MKC_ACCESS_MODE_MTT,
970 struct mlx5_cache_ent *ent;
971 struct rb_node *node;
975 mutex_init(&dev->slow_path_mutex);
976 mutex_init(&dev->cache.rb_lock);
977 dev->cache.rb_root = RB_ROOT;
978 INIT_DELAYED_WORK(&dev->cache.remove_ent_dwork, remove_ent_work_func);
979 cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM);
981 mlx5_ib_warn(dev, "failed to create work queue\n");
985 mlx5_cmd_init_async_ctx(dev->mdev, &dev->async_ctx);
986 timer_setup(&dev->delay_timer, delay_time_func, 0);
987 mlx5_mkey_cache_debugfs_init(dev);
988 mutex_lock(&cache->rb_lock);
989 for (i = 0; i <= mkey_cache_max_order(dev); i++) {
990 rb_key.ndescs = 1 << (i + 2);
991 ent = mlx5r_cache_create_ent_locked(dev, rb_key, true);
998 ret = mlx5_odp_init_mkey_cache(dev);
1002 mutex_unlock(&cache->rb_lock);
1003 for (node = rb_first(root); node; node = rb_next(node)) {
1004 ent = rb_entry(node, struct mlx5_cache_ent, node);
1005 xa_lock_irq(&ent->mkeys);
1006 queue_adjust_cache_locked(ent);
1007 xa_unlock_irq(&ent->mkeys);
1013 mutex_unlock(&cache->rb_lock);
1014 mlx5_mkey_cache_debugfs_cleanup(dev);
1015 mlx5_ib_warn(dev, "failed to create mkey cache entry\n");
1019 void mlx5_mkey_cache_cleanup(struct mlx5_ib_dev *dev)
1021 struct rb_root *root = &dev->cache.rb_root;
1022 struct mlx5_cache_ent *ent;
1023 struct rb_node *node;
1028 mutex_lock(&dev->cache.rb_lock);
1029 for (node = rb_first(root); node; node = rb_next(node)) {
1030 ent = rb_entry(node, struct mlx5_cache_ent, node);
1031 xa_lock_irq(&ent->mkeys);
1032 ent->disabled = true;
1033 xa_unlock_irq(&ent->mkeys);
1035 mutex_unlock(&dev->cache.rb_lock);
1038 * After all entries are disabled and will not reschedule on WQ,
1039 * flush it and all async commands.
1041 flush_workqueue(dev->cache.wq);
1043 mlx5_mkey_cache_debugfs_cleanup(dev);
1044 mlx5_cmd_cleanup_async_ctx(&dev->async_ctx);
1046 /* At this point all entries are disabled and have no concurrent work. */
1047 mutex_lock(&dev->cache.rb_lock);
1048 node = rb_first(root);
1050 ent = rb_entry(node, struct mlx5_cache_ent, node);
1051 node = rb_next(node);
1052 clean_keys(dev, ent);
1053 rb_erase(&ent->node, root);
1056 mutex_unlock(&dev->cache.rb_lock);
1058 destroy_workqueue(dev->cache.wq);
1059 del_timer_sync(&dev->delay_timer);
1062 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc)
1064 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1065 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1066 struct mlx5_ib_mr *mr;
1071 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1073 return ERR_PTR(-ENOMEM);
1075 in = kzalloc(inlen, GFP_KERNEL);
1081 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1083 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);
1084 MLX5_SET(mkc, mkc, length64, 1);
1085 set_mkc_access_pd_addr_fields(mkc, acc | IB_ACCESS_RELAXED_ORDERING, 0,
1088 err = mlx5_ib_create_mkey(dev, &mr->mmkey, in, inlen);
1093 mr->mmkey.type = MLX5_MKEY_MR;
1094 mr->ibmr.lkey = mr->mmkey.key;
1095 mr->ibmr.rkey = mr->mmkey.key;
1106 return ERR_PTR(err);
1109 static int get_octo_len(u64 addr, u64 len, int page_shift)
1111 u64 page_size = 1ULL << page_shift;
1115 offset = addr & (page_size - 1);
1116 npages = ALIGN(len + offset, page_size) >> page_shift;
1117 return (npages + 1) / 2;
1120 static int mkey_cache_max_order(struct mlx5_ib_dev *dev)
1122 if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset))
1123 return MKEY_CACHE_LAST_STD_ENTRY;
1124 return MLX5_MAX_UMR_SHIFT;
1127 static void set_mr_fields(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr,
1128 u64 length, int access_flags, u64 iova)
1130 mr->ibmr.lkey = mr->mmkey.key;
1131 mr->ibmr.rkey = mr->mmkey.key;
1132 mr->ibmr.length = length;
1133 mr->ibmr.device = &dev->ib_dev;
1134 mr->ibmr.iova = iova;
1135 mr->access_flags = access_flags;
1138 static unsigned int mlx5_umem_dmabuf_default_pgsz(struct ib_umem *umem,
1142 * The alignment of iova has already been checked upon entering
1143 * UVERBS_METHOD_REG_DMABUF_MR
1149 static struct mlx5_ib_mr *alloc_cacheable_mr(struct ib_pd *pd,
1150 struct ib_umem *umem, u64 iova,
1153 struct mlx5r_cache_rb_key rb_key = {
1154 .access_mode = MLX5_MKC_ACCESS_MODE_MTT,
1156 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1157 struct mlx5_cache_ent *ent;
1158 struct mlx5_ib_mr *mr;
1159 unsigned int page_size;
1161 if (umem->is_dmabuf)
1162 page_size = mlx5_umem_dmabuf_default_pgsz(umem, iova);
1164 page_size = mlx5_umem_find_best_pgsz(umem, mkc, log_page_size,
1166 if (WARN_ON(!page_size))
1167 return ERR_PTR(-EINVAL);
1169 rb_key.ndescs = ib_umem_num_dma_blocks(umem, page_size);
1170 rb_key.ats = mlx5_umem_needs_ats(dev, umem, access_flags);
1171 rb_key.access_flags = get_unchangeable_access_flags(dev, access_flags);
1172 ent = mkey_cache_ent_from_rb_key(dev, rb_key);
1174 * If the MR can't come from the cache then synchronously create an uncached
1178 mutex_lock(&dev->slow_path_mutex);
1179 mr = reg_create(pd, umem, iova, access_flags, page_size, false);
1180 mutex_unlock(&dev->slow_path_mutex);
1183 mr->mmkey.rb_key = rb_key;
1187 mr = _mlx5_mr_cache_alloc(dev, ent, access_flags);
1193 mr->page_shift = order_base_2(page_size);
1194 set_mr_fields(dev, mr, umem->length, access_flags, iova);
1200 * If ibmr is NULL it will be allocated by reg_create.
1201 * Else, the given ibmr will be used.
1203 static struct mlx5_ib_mr *reg_create(struct ib_pd *pd, struct ib_umem *umem,
1204 u64 iova, int access_flags,
1205 unsigned int page_size, bool populate)
1207 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1208 struct mlx5_ib_mr *mr;
1214 bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg));
1217 return ERR_PTR(-EINVAL);
1218 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1220 return ERR_PTR(-ENOMEM);
1223 mr->access_flags = access_flags;
1224 mr->page_shift = order_base_2(page_size);
1226 inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1228 inlen += sizeof(*pas) *
1229 roundup(ib_umem_num_dma_blocks(umem, page_size), 2);
1230 in = kvzalloc(inlen, GFP_KERNEL);
1235 pas = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
1237 if (WARN_ON(access_flags & IB_ACCESS_ON_DEMAND)) {
1241 mlx5_ib_populate_pas(umem, 1UL << mr->page_shift, pas,
1242 pg_cap ? MLX5_IB_MTT_PRESENT : 0);
1245 /* The pg_access bit allows setting the access flags
1246 * in the page list submitted with the command.
1248 MLX5_SET(create_mkey_in, in, pg_access, !!(pg_cap));
1250 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1251 set_mkc_access_pd_addr_fields(mkc, access_flags, iova,
1252 populate ? pd : dev->umrc.pd);
1253 MLX5_SET(mkc, mkc, free, !populate);
1254 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
1255 MLX5_SET(mkc, mkc, umr_en, 1);
1257 MLX5_SET64(mkc, mkc, len, umem->length);
1258 MLX5_SET(mkc, mkc, bsf_octword_size, 0);
1259 MLX5_SET(mkc, mkc, translations_octword_size,
1260 get_octo_len(iova, umem->length, mr->page_shift));
1261 MLX5_SET(mkc, mkc, log_page_size, mr->page_shift);
1262 if (mlx5_umem_needs_ats(dev, umem, access_flags))
1263 MLX5_SET(mkc, mkc, ma_translation_mode, 1);
1265 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
1266 get_octo_len(iova, umem->length, mr->page_shift));
1269 err = mlx5_ib_create_mkey(dev, &mr->mmkey, in, inlen);
1271 mlx5_ib_warn(dev, "create mkey failed\n");
1274 mr->mmkey.type = MLX5_MKEY_MR;
1275 mr->mmkey.ndescs = get_octo_len(iova, umem->length, mr->page_shift);
1277 set_mr_fields(dev, mr, umem->length, access_flags, iova);
1280 mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmkey.key);
1288 return ERR_PTR(err);
1291 static struct ib_mr *mlx5_ib_get_dm_mr(struct ib_pd *pd, u64 start_addr,
1292 u64 length, int acc, int mode)
1294 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1295 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1296 struct mlx5_ib_mr *mr;
1301 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1303 return ERR_PTR(-ENOMEM);
1305 in = kzalloc(inlen, GFP_KERNEL);
1311 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1313 MLX5_SET(mkc, mkc, access_mode_1_0, mode & 0x3);
1314 MLX5_SET(mkc, mkc, access_mode_4_2, (mode >> 2) & 0x7);
1315 MLX5_SET64(mkc, mkc, len, length);
1316 set_mkc_access_pd_addr_fields(mkc, acc, start_addr, pd);
1318 err = mlx5_ib_create_mkey(dev, &mr->mmkey, in, inlen);
1324 set_mr_fields(dev, mr, length, acc, start_addr);
1334 return ERR_PTR(err);
1337 int mlx5_ib_advise_mr(struct ib_pd *pd,
1338 enum ib_uverbs_advise_mr_advice advice,
1340 struct ib_sge *sg_list,
1342 struct uverbs_attr_bundle *attrs)
1344 if (advice != IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH &&
1345 advice != IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE &&
1346 advice != IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT)
1349 return mlx5_ib_advise_mr_prefetch(pd, advice, flags,
1353 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1354 struct ib_dm_mr_attr *attr,
1355 struct uverbs_attr_bundle *attrs)
1357 struct mlx5_ib_dm *mdm = to_mdm(dm);
1358 struct mlx5_core_dev *dev = to_mdev(dm->device)->mdev;
1359 u64 start_addr = mdm->dev_addr + attr->offset;
1362 switch (mdm->type) {
1363 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
1364 if (attr->access_flags & ~MLX5_IB_DM_MEMIC_ALLOWED_ACCESS)
1365 return ERR_PTR(-EINVAL);
1367 mode = MLX5_MKC_ACCESS_MODE_MEMIC;
1368 start_addr -= pci_resource_start(dev->pdev, 0);
1370 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
1371 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
1372 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_PATTERN_SW_ICM:
1373 if (attr->access_flags & ~MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS)
1374 return ERR_PTR(-EINVAL);
1376 mode = MLX5_MKC_ACCESS_MODE_SW_ICM;
1379 return ERR_PTR(-EINVAL);
1382 return mlx5_ib_get_dm_mr(pd, start_addr, attr->length,
1383 attr->access_flags, mode);
1386 static struct ib_mr *create_real_mr(struct ib_pd *pd, struct ib_umem *umem,
1387 u64 iova, int access_flags)
1389 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1390 struct mlx5_ib_mr *mr = NULL;
1394 xlt_with_umr = mlx5r_umr_can_load_pas(dev, umem->length);
1396 mr = alloc_cacheable_mr(pd, umem, iova, access_flags);
1398 unsigned int page_size = mlx5_umem_find_best_pgsz(
1399 umem, mkc, log_page_size, 0, iova);
1401 mutex_lock(&dev->slow_path_mutex);
1402 mr = reg_create(pd, umem, iova, access_flags, page_size, true);
1403 mutex_unlock(&dev->slow_path_mutex);
1406 ib_umem_release(umem);
1407 return ERR_CAST(mr);
1410 mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key);
1412 atomic_add(ib_umem_num_pages(umem), &dev->mdev->priv.reg_pages);
1416 * If the MR was created with reg_create then it will be
1417 * configured properly but left disabled. It is safe to go ahead
1418 * and configure it again via UMR while enabling it.
1420 err = mlx5r_umr_update_mr_pas(mr, MLX5_IB_UPD_XLT_ENABLE);
1422 mlx5_ib_dereg_mr(&mr->ibmr, NULL);
1423 return ERR_PTR(err);
1429 static struct ib_mr *create_user_odp_mr(struct ib_pd *pd, u64 start, u64 length,
1430 u64 iova, int access_flags,
1431 struct ib_udata *udata)
1433 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1434 struct ib_umem_odp *odp;
1435 struct mlx5_ib_mr *mr;
1438 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING))
1439 return ERR_PTR(-EOPNOTSUPP);
1441 err = mlx5r_odp_create_eq(dev, &dev->odp_pf_eq);
1443 return ERR_PTR(err);
1444 if (!start && length == U64_MAX) {
1446 return ERR_PTR(-EINVAL);
1447 if (!(dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT))
1448 return ERR_PTR(-EINVAL);
1450 mr = mlx5_ib_alloc_implicit_mr(to_mpd(pd), access_flags);
1452 return ERR_CAST(mr);
1456 /* ODP requires xlt update via umr to work. */
1457 if (!mlx5r_umr_can_load_pas(dev, length))
1458 return ERR_PTR(-EINVAL);
1460 odp = ib_umem_odp_get(&dev->ib_dev, start, length, access_flags,
1463 return ERR_CAST(odp);
1465 mr = alloc_cacheable_mr(pd, &odp->umem, iova, access_flags);
1467 ib_umem_release(&odp->umem);
1468 return ERR_CAST(mr);
1470 xa_init(&mr->implicit_children);
1473 err = mlx5r_store_odp_mkey(dev, &mr->mmkey);
1477 err = mlx5_ib_init_odp_mr(mr);
1483 mlx5_ib_dereg_mr(&mr->ibmr, NULL);
1484 return ERR_PTR(err);
1487 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1488 u64 iova, int access_flags,
1489 struct ib_udata *udata)
1491 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1492 struct ib_umem *umem;
1494 if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM))
1495 return ERR_PTR(-EOPNOTSUPP);
1497 mlx5_ib_dbg(dev, "start 0x%llx, iova 0x%llx, length 0x%llx, access_flags 0x%x\n",
1498 start, iova, length, access_flags);
1500 if (access_flags & IB_ACCESS_ON_DEMAND)
1501 return create_user_odp_mr(pd, start, length, iova, access_flags,
1503 umem = ib_umem_get(&dev->ib_dev, start, length, access_flags);
1505 return ERR_CAST(umem);
1506 return create_real_mr(pd, umem, iova, access_flags);
1509 static void mlx5_ib_dmabuf_invalidate_cb(struct dma_buf_attachment *attach)
1511 struct ib_umem_dmabuf *umem_dmabuf = attach->importer_priv;
1512 struct mlx5_ib_mr *mr = umem_dmabuf->private;
1514 dma_resv_assert_held(umem_dmabuf->attach->dmabuf->resv);
1516 if (!umem_dmabuf->sgt)
1519 mlx5r_umr_update_mr_pas(mr, MLX5_IB_UPD_XLT_ZAP);
1520 ib_umem_dmabuf_unmap_pages(umem_dmabuf);
1523 static struct dma_buf_attach_ops mlx5_ib_dmabuf_attach_ops = {
1524 .allow_peer2peer = 1,
1525 .move_notify = mlx5_ib_dmabuf_invalidate_cb,
1528 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 offset,
1529 u64 length, u64 virt_addr,
1530 int fd, int access_flags,
1531 struct ib_udata *udata)
1533 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1534 struct mlx5_ib_mr *mr = NULL;
1535 struct ib_umem_dmabuf *umem_dmabuf;
1538 if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM) ||
1539 !IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING))
1540 return ERR_PTR(-EOPNOTSUPP);
1543 "offset 0x%llx, virt_addr 0x%llx, length 0x%llx, fd %d, access_flags 0x%x\n",
1544 offset, virt_addr, length, fd, access_flags);
1546 /* dmabuf requires xlt update via umr to work. */
1547 if (!mlx5r_umr_can_load_pas(dev, length))
1548 return ERR_PTR(-EINVAL);
1550 umem_dmabuf = ib_umem_dmabuf_get(&dev->ib_dev, offset, length, fd,
1552 &mlx5_ib_dmabuf_attach_ops);
1553 if (IS_ERR(umem_dmabuf)) {
1554 mlx5_ib_dbg(dev, "umem_dmabuf get failed (%ld)\n",
1555 PTR_ERR(umem_dmabuf));
1556 return ERR_CAST(umem_dmabuf);
1559 mr = alloc_cacheable_mr(pd, &umem_dmabuf->umem, virt_addr,
1562 ib_umem_release(&umem_dmabuf->umem);
1563 return ERR_CAST(mr);
1566 mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key);
1568 atomic_add(ib_umem_num_pages(mr->umem), &dev->mdev->priv.reg_pages);
1569 umem_dmabuf->private = mr;
1570 err = mlx5r_store_odp_mkey(dev, &mr->mmkey);
1574 err = mlx5_ib_init_dmabuf_mr(mr);
1580 mlx5_ib_dereg_mr(&mr->ibmr, NULL);
1581 return ERR_PTR(err);
1585 * True if the change in access flags can be done via UMR, only some access
1586 * flags can be updated.
1588 static bool can_use_umr_rereg_access(struct mlx5_ib_dev *dev,
1589 unsigned int current_access_flags,
1590 unsigned int target_access_flags)
1592 unsigned int diffs = current_access_flags ^ target_access_flags;
1594 if (diffs & ~(IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE |
1595 IB_ACCESS_REMOTE_READ | IB_ACCESS_RELAXED_ORDERING))
1597 return mlx5r_umr_can_reconfig(dev, current_access_flags,
1598 target_access_flags);
1601 static bool can_use_umr_rereg_pas(struct mlx5_ib_mr *mr,
1602 struct ib_umem *new_umem,
1603 int new_access_flags, u64 iova,
1604 unsigned long *page_size)
1606 struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device);
1608 /* We only track the allocated sizes of MRs from the cache */
1609 if (!mr->mmkey.cache_ent)
1611 if (!mlx5r_umr_can_load_pas(dev, new_umem->length))
1615 mlx5_umem_find_best_pgsz(new_umem, mkc, log_page_size, 0, iova);
1616 if (WARN_ON(!*page_size))
1618 return (mr->mmkey.cache_ent->rb_key.ndescs) >=
1619 ib_umem_num_dma_blocks(new_umem, *page_size);
1622 static int umr_rereg_pas(struct mlx5_ib_mr *mr, struct ib_pd *pd,
1623 int access_flags, int flags, struct ib_umem *new_umem,
1624 u64 iova, unsigned long page_size)
1626 struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device);
1627 int upd_flags = MLX5_IB_UPD_XLT_ADDR | MLX5_IB_UPD_XLT_ENABLE;
1628 struct ib_umem *old_umem = mr->umem;
1632 * To keep everything simple the MR is revoked before we start to mess
1633 * with it. This ensure the change is atomic relative to any use of the
1636 err = mlx5r_umr_revoke_mr(mr);
1640 if (flags & IB_MR_REREG_PD) {
1642 upd_flags |= MLX5_IB_UPD_XLT_PD;
1644 if (flags & IB_MR_REREG_ACCESS) {
1645 mr->access_flags = access_flags;
1646 upd_flags |= MLX5_IB_UPD_XLT_ACCESS;
1649 mr->ibmr.iova = iova;
1650 mr->ibmr.length = new_umem->length;
1651 mr->page_shift = order_base_2(page_size);
1652 mr->umem = new_umem;
1653 err = mlx5r_umr_update_mr_pas(mr, upd_flags);
1656 * The MR is revoked at this point so there is no issue to free
1659 mr->umem = old_umem;
1663 atomic_sub(ib_umem_num_pages(old_umem), &dev->mdev->priv.reg_pages);
1664 ib_umem_release(old_umem);
1665 atomic_add(ib_umem_num_pages(new_umem), &dev->mdev->priv.reg_pages);
1669 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1670 u64 length, u64 iova, int new_access_flags,
1671 struct ib_pd *new_pd,
1672 struct ib_udata *udata)
1674 struct mlx5_ib_dev *dev = to_mdev(ib_mr->device);
1675 struct mlx5_ib_mr *mr = to_mmr(ib_mr);
1678 if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM))
1679 return ERR_PTR(-EOPNOTSUPP);
1683 "start 0x%llx, iova 0x%llx, length 0x%llx, access_flags 0x%x\n",
1684 start, iova, length, new_access_flags);
1686 if (flags & ~(IB_MR_REREG_TRANS | IB_MR_REREG_PD | IB_MR_REREG_ACCESS))
1687 return ERR_PTR(-EOPNOTSUPP);
1689 if (!(flags & IB_MR_REREG_ACCESS))
1690 new_access_flags = mr->access_flags;
1691 if (!(flags & IB_MR_REREG_PD))
1694 if (!(flags & IB_MR_REREG_TRANS)) {
1695 struct ib_umem *umem;
1697 /* Fast path for PD/access change */
1698 if (can_use_umr_rereg_access(dev, mr->access_flags,
1699 new_access_flags)) {
1700 err = mlx5r_umr_rereg_pd_access(mr, new_pd,
1703 return ERR_PTR(err);
1706 /* DM or ODP MR's don't have a normal umem so we can't re-use it */
1707 if (!mr->umem || is_odp_mr(mr) || is_dmabuf_mr(mr))
1711 * Only one active MR can refer to a umem at one time, revoke
1712 * the old MR before assigning the umem to the new one.
1714 err = mlx5r_umr_revoke_mr(mr);
1716 return ERR_PTR(err);
1719 atomic_sub(ib_umem_num_pages(umem), &dev->mdev->priv.reg_pages);
1721 return create_real_mr(new_pd, umem, mr->ibmr.iova,
1726 * DM doesn't have a PAS list so we can't re-use it, odp/dmabuf does
1727 * but the logic around releasing the umem is different
1729 if (!mr->umem || is_odp_mr(mr) || is_dmabuf_mr(mr))
1732 if (!(new_access_flags & IB_ACCESS_ON_DEMAND) &&
1733 can_use_umr_rereg_access(dev, mr->access_flags, new_access_flags)) {
1734 struct ib_umem *new_umem;
1735 unsigned long page_size;
1737 new_umem = ib_umem_get(&dev->ib_dev, start, length,
1739 if (IS_ERR(new_umem))
1740 return ERR_CAST(new_umem);
1742 /* Fast path for PAS change */
1743 if (can_use_umr_rereg_pas(mr, new_umem, new_access_flags, iova,
1745 err = umr_rereg_pas(mr, new_pd, new_access_flags, flags,
1746 new_umem, iova, page_size);
1748 ib_umem_release(new_umem);
1749 return ERR_PTR(err);
1753 return create_real_mr(new_pd, new_umem, iova, new_access_flags);
1757 * Everything else has no state we can preserve, just create a new MR
1761 return mlx5_ib_reg_user_mr(new_pd, start, length, iova,
1762 new_access_flags, udata);
1766 mlx5_alloc_priv_descs(struct ib_device *device,
1767 struct mlx5_ib_mr *mr,
1771 struct mlx5_ib_dev *dev = to_mdev(device);
1772 struct device *ddev = &dev->mdev->pdev->dev;
1773 int size = ndescs * desc_size;
1777 add_size = max_t(int, MLX5_UMR_ALIGN - ARCH_KMALLOC_MINALIGN, 0);
1778 if (is_power_of_2(MLX5_UMR_ALIGN) && add_size) {
1779 int end = max_t(int, MLX5_UMR_ALIGN, roundup_pow_of_two(size));
1781 add_size = min_t(int, end - size, add_size);
1784 mr->descs_alloc = kzalloc(size + add_size, GFP_KERNEL);
1785 if (!mr->descs_alloc)
1788 mr->descs = PTR_ALIGN(mr->descs_alloc, MLX5_UMR_ALIGN);
1790 mr->desc_map = dma_map_single(ddev, mr->descs, size, DMA_TO_DEVICE);
1791 if (dma_mapping_error(ddev, mr->desc_map)) {
1798 kfree(mr->descs_alloc);
1804 mlx5_free_priv_descs(struct mlx5_ib_mr *mr)
1806 if (!mr->umem && mr->descs) {
1807 struct ib_device *device = mr->ibmr.device;
1808 int size = mr->max_descs * mr->desc_size;
1809 struct mlx5_ib_dev *dev = to_mdev(device);
1811 dma_unmap_single(&dev->mdev->pdev->dev, mr->desc_map, size,
1813 kfree(mr->descs_alloc);
1818 static int cache_ent_find_and_store(struct mlx5_ib_dev *dev,
1819 struct mlx5_ib_mr *mr)
1821 struct mlx5_mkey_cache *cache = &dev->cache;
1822 struct mlx5_cache_ent *ent;
1825 if (mr->mmkey.cache_ent) {
1826 xa_lock_irq(&mr->mmkey.cache_ent->mkeys);
1827 mr->mmkey.cache_ent->in_use--;
1831 mutex_lock(&cache->rb_lock);
1832 ent = mkey_cache_ent_from_rb_key(dev, mr->mmkey.rb_key);
1834 if (ent->rb_key.ndescs == mr->mmkey.rb_key.ndescs) {
1835 if (ent->disabled) {
1836 mutex_unlock(&cache->rb_lock);
1839 mr->mmkey.cache_ent = ent;
1840 xa_lock_irq(&mr->mmkey.cache_ent->mkeys);
1841 mutex_unlock(&cache->rb_lock);
1846 ent = mlx5r_cache_create_ent_locked(dev, mr->mmkey.rb_key, false);
1847 mutex_unlock(&cache->rb_lock);
1849 return PTR_ERR(ent);
1851 mr->mmkey.cache_ent = ent;
1852 xa_lock_irq(&mr->mmkey.cache_ent->mkeys);
1855 ret = push_mkey_locked(mr->mmkey.cache_ent, false,
1856 xa_mk_value(mr->mmkey.key));
1857 xa_unlock_irq(&mr->mmkey.cache_ent->mkeys);
1861 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata)
1863 struct mlx5_ib_mr *mr = to_mmr(ibmr);
1864 struct mlx5_ib_dev *dev = to_mdev(ibmr->device);
1868 * Any async use of the mr must hold the refcount, once the refcount
1869 * goes to zero no other thread, such as ODP page faults, prefetch, any
1870 * UMR activity, etc can touch the mkey. Thus it is safe to destroy it.
1872 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) &&
1873 refcount_read(&mr->mmkey.usecount) != 0 &&
1874 xa_erase(&mr_to_mdev(mr)->odp_mkeys, mlx5_base_mkey(mr->mmkey.key)))
1875 mlx5r_deref_wait_odp_mkey(&mr->mmkey);
1877 if (ibmr->type == IB_MR_TYPE_INTEGRITY) {
1878 xa_cmpxchg(&dev->sig_mrs, mlx5_base_mkey(mr->mmkey.key),
1879 mr->sig, NULL, GFP_KERNEL);
1882 rc = mlx5_ib_dereg_mr(&mr->mtt_mr->ibmr, NULL);
1888 rc = mlx5_ib_dereg_mr(&mr->klm_mr->ibmr, NULL);
1894 if (mlx5_core_destroy_psv(dev->mdev,
1895 mr->sig->psv_memory.psv_idx))
1896 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n",
1897 mr->sig->psv_memory.psv_idx);
1898 if (mlx5_core_destroy_psv(dev->mdev, mr->sig->psv_wire.psv_idx))
1899 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n",
1900 mr->sig->psv_wire.psv_idx);
1906 if (mr->umem && mlx5r_umr_can_load_pas(dev, mr->umem->length))
1907 if (mlx5r_umr_revoke_mr(mr) ||
1908 cache_ent_find_and_store(dev, mr))
1909 mr->mmkey.cache_ent = NULL;
1911 if (!mr->mmkey.cache_ent) {
1912 rc = destroy_mkey(to_mdev(mr->ibmr.device), mr);
1918 bool is_odp = is_odp_mr(mr);
1921 atomic_sub(ib_umem_num_pages(mr->umem),
1922 &dev->mdev->priv.reg_pages);
1923 ib_umem_release(mr->umem);
1925 mlx5_ib_free_odp_mr(mr);
1928 if (!mr->mmkey.cache_ent)
1929 mlx5_free_priv_descs(mr);
1935 static void mlx5_set_umr_free_mkey(struct ib_pd *pd, u32 *in, int ndescs,
1936 int access_mode, int page_shift)
1940 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1942 /* This is only used from the kernel, so setting the PD is OK. */
1943 set_mkc_access_pd_addr_fields(mkc, IB_ACCESS_RELAXED_ORDERING, 0, pd);
1944 MLX5_SET(mkc, mkc, free, 1);
1945 MLX5_SET(mkc, mkc, translations_octword_size, ndescs);
1946 MLX5_SET(mkc, mkc, access_mode_1_0, access_mode & 0x3);
1947 MLX5_SET(mkc, mkc, access_mode_4_2, (access_mode >> 2) & 0x7);
1948 MLX5_SET(mkc, mkc, umr_en, 1);
1949 MLX5_SET(mkc, mkc, log_page_size, page_shift);
1952 static int _mlx5_alloc_mkey_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr,
1953 int ndescs, int desc_size, int page_shift,
1954 int access_mode, u32 *in, int inlen)
1956 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1959 mr->access_mode = access_mode;
1960 mr->desc_size = desc_size;
1961 mr->max_descs = ndescs;
1963 err = mlx5_alloc_priv_descs(pd->device, mr, ndescs, desc_size);
1967 mlx5_set_umr_free_mkey(pd, in, ndescs, access_mode, page_shift);
1969 err = mlx5_ib_create_mkey(dev, &mr->mmkey, in, inlen);
1971 goto err_free_descs;
1973 mr->mmkey.type = MLX5_MKEY_MR;
1974 mr->ibmr.lkey = mr->mmkey.key;
1975 mr->ibmr.rkey = mr->mmkey.key;
1980 mlx5_free_priv_descs(mr);
1984 static struct mlx5_ib_mr *mlx5_ib_alloc_pi_mr(struct ib_pd *pd,
1985 u32 max_num_sg, u32 max_num_meta_sg,
1986 int desc_size, int access_mode)
1988 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1989 int ndescs = ALIGN(max_num_sg + max_num_meta_sg, 4);
1991 struct mlx5_ib_mr *mr;
1995 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1997 return ERR_PTR(-ENOMEM);
2000 mr->ibmr.device = pd->device;
2002 in = kzalloc(inlen, GFP_KERNEL);
2008 if (access_mode == MLX5_MKC_ACCESS_MODE_MTT)
2009 page_shift = PAGE_SHIFT;
2011 err = _mlx5_alloc_mkey_descs(pd, mr, ndescs, desc_size, page_shift,
2012 access_mode, in, inlen);
2025 return ERR_PTR(err);
2028 static int mlx5_alloc_mem_reg_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr,
2029 int ndescs, u32 *in, int inlen)
2031 return _mlx5_alloc_mkey_descs(pd, mr, ndescs, sizeof(struct mlx5_mtt),
2032 PAGE_SHIFT, MLX5_MKC_ACCESS_MODE_MTT, in,
2036 static int mlx5_alloc_sg_gaps_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr,
2037 int ndescs, u32 *in, int inlen)
2039 return _mlx5_alloc_mkey_descs(pd, mr, ndescs, sizeof(struct mlx5_klm),
2040 0, MLX5_MKC_ACCESS_MODE_KLMS, in, inlen);
2043 static int mlx5_alloc_integrity_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr,
2044 int max_num_sg, int max_num_meta_sg,
2047 struct mlx5_ib_dev *dev = to_mdev(pd->device);
2052 mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL);
2056 /* create mem & wire PSVs */
2057 err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn, 2, psv_index);
2061 mr->sig->psv_memory.psv_idx = psv_index[0];
2062 mr->sig->psv_wire.psv_idx = psv_index[1];
2064 mr->sig->sig_status_checked = true;
2065 mr->sig->sig_err_exists = false;
2066 /* Next UMR, Arm SIGERR */
2067 ++mr->sig->sigerr_count;
2068 mr->klm_mr = mlx5_ib_alloc_pi_mr(pd, max_num_sg, max_num_meta_sg,
2069 sizeof(struct mlx5_klm),
2070 MLX5_MKC_ACCESS_MODE_KLMS);
2071 if (IS_ERR(mr->klm_mr)) {
2072 err = PTR_ERR(mr->klm_mr);
2073 goto err_destroy_psv;
2075 mr->mtt_mr = mlx5_ib_alloc_pi_mr(pd, max_num_sg, max_num_meta_sg,
2076 sizeof(struct mlx5_mtt),
2077 MLX5_MKC_ACCESS_MODE_MTT);
2078 if (IS_ERR(mr->mtt_mr)) {
2079 err = PTR_ERR(mr->mtt_mr);
2080 goto err_free_klm_mr;
2083 /* Set bsf descriptors for mkey */
2084 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
2085 MLX5_SET(mkc, mkc, bsf_en, 1);
2086 MLX5_SET(mkc, mkc, bsf_octword_size, MLX5_MKEY_BSF_OCTO_SIZE);
2088 err = _mlx5_alloc_mkey_descs(pd, mr, 4, sizeof(struct mlx5_klm), 0,
2089 MLX5_MKC_ACCESS_MODE_KLMS, in, inlen);
2091 goto err_free_mtt_mr;
2093 err = xa_err(xa_store(&dev->sig_mrs, mlx5_base_mkey(mr->mmkey.key),
2094 mr->sig, GFP_KERNEL));
2096 goto err_free_descs;
2100 destroy_mkey(dev, mr);
2101 mlx5_free_priv_descs(mr);
2103 mlx5_ib_dereg_mr(&mr->mtt_mr->ibmr, NULL);
2106 mlx5_ib_dereg_mr(&mr->klm_mr->ibmr, NULL);
2109 if (mlx5_core_destroy_psv(dev->mdev, mr->sig->psv_memory.psv_idx))
2110 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n",
2111 mr->sig->psv_memory.psv_idx);
2112 if (mlx5_core_destroy_psv(dev->mdev, mr->sig->psv_wire.psv_idx))
2113 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n",
2114 mr->sig->psv_wire.psv_idx);
2121 static struct ib_mr *__mlx5_ib_alloc_mr(struct ib_pd *pd,
2122 enum ib_mr_type mr_type, u32 max_num_sg,
2123 u32 max_num_meta_sg)
2125 struct mlx5_ib_dev *dev = to_mdev(pd->device);
2126 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
2127 int ndescs = ALIGN(max_num_sg, 4);
2128 struct mlx5_ib_mr *mr;
2132 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
2134 return ERR_PTR(-ENOMEM);
2136 in = kzalloc(inlen, GFP_KERNEL);
2142 mr->ibmr.device = pd->device;
2146 case IB_MR_TYPE_MEM_REG:
2147 err = mlx5_alloc_mem_reg_descs(pd, mr, ndescs, in, inlen);
2149 case IB_MR_TYPE_SG_GAPS:
2150 err = mlx5_alloc_sg_gaps_descs(pd, mr, ndescs, in, inlen);
2152 case IB_MR_TYPE_INTEGRITY:
2153 err = mlx5_alloc_integrity_descs(pd, mr, max_num_sg,
2154 max_num_meta_sg, in, inlen);
2157 mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type);
2172 return ERR_PTR(err);
2175 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
2178 return __mlx5_ib_alloc_mr(pd, mr_type, max_num_sg, 0);
2181 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd,
2182 u32 max_num_sg, u32 max_num_meta_sg)
2184 return __mlx5_ib_alloc_mr(pd, IB_MR_TYPE_INTEGRITY, max_num_sg,
2188 int mlx5_ib_alloc_mw(struct ib_mw *ibmw, struct ib_udata *udata)
2190 struct mlx5_ib_dev *dev = to_mdev(ibmw->device);
2191 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
2192 struct mlx5_ib_mw *mw = to_mmw(ibmw);
2193 unsigned int ndescs;
2197 struct mlx5_ib_alloc_mw req = {};
2200 __u32 response_length;
2203 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
2207 if (req.comp_mask || req.reserved1 || req.reserved2)
2210 if (udata->inlen > sizeof(req) &&
2211 !ib_is_udata_cleared(udata, sizeof(req),
2212 udata->inlen - sizeof(req)))
2215 ndescs = req.num_klms ? roundup(req.num_klms, 4) : roundup(1, 4);
2217 in = kzalloc(inlen, GFP_KERNEL);
2221 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
2223 MLX5_SET(mkc, mkc, free, 1);
2224 MLX5_SET(mkc, mkc, translations_octword_size, ndescs);
2225 MLX5_SET(mkc, mkc, pd, to_mpd(ibmw->pd)->pdn);
2226 MLX5_SET(mkc, mkc, umr_en, 1);
2227 MLX5_SET(mkc, mkc, lr, 1);
2228 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS);
2229 MLX5_SET(mkc, mkc, en_rinval, !!((ibmw->type == IB_MW_TYPE_2)));
2230 MLX5_SET(mkc, mkc, qpn, 0xffffff);
2232 err = mlx5_ib_create_mkey(dev, &mw->mmkey, in, inlen);
2236 mw->mmkey.type = MLX5_MKEY_MW;
2237 ibmw->rkey = mw->mmkey.key;
2238 mw->mmkey.ndescs = ndescs;
2240 resp.response_length =
2241 min(offsetofend(typeof(resp), response_length), udata->outlen);
2242 if (resp.response_length) {
2243 err = ib_copy_to_udata(udata, &resp, resp.response_length);
2248 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
2249 err = mlx5r_store_odp_mkey(dev, &mw->mmkey);
2258 mlx5_core_destroy_mkey(dev->mdev, mw->mmkey.key);
2264 int mlx5_ib_dealloc_mw(struct ib_mw *mw)
2266 struct mlx5_ib_dev *dev = to_mdev(mw->device);
2267 struct mlx5_ib_mw *mmw = to_mmw(mw);
2269 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) &&
2270 xa_erase(&dev->odp_mkeys, mlx5_base_mkey(mmw->mmkey.key)))
2272 * pagefault_single_data_segment() may be accessing mmw
2273 * if the user bound an ODP MR to this MW.
2275 mlx5r_deref_wait_odp_mkey(&mmw->mmkey);
2277 return mlx5_core_destroy_mkey(dev->mdev, mmw->mmkey.key);
2280 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
2281 struct ib_mr_status *mr_status)
2283 struct mlx5_ib_mr *mmr = to_mmr(ibmr);
2286 if (check_mask & ~IB_MR_CHECK_SIG_STATUS) {
2287 pr_err("Invalid status check mask\n");
2292 mr_status->fail_status = 0;
2293 if (check_mask & IB_MR_CHECK_SIG_STATUS) {
2296 pr_err("signature status check requested on a non-signature enabled MR\n");
2300 mmr->sig->sig_status_checked = true;
2301 if (!mmr->sig->sig_err_exists)
2304 if (ibmr->lkey == mmr->sig->err_item.key)
2305 memcpy(&mr_status->sig_err, &mmr->sig->err_item,
2306 sizeof(mr_status->sig_err));
2308 mr_status->sig_err.err_type = IB_SIG_BAD_GUARD;
2309 mr_status->sig_err.sig_err_offset = 0;
2310 mr_status->sig_err.key = mmr->sig->err_item.key;
2313 mmr->sig->sig_err_exists = false;
2314 mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS;
2322 mlx5_ib_map_pa_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
2323 int data_sg_nents, unsigned int *data_sg_offset,
2324 struct scatterlist *meta_sg, int meta_sg_nents,
2325 unsigned int *meta_sg_offset)
2327 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2328 unsigned int sg_offset = 0;
2331 mr->meta_length = 0;
2332 if (data_sg_nents == 1) {
2334 mr->mmkey.ndescs = 1;
2336 sg_offset = *data_sg_offset;
2337 mr->data_length = sg_dma_len(data_sg) - sg_offset;
2338 mr->data_iova = sg_dma_address(data_sg) + sg_offset;
2339 if (meta_sg_nents == 1) {
2341 mr->meta_ndescs = 1;
2343 sg_offset = *meta_sg_offset;
2346 mr->meta_length = sg_dma_len(meta_sg) - sg_offset;
2347 mr->pi_iova = sg_dma_address(meta_sg) + sg_offset;
2349 ibmr->length = mr->data_length + mr->meta_length;
2356 mlx5_ib_sg_to_klms(struct mlx5_ib_mr *mr,
2357 struct scatterlist *sgl,
2358 unsigned short sg_nents,
2359 unsigned int *sg_offset_p,
2360 struct scatterlist *meta_sgl,
2361 unsigned short meta_sg_nents,
2362 unsigned int *meta_sg_offset_p)
2364 struct scatterlist *sg = sgl;
2365 struct mlx5_klm *klms = mr->descs;
2366 unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0;
2367 u32 lkey = mr->ibmr.pd->local_dma_lkey;
2370 mr->ibmr.iova = sg_dma_address(sg) + sg_offset;
2371 mr->ibmr.length = 0;
2373 for_each_sg(sgl, sg, sg_nents, i) {
2374 if (unlikely(i >= mr->max_descs))
2376 klms[i].va = cpu_to_be64(sg_dma_address(sg) + sg_offset);
2377 klms[i].bcount = cpu_to_be32(sg_dma_len(sg) - sg_offset);
2378 klms[i].key = cpu_to_be32(lkey);
2379 mr->ibmr.length += sg_dma_len(sg) - sg_offset;
2385 *sg_offset_p = sg_offset;
2387 mr->mmkey.ndescs = i;
2388 mr->data_length = mr->ibmr.length;
2390 if (meta_sg_nents) {
2392 sg_offset = meta_sg_offset_p ? *meta_sg_offset_p : 0;
2393 for_each_sg(meta_sgl, sg, meta_sg_nents, j) {
2394 if (unlikely(i + j >= mr->max_descs))
2396 klms[i + j].va = cpu_to_be64(sg_dma_address(sg) +
2398 klms[i + j].bcount = cpu_to_be32(sg_dma_len(sg) -
2400 klms[i + j].key = cpu_to_be32(lkey);
2401 mr->ibmr.length += sg_dma_len(sg) - sg_offset;
2405 if (meta_sg_offset_p)
2406 *meta_sg_offset_p = sg_offset;
2408 mr->meta_ndescs = j;
2409 mr->meta_length = mr->ibmr.length - mr->data_length;
2415 static int mlx5_set_page(struct ib_mr *ibmr, u64 addr)
2417 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2420 if (unlikely(mr->mmkey.ndescs == mr->max_descs))
2424 descs[mr->mmkey.ndescs++] = cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR);
2429 static int mlx5_set_page_pi(struct ib_mr *ibmr, u64 addr)
2431 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2434 if (unlikely(mr->mmkey.ndescs + mr->meta_ndescs == mr->max_descs))
2438 descs[mr->mmkey.ndescs + mr->meta_ndescs++] =
2439 cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR);
2445 mlx5_ib_map_mtt_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
2446 int data_sg_nents, unsigned int *data_sg_offset,
2447 struct scatterlist *meta_sg, int meta_sg_nents,
2448 unsigned int *meta_sg_offset)
2450 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2451 struct mlx5_ib_mr *pi_mr = mr->mtt_mr;
2454 pi_mr->mmkey.ndescs = 0;
2455 pi_mr->meta_ndescs = 0;
2456 pi_mr->meta_length = 0;
2458 ib_dma_sync_single_for_cpu(ibmr->device, pi_mr->desc_map,
2459 pi_mr->desc_size * pi_mr->max_descs,
2462 pi_mr->ibmr.page_size = ibmr->page_size;
2463 n = ib_sg_to_pages(&pi_mr->ibmr, data_sg, data_sg_nents, data_sg_offset,
2465 if (n != data_sg_nents)
2468 pi_mr->data_iova = pi_mr->ibmr.iova;
2469 pi_mr->data_length = pi_mr->ibmr.length;
2470 pi_mr->ibmr.length = pi_mr->data_length;
2471 ibmr->length = pi_mr->data_length;
2473 if (meta_sg_nents) {
2474 u64 page_mask = ~((u64)ibmr->page_size - 1);
2475 u64 iova = pi_mr->data_iova;
2477 n += ib_sg_to_pages(&pi_mr->ibmr, meta_sg, meta_sg_nents,
2478 meta_sg_offset, mlx5_set_page_pi);
2480 pi_mr->meta_length = pi_mr->ibmr.length;
2482 * PI address for the HW is the offset of the metadata address
2483 * relative to the first data page address.
2484 * It equals to first data page address + size of data pages +
2485 * metadata offset at the first metadata page
2487 pi_mr->pi_iova = (iova & page_mask) +
2488 pi_mr->mmkey.ndescs * ibmr->page_size +
2489 (pi_mr->ibmr.iova & ~page_mask);
2491 * In order to use one MTT MR for data and metadata, we register
2492 * also the gaps between the end of the data and the start of
2493 * the metadata (the sig MR will verify that the HW will access
2494 * to right addresses). This mapping is safe because we use
2495 * internal mkey for the registration.
2497 pi_mr->ibmr.length = pi_mr->pi_iova + pi_mr->meta_length - iova;
2498 pi_mr->ibmr.iova = iova;
2499 ibmr->length += pi_mr->meta_length;
2502 ib_dma_sync_single_for_device(ibmr->device, pi_mr->desc_map,
2503 pi_mr->desc_size * pi_mr->max_descs,
2510 mlx5_ib_map_klm_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
2511 int data_sg_nents, unsigned int *data_sg_offset,
2512 struct scatterlist *meta_sg, int meta_sg_nents,
2513 unsigned int *meta_sg_offset)
2515 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2516 struct mlx5_ib_mr *pi_mr = mr->klm_mr;
2519 pi_mr->mmkey.ndescs = 0;
2520 pi_mr->meta_ndescs = 0;
2521 pi_mr->meta_length = 0;
2523 ib_dma_sync_single_for_cpu(ibmr->device, pi_mr->desc_map,
2524 pi_mr->desc_size * pi_mr->max_descs,
2527 n = mlx5_ib_sg_to_klms(pi_mr, data_sg, data_sg_nents, data_sg_offset,
2528 meta_sg, meta_sg_nents, meta_sg_offset);
2530 ib_dma_sync_single_for_device(ibmr->device, pi_mr->desc_map,
2531 pi_mr->desc_size * pi_mr->max_descs,
2534 /* This is zero-based memory region */
2535 pi_mr->data_iova = 0;
2536 pi_mr->ibmr.iova = 0;
2537 pi_mr->pi_iova = pi_mr->data_length;
2538 ibmr->length = pi_mr->ibmr.length;
2543 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
2544 int data_sg_nents, unsigned int *data_sg_offset,
2545 struct scatterlist *meta_sg, int meta_sg_nents,
2546 unsigned int *meta_sg_offset)
2548 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2549 struct mlx5_ib_mr *pi_mr = NULL;
2552 WARN_ON(ibmr->type != IB_MR_TYPE_INTEGRITY);
2554 mr->mmkey.ndescs = 0;
2555 mr->data_length = 0;
2557 mr->meta_ndescs = 0;
2560 * As a performance optimization, if possible, there is no need to
2561 * perform UMR operation to register the data/metadata buffers.
2562 * First try to map the sg lists to PA descriptors with local_dma_lkey.
2563 * Fallback to UMR only in case of a failure.
2565 n = mlx5_ib_map_pa_mr_sg_pi(ibmr, data_sg, data_sg_nents,
2566 data_sg_offset, meta_sg, meta_sg_nents,
2568 if (n == data_sg_nents + meta_sg_nents)
2571 * As a performance optimization, if possible, there is no need to map
2572 * the sg lists to KLM descriptors. First try to map the sg lists to MTT
2573 * descriptors and fallback to KLM only in case of a failure.
2574 * It's more efficient for the HW to work with MTT descriptors
2575 * (especially in high load).
2576 * Use KLM (indirect access) only if it's mandatory.
2579 n = mlx5_ib_map_mtt_mr_sg_pi(ibmr, data_sg, data_sg_nents,
2580 data_sg_offset, meta_sg, meta_sg_nents,
2582 if (n == data_sg_nents + meta_sg_nents)
2586 n = mlx5_ib_map_klm_mr_sg_pi(ibmr, data_sg, data_sg_nents,
2587 data_sg_offset, meta_sg, meta_sg_nents,
2589 if (unlikely(n != data_sg_nents + meta_sg_nents))
2593 /* This is zero-based memory region */
2597 ibmr->sig_attrs->meta_length = pi_mr->meta_length;
2599 ibmr->sig_attrs->meta_length = mr->meta_length;
2604 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
2605 unsigned int *sg_offset)
2607 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2610 mr->mmkey.ndescs = 0;
2612 ib_dma_sync_single_for_cpu(ibmr->device, mr->desc_map,
2613 mr->desc_size * mr->max_descs,
2616 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
2617 n = mlx5_ib_sg_to_klms(mr, sg, sg_nents, sg_offset, NULL, 0,
2620 n = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset,
2623 ib_dma_sync_single_for_device(ibmr->device, mr->desc_map,
2624 mr->desc_size * mr->max_descs,