drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/errno.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/slab.h>
  40 #if defined(CONFIG_X86)
  41 #include <asm/pat.h>
  42 #endif
  43 #include <linux/sched.h>
  44 #include <linux/sched/mm.h>
  45 #include <linux/sched/task.h>
  46 #include <linux/delay.h>
  47 #include <rdma/ib_user_verbs.h>
  48 #include <rdma/ib_addr.h>
  49 #include <rdma/ib_cache.h>
  50 #include <linux/mlx5/port.h>
  51 #include <linux/mlx5/vport.h>
  52 #include <linux/list.h>
  53 #include <rdma/ib_smi.h>
  54 #include <rdma/ib_umem.h>
  55 #include <linux/in.h>
  56 #include <linux/etherdevice.h>
  57 #include <linux/mlx5/fs.h>
  58 #include <linux/mlx5/vport.h>
  59 #include "mlx5_ib.h"
  60 #include "cmd.h"
  61 #include <linux/mlx5/vport.h>
  62
  63 #define DRIVER_NAME "mlx5_ib"
  64 #define DRIVER_VERSION "5.0-0"
  65
  66 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  67 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  68 MODULE_LICENSE("Dual BSD/GPL");
  69 MODULE_VERSION(DRIVER_VERSION);
  70
  71 static char mlx5_version[] =
  72         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  73         DRIVER_VERSION "\n";
  74
  75 enum {
  76         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  77 };
  78
  79 static enum rdma_link_layer
  80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  81 {
  82         switch (port_type_cap) {
  83         case MLX5_CAP_PORT_TYPE_IB:
  84                 return IB_LINK_LAYER_INFINIBAND;
  85         case MLX5_CAP_PORT_TYPE_ETH:
  86                 return IB_LINK_LAYER_ETHERNET;
  87         default:
  88                 return IB_LINK_LAYER_UNSPECIFIED;
  89         }
  90 }
  91
  92 static enum rdma_link_layer
  93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  94 {
  95         struct mlx5_ib_dev *dev = to_mdev(device);
  96         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  97
  98         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  99 }
 100
 101 static int get_port_state(struct ib_device *ibdev,
 102                           u8 port_num,
 103                           enum ib_port_state *state)
 104 {
 105         struct ib_port_attr attr;
 106         int ret;
 107
 108         memset(&attr, 0, sizeof(attr));
 109         ret = mlx5_ib_query_port(ibdev, port_num, &attr);
 110         if (!ret)
 111                 *state = attr.state;
 112         return ret;
 113 }
 114
 115 static int mlx5_netdev_event(struct notifier_block *this,
 116                              unsigned long event, void *ptr)
 117 {
 118         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 119         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 120                                                  roce.nb);
 121
 122         switch (event) {
 123         case NETDEV_REGISTER:
 124         case NETDEV_UNREGISTER:
 125                 write_lock(&ibdev->roce.netdev_lock);
 126                 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
 127                         ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
 128                                              NULL : ndev;
 129                 write_unlock(&ibdev->roce.netdev_lock);
 130                 break;
 131
 132         case NETDEV_CHANGE:
 133         case NETDEV_UP:
 134         case NETDEV_DOWN: {
 135                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 136                 struct net_device *upper = NULL;
 137
 138                 if (lag_ndev) {
 139                         upper = netdev_master_upper_dev_get(lag_ndev);
 140                         dev_put(lag_ndev);
 141                 }
 142
 143                 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
 144                     && ibdev->ib_active) {
 145                         struct ib_event ibev = { };
 146                         enum ib_port_state port_state;
 147
 148                         if (get_port_state(&ibdev->ib_dev, 1, &port_state))
 149                                 return NOTIFY_DONE;
 150
 151                         if (ibdev->roce.last_port_state == port_state)
 152                                 return NOTIFY_DONE;
 153
 154                         ibdev->roce.last_port_state = port_state;
 155                         ibev.device = &ibdev->ib_dev;
 156                         if (port_state == IB_PORT_DOWN)
 157                                 ibev.event = IB_EVENT_PORT_ERR;
 158                         else if (port_state == IB_PORT_ACTIVE)
 159                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 160                         else
 161                                 return NOTIFY_DONE;
 162
 163                         ibev.element.port_num = 1;
 164                         ib_dispatch_event(&ibev);
 165                 }
 166                 break;
 167         }
 168
 169         default:
 170                 break;
 171         }
 172
 173         return NOTIFY_DONE;
 174 }
 175
 176 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 177                                              u8 port_num)
 178 {
 179         struct mlx5_ib_dev *ibdev = to_mdev(device);
 180         struct net_device *ndev;
 181
 182         ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 183         if (ndev)
 184                 return ndev;
 185
 186         /* Ensure ndev does not disappear before we invoke dev_hold()
 187          */
 188         read_lock(&ibdev->roce.netdev_lock);
 189         ndev = ibdev->roce.netdev;
 190         if (ndev)
 191                 dev_hold(ndev);
 192         read_unlock(&ibdev->roce.netdev_lock);
 193
 194         return ndev;
 195 }
 196
 197 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 198                                     u8 *active_width)
 199 {
 200         switch (eth_proto_oper) {
 201         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 202         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 203         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 204         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 205                 *active_width = IB_WIDTH_1X;
 206                 *active_speed = IB_SPEED_SDR;
 207                 break;
 208         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 209         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 210         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 211         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 212         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 213         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 214         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 215                 *active_width = IB_WIDTH_1X;
 216                 *active_speed = IB_SPEED_QDR;
 217                 break;
 218         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 219         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 220         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 221                 *active_width = IB_WIDTH_1X;
 222                 *active_speed = IB_SPEED_EDR;
 223                 break;
 224         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 225         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 226         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 227         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 228                 *active_width = IB_WIDTH_4X;
 229                 *active_speed = IB_SPEED_QDR;
 230                 break;
 231         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 232         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 233         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 234                 *active_width = IB_WIDTH_1X;
 235                 *active_speed = IB_SPEED_HDR;
 236                 break;
 237         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 238                 *active_width = IB_WIDTH_4X;
 239                 *active_speed = IB_SPEED_FDR;
 240                 break;
 241         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 242         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 243         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 244         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 245                 *active_width = IB_WIDTH_4X;
 246                 *active_speed = IB_SPEED_EDR;
 247                 break;
 248         default:
 249                 return -EINVAL;
 250         }
 251
 252         return 0;
 253 }
 254
 255 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 256                                 struct ib_port_attr *props)
 257 {
 258         struct mlx5_ib_dev *dev = to_mdev(device);
 259         struct mlx5_core_dev *mdev = dev->mdev;
 260         struct net_device *ndev, *upper;
 261         enum ib_mtu ndev_ib_mtu;
 262         u16 qkey_viol_cntr;
 263         u32 eth_prot_oper;
 264         int err;
 265
 266         /* Possible bad flows are checked before filling out props so in case
 267          * of an error it will still be zeroed out.
 268          */
 269         err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
 270         if (err)
 271                 return err;
 272
 273         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 274                                  &props->active_width);
 275
 276         props->port_cap_flags  |= IB_PORT_CM_SUP;
 277         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 278
 279         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 280                                                 roce_address_table_size);
 281         props->max_mtu          = IB_MTU_4096;
 282         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 283         props->pkey_tbl_len     = 1;
 284         props->state            = IB_PORT_DOWN;
 285         props->phys_state       = 3;
 286
 287         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 288         props->qkey_viol_cntr = qkey_viol_cntr;
 289
 290         ndev = mlx5_ib_get_netdev(device, port_num);
 291         if (!ndev)
 292                 return 0;
 293
 294         if (mlx5_lag_is_active(dev->mdev)) {
 295                 rcu_read_lock();
 296                 upper = netdev_master_upper_dev_get_rcu(ndev);
 297                 if (upper) {
 298                         dev_put(ndev);
 299                         ndev = upper;
 300                         dev_hold(ndev);
 301                 }
 302                 rcu_read_unlock();
 303         }
 304
 305         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 306                 props->state      = IB_PORT_ACTIVE;
 307                 props->phys_state = 5;
 308         }
 309
 310         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 311
 312         dev_put(ndev);
 313
 314         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 315         return 0;
 316 }
 317
 318 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 319                          unsigned int index, const union ib_gid *gid,
 320                          const struct ib_gid_attr *attr)
 321 {
 322         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 323         u8 roce_version = 0;
 324         u8 roce_l3_type = 0;
 325         bool vlan = false;
 326         u8 mac[ETH_ALEN];
 327         u16 vlan_id = 0;
 328
 329         if (gid) {
 330                 gid_type = attr->gid_type;
 331                 ether_addr_copy(mac, attr->ndev->dev_addr);
 332
 333                 if (is_vlan_dev(attr->ndev)) {
 334                         vlan = true;
 335                         vlan_id = vlan_dev_vlan_id(attr->ndev);
 336                 }
 337         }
 338
 339         switch (gid_type) {
 340         case IB_GID_TYPE_IB:
 341                 roce_version = MLX5_ROCE_VERSION_1;
 342                 break;
 343         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 344                 roce_version = MLX5_ROCE_VERSION_2;
 345                 if (ipv6_addr_v4mapped((void *)gid))
 346                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 347                 else
 348                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 349                 break;
 350
 351         default:
 352                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 353         }
 354
 355         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 356                                       roce_l3_type, gid->raw, mac, vlan,
 357                                       vlan_id);
 358 }
 359
 360 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 361                            unsigned int index, const union ib_gid *gid,
 362                            const struct ib_gid_attr *attr,
 363                            __always_unused void **context)
 364 {
 365         return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
 366 }
 367
 368 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 369                            unsigned int index, __always_unused void **context)
 370 {
 371         return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
 372 }
 373
 374 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 375                                int index)
 376 {
 377         struct ib_gid_attr attr;
 378         union ib_gid gid;
 379
 380         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 381                 return 0;
 382
 383         if (!attr.ndev)
 384                 return 0;
 385
 386         dev_put(attr.ndev);
 387
 388         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 389                 return 0;
 390
 391         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 392 }
 393
 394 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
 395                            int index, enum ib_gid_type *gid_type)
 396 {
 397         struct ib_gid_attr attr;
 398         union ib_gid gid;
 399         int ret;
 400
 401         ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
 402         if (ret)
 403                 return ret;
 404
 405         if (!attr.ndev)
 406                 return -ENODEV;
 407
 408         dev_put(attr.ndev);
 409
 410         *gid_type = attr.gid_type;
 411
 412         return 0;
 413 }
 414
 415 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 416 {
 417         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 418                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 419         return 0;
 420 }
 421
 422 enum {
 423         MLX5_VPORT_ACCESS_METHOD_MAD,
 424         MLX5_VPORT_ACCESS_METHOD_HCA,
 425         MLX5_VPORT_ACCESS_METHOD_NIC,
 426 };
 427
 428 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 429 {
 430         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 431                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 432
 433         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 434             IB_LINK_LAYER_ETHERNET)
 435                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 436
 437         return MLX5_VPORT_ACCESS_METHOD_HCA;
 438 }
 439
 440 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 441                             struct ib_device_attr *props)
 442 {
 443         u8 tmp;
 444         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 445         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 446         u8 atomic_req_8B_endianness_mode =
 447                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 448
 449         /* Check if HW supports 8 bytes standard atomic operations and capable
 450          * of host endianness respond
 451          */
 452         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 453         if (((atomic_operations & tmp) == tmp) &&
 454             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 455             (atomic_req_8B_endianness_mode)) {
 456                 props->atomic_cap = IB_ATOMIC_HCA;
 457         } else {
 458                 props->atomic_cap = IB_ATOMIC_NONE;
 459         }
 460 }
 461
 462 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 463                                         __be64 *sys_image_guid)
 464 {
 465         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 466         struct mlx5_core_dev *mdev = dev->mdev;
 467         u64 tmp;
 468         int err;
 469
 470         switch (mlx5_get_vport_access_method(ibdev)) {
 471         case MLX5_VPORT_ACCESS_METHOD_MAD:
 472                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 473                                                             sys_image_guid);
 474
 475         case MLX5_VPORT_ACCESS_METHOD_HCA:
 476                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 477                 break;
 478
 479         case MLX5_VPORT_ACCESS_METHOD_NIC:
 480                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 481                 break;
 482
 483         default:
 484                 return -EINVAL;
 485         }
 486
 487         if (!err)
 488                 *sys_image_guid = cpu_to_be64(tmp);
 489
 490         return err;
 491
 492 }
 493
 494 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 495                                 u16 *max_pkeys)
 496 {
 497         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 498         struct mlx5_core_dev *mdev = dev->mdev;
 499
 500         switch (mlx5_get_vport_access_method(ibdev)) {
 501         case MLX5_VPORT_ACCESS_METHOD_MAD:
 502                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 503
 504         case MLX5_VPORT_ACCESS_METHOD_HCA:
 505         case MLX5_VPORT_ACCESS_METHOD_NIC:
 506                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 507                                                 pkey_table_size));
 508                 return 0;
 509
 510         default:
 511                 return -EINVAL;
 512         }
 513 }
 514
 515 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 516                                 u32 *vendor_id)
 517 {
 518         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 519
 520         switch (mlx5_get_vport_access_method(ibdev)) {
 521         case MLX5_VPORT_ACCESS_METHOD_MAD:
 522                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 523
 524         case MLX5_VPORT_ACCESS_METHOD_HCA:
 525         case MLX5_VPORT_ACCESS_METHOD_NIC:
 526                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 527
 528         default:
 529                 return -EINVAL;
 530         }
 531 }
 532
 533 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 534                                 __be64 *node_guid)
 535 {
 536         u64 tmp;
 537         int err;
 538
 539         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 540         case MLX5_VPORT_ACCESS_METHOD_MAD:
 541                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 542
 543         case MLX5_VPORT_ACCESS_METHOD_HCA:
 544                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 545                 break;
 546
 547         case MLX5_VPORT_ACCESS_METHOD_NIC:
 548                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 549                 break;
 550
 551         default:
 552                 return -EINVAL;
 553         }
 554
 555         if (!err)
 556                 *node_guid = cpu_to_be64(tmp);
 557
 558         return err;
 559 }
 560
 561 struct mlx5_reg_node_desc {
 562         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 563 };
 564
 565 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 566 {
 567         struct mlx5_reg_node_desc in;
 568
 569         if (mlx5_use_mad_ifc(dev))
 570                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 571
 572         memset(&in, 0, sizeof(in));
 573
 574         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 575                                     sizeof(struct mlx5_reg_node_desc),
 576                                     MLX5_REG_NODE_DESC, 0, 0);
 577 }
 578
 579 static int mlx5_ib_query_device(struct ib_device *ibdev,
 580                                 struct ib_device_attr *props,
 581                                 struct ib_udata *uhw)
 582 {
 583         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 584         struct mlx5_core_dev *mdev = dev->mdev;
 585         int err = -ENOMEM;
 586         int max_sq_desc;
 587         int max_rq_sg;
 588         int max_sq_sg;
 589         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 590         struct mlx5_ib_query_device_resp resp = {};
 591         size_t resp_len;
 592         u64 max_tso;
 593
 594         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 595         if (uhw->outlen && uhw->outlen < resp_len)
 596                 return -EINVAL;
 597         else
 598                 resp.response_length = resp_len;
 599
 600         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 601                 return -EINVAL;
 602
 603         memset(props, 0, sizeof(*props));
 604         err = mlx5_query_system_image_guid(ibdev,
 605                                            &props->sys_image_guid);
 606         if (err)
 607                 return err;
 608
 609         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 610         if (err)
 611                 return err;
 612
 613         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 614         if (err)
 615                 return err;
 616
 617         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 618                 (fw_rev_min(dev->mdev) << 16) |
 619                 fw_rev_sub(dev->mdev);
 620         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 621                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 622                 IB_DEVICE_SYS_IMAGE_GUID                |
 623                 IB_DEVICE_RC_RNR_NAK_GEN;
 624
 625         if (MLX5_CAP_GEN(mdev, pkv))
 626                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 627         if (MLX5_CAP_GEN(mdev, qkv))
 628                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 629         if (MLX5_CAP_GEN(mdev, apm))
 630                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 631         if (MLX5_CAP_GEN(mdev, xrc))
 632                 props->device_cap_flags |= IB_DEVICE_XRC;
 633         if (MLX5_CAP_GEN(mdev, imaicl)) {
 634                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 635                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 636                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 637                 /* We support 'Gappy' memory registration too */
 638                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 639         }
 640         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 641         if (MLX5_CAP_GEN(mdev, sho)) {
 642                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 643                 /* At this stage no support for signature handover */
 644                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 645                                       IB_PROT_T10DIF_TYPE_2 |
 646                                       IB_PROT_T10DIF_TYPE_3;
 647                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 648                                        IB_GUARD_T10DIF_CSUM;
 649         }
 650         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 651                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 652
 653         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
 654                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 655                         /* Legacy bit to support old userspace libraries */
 656                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 657                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 658                 }
 659
 660                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 661                         props->raw_packet_caps |=
 662                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 663
 664                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 665                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 666                         if (max_tso) {
 667                                 resp.tso_caps.max_tso = 1 << max_tso;
 668                                 resp.tso_caps.supported_qpts |=
 669                                         1 << IB_QPT_RAW_PACKET;
 670                                 resp.response_length += sizeof(resp.tso_caps);
 671                         }
 672                 }
 673
 674                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 675                         resp.rss_caps.rx_hash_function =
 676                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 677                         resp.rss_caps.rx_hash_fields_mask =
 678                                                 MLX5_RX_HASH_SRC_IPV4 |
 679                                                 MLX5_RX_HASH_DST_IPV4 |
 680                                                 MLX5_RX_HASH_SRC_IPV6 |
 681                                                 MLX5_RX_HASH_DST_IPV6 |
 682                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 683                                                 MLX5_RX_HASH_DST_PORT_TCP |
 684                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 685                                                 MLX5_RX_HASH_DST_PORT_UDP;
 686                         resp.response_length += sizeof(resp.rss_caps);
 687                 }
 688         } else {
 689                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 690                         resp.response_length += sizeof(resp.tso_caps);
 691                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 692                         resp.response_length += sizeof(resp.rss_caps);
 693         }
 694
 695         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 696                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 697                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 698         }
 699
 700         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 701             MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
 702                 /* Legacy bit to support old userspace libraries */
 703                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 704                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 705         }
 706
 707         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 708                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 709
 710         props->vendor_part_id      = mdev->pdev->device;
 711         props->hw_ver              = mdev->pdev->revision;
 712
 713         props->max_mr_size         = ~0ull;
 714         props->page_size_cap       = ~(min_page_size - 1);
 715         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 716         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 717         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 718                      sizeof(struct mlx5_wqe_data_seg);
 719         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 720         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 721                      sizeof(struct mlx5_wqe_raddr_seg)) /
 722                 sizeof(struct mlx5_wqe_data_seg);
 723         props->max_sge = min(max_rq_sg, max_sq_sg);
 724         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 725         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 726         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 727         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 728         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 729         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 730         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 731         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 732         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 733         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 734         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 735         props->max_srq_sge         = max_rq_sg - 1;
 736         props->max_fast_reg_page_list_len =
 737                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 738         get_atomic_caps(dev, props);
 739         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 740         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 741         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 742         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 743                                            props->max_mcast_grp;
 744         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 745         props->max_ah = INT_MAX;
 746         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 747         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 748
 749 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 750         if (MLX5_CAP_GEN(mdev, pg))
 751                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 752         props->odp_caps = dev->odp_caps;
 753 #endif
 754
 755         if (MLX5_CAP_GEN(mdev, cd))
 756                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 757
 758         if (!mlx5_core_is_pf(mdev))
 759                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 760
 761         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 762             IB_LINK_LAYER_ETHERNET) {
 763                 props->rss_caps.max_rwq_indirection_tables =
 764                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 765                 props->rss_caps.max_rwq_indirection_table_size =
 766                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 767                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 768                 props->max_wq_type_rq =
 769                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 770         }
 771
 772         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
 773                 resp.cqe_comp_caps.max_num =
 774                         MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
 775                         MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
 776                 resp.cqe_comp_caps.supported_format =
 777                         MLX5_IB_CQE_RES_FORMAT_HASH |
 778                         MLX5_IB_CQE_RES_FORMAT_CSUM;
 779                 resp.response_length += sizeof(resp.cqe_comp_caps);
 780         }
 781
 782         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
 783                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
 784                     MLX5_CAP_GEN(mdev, qos)) {
 785                         resp.packet_pacing_caps.qp_rate_limit_max =
 786                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
 787                         resp.packet_pacing_caps.qp_rate_limit_min =
 788                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
 789                         resp.packet_pacing_caps.supported_qpts |=
 790                                 1 << IB_QPT_RAW_PACKET;
 791                 }
 792                 resp.response_length += sizeof(resp.packet_pacing_caps);
 793         }
 794
 795         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
 796                         uhw->outlen)) {
 797                 resp.mlx5_ib_support_multi_pkt_send_wqes =
 798                         MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
 799                 resp.response_length +=
 800                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
 801         }
 802
 803         if (field_avail(typeof(resp), reserved, uhw->outlen))
 804                 resp.response_length += sizeof(resp.reserved);
 805
 806         if (uhw->outlen) {
 807                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
 808
 809                 if (err)
 810                         return err;
 811         }
 812
 813         return 0;
 814 }
 815
 816 enum mlx5_ib_width {
 817         MLX5_IB_WIDTH_1X        = 1 << 0,
 818         MLX5_IB_WIDTH_2X        = 1 << 1,
 819         MLX5_IB_WIDTH_4X        = 1 << 2,
 820         MLX5_IB_WIDTH_8X        = 1 << 3,
 821         MLX5_IB_WIDTH_12X       = 1 << 4
 822 };
 823
 824 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 825                                   u8 *ib_width)
 826 {
 827         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 828         int err = 0;
 829
 830         if (active_width & MLX5_IB_WIDTH_1X) {
 831                 *ib_width = IB_WIDTH_1X;
 832         } else if (active_width & MLX5_IB_WIDTH_2X) {
 833                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 834                             (int)active_width);
 835                 err = -EINVAL;
 836         } else if (active_width & MLX5_IB_WIDTH_4X) {
 837                 *ib_width = IB_WIDTH_4X;
 838         } else if (active_width & MLX5_IB_WIDTH_8X) {
 839                 *ib_width = IB_WIDTH_8X;
 840         } else if (active_width & MLX5_IB_WIDTH_12X) {
 841                 *ib_width = IB_WIDTH_12X;
 842         } else {
 843                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 844                             (int)active_width);
 845                 err = -EINVAL;
 846         }
 847
 848         return err;
 849 }
 850
 851 static int mlx5_mtu_to_ib_mtu(int mtu)
 852 {
 853         switch (mtu) {
 854         case 256: return 1;
 855         case 512: return 2;
 856         case 1024: return 3;
 857         case 2048: return 4;
 858         case 4096: return 5;
 859         default:
 860                 pr_warn("invalid mtu\n");
 861                 return -1;
 862         }
 863 }
 864
 865 enum ib_max_vl_num {
 866         __IB_MAX_VL_0           = 1,
 867         __IB_MAX_VL_0_1         = 2,
 868         __IB_MAX_VL_0_3         = 3,
 869         __IB_MAX_VL_0_7         = 4,
 870         __IB_MAX_VL_0_14        = 5,
 871 };
 872
 873 enum mlx5_vl_hw_cap {
 874         MLX5_VL_HW_0    = 1,
 875         MLX5_VL_HW_0_1  = 2,
 876         MLX5_VL_HW_0_2  = 3,
 877         MLX5_VL_HW_0_3  = 4,
 878         MLX5_VL_HW_0_4  = 5,
 879         MLX5_VL_HW_0_5  = 6,
 880         MLX5_VL_HW_0_6  = 7,
 881         MLX5_VL_HW_0_7  = 8,
 882         MLX5_VL_HW_0_14 = 15
 883 };
 884
 885 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 886                                 u8 *max_vl_num)
 887 {
 888         switch (vl_hw_cap) {
 889         case MLX5_VL_HW_0:
 890                 *max_vl_num = __IB_MAX_VL_0;
 891                 break;
 892         case MLX5_VL_HW_0_1:
 893                 *max_vl_num = __IB_MAX_VL_0_1;
 894                 break;
 895         case MLX5_VL_HW_0_3:
 896                 *max_vl_num = __IB_MAX_VL_0_3;
 897                 break;
 898         case MLX5_VL_HW_0_7:
 899                 *max_vl_num = __IB_MAX_VL_0_7;
 900                 break;
 901         case MLX5_VL_HW_0_14:
 902                 *max_vl_num = __IB_MAX_VL_0_14;
 903                 break;
 904
 905         default:
 906                 return -EINVAL;
 907         }
 908
 909         return 0;
 910 }
 911
 912 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
 913                                struct ib_port_attr *props)
 914 {
 915         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 916         struct mlx5_core_dev *mdev = dev->mdev;
 917         struct mlx5_hca_vport_context *rep;
 918         u16 max_mtu;
 919         u16 oper_mtu;
 920         int err;
 921         u8 ib_link_width_oper;
 922         u8 vl_hw_cap;
 923
 924         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
 925         if (!rep) {
 926                 err = -ENOMEM;
 927                 goto out;
 928         }
 929
 930         /* props being zeroed by the caller, avoid zeroing it here */
 931
 932         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
 933         if (err)
 934                 goto out;
 935
 936         props->lid              = rep->lid;
 937         props->lmc              = rep->lmc;
 938         props->sm_lid           = rep->sm_lid;
 939         props->sm_sl            = rep->sm_sl;
 940         props->state            = rep->vport_state;
 941         props->phys_state       = rep->port_physical_state;
 942         props->port_cap_flags   = rep->cap_mask1;
 943         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
 944         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
 945         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
 946         props->bad_pkey_cntr    = rep->pkey_violation_counter;
 947         props->qkey_viol_cntr   = rep->qkey_violation_counter;
 948         props->subnet_timeout   = rep->subnet_timeout;
 949         props->init_type_reply  = rep->init_type_reply;
 950         props->grh_required     = rep->grh_required;
 951
 952         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
 953         if (err)
 954                 goto out;
 955
 956         err = translate_active_width(ibdev, ib_link_width_oper,
 957                                      &props->active_width);
 958         if (err)
 959                 goto out;
 960         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
 961         if (err)
 962                 goto out;
 963
 964         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
 965
 966         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
 967
 968         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
 969
 970         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
 971
 972         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
 973         if (err)
 974                 goto out;
 975
 976         err = translate_max_vl_num(ibdev, vl_hw_cap,
 977                                    &props->max_vl_num);
 978 out:
 979         kfree(rep);
 980         return err;
 981 }
 982
 983 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 984                        struct ib_port_attr *props)
 985 {
 986         unsigned int count;
 987         int ret;
 988
 989         switch (mlx5_get_vport_access_method(ibdev)) {
 990         case MLX5_VPORT_ACCESS_METHOD_MAD:
 991                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
 992                 break;
 993
 994         case MLX5_VPORT_ACCESS_METHOD_HCA:
 995                 ret = mlx5_query_hca_port(ibdev, port, props);
 996                 break;
 997
 998         case MLX5_VPORT_ACCESS_METHOD_NIC:
 999                 ret = mlx5_query_port_roce(ibdev, port, props);
1000                 break;
1001
1002         default:
1003                 ret = -EINVAL;
1004         }
1005
1006         if (!ret && props) {
1007                 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
1008                 props->gid_tbl_len -= count;
1009         }
1010         return ret;
1011 }
1012
1013 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1014                              union ib_gid *gid)
1015 {
1016         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1017         struct mlx5_core_dev *mdev = dev->mdev;
1018
1019         switch (mlx5_get_vport_access_method(ibdev)) {
1020         case MLX5_VPORT_ACCESS_METHOD_MAD:
1021                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1022
1023         case MLX5_VPORT_ACCESS_METHOD_HCA:
1024                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1025
1026         default:
1027                 return -EINVAL;
1028         }
1029
1030 }
1031
1032 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1033                               u16 *pkey)
1034 {
1035         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1036         struct mlx5_core_dev *mdev = dev->mdev;
1037
1038         switch (mlx5_get_vport_access_method(ibdev)) {
1039         case MLX5_VPORT_ACCESS_METHOD_MAD:
1040                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1041
1042         case MLX5_VPORT_ACCESS_METHOD_HCA:
1043         case MLX5_VPORT_ACCESS_METHOD_NIC:
1044                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
1045                                                  pkey);
1046         default:
1047                 return -EINVAL;
1048         }
1049 }
1050
1051 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1052                                  struct ib_device_modify *props)
1053 {
1054         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1055         struct mlx5_reg_node_desc in;
1056         struct mlx5_reg_node_desc out;
1057         int err;
1058
1059         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1060                 return -EOPNOTSUPP;
1061
1062         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1063                 return 0;
1064
1065         /*
1066          * If possible, pass node desc to FW, so it can generate
1067          * a 144 trap.  If cmd fails, just ignore.
1068          */
1069         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1070         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1071                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1072         if (err)
1073                 return err;
1074
1075         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1076
1077         return err;
1078 }
1079
1080 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1081                                 u32 value)
1082 {
1083         struct mlx5_hca_vport_context ctx = {};
1084         int err;
1085
1086         err = mlx5_query_hca_vport_context(dev->mdev, 0,
1087                                            port_num, 0, &ctx);
1088         if (err)
1089                 return err;
1090
1091         if (~ctx.cap_mask1_perm & mask) {
1092                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1093                              mask, ctx.cap_mask1_perm);
1094                 return -EINVAL;
1095         }
1096
1097         ctx.cap_mask1 = value;
1098         ctx.cap_mask1_perm = mask;
1099         err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1100                                                  port_num, 0, &ctx);
1101
1102         return err;
1103 }
1104
1105 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1106                                struct ib_port_modify *props)
1107 {
1108         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1109         struct ib_port_attr attr;
1110         u32 tmp;
1111         int err;
1112         u32 change_mask;
1113         u32 value;
1114         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1115                       IB_LINK_LAYER_INFINIBAND);
1116
1117         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1118                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1119                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1120                 return set_port_caps_atomic(dev, port, change_mask, value);
1121         }
1122
1123         mutex_lock(&dev->cap_mask_mutex);
1124
1125         err = ib_query_port(ibdev, port, &attr);
1126         if (err)
1127                 goto out;
1128
1129         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1130                 ~props->clr_port_cap_mask;
1131
1132         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1133
1134 out:
1135         mutex_unlock(&dev->cap_mask_mutex);
1136         return err;
1137 }
1138
1139 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1140 {
1141         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1142                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1143 }
1144
1145 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1146                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1147                              u32 *num_sys_pages)
1148 {
1149         int uars_per_sys_page;
1150         int bfregs_per_sys_page;
1151         int ref_bfregs = req->total_num_bfregs;
1152
1153         if (req->total_num_bfregs == 0)
1154                 return -EINVAL;
1155
1156         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1157         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1158
1159         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1160                 return -ENOMEM;
1161
1162         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1163         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1164         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1165         *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1166
1167         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1168                 return -EINVAL;
1169
1170         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n",
1171                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1172                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1173                     req->total_num_bfregs, *num_sys_pages);
1174
1175         return 0;
1176 }
1177
1178 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1179 {
1180         struct mlx5_bfreg_info *bfregi;
1181         int err;
1182         int i;
1183
1184         bfregi = &context->bfregi;
1185         for (i = 0; i < bfregi->num_sys_pages; i++) {
1186                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1187                 if (err)
1188                         goto error;
1189
1190                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1191         }
1192         return 0;
1193
1194 error:
1195         for (--i; i >= 0; i--)
1196                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1197                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1198
1199         return err;
1200 }
1201
1202 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1203 {
1204         struct mlx5_bfreg_info *bfregi;
1205         int err;
1206         int i;
1207
1208         bfregi = &context->bfregi;
1209         for (i = 0; i < bfregi->num_sys_pages; i++) {
1210                 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1211                 if (err) {
1212                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1213                         return err;
1214                 }
1215         }
1216         return 0;
1217 }
1218
1219 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1220 {
1221         int err;
1222
1223         err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1224         if (err)
1225                 return err;
1226
1227         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1228             !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1229                 return err;
1230
1231         mutex_lock(&dev->lb_mutex);
1232         dev->user_td++;
1233
1234         if (dev->user_td == 2)
1235                 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1236
1237         mutex_unlock(&dev->lb_mutex);
1238         return err;
1239 }
1240
1241 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1242 {
1243         mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1244
1245         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1246             !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1247                 return;
1248
1249         mutex_lock(&dev->lb_mutex);
1250         dev->user_td--;
1251
1252         if (dev->user_td < 2)
1253                 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1254
1255         mutex_unlock(&dev->lb_mutex);
1256 }
1257
1258 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1259                                                   struct ib_udata *udata)
1260 {
1261         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1262         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1263         struct mlx5_ib_alloc_ucontext_resp resp = {};
1264         struct mlx5_ib_ucontext *context;
1265         struct mlx5_bfreg_info *bfregi;
1266         int ver;
1267         int err;
1268         size_t reqlen;
1269         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1270                                      max_cqe_version);
1271         bool lib_uar_4k;
1272
1273         if (!dev->ib_active)
1274                 return ERR_PTR(-EAGAIN);
1275
1276         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1277                 return ERR_PTR(-EINVAL);
1278
1279         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1280         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1281                 ver = 0;
1282         else if (reqlen >= min_req_v2)
1283                 ver = 2;
1284         else
1285                 return ERR_PTR(-EINVAL);
1286
1287         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
1288         if (err)
1289                 return ERR_PTR(err);
1290
1291         if (req.flags)
1292                 return ERR_PTR(-EINVAL);
1293
1294         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1295                 return ERR_PTR(-EOPNOTSUPP);
1296
1297         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1298                                     MLX5_NON_FP_BFREGS_PER_UAR);
1299         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1300                 return ERR_PTR(-EINVAL);
1301
1302         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1303         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1304                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1305         resp.cache_line_size = cache_line_size();
1306         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1307         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1308         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1309         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1310         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1311         resp.cqe_version = min_t(__u8,
1312                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1313                                  req.max_cqe_version);
1314         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1315                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1316         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1317                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1318         resp.response_length = min(offsetof(typeof(resp), response_length) +
1319                                    sizeof(resp.response_length), udata->outlen);
1320
1321         context = kzalloc(sizeof(*context), GFP_KERNEL);
1322         if (!context)
1323                 return ERR_PTR(-ENOMEM);
1324
1325         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1326         bfregi = &context->bfregi;
1327
1328         /* updates req->total_num_bfregs */
1329         err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1330         if (err)
1331                 goto out_ctx;
1332
1333         mutex_init(&bfregi->lock);
1334         bfregi->lib_uar_4k = lib_uar_4k;
1335         bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
1336                                 GFP_KERNEL);
1337         if (!bfregi->count) {
1338                 err = -ENOMEM;
1339                 goto out_ctx;
1340         }
1341
1342         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1343                                     sizeof(*bfregi->sys_pages),
1344                                     GFP_KERNEL);
1345         if (!bfregi->sys_pages) {
1346                 err = -ENOMEM;
1347                 goto out_count;
1348         }
1349
1350         err = allocate_uars(dev, context);
1351         if (err)
1352                 goto out_sys_pages;
1353
1354 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1355         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1356 #endif
1357
1358         context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1359         if (!context->upd_xlt_page) {
1360                 err = -ENOMEM;
1361                 goto out_uars;
1362         }
1363         mutex_init(&context->upd_xlt_page_mutex);
1364
1365         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1366                 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1367                 if (err)
1368                         goto out_page;
1369         }
1370
1371         INIT_LIST_HEAD(&context->vma_private_list);
1372         INIT_LIST_HEAD(&context->db_page_list);
1373         mutex_init(&context->db_page_mutex);
1374
1375         resp.tot_bfregs = req.total_num_bfregs;
1376         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1377
1378         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1379                 resp.response_length += sizeof(resp.cqe_version);
1380
1381         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1382                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1383                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1384                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1385         }
1386
1387         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1388                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1389                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1390                         resp.eth_min_inline++;
1391                 }
1392                 resp.response_length += sizeof(resp.eth_min_inline);
1393         }
1394
1395         /*
1396          * We don't want to expose information from the PCI bar that is located
1397          * after 4096 bytes, so if the arch only supports larger pages, let's
1398          * pretend we don't support reading the HCA's core clock. This is also
1399          * forced by mmap function.
1400          */
1401         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1402                 if (PAGE_SIZE <= 4096) {
1403                         resp.comp_mask |=
1404                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1405                         resp.hca_core_clock_offset =
1406                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1407                 }
1408                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1409                                         sizeof(resp.reserved2);
1410         }
1411
1412         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1413                 resp.response_length += sizeof(resp.log_uar_size);
1414
1415         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1416                 resp.response_length += sizeof(resp.num_uars_per_page);
1417
1418         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1419         if (err)
1420                 goto out_td;
1421
1422         bfregi->ver = ver;
1423         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1424         context->cqe_version = resp.cqe_version;
1425         context->lib_caps = req.lib_caps;
1426         print_lib_caps(dev, context->lib_caps);
1427
1428         return &context->ibucontext;
1429
1430 out_td:
1431         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1432                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1433
1434 out_page:
1435         free_page(context->upd_xlt_page);
1436
1437 out_uars:
1438         deallocate_uars(dev, context);
1439
1440 out_sys_pages:
1441         kfree(bfregi->sys_pages);
1442
1443 out_count:
1444         kfree(bfregi->count);
1445
1446 out_ctx:
1447         kfree(context);
1448
1449         return ERR_PTR(err);
1450 }
1451
1452 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1453 {
1454         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1455         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1456         struct mlx5_bfreg_info *bfregi;
1457
1458         bfregi = &context->bfregi;
1459         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1460                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1461
1462         free_page(context->upd_xlt_page);
1463         deallocate_uars(dev, context);
1464         kfree(bfregi->sys_pages);
1465         kfree(bfregi->count);
1466         kfree(context);
1467
1468         return 0;
1469 }
1470
1471 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1472                                  struct mlx5_bfreg_info *bfregi,
1473                                  int idx)
1474 {
1475         int fw_uars_per_page;
1476
1477         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1478
1479         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1480                         bfregi->sys_pages[idx] / fw_uars_per_page;
1481 }
1482
1483 static int get_command(unsigned long offset)
1484 {
1485         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1486 }
1487
1488 static int get_arg(unsigned long offset)
1489 {
1490         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1491 }
1492
1493 static int get_index(unsigned long offset)
1494 {
1495         return get_arg(offset);
1496 }
1497
1498 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1499 {
1500         /* vma_open is called when a new VMA is created on top of our VMA.  This
1501          * is done through either mremap flow or split_vma (usually due to
1502          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1503          * as this VMA is strongly hardware related.  Therefore we set the
1504          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1505          * calling us again and trying to do incorrect actions.  We assume that
1506          * the original VMA size is exactly a single page, and therefore all
1507          * "splitting" operation will not happen to it.
1508          */
1509         area->vm_ops = NULL;
1510 }
1511
1512 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1513 {
1514         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1515
1516         /* It's guaranteed that all VMAs opened on a FD are closed before the
1517          * file itself is closed, therefore no sync is needed with the regular
1518          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1519          * However need a sync with accessing the vma as part of
1520          * mlx5_ib_disassociate_ucontext.
1521          * The close operation is usually called under mm->mmap_sem except when
1522          * process is exiting.
1523          * The exiting case is handled explicitly as part of
1524          * mlx5_ib_disassociate_ucontext.
1525          */
1526         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1527
1528         /* setting the vma context pointer to null in the mlx5_ib driver's
1529          * private data, to protect a race condition in
1530          * mlx5_ib_disassociate_ucontext().
1531          */
1532         mlx5_ib_vma_priv_data->vma = NULL;
1533         list_del(&mlx5_ib_vma_priv_data->list);
1534         kfree(mlx5_ib_vma_priv_data);
1535 }
1536
1537 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1538         .open = mlx5_ib_vma_open,
1539         .close = mlx5_ib_vma_close
1540 };
1541
1542 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1543                                 struct mlx5_ib_ucontext *ctx)
1544 {
1545         struct mlx5_ib_vma_private_data *vma_prv;
1546         struct list_head *vma_head = &ctx->vma_private_list;
1547
1548         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1549         if (!vma_prv)
1550                 return -ENOMEM;
1551
1552         vma_prv->vma = vma;
1553         vma->vm_private_data = vma_prv;
1554         vma->vm_ops =  &mlx5_ib_vm_ops;
1555
1556         list_add(&vma_prv->list, vma_head);
1557
1558         return 0;
1559 }
1560
1561 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1562 {
1563         int ret;
1564         struct vm_area_struct *vma;
1565         struct mlx5_ib_vma_private_data *vma_private, *n;
1566         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1567         struct task_struct *owning_process  = NULL;
1568         struct mm_struct   *owning_mm       = NULL;
1569
1570         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1571         if (!owning_process)
1572                 return;
1573
1574         owning_mm = get_task_mm(owning_process);
1575         if (!owning_mm) {
1576                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1577                 while (1) {
1578                         put_task_struct(owning_process);
1579                         usleep_range(1000, 2000);
1580                         owning_process = get_pid_task(ibcontext->tgid,
1581                                                       PIDTYPE_PID);
1582                         if (!owning_process ||
1583                             owning_process->state == TASK_DEAD) {
1584                                 pr_info("disassociate ucontext done, task was terminated\n");
1585                                 /* in case task was dead need to release the
1586                                  * task struct.
1587                                  */
1588                                 if (owning_process)
1589                                         put_task_struct(owning_process);
1590                                 return;
1591                         }
1592                 }
1593         }
1594
1595         /* need to protect from a race on closing the vma as part of
1596          * mlx5_ib_vma_close.
1597          */
1598         down_write(&owning_mm->mmap_sem);
1599         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1600                                  list) {
1601                 vma = vma_private->vma;
1602                 ret = zap_vma_ptes(vma, vma->vm_start,
1603                                    PAGE_SIZE);
1604                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1605                 /* context going to be destroyed, should
1606                  * not access ops any more.
1607                  */
1608                 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1609                 vma->vm_ops = NULL;
1610                 list_del(&vma_private->list);
1611                 kfree(vma_private);
1612         }
1613         up_write(&owning_mm->mmap_sem);
1614         mmput(owning_mm);
1615         put_task_struct(owning_process);
1616 }
1617
1618 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1619 {
1620         switch (cmd) {
1621         case MLX5_IB_MMAP_WC_PAGE:
1622                 return "WC";
1623         case MLX5_IB_MMAP_REGULAR_PAGE:
1624                 return "best effort WC";
1625         case MLX5_IB_MMAP_NC_PAGE:
1626                 return "NC";
1627         default:
1628                 return NULL;
1629         }
1630 }
1631
1632 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1633                     struct vm_area_struct *vma,
1634                     struct mlx5_ib_ucontext *context)
1635 {
1636         struct mlx5_bfreg_info *bfregi = &context->bfregi;
1637         int err;
1638         unsigned long idx;
1639         phys_addr_t pfn, pa;
1640         pgprot_t prot;
1641         int uars_per_page;
1642
1643         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1644                 return -EINVAL;
1645
1646         uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1647         idx = get_index(vma->vm_pgoff);
1648         if (idx % uars_per_page ||
1649             idx * uars_per_page >= bfregi->num_sys_pages) {
1650                 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1651                 return -EINVAL;
1652         }
1653
1654         switch (cmd) {
1655         case MLX5_IB_MMAP_WC_PAGE:
1656 /* Some architectures don't support WC memory */
1657 #if defined(CONFIG_X86)
1658                 if (!pat_enabled())
1659                         return -EPERM;
1660 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1661                         return -EPERM;
1662 #endif
1663         /* fall through */
1664         case MLX5_IB_MMAP_REGULAR_PAGE:
1665                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1666                 prot = pgprot_writecombine(vma->vm_page_prot);
1667                 break;
1668         case MLX5_IB_MMAP_NC_PAGE:
1669                 prot = pgprot_noncached(vma->vm_page_prot);
1670                 break;
1671         default:
1672                 return -EINVAL;
1673         }
1674
1675         pfn = uar_index2pfn(dev, bfregi, idx);
1676         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1677
1678         vma->vm_page_prot = prot;
1679         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1680                                  PAGE_SIZE, vma->vm_page_prot);
1681         if (err) {
1682                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1683                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1684                 return -EAGAIN;
1685         }
1686
1687         pa = pfn << PAGE_SHIFT;
1688         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1689                     vma->vm_start, &pa);
1690
1691         return mlx5_ib_set_vma_data(vma, context);
1692 }
1693
1694 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1695 {
1696         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1697         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1698         unsigned long command;
1699         phys_addr_t pfn;
1700
1701         command = get_command(vma->vm_pgoff);
1702         switch (command) {
1703         case MLX5_IB_MMAP_WC_PAGE:
1704         case MLX5_IB_MMAP_NC_PAGE:
1705         case MLX5_IB_MMAP_REGULAR_PAGE:
1706                 return uar_mmap(dev, command, vma, context);
1707
1708         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1709                 return -ENOSYS;
1710
1711         case MLX5_IB_MMAP_CORE_CLOCK:
1712                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1713                         return -EINVAL;
1714
1715                 if (vma->vm_flags & VM_WRITE)
1716                         return -EPERM;
1717
1718                 /* Don't expose to user-space information it shouldn't have */
1719                 if (PAGE_SIZE > 4096)
1720                         return -EOPNOTSUPP;
1721
1722                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1723                 pfn = (dev->mdev->iseg_base +
1724                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1725                         PAGE_SHIFT;
1726                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1727                                        PAGE_SIZE, vma->vm_page_prot))
1728                         return -EAGAIN;
1729
1730                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1731                             vma->vm_start,
1732                             (unsigned long long)pfn << PAGE_SHIFT);
1733                 break;
1734
1735         default:
1736                 return -EINVAL;
1737         }
1738
1739         return 0;
1740 }
1741
1742 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1743                                       struct ib_ucontext *context,
1744                                       struct ib_udata *udata)
1745 {
1746         struct mlx5_ib_alloc_pd_resp resp;
1747         struct mlx5_ib_pd *pd;
1748         int err;
1749
1750         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1751         if (!pd)
1752                 return ERR_PTR(-ENOMEM);
1753
1754         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1755         if (err) {
1756                 kfree(pd);
1757                 return ERR_PTR(err);
1758         }
1759
1760         if (context) {
1761                 resp.pdn = pd->pdn;
1762                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1763                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1764                         kfree(pd);
1765                         return ERR_PTR(-EFAULT);
1766                 }
1767         }
1768
1769         return &pd->ibpd;
1770 }
1771
1772 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1773 {
1774         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1775         struct mlx5_ib_pd *mpd = to_mpd(pd);
1776
1777         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1778         kfree(mpd);
1779
1780         return 0;
1781 }
1782
1783 enum {
1784         MATCH_CRITERIA_ENABLE_OUTER_BIT,
1785         MATCH_CRITERIA_ENABLE_MISC_BIT,
1786         MATCH_CRITERIA_ENABLE_INNER_BIT
1787 };
1788
1789 #define HEADER_IS_ZERO(match_criteria, headers)                            \
1790         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1791                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
1792
1793 static u8 get_match_criteria_enable(u32 *match_criteria)
1794 {
1795         u8 match_criteria_enable;
1796
1797         match_criteria_enable =
1798                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1799                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1800         match_criteria_enable |=
1801                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1802                 MATCH_CRITERIA_ENABLE_MISC_BIT;
1803         match_criteria_enable |=
1804                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1805                 MATCH_CRITERIA_ENABLE_INNER_BIT;
1806
1807         return match_criteria_enable;
1808 }
1809
1810 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1811 {
1812         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1813         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1814 }
1815
1816 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1817                            bool inner)
1818 {
1819         if (inner) {
1820                 MLX5_SET(fte_match_set_misc,
1821                          misc_c, inner_ipv6_flow_label, mask);
1822                 MLX5_SET(fte_match_set_misc,
1823                          misc_v, inner_ipv6_flow_label, val);
1824         } else {
1825                 MLX5_SET(fte_match_set_misc,
1826                          misc_c, outer_ipv6_flow_label, mask);
1827                 MLX5_SET(fte_match_set_misc,
1828                          misc_v, outer_ipv6_flow_label, val);
1829         }
1830 }
1831
1832 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1833 {
1834         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1835         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1836         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1837         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1838 }
1839
1840 #define LAST_ETH_FIELD vlan_tag
1841 #define LAST_IB_FIELD sl
1842 #define LAST_IPV4_FIELD tos
1843 #define LAST_IPV6_FIELD traffic_class
1844 #define LAST_TCP_UDP_FIELD src_port
1845 #define LAST_TUNNEL_FIELD tunnel_id
1846 #define LAST_FLOW_TAG_FIELD tag_id
1847 #define LAST_DROP_FIELD size
1848
1849 /* Field is the last supported field */
1850 #define FIELDS_NOT_SUPPORTED(filter, field)\
1851         memchr_inv((void *)&filter.field  +\
1852                    sizeof(filter.field), 0,\
1853                    sizeof(filter) -\
1854                    offsetof(typeof(filter), field) -\
1855                    sizeof(filter.field))
1856
1857 #define IPV4_VERSION 4
1858 #define IPV6_VERSION 6
1859 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
1860                            u32 *match_v, const union ib_flow_spec *ib_spec,
1861                            u32 *tag_id, bool *is_drop)
1862 {
1863         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1864                                            misc_parameters);
1865         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1866                                            misc_parameters);
1867         void *headers_c;
1868         void *headers_v;
1869         int match_ipv;
1870
1871         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1872                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1873                                          inner_headers);
1874                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1875                                          inner_headers);
1876                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1877                                         ft_field_support.inner_ip_version);
1878         } else {
1879                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1880                                          outer_headers);
1881                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1882                                          outer_headers);
1883                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1884                                         ft_field_support.outer_ip_version);
1885         }
1886
1887         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
1888         case IB_FLOW_SPEC_ETH:
1889                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1890                         return -EOPNOTSUPP;
1891
1892                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1893                                              dmac_47_16),
1894                                 ib_spec->eth.mask.dst_mac);
1895                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1896                                              dmac_47_16),
1897                                 ib_spec->eth.val.dst_mac);
1898
1899                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1900                                              smac_47_16),
1901                                 ib_spec->eth.mask.src_mac);
1902                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1903                                              smac_47_16),
1904                                 ib_spec->eth.val.src_mac);
1905
1906                 if (ib_spec->eth.mask.vlan_tag) {
1907                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1908                                  cvlan_tag, 1);
1909                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1910                                  cvlan_tag, 1);
1911
1912                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1913                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1914                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1915                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1916
1917                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1918                                  first_cfi,
1919                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1920                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1921                                  first_cfi,
1922                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1923
1924                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1925                                  first_prio,
1926                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1927                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1928                                  first_prio,
1929                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1930                 }
1931                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1932                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1933                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1934                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1935                 break;
1936         case IB_FLOW_SPEC_IPV4:
1937                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1938                         return -EOPNOTSUPP;
1939
1940                 if (match_ipv) {
1941                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1942                                  ip_version, 0xf);
1943                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1944                                  ip_version, IPV4_VERSION);
1945                 } else {
1946                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1947                                  ethertype, 0xffff);
1948                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1949                                  ethertype, ETH_P_IP);
1950                 }
1951
1952                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1953                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1954                        &ib_spec->ipv4.mask.src_ip,
1955                        sizeof(ib_spec->ipv4.mask.src_ip));
1956                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1957                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1958                        &ib_spec->ipv4.val.src_ip,
1959                        sizeof(ib_spec->ipv4.val.src_ip));
1960                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1961                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1962                        &ib_spec->ipv4.mask.dst_ip,
1963                        sizeof(ib_spec->ipv4.mask.dst_ip));
1964                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1965                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1966                        &ib_spec->ipv4.val.dst_ip,
1967                        sizeof(ib_spec->ipv4.val.dst_ip));
1968
1969                 set_tos(headers_c, headers_v,
1970                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1971
1972                 set_proto(headers_c, headers_v,
1973                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1974                 break;
1975         case IB_FLOW_SPEC_IPV6:
1976                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1977                         return -EOPNOTSUPP;
1978
1979                 if (match_ipv) {
1980                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1981                                  ip_version, 0xf);
1982                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1983                                  ip_version, IPV6_VERSION);
1984                 } else {
1985                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1986                                  ethertype, 0xffff);
1987                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1988                                  ethertype, ETH_P_IPV6);
1989                 }
1990
1991                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1992                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1993                        &ib_spec->ipv6.mask.src_ip,
1994                        sizeof(ib_spec->ipv6.mask.src_ip));
1995                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1996                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1997                        &ib_spec->ipv6.val.src_ip,
1998                        sizeof(ib_spec->ipv6.val.src_ip));
1999                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2000                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2001                        &ib_spec->ipv6.mask.dst_ip,
2002                        sizeof(ib_spec->ipv6.mask.dst_ip));
2003                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2004                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2005                        &ib_spec->ipv6.val.dst_ip,
2006                        sizeof(ib_spec->ipv6.val.dst_ip));
2007
2008                 set_tos(headers_c, headers_v,
2009                         ib_spec->ipv6.mask.traffic_class,
2010                         ib_spec->ipv6.val.traffic_class);
2011
2012                 set_proto(headers_c, headers_v,
2013                           ib_spec->ipv6.mask.next_hdr,
2014                           ib_spec->ipv6.val.next_hdr);
2015
2016                 set_flow_label(misc_params_c, misc_params_v,
2017                                ntohl(ib_spec->ipv6.mask.flow_label),
2018                                ntohl(ib_spec->ipv6.val.flow_label),
2019                                ib_spec->type & IB_FLOW_SPEC_INNER);
2020
2021                 break;
2022         case IB_FLOW_SPEC_TCP:
2023                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2024                                          LAST_TCP_UDP_FIELD))
2025                         return -EOPNOTSUPP;
2026
2027                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2028                          0xff);
2029                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2030                          IPPROTO_TCP);
2031
2032                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2033                          ntohs(ib_spec->tcp_udp.mask.src_port));
2034                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2035                          ntohs(ib_spec->tcp_udp.val.src_port));
2036
2037                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2038                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2039                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2040                          ntohs(ib_spec->tcp_udp.val.dst_port));
2041                 break;
2042         case IB_FLOW_SPEC_UDP:
2043                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2044                                          LAST_TCP_UDP_FIELD))
2045                         return -EOPNOTSUPP;
2046
2047                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2048                          0xff);
2049                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2050                          IPPROTO_UDP);
2051
2052                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2053                          ntohs(ib_spec->tcp_udp.mask.src_port));
2054                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2055                          ntohs(ib_spec->tcp_udp.val.src_port));
2056
2057                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2058                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2059                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2060                          ntohs(ib_spec->tcp_udp.val.dst_port));
2061                 break;
2062         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2063                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2064                                          LAST_TUNNEL_FIELD))
2065                         return -EOPNOTSUPP;
2066
2067                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2068                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2069                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2070                          ntohl(ib_spec->tunnel.val.tunnel_id));
2071                 break;
2072         case IB_FLOW_SPEC_ACTION_TAG:
2073                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2074                                          LAST_FLOW_TAG_FIELD))
2075                         return -EOPNOTSUPP;
2076                 if (ib_spec->flow_tag.tag_id >= BIT(24))
2077                         return -EINVAL;
2078
2079                 *tag_id = ib_spec->flow_tag.tag_id;
2080                 break;
2081         case IB_FLOW_SPEC_ACTION_DROP:
2082                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2083                                          LAST_DROP_FIELD))
2084                         return -EOPNOTSUPP;
2085                 *is_drop = true;
2086                 break;
2087         default:
2088                 return -EINVAL;
2089         }
2090
2091         return 0;
2092 }
2093
2094 /* If a flow could catch both multicast and unicast packets,
2095  * it won't fall into the multicast flow steering table and this rule
2096  * could steal other multicast packets.
2097  */
2098 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
2099 {
2100         struct ib_flow_spec_eth *eth_spec;
2101
2102         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2103             ib_attr->size < sizeof(struct ib_flow_attr) +
2104             sizeof(struct ib_flow_spec_eth) ||
2105             ib_attr->num_of_specs < 1)
2106                 return false;
2107
2108         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
2109         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
2110             eth_spec->size != sizeof(*eth_spec))
2111                 return false;
2112
2113         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2114                is_multicast_ether_addr(eth_spec->val.dst_mac);
2115 }
2116
2117 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2118                                const struct ib_flow_attr *flow_attr,
2119                                bool check_inner)
2120 {
2121         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2122         int match_ipv = check_inner ?
2123                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2124                                         ft_field_support.inner_ip_version) :
2125                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2126                                         ft_field_support.outer_ip_version);
2127         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2128         bool ipv4_spec_valid, ipv6_spec_valid;
2129         unsigned int ip_spec_type = 0;
2130         bool has_ethertype = false;
2131         unsigned int spec_index;
2132         bool mask_valid = true;
2133         u16 eth_type = 0;
2134         bool type_valid;
2135
2136         /* Validate that ethertype is correct */
2137         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2138                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2139                     ib_spec->eth.mask.ether_type) {
2140                         mask_valid = (ib_spec->eth.mask.ether_type ==
2141                                       htons(0xffff));
2142                         has_ethertype = true;
2143                         eth_type = ntohs(ib_spec->eth.val.ether_type);
2144                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2145                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2146                         ip_spec_type = ib_spec->type;
2147                 }
2148                 ib_spec = (void *)ib_spec + ib_spec->size;
2149         }
2150
2151         type_valid = (!has_ethertype) || (!ip_spec_type);
2152         if (!type_valid && mask_valid) {
2153                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2154                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2155                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2156                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2157
2158                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2159                              (((eth_type == ETH_P_MPLS_UC) ||
2160                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2161         }
2162
2163         return type_valid;
2164 }
2165
2166 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2167                           const struct ib_flow_attr *flow_attr)
2168 {
2169         return is_valid_ethertype(mdev, flow_attr, false) &&
2170                is_valid_ethertype(mdev, flow_attr, true);
2171 }
2172
2173 static void put_flow_table(struct mlx5_ib_dev *dev,
2174                            struct mlx5_ib_flow_prio *prio, bool ft_added)
2175 {
2176         prio->refcount -= !!ft_added;
2177         if (!prio->refcount) {
2178                 mlx5_destroy_flow_table(prio->flow_table);
2179                 prio->flow_table = NULL;
2180         }
2181 }
2182
2183 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2184 {
2185         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2186         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2187                                                           struct mlx5_ib_flow_handler,
2188                                                           ibflow);
2189         struct mlx5_ib_flow_handler *iter, *tmp;
2190
2191         mutex_lock(&dev->flow_db.lock);
2192
2193         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2194                 mlx5_del_flow_rules(iter->rule);
2195                 put_flow_table(dev, iter->prio, true);
2196                 list_del(&iter->list);
2197                 kfree(iter);
2198         }
2199
2200         mlx5_del_flow_rules(handler->rule);
2201         put_flow_table(dev, handler->prio, true);
2202         mutex_unlock(&dev->flow_db.lock);
2203
2204         kfree(handler);
2205
2206         return 0;
2207 }
2208
2209 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2210 {
2211         priority *= 2;
2212         if (!dont_trap)
2213                 priority++;
2214         return priority;
2215 }
2216
2217 enum flow_table_type {
2218         MLX5_IB_FT_RX,
2219         MLX5_IB_FT_TX
2220 };
2221
2222 #define MLX5_FS_MAX_TYPES        6
2223 #define MLX5_FS_MAX_ENTRIES      BIT(16)
2224 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2225                                                 struct ib_flow_attr *flow_attr,
2226                                                 enum flow_table_type ft_type)
2227 {
2228         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2229         struct mlx5_flow_namespace *ns = NULL;
2230         struct mlx5_ib_flow_prio *prio;
2231         struct mlx5_flow_table *ft;
2232         int max_table_size;
2233         int num_entries;
2234         int num_groups;
2235         int priority;
2236         int err = 0;
2237
2238         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2239                                                        log_max_ft_size));
2240         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2241                 if (flow_is_multicast_only(flow_attr) &&
2242                     !dont_trap)
2243                         priority = MLX5_IB_FLOW_MCAST_PRIO;
2244                 else
2245                         priority = ib_prio_to_core_prio(flow_attr->priority,
2246                                                         dont_trap);
2247                 ns = mlx5_get_flow_namespace(dev->mdev,
2248                                              MLX5_FLOW_NAMESPACE_BYPASS);
2249                 num_entries = MLX5_FS_MAX_ENTRIES;
2250                 num_groups = MLX5_FS_MAX_TYPES;
2251                 prio = &dev->flow_db.prios[priority];
2252         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2253                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2254                 ns = mlx5_get_flow_namespace(dev->mdev,
2255                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
2256                 build_leftovers_ft_param(&priority,
2257                                          &num_entries,
2258                                          &num_groups);
2259                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2260         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2261                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2262                                         allow_sniffer_and_nic_rx_shared_tir))
2263                         return ERR_PTR(-ENOTSUPP);
2264
2265                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2266                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2267                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2268
2269                 prio = &dev->flow_db.sniffer[ft_type];
2270                 priority = 0;
2271                 num_entries = 1;
2272                 num_groups = 1;
2273         }
2274
2275         if (!ns)
2276                 return ERR_PTR(-ENOTSUPP);
2277
2278         if (num_entries > max_table_size)
2279                 return ERR_PTR(-ENOMEM);
2280
2281         ft = prio->flow_table;
2282         if (!ft) {
2283                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2284                                                          num_entries,
2285                                                          num_groups,
2286                                                          0, 0);
2287
2288                 if (!IS_ERR(ft)) {
2289                         prio->refcount = 0;
2290                         prio->flow_table = ft;
2291                 } else {
2292                         err = PTR_ERR(ft);
2293                 }
2294         }
2295
2296         return err ? ERR_PTR(err) : prio;
2297 }
2298
2299 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2300                                                      struct mlx5_ib_flow_prio *ft_prio,
2301                                                      const struct ib_flow_attr *flow_attr,
2302                                                      struct mlx5_flow_destination *dst)
2303 {
2304         struct mlx5_flow_table  *ft = ft_prio->flow_table;
2305         struct mlx5_ib_flow_handler *handler;
2306         struct mlx5_flow_act flow_act = {0};
2307         struct mlx5_flow_spec *spec;
2308         struct mlx5_flow_destination *rule_dst = dst;
2309         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2310         unsigned int spec_index;
2311         u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2312         bool is_drop = false;
2313         int err = 0;
2314         int dest_num = 1;
2315
2316         if (!is_valid_attr(dev->mdev, flow_attr))
2317                 return ERR_PTR(-EINVAL);
2318
2319         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2320         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2321         if (!handler || !spec) {
2322                 err = -ENOMEM;
2323                 goto free;
2324         }
2325
2326         INIT_LIST_HEAD(&handler->list);
2327
2328         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2329                 err = parse_flow_attr(dev->mdev, spec->match_criteria,
2330                                       spec->match_value,
2331                                       ib_flow, &flow_tag, &is_drop);
2332                 if (err < 0)
2333                         goto free;
2334
2335                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2336         }
2337
2338         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2339         if (is_drop) {
2340                 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2341                 rule_dst = NULL;
2342                 dest_num = 0;
2343         } else {
2344                 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2345                     MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2346         }
2347
2348         if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2349             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2350              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2351                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2352                              flow_tag, flow_attr->type);
2353                 err = -EINVAL;
2354                 goto free;
2355         }
2356         flow_act.flow_tag = flow_tag;
2357         handler->rule = mlx5_add_flow_rules(ft, spec,
2358                                             &flow_act,
2359                                             rule_dst, dest_num);
2360
2361         if (IS_ERR(handler->rule)) {
2362                 err = PTR_ERR(handler->rule);
2363                 goto free;
2364         }
2365
2366         ft_prio->refcount++;
2367         handler->prio = ft_prio;
2368
2369         ft_prio->flow_table = ft;
2370 free:
2371         if (err)
2372                 kfree(handler);
2373         kvfree(spec);
2374         return err ? ERR_PTR(err) : handler;
2375 }
2376
2377 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2378                                                           struct mlx5_ib_flow_prio *ft_prio,
2379                                                           struct ib_flow_attr *flow_attr,
2380                                                           struct mlx5_flow_destination *dst)
2381 {
2382         struct mlx5_ib_flow_handler *handler_dst = NULL;
2383         struct mlx5_ib_flow_handler *handler = NULL;
2384
2385         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2386         if (!IS_ERR(handler)) {
2387                 handler_dst = create_flow_rule(dev, ft_prio,
2388                                                flow_attr, dst);
2389                 if (IS_ERR(handler_dst)) {
2390                         mlx5_del_flow_rules(handler->rule);
2391                         ft_prio->refcount--;
2392                         kfree(handler);
2393                         handler = handler_dst;
2394                 } else {
2395                         list_add(&handler_dst->list, &handler->list);
2396                 }
2397         }
2398
2399         return handler;
2400 }
2401 enum {
2402         LEFTOVERS_MC,
2403         LEFTOVERS_UC,
2404 };
2405
2406 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2407                                                           struct mlx5_ib_flow_prio *ft_prio,
2408                                                           struct ib_flow_attr *flow_attr,
2409                                                           struct mlx5_flow_destination *dst)
2410 {
2411         struct mlx5_ib_flow_handler *handler_ucast = NULL;
2412         struct mlx5_ib_flow_handler *handler = NULL;
2413
2414         static struct {
2415                 struct ib_flow_attr     flow_attr;
2416                 struct ib_flow_spec_eth eth_flow;
2417         } leftovers_specs[] = {
2418                 [LEFTOVERS_MC] = {
2419                         .flow_attr = {
2420                                 .num_of_specs = 1,
2421                                 .size = sizeof(leftovers_specs[0])
2422                         },
2423                         .eth_flow = {
2424                                 .type = IB_FLOW_SPEC_ETH,
2425                                 .size = sizeof(struct ib_flow_spec_eth),
2426                                 .mask = {.dst_mac = {0x1} },
2427                                 .val =  {.dst_mac = {0x1} }
2428                         }
2429                 },
2430                 [LEFTOVERS_UC] = {
2431                         .flow_attr = {
2432                                 .num_of_specs = 1,
2433                                 .size = sizeof(leftovers_specs[0])
2434                         },
2435                         .eth_flow = {
2436                                 .type = IB_FLOW_SPEC_ETH,
2437                                 .size = sizeof(struct ib_flow_spec_eth),
2438                                 .mask = {.dst_mac = {0x1} },
2439                                 .val = {.dst_mac = {} }
2440                         }
2441                 }
2442         };
2443
2444         handler = create_flow_rule(dev, ft_prio,
2445                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
2446                                    dst);
2447         if (!IS_ERR(handler) &&
2448             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2449                 handler_ucast = create_flow_rule(dev, ft_prio,
2450                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
2451                                                  dst);
2452                 if (IS_ERR(handler_ucast)) {
2453                         mlx5_del_flow_rules(handler->rule);
2454                         ft_prio->refcount--;
2455                         kfree(handler);
2456                         handler = handler_ucast;
2457                 } else {
2458                         list_add(&handler_ucast->list, &handler->list);
2459                 }
2460         }
2461
2462         return handler;
2463 }
2464
2465 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2466                                                         struct mlx5_ib_flow_prio *ft_rx,
2467                                                         struct mlx5_ib_flow_prio *ft_tx,
2468                                                         struct mlx5_flow_destination *dst)
2469 {
2470         struct mlx5_ib_flow_handler *handler_rx;
2471         struct mlx5_ib_flow_handler *handler_tx;
2472         int err;
2473         static const struct ib_flow_attr flow_attr  = {
2474                 .num_of_specs = 0,
2475                 .size = sizeof(flow_attr)
2476         };
2477
2478         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2479         if (IS_ERR(handler_rx)) {
2480                 err = PTR_ERR(handler_rx);
2481                 goto err;
2482         }
2483
2484         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2485         if (IS_ERR(handler_tx)) {
2486                 err = PTR_ERR(handler_tx);
2487                 goto err_tx;
2488         }
2489
2490         list_add(&handler_tx->list, &handler_rx->list);
2491
2492         return handler_rx;
2493
2494 err_tx:
2495         mlx5_del_flow_rules(handler_rx->rule);
2496         ft_rx->refcount--;
2497         kfree(handler_rx);
2498 err:
2499         return ERR_PTR(err);
2500 }
2501
2502 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2503                                            struct ib_flow_attr *flow_attr,
2504                                            int domain)
2505 {
2506         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2507         struct mlx5_ib_qp *mqp = to_mqp(qp);
2508         struct mlx5_ib_flow_handler *handler = NULL;
2509         struct mlx5_flow_destination *dst = NULL;
2510         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2511         struct mlx5_ib_flow_prio *ft_prio;
2512         int err;
2513
2514         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2515                 return ERR_PTR(-ENOMEM);
2516
2517         if (domain != IB_FLOW_DOMAIN_USER ||
2518             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2519             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2520                 return ERR_PTR(-EINVAL);
2521
2522         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2523         if (!dst)
2524                 return ERR_PTR(-ENOMEM);
2525
2526         mutex_lock(&dev->flow_db.lock);
2527
2528         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2529         if (IS_ERR(ft_prio)) {
2530                 err = PTR_ERR(ft_prio);
2531                 goto unlock;
2532         }
2533         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2534                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2535                 if (IS_ERR(ft_prio_tx)) {
2536                         err = PTR_ERR(ft_prio_tx);
2537                         ft_prio_tx = NULL;
2538                         goto destroy_ft;
2539                 }
2540         }
2541
2542         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2543         if (mqp->flags & MLX5_IB_QP_RSS)
2544                 dst->tir_num = mqp->rss_qp.tirn;
2545         else
2546                 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2547
2548         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2549                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
2550                         handler = create_dont_trap_rule(dev, ft_prio,
2551                                                         flow_attr, dst);
2552                 } else {
2553                         handler = create_flow_rule(dev, ft_prio, flow_attr,
2554                                                    dst);
2555                 }
2556         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2557                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2558                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2559                                                 dst);
2560         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2561                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2562         } else {
2563                 err = -EINVAL;
2564                 goto destroy_ft;
2565         }
2566
2567         if (IS_ERR(handler)) {
2568                 err = PTR_ERR(handler);
2569                 handler = NULL;
2570                 goto destroy_ft;
2571         }
2572
2573         mutex_unlock(&dev->flow_db.lock);
2574         kfree(dst);
2575
2576         return &handler->ibflow;
2577
2578 destroy_ft:
2579         put_flow_table(dev, ft_prio, false);
2580         if (ft_prio_tx)
2581                 put_flow_table(dev, ft_prio_tx, false);
2582 unlock:
2583         mutex_unlock(&dev->flow_db.lock);
2584         kfree(dst);
2585         kfree(handler);
2586         return ERR_PTR(err);
2587 }
2588
2589 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2590 {
2591         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2592         int err;
2593
2594         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2595         if (err)
2596                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2597                              ibqp->qp_num, gid->raw);
2598
2599         return err;
2600 }
2601
2602 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2603 {
2604         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2605         int err;
2606
2607         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2608         if (err)
2609                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2610                              ibqp->qp_num, gid->raw);
2611
2612         return err;
2613 }
2614
2615 static int init_node_data(struct mlx5_ib_dev *dev)
2616 {
2617         int err;
2618
2619         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2620         if (err)
2621                 return err;
2622
2623         dev->mdev->rev_id = dev->mdev->pdev->revision;
2624
2625         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2626 }
2627
2628 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2629                              char *buf)
2630 {
2631         struct mlx5_ib_dev *dev =
2632                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2633
2634         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2635 }
2636
2637 static ssize_t show_reg_pages(struct device *device,
2638                               struct device_attribute *attr, char *buf)
2639 {
2640         struct mlx5_ib_dev *dev =
2641                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2642
2643         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2644 }
2645
2646 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2647                         char *buf)
2648 {
2649         struct mlx5_ib_dev *dev =
2650                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2651         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2652 }
2653
2654 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2655                         char *buf)
2656 {
2657         struct mlx5_ib_dev *dev =
2658                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2659         return sprintf(buf, "%x\n", dev->mdev->rev_id);
2660 }
2661
2662 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2663                           char *buf)
2664 {
2665         struct mlx5_ib_dev *dev =
2666                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2667         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2668                        dev->mdev->board_id);
2669 }
2670
2671 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
2672 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
2673 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
2674 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2675 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2676
2677 static struct device_attribute *mlx5_class_attributes[] = {
2678         &dev_attr_hw_rev,
2679         &dev_attr_hca_type,
2680         &dev_attr_board_id,
2681         &dev_attr_fw_pages,
2682         &dev_attr_reg_pages,
2683 };
2684
2685 static void pkey_change_handler(struct work_struct *work)
2686 {
2687         struct mlx5_ib_port_resources *ports =
2688                 container_of(work, struct mlx5_ib_port_resources,
2689                              pkey_change_work);
2690
2691         mutex_lock(&ports->devr->mutex);
2692         mlx5_ib_gsi_pkey_change(ports->gsi);
2693         mutex_unlock(&ports->devr->mutex);
2694 }
2695
2696 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2697 {
2698         struct mlx5_ib_qp *mqp;
2699         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2700         struct mlx5_core_cq *mcq;
2701         struct list_head cq_armed_list;
2702         unsigned long flags_qp;
2703         unsigned long flags_cq;
2704         unsigned long flags;
2705
2706         INIT_LIST_HEAD(&cq_armed_list);
2707
2708         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2709         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2710         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2711                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2712                 if (mqp->sq.tail != mqp->sq.head) {
2713                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2714                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2715                         if (send_mcq->mcq.comp &&
2716                             mqp->ibqp.send_cq->comp_handler) {
2717                                 if (!send_mcq->mcq.reset_notify_added) {
2718                                         send_mcq->mcq.reset_notify_added = 1;
2719                                         list_add_tail(&send_mcq->mcq.reset_notify,
2720                                                       &cq_armed_list);
2721                                 }
2722                         }
2723                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2724                 }
2725                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2726                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2727                 /* no handling is needed for SRQ */
2728                 if (!mqp->ibqp.srq) {
2729                         if (mqp->rq.tail != mqp->rq.head) {
2730                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2731                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2732                                 if (recv_mcq->mcq.comp &&
2733                                     mqp->ibqp.recv_cq->comp_handler) {
2734                                         if (!recv_mcq->mcq.reset_notify_added) {
2735                                                 recv_mcq->mcq.reset_notify_added = 1;
2736                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2737                                                               &cq_armed_list);
2738                                         }
2739                                 }
2740                                 spin_unlock_irqrestore(&recv_mcq->lock,
2741                                                        flags_cq);
2742                         }
2743                 }
2744                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2745         }
2746         /*At that point all inflight post send were put to be executed as of we
2747          * lock/unlock above locks Now need to arm all involved CQs.
2748          */
2749         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2750                 mcq->comp(mcq);
2751         }
2752         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2753 }
2754
2755 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2756                           enum mlx5_dev_event event, unsigned long param)
2757 {
2758         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2759         struct ib_event ibev;
2760         bool fatal = false;
2761         u8 port = 0;
2762
2763         switch (event) {
2764         case MLX5_DEV_EVENT_SYS_ERROR:
2765                 ibev.event = IB_EVENT_DEVICE_FATAL;
2766                 mlx5_ib_handle_internal_error(ibdev);
2767                 fatal = true;
2768                 break;
2769
2770         case MLX5_DEV_EVENT_PORT_UP:
2771         case MLX5_DEV_EVENT_PORT_DOWN:
2772         case MLX5_DEV_EVENT_PORT_INITIALIZED:
2773                 port = (u8)param;
2774
2775                 /* In RoCE, port up/down events are handled in
2776                  * mlx5_netdev_event().
2777                  */
2778                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2779                         IB_LINK_LAYER_ETHERNET)
2780                         return;
2781
2782                 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2783                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2784                 break;
2785
2786         case MLX5_DEV_EVENT_LID_CHANGE:
2787                 ibev.event = IB_EVENT_LID_CHANGE;
2788                 port = (u8)param;
2789                 break;
2790
2791         case MLX5_DEV_EVENT_PKEY_CHANGE:
2792                 ibev.event = IB_EVENT_PKEY_CHANGE;
2793                 port = (u8)param;
2794
2795                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2796                 break;
2797
2798         case MLX5_DEV_EVENT_GUID_CHANGE:
2799                 ibev.event = IB_EVENT_GID_CHANGE;
2800                 port = (u8)param;
2801                 break;
2802
2803         case MLX5_DEV_EVENT_CLIENT_REREG:
2804                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2805                 port = (u8)param;
2806                 break;
2807         default:
2808                 return;
2809         }
2810
2811         ibev.device           = &ibdev->ib_dev;
2812         ibev.element.port_num = port;
2813
2814         if (port < 1 || port > ibdev->num_ports) {
2815                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2816                 return;
2817         }
2818
2819         if (ibdev->ib_active)
2820                 ib_dispatch_event(&ibev);
2821
2822         if (fatal)
2823                 ibdev->ib_active = false;
2824 }
2825
2826 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2827 {
2828         struct mlx5_hca_vport_context vport_ctx;
2829         int err;
2830         int port;
2831
2832         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2833                 dev->mdev->port_caps[port - 1].has_smi = false;
2834                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2835                     MLX5_CAP_PORT_TYPE_IB) {
2836                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2837                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2838                                                                    port, 0,
2839                                                                    &vport_ctx);
2840                                 if (err) {
2841                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2842                                                     port, err);
2843                                         return err;
2844                                 }
2845                                 dev->mdev->port_caps[port - 1].has_smi =
2846                                         vport_ctx.has_smi;
2847                         } else {
2848                                 dev->mdev->port_caps[port - 1].has_smi = true;
2849                         }
2850                 }
2851         }
2852         return 0;
2853 }
2854
2855 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2856 {
2857         int port;
2858
2859         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2860                 mlx5_query_ext_port_caps(dev, port);
2861 }
2862
2863 static int get_port_caps(struct mlx5_ib_dev *dev)
2864 {
2865         struct ib_device_attr *dprops = NULL;
2866         struct ib_port_attr *pprops = NULL;
2867         int err = -ENOMEM;
2868         int port;
2869         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2870
2871         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2872         if (!pprops)
2873                 goto out;
2874
2875         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2876         if (!dprops)
2877                 goto out;
2878
2879         err = set_has_smi_cap(dev);
2880         if (err)
2881                 goto out;
2882
2883         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2884         if (err) {
2885                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2886                 goto out;
2887         }
2888
2889         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2890                 memset(pprops, 0, sizeof(*pprops));
2891                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2892                 if (err) {
2893                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
2894                                      port, err);
2895                         break;
2896                 }
2897                 dev->mdev->port_caps[port - 1].pkey_table_len =
2898                                                 dprops->max_pkeys;
2899                 dev->mdev->port_caps[port - 1].gid_table_len =
2900                                                 pprops->gid_tbl_len;
2901                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2902                             dprops->max_pkeys, pprops->gid_tbl_len);
2903         }
2904
2905 out:
2906         kfree(pprops);
2907         kfree(dprops);
2908
2909         return err;
2910 }
2911
2912 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2913 {
2914         int err;
2915
2916         err = mlx5_mr_cache_cleanup(dev);
2917         if (err)
2918                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2919
2920         mlx5_ib_destroy_qp(dev->umrc.qp);
2921         ib_free_cq(dev->umrc.cq);
2922         ib_dealloc_pd(dev->umrc.pd);
2923 }
2924
2925 enum {
2926         MAX_UMR_WR = 128,
2927 };
2928
2929 static int create_umr_res(struct mlx5_ib_dev *dev)
2930 {
2931         struct ib_qp_init_attr *init_attr = NULL;
2932         struct ib_qp_attr *attr = NULL;
2933         struct ib_pd *pd;
2934         struct ib_cq *cq;
2935         struct ib_qp *qp;
2936         int ret;
2937
2938         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2939         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2940         if (!attr || !init_attr) {
2941                 ret = -ENOMEM;
2942                 goto error_0;
2943         }
2944
2945         pd = ib_alloc_pd(&dev->ib_dev, 0);
2946         if (IS_ERR(pd)) {
2947                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2948                 ret = PTR_ERR(pd);
2949                 goto error_0;
2950         }
2951
2952         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2953         if (IS_ERR(cq)) {
2954                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2955                 ret = PTR_ERR(cq);
2956                 goto error_2;
2957         }
2958
2959         init_attr->send_cq = cq;
2960         init_attr->recv_cq = cq;
2961         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2962         init_attr->cap.max_send_wr = MAX_UMR_WR;
2963         init_attr->cap.max_send_sge = 1;
2964         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2965         init_attr->port_num = 1;
2966         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2967         if (IS_ERR(qp)) {
2968                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2969                 ret = PTR_ERR(qp);
2970                 goto error_3;
2971         }
2972         qp->device     = &dev->ib_dev;
2973         qp->real_qp    = qp;
2974         qp->uobject    = NULL;
2975         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
2976
2977         attr->qp_state = IB_QPS_INIT;
2978         attr->port_num = 1;
2979         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2980                                 IB_QP_PORT, NULL);
2981         if (ret) {
2982                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2983                 goto error_4;
2984         }
2985
2986         memset(attr, 0, sizeof(*attr));
2987         attr->qp_state = IB_QPS_RTR;
2988         attr->path_mtu = IB_MTU_256;
2989
2990         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2991         if (ret) {
2992                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2993                 goto error_4;
2994         }
2995
2996         memset(attr, 0, sizeof(*attr));
2997         attr->qp_state = IB_QPS_RTS;
2998         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2999         if (ret) {
3000                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3001                 goto error_4;
3002         }
3003
3004         dev->umrc.qp = qp;
3005         dev->umrc.cq = cq;
3006         dev->umrc.pd = pd;
3007
3008         sema_init(&dev->umrc.sem, MAX_UMR_WR);
3009         ret = mlx5_mr_cache_init(dev);
3010         if (ret) {
3011                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3012                 goto error_4;
3013         }
3014
3015         kfree(attr);
3016         kfree(init_attr);
3017
3018         return 0;
3019
3020 error_4:
3021         mlx5_ib_destroy_qp(qp);
3022
3023 error_3:
3024         ib_free_cq(cq);
3025
3026 error_2:
3027         ib_dealloc_pd(pd);
3028
3029 error_0:
3030         kfree(attr);
3031         kfree(init_attr);
3032         return ret;
3033 }
3034
3035 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3036 {
3037         switch (umr_fence_cap) {
3038         case MLX5_CAP_UMR_FENCE_NONE:
3039                 return MLX5_FENCE_MODE_NONE;
3040         case MLX5_CAP_UMR_FENCE_SMALL:
3041                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3042         default:
3043                 return MLX5_FENCE_MODE_STRONG_ORDERING;
3044         }
3045 }
3046
3047 static int create_dev_resources(struct mlx5_ib_resources *devr)
3048 {
3049         struct ib_srq_init_attr attr;
3050         struct mlx5_ib_dev *dev;
3051         struct ib_cq_init_attr cq_attr = {.cqe = 1};
3052         int port;
3053         int ret = 0;
3054
3055         dev = container_of(devr, struct mlx5_ib_dev, devr);
3056
3057         mutex_init(&devr->mutex);
3058
3059         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3060         if (IS_ERR(devr->p0)) {
3061                 ret = PTR_ERR(devr->p0);
3062                 goto error0;
3063         }
3064         devr->p0->device  = &dev->ib_dev;
3065         devr->p0->uobject = NULL;
3066         atomic_set(&devr->p0->usecnt, 0);
3067
3068         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
3069         if (IS_ERR(devr->c0)) {
3070                 ret = PTR_ERR(devr->c0);
3071                 goto error1;
3072         }
3073         devr->c0->device        = &dev->ib_dev;
3074         devr->c0->uobject       = NULL;
3075         devr->c0->comp_handler  = NULL;
3076         devr->c0->event_handler = NULL;
3077         devr->c0->cq_context    = NULL;
3078         atomic_set(&devr->c0->usecnt, 0);
3079
3080         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3081         if (IS_ERR(devr->x0)) {
3082                 ret = PTR_ERR(devr->x0);
3083                 goto error2;
3084         }
3085         devr->x0->device = &dev->ib_dev;
3086         devr->x0->inode = NULL;
3087         atomic_set(&devr->x0->usecnt, 0);
3088         mutex_init(&devr->x0->tgt_qp_mutex);
3089         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3090
3091         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3092         if (IS_ERR(devr->x1)) {
3093                 ret = PTR_ERR(devr->x1);
3094                 goto error3;
3095         }
3096         devr->x1->device = &dev->ib_dev;
3097         devr->x1->inode = NULL;
3098         atomic_set(&devr->x1->usecnt, 0);
3099         mutex_init(&devr->x1->tgt_qp_mutex);
3100         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3101
3102         memset(&attr, 0, sizeof(attr));
3103         attr.attr.max_sge = 1;
3104         attr.attr.max_wr = 1;
3105         attr.srq_type = IB_SRQT_XRC;
3106         attr.ext.xrc.cq = devr->c0;
3107         attr.ext.xrc.xrcd = devr->x0;
3108
3109         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3110         if (IS_ERR(devr->s0)) {
3111                 ret = PTR_ERR(devr->s0);
3112                 goto error4;
3113         }
3114         devr->s0->device        = &dev->ib_dev;
3115         devr->s0->pd            = devr->p0;
3116         devr->s0->uobject       = NULL;
3117         devr->s0->event_handler = NULL;
3118         devr->s0->srq_context   = NULL;
3119         devr->s0->srq_type      = IB_SRQT_XRC;
3120         devr->s0->ext.xrc.xrcd  = devr->x0;
3121         devr->s0->ext.xrc.cq    = devr->c0;
3122         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3123         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
3124         atomic_inc(&devr->p0->usecnt);
3125         atomic_set(&devr->s0->usecnt, 0);
3126
3127         memset(&attr, 0, sizeof(attr));
3128         attr.attr.max_sge = 1;
3129         attr.attr.max_wr = 1;
3130         attr.srq_type = IB_SRQT_BASIC;
3131         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3132         if (IS_ERR(devr->s1)) {
3133                 ret = PTR_ERR(devr->s1);
3134                 goto error5;
3135         }
3136         devr->s1->device        = &dev->ib_dev;
3137         devr->s1->pd            = devr->p0;
3138         devr->s1->uobject       = NULL;
3139         devr->s1->event_handler = NULL;
3140         devr->s1->srq_context   = NULL;
3141         devr->s1->srq_type      = IB_SRQT_BASIC;
3142         devr->s1->ext.xrc.cq    = devr->c0;
3143         atomic_inc(&devr->p0->usecnt);
3144         atomic_set(&devr->s0->usecnt, 0);
3145
3146         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3147                 INIT_WORK(&devr->ports[port].pkey_change_work,
3148                           pkey_change_handler);
3149                 devr->ports[port].devr = devr;
3150         }
3151
3152         return 0;
3153
3154 error5:
3155         mlx5_ib_destroy_srq(devr->s0);
3156 error4:
3157         mlx5_ib_dealloc_xrcd(devr->x1);
3158 error3:
3159         mlx5_ib_dealloc_xrcd(devr->x0);
3160 error2:
3161         mlx5_ib_destroy_cq(devr->c0);
3162 error1:
3163         mlx5_ib_dealloc_pd(devr->p0);
3164 error0:
3165         return ret;
3166 }
3167
3168 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3169 {
3170         struct mlx5_ib_dev *dev =
3171                 container_of(devr, struct mlx5_ib_dev, devr);
3172         int port;
3173
3174         mlx5_ib_destroy_srq(devr->s1);
3175         mlx5_ib_destroy_srq(devr->s0);
3176         mlx5_ib_dealloc_xrcd(devr->x0);
3177         mlx5_ib_dealloc_xrcd(devr->x1);
3178         mlx5_ib_destroy_cq(devr->c0);
3179         mlx5_ib_dealloc_pd(devr->p0);
3180
3181         /* Make sure no change P_Key work items are still executing */
3182         for (port = 0; port < dev->num_ports; ++port)
3183                 cancel_work_sync(&devr->ports[port].pkey_change_work);
3184 }
3185
3186 static u32 get_core_cap_flags(struct ib_device *ibdev)
3187 {
3188         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3189         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3190         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3191         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3192         u32 ret = 0;
3193
3194         if (ll == IB_LINK_LAYER_INFINIBAND)
3195                 return RDMA_CORE_PORT_IBA_IB;
3196
3197         ret = RDMA_CORE_PORT_RAW_PACKET;
3198
3199         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3200                 return ret;
3201
3202         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3203                 return ret;
3204
3205         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3206                 ret |= RDMA_CORE_PORT_IBA_ROCE;
3207
3208         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3209                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3210
3211         return ret;
3212 }
3213
3214 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3215                                struct ib_port_immutable *immutable)
3216 {
3217         struct ib_port_attr attr;
3218         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3219         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3220         int err;
3221
3222         immutable->core_cap_flags = get_core_cap_flags(ibdev);
3223
3224         err = ib_query_port(ibdev, port_num, &attr);
3225         if (err)
3226                 return err;
3227
3228         immutable->pkey_tbl_len = attr.pkey_tbl_len;
3229         immutable->gid_tbl_len = attr.gid_tbl_len;
3230         immutable->core_cap_flags = get_core_cap_flags(ibdev);
3231         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3232                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3233
3234         return 0;
3235 }
3236
3237 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
3238                            size_t str_len)
3239 {
3240         struct mlx5_ib_dev *dev =
3241                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3242         snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
3243                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
3244 }
3245
3246 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3247 {
3248         struct mlx5_core_dev *mdev = dev->mdev;
3249         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3250                                                                  MLX5_FLOW_NAMESPACE_LAG);
3251         struct mlx5_flow_table *ft;
3252         int err;
3253
3254         if (!ns || !mlx5_lag_is_active(mdev))
3255                 return 0;
3256
3257         err = mlx5_cmd_create_vport_lag(mdev);
3258         if (err)
3259                 return err;
3260
3261         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3262         if (IS_ERR(ft)) {
3263                 err = PTR_ERR(ft);
3264                 goto err_destroy_vport_lag;
3265         }
3266
3267         dev->flow_db.lag_demux_ft = ft;
3268         return 0;
3269
3270 err_destroy_vport_lag:
3271         mlx5_cmd_destroy_vport_lag(mdev);
3272         return err;
3273 }
3274
3275 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3276 {
3277         struct mlx5_core_dev *mdev = dev->mdev;
3278
3279         if (dev->flow_db.lag_demux_ft) {
3280                 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3281                 dev->flow_db.lag_demux_ft = NULL;
3282
3283                 mlx5_cmd_destroy_vport_lag(mdev);
3284         }
3285 }
3286
3287 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3288 {
3289         int err;
3290
3291         dev->roce.nb.notifier_call = mlx5_netdev_event;
3292         err = register_netdevice_notifier(&dev->roce.nb);
3293         if (err) {
3294                 dev->roce.nb.notifier_call = NULL;
3295                 return err;
3296         }
3297
3298         return 0;
3299 }
3300
3301 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
3302 {
3303         if (dev->roce.nb.notifier_call) {
3304                 unregister_netdevice_notifier(&dev->roce.nb);
3305                 dev->roce.nb.notifier_call = NULL;
3306         }
3307 }
3308
3309 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3310 {
3311         int err;
3312
3313         err = mlx5_add_netdev_notifier(dev);
3314         if (err)
3315                 return err;
3316
3317         if (MLX5_CAP_GEN(dev->mdev, roce)) {
3318                 err = mlx5_nic_vport_enable_roce(dev->mdev);
3319                 if (err)
3320                         goto err_unregister_netdevice_notifier;
3321         }
3322
3323         err = mlx5_eth_lag_init(dev);
3324         if (err)
3325                 goto err_disable_roce;
3326
3327         return 0;
3328
3329 err_disable_roce:
3330         if (MLX5_CAP_GEN(dev->mdev, roce))
3331                 mlx5_nic_vport_disable_roce(dev->mdev);
3332
3333 err_unregister_netdevice_notifier:
3334         mlx5_remove_netdev_notifier(dev);
3335         return err;
3336 }
3337
3338 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3339 {
3340         mlx5_eth_lag_cleanup(dev);
3341         if (MLX5_CAP_GEN(dev->mdev, roce))
3342                 mlx5_nic_vport_disable_roce(dev->mdev);
3343 }
3344
3345 struct mlx5_ib_counter {
3346         const char *name;
3347         size_t offset;
3348 };
3349
3350 #define INIT_Q_COUNTER(_name)           \
3351         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3352
3353 static const struct mlx5_ib_counter basic_q_cnts[] = {
3354         INIT_Q_COUNTER(rx_write_requests),
3355         INIT_Q_COUNTER(rx_read_requests),
3356         INIT_Q_COUNTER(rx_atomic_requests),
3357         INIT_Q_COUNTER(out_of_buffer),
3358 };
3359
3360 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
3361         INIT_Q_COUNTER(out_of_sequence),
3362 };
3363
3364 static const struct mlx5_ib_counter retrans_q_cnts[] = {
3365         INIT_Q_COUNTER(duplicate_request),
3366         INIT_Q_COUNTER(rnr_nak_retry_err),
3367         INIT_Q_COUNTER(packet_seq_err),
3368         INIT_Q_COUNTER(implied_nak_seq_err),
3369         INIT_Q_COUNTER(local_ack_timeout_err),
3370 };
3371
3372 #define INIT_CONG_COUNTER(_name)                \
3373         { .name = #_name, .offset =     \
3374                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3375
3376 static const struct mlx5_ib_counter cong_cnts[] = {
3377         INIT_CONG_COUNTER(rp_cnp_ignored),
3378         INIT_CONG_COUNTER(rp_cnp_handled),
3379         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3380         INIT_CONG_COUNTER(np_cnp_sent),
3381 };
3382
3383 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
3384 {
3385         unsigned int i;
3386
3387         for (i = 0; i < dev->num_ports; i++) {
3388                 mlx5_core_dealloc_q_counter(dev->mdev,
3389                                             dev->port[i].cnts.set_id);
3390                 kfree(dev->port[i].cnts.names);
3391                 kfree(dev->port[i].cnts.offsets);
3392         }
3393 }
3394
3395 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3396                                     struct mlx5_ib_counters *cnts)
3397 {
3398         u32 num_counters;
3399
3400         num_counters = ARRAY_SIZE(basic_q_cnts);
3401
3402         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3403                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3404
3405         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3406                 num_counters += ARRAY_SIZE(retrans_q_cnts);
3407         cnts->num_q_counters = num_counters;
3408
3409         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3410                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3411                 num_counters += ARRAY_SIZE(cong_cnts);
3412         }
3413
3414         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3415         if (!cnts->names)
3416                 return -ENOMEM;
3417
3418         cnts->offsets = kcalloc(num_counters,
3419                                 sizeof(cnts->offsets), GFP_KERNEL);
3420         if (!cnts->offsets)
3421                 goto err_names;
3422
3423         return 0;
3424
3425 err_names:
3426         kfree(cnts->names);
3427         return -ENOMEM;
3428 }
3429
3430 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3431                                   const char **names,
3432                                   size_t *offsets)
3433 {
3434         int i;
3435         int j = 0;
3436
3437         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3438                 names[j] = basic_q_cnts[i].name;
3439                 offsets[j] = basic_q_cnts[i].offset;
3440         }
3441
3442         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3443                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3444                         names[j] = out_of_seq_q_cnts[i].name;
3445                         offsets[j] = out_of_seq_q_cnts[i].offset;
3446                 }
3447         }
3448
3449         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3450                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3451                         names[j] = retrans_q_cnts[i].name;
3452                         offsets[j] = retrans_q_cnts[i].offset;
3453                 }
3454         }
3455
3456         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3457                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3458                         names[j] = cong_cnts[i].name;
3459                         offsets[j] = cong_cnts[i].offset;
3460                 }
3461         }
3462 }
3463
3464 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
3465 {
3466         int i;
3467         int ret;
3468
3469         for (i = 0; i < dev->num_ports; i++) {
3470                 struct mlx5_ib_port *port = &dev->port[i];
3471
3472                 ret = mlx5_core_alloc_q_counter(dev->mdev,
3473                                                 &port->cnts.set_id);
3474                 if (ret) {
3475                         mlx5_ib_warn(dev,
3476                                      "couldn't allocate queue counter for port %d, err %d\n",
3477                                      i + 1, ret);
3478                         goto dealloc_counters;
3479                 }
3480
3481                 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
3482                 if (ret)
3483                         goto dealloc_counters;
3484
3485                 mlx5_ib_fill_counters(dev, port->cnts.names,
3486                                       port->cnts.offsets);
3487         }
3488
3489         return 0;
3490
3491 dealloc_counters:
3492         while (--i >= 0)
3493                 mlx5_core_dealloc_q_counter(dev->mdev,
3494                                             dev->port[i].cnts.set_id);
3495
3496         return ret;
3497 }
3498
3499 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3500                                                     u8 port_num)
3501 {
3502         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3503         struct mlx5_ib_port *port = &dev->port[port_num - 1];
3504
3505         /* We support only per port stats */
3506         if (port_num == 0)
3507                 return NULL;
3508
3509         return rdma_alloc_hw_stats_struct(port->cnts.names,
3510                                           port->cnts.num_q_counters +
3511                                           port->cnts.num_cong_counters,
3512                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
3513 }
3514
3515 static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3516                                     struct mlx5_ib_port *port,
3517                                     struct rdma_hw_stats *stats)
3518 {
3519         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3520         void *out;
3521         __be32 val;
3522         int ret, i;
3523
3524         out = kvzalloc(outlen, GFP_KERNEL);
3525         if (!out)
3526                 return -ENOMEM;
3527
3528         ret = mlx5_core_query_q_counter(dev->mdev,
3529                                         port->cnts.set_id, 0,
3530                                         out, outlen);
3531         if (ret)
3532                 goto free;
3533
3534         for (i = 0; i < port->cnts.num_q_counters; i++) {
3535                 val = *(__be32 *)(out + port->cnts.offsets[i]);
3536                 stats->value[i] = (u64)be32_to_cpu(val);
3537         }
3538
3539 free:
3540         kvfree(out);
3541         return ret;
3542 }
3543
3544 static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev,
3545                                        struct mlx5_ib_port *port,
3546                                        struct rdma_hw_stats *stats)
3547 {
3548         int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3549         void *out;
3550         int ret, i;
3551         int offset = port->cnts.num_q_counters;
3552
3553         out = kvzalloc(outlen, GFP_KERNEL);
3554         if (!out)
3555                 return -ENOMEM;
3556
3557         ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3558         if (ret)
3559                 goto free;
3560
3561         for (i = 0; i < port->cnts.num_cong_counters; i++) {
3562                 stats->value[i + offset] =
3563                         be64_to_cpup((__be64 *)(out +
3564                                      port->cnts.offsets[i + offset]));
3565         }
3566
3567 free:
3568         kvfree(out);
3569         return ret;
3570 }
3571
3572 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3573                                 struct rdma_hw_stats *stats,
3574                                 u8 port_num, int index)
3575 {
3576         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3577         struct mlx5_ib_port *port = &dev->port[port_num - 1];
3578         int ret, num_counters;
3579
3580         if (!stats)
3581                 return -EINVAL;
3582
3583         ret = mlx5_ib_query_q_counters(dev, port, stats);
3584         if (ret)
3585                 return ret;
3586         num_counters = port->cnts.num_q_counters;
3587
3588         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3589                 ret = mlx5_ib_query_cong_counters(dev, port, stats);
3590                 if (ret)
3591                         return ret;
3592                 num_counters += port->cnts.num_cong_counters;
3593         }
3594
3595         return num_counters;
3596 }
3597
3598 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3599 {
3600         return mlx5_rdma_netdev_free(netdev);
3601 }
3602
3603 static struct net_device*
3604 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3605                           u8 port_num,
3606                           enum rdma_netdev_t type,
3607                           const char *name,
3608                           unsigned char name_assign_type,
3609                           void (*setup)(struct net_device *))
3610 {
3611         struct net_device *netdev;
3612         struct rdma_netdev *rn;
3613
3614         if (type != RDMA_NETDEV_IPOIB)
3615                 return ERR_PTR(-EOPNOTSUPP);
3616
3617         netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3618                                         name, setup);
3619         if (likely(!IS_ERR_OR_NULL(netdev))) {
3620                 rn = netdev_priv(netdev);
3621                 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3622         }
3623         return netdev;
3624 }
3625
3626 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3627 {
3628         struct mlx5_ib_dev *dev;
3629         enum rdma_link_layer ll;
3630         int port_type_cap;
3631         const char *name;
3632         int err;
3633         int i;
3634
3635         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3636         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3637
3638         printk_once(KERN_INFO "%s", mlx5_version);
3639
3640         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3641         if (!dev)
3642                 return NULL;
3643
3644         dev->mdev = mdev;
3645
3646         dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3647                             GFP_KERNEL);
3648         if (!dev->port)
3649                 goto err_dealloc;
3650
3651         rwlock_init(&dev->roce.netdev_lock);
3652         err = get_port_caps(dev);
3653         if (err)
3654                 goto err_free_port;
3655
3656         if (mlx5_use_mad_ifc(dev))
3657                 get_ext_port_caps(dev);
3658
3659         if (!mlx5_lag_is_active(mdev))
3660                 name = "mlx5_%d";
3661         else
3662                 name = "mlx5_bond_%d";
3663
3664         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
3665         dev->ib_dev.owner               = THIS_MODULE;
3666         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
3667         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
3668         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
3669         dev->ib_dev.phys_port_cnt     = dev->num_ports;
3670         dev->ib_dev.num_comp_vectors    =
3671                 dev->mdev->priv.eq_table.num_comp_vectors;
3672         dev->ib_dev.dev.parent          = &mdev->pdev->dev;
3673
3674         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
3675         dev->ib_dev.uverbs_cmd_mask     =
3676                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
3677                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
3678                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
3679                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
3680                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
3681                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
3682                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
3683                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
3684                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
3685                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
3686                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3687                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
3688                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
3689                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
3690                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
3691                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
3692                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
3693                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
3694                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
3695                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
3696                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
3697                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
3698                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
3699                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
3700                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
3701                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3702         dev->ib_dev.uverbs_ex_cmd_mask =
3703                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
3704                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
3705                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
3706                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
3707
3708         dev->ib_dev.query_device        = mlx5_ib_query_device;
3709         dev->ib_dev.query_port          = mlx5_ib_query_port;
3710         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
3711         if (ll == IB_LINK_LAYER_ETHERNET)
3712                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
3713         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
3714         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
3715         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
3716         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
3717         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
3718         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
3719         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
3720         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
3721         dev->ib_dev.mmap                = mlx5_ib_mmap;
3722         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
3723         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
3724         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
3725         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
3726         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
3727         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
3728         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
3729         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
3730         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
3731         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
3732         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
3733         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
3734         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
3735         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
3736         dev->ib_dev.post_send           = mlx5_ib_post_send;
3737         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
3738         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
3739         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
3740         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
3741         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
3742         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
3743         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
3744         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
3745         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
3746         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
3747         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
3748         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
3749         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
3750         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
3751         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
3752         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
3753         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
3754         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
3755         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
3756         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
3757                 dev->ib_dev.alloc_rdma_netdev   = mlx5_ib_alloc_rdma_netdev;
3758
3759         if (mlx5_core_is_pf(mdev)) {
3760                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
3761                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
3762                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
3763                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
3764         }
3765
3766         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3767
3768         mlx5_ib_internal_fill_odp_caps(dev);
3769
3770         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3771
3772         if (MLX5_CAP_GEN(mdev, imaicl)) {
3773                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
3774                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
3775                 dev->ib_dev.uverbs_cmd_mask |=
3776                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
3777                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3778         }
3779
3780         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3781                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
3782                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
3783         }
3784
3785         if (MLX5_CAP_GEN(mdev, xrc)) {
3786                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3787                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3788                 dev->ib_dev.uverbs_cmd_mask |=
3789                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3790                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3791         }
3792
3793         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3794             IB_LINK_LAYER_ETHERNET) {
3795                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3796                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3797                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
3798                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
3799                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
3800                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3801                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3802                 dev->ib_dev.uverbs_ex_cmd_mask |=
3803                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3804                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3805                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3806                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3807                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3808                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3809                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3810         }
3811         err = init_node_data(dev);
3812         if (err)
3813                 goto err_free_port;
3814
3815         mutex_init(&dev->flow_db.lock);
3816         mutex_init(&dev->cap_mask_mutex);
3817         INIT_LIST_HEAD(&dev->qp_list);
3818         spin_lock_init(&dev->reset_flow_resource_lock);
3819
3820         if (ll == IB_LINK_LAYER_ETHERNET) {
3821                 err = mlx5_enable_eth(dev);
3822                 if (err)
3823                         goto err_free_port;
3824                 dev->roce.last_port_state = IB_PORT_DOWN;
3825         }
3826
3827         err = create_dev_resources(&dev->devr);
3828         if (err)
3829                 goto err_disable_eth;
3830
3831         err = mlx5_ib_odp_init_one(dev);
3832         if (err)
3833                 goto err_rsrc;
3834
3835         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3836                 err = mlx5_ib_alloc_counters(dev);
3837                 if (err)
3838                         goto err_odp;
3839         }
3840
3841         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
3842         if (!dev->mdev->priv.uar)
3843                 goto err_cnt;
3844
3845         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
3846         if (err)
3847                 goto err_uar_page;
3848
3849         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
3850         if (err)
3851                 goto err_bfreg;
3852
3853         err = ib_register_device(&dev->ib_dev, NULL);
3854         if (err)
3855                 goto err_fp_bfreg;
3856
3857         err = create_umr_res(dev);
3858         if (err)
3859                 goto err_dev;
3860
3861         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3862                 err = device_create_file(&dev->ib_dev.dev,
3863                                          mlx5_class_attributes[i]);
3864                 if (err)
3865                         goto err_umrc;
3866         }
3867
3868         if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
3869             MLX5_CAP_GEN(mdev, disable_local_lb))
3870                 mutex_init(&dev->lb_mutex);
3871
3872         dev->ib_active = true;
3873
3874         return dev;
3875
3876 err_umrc:
3877         destroy_umrc_res(dev);
3878
3879 err_dev:
3880         ib_unregister_device(&dev->ib_dev);
3881
3882 err_fp_bfreg:
3883         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3884
3885 err_bfreg:
3886         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3887
3888 err_uar_page:
3889         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
3890
3891 err_cnt:
3892         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3893                 mlx5_ib_dealloc_counters(dev);
3894
3895 err_odp:
3896         mlx5_ib_odp_remove_one(dev);
3897
3898 err_rsrc:
3899         destroy_dev_resources(&dev->devr);
3900
3901 err_disable_eth:
3902         if (ll == IB_LINK_LAYER_ETHERNET) {
3903                 mlx5_disable_eth(dev);
3904                 mlx5_remove_netdev_notifier(dev);
3905         }
3906
3907 err_free_port:
3908         kfree(dev->port);
3909
3910 err_dealloc:
3911         ib_dealloc_device((struct ib_device *)dev);
3912
3913         return NULL;
3914 }
3915
3916 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3917 {
3918         struct mlx5_ib_dev *dev = context;
3919         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3920
3921         mlx5_remove_netdev_notifier(dev);
3922         ib_unregister_device(&dev->ib_dev);
3923         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3924         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3925         mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
3926         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3927                 mlx5_ib_dealloc_counters(dev);
3928         destroy_umrc_res(dev);
3929         mlx5_ib_odp_remove_one(dev);
3930         destroy_dev_resources(&dev->devr);
3931         if (ll == IB_LINK_LAYER_ETHERNET)
3932                 mlx5_disable_eth(dev);
3933         kfree(dev->port);
3934         ib_dealloc_device(&dev->ib_dev);
3935 }
3936
3937 static struct mlx5_interface mlx5_ib_interface = {
3938         .add            = mlx5_ib_add,
3939         .remove         = mlx5_ib_remove,
3940         .event          = mlx5_ib_event,
3941 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3942         .pfault         = mlx5_ib_pfault,
3943 #endif
3944         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
3945 };
3946
3947 static int __init mlx5_ib_init(void)
3948 {
3949         int err;
3950
3951         mlx5_ib_odp_init();
3952
3953         err = mlx5_register_interface(&mlx5_ib_interface);
3954
3955         return err;
3956 }
3957
3958 static void __exit mlx5_ib_cleanup(void)
3959 {
3960         mlx5_unregister_interface(&mlx5_ib_interface);
3961 }
3962
3963 module_init(mlx5_ib_init);
3964 module_exit(mlx5_ib_cleanup);