drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/errno.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/slab.h>
  40 #if defined(CONFIG_X86)
  41 #include <asm/pat.h>
  42 #endif
  43 #include <linux/sched.h>
  44 #include <linux/sched/mm.h>
  45 #include <linux/sched/task.h>
  46 #include <linux/delay.h>
  47 #include <rdma/ib_user_verbs.h>
  48 #include <rdma/ib_addr.h>
  49 #include <rdma/ib_cache.h>
  50 #include <linux/mlx5/port.h>
  51 #include <linux/mlx5/vport.h>
  52 #include <linux/list.h>
  53 #include <rdma/ib_smi.h>
  54 #include <rdma/ib_umem.h>
  55 #include <linux/in.h>
  56 #include <linux/etherdevice.h>
  57 #include <linux/mlx5/fs.h>
  58 #include <linux/mlx5/vport.h>
  59 #include "mlx5_ib.h"
  60 #include "cmd.h"
  61 #include <linux/mlx5/vport.h>
  62
  63 #define DRIVER_NAME "mlx5_ib"
  64 #define DRIVER_VERSION "5.0-0"
  65
  66 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  67 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  68 MODULE_LICENSE("Dual BSD/GPL");
  69 MODULE_VERSION(DRIVER_VERSION);
  70
  71 static char mlx5_version[] =
  72         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  73         DRIVER_VERSION "\n";
  74
  75 enum {
  76         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  77 };
  78
  79 static enum rdma_link_layer
  80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  81 {
  82         switch (port_type_cap) {
  83         case MLX5_CAP_PORT_TYPE_IB:
  84                 return IB_LINK_LAYER_INFINIBAND;
  85         case MLX5_CAP_PORT_TYPE_ETH:
  86                 return IB_LINK_LAYER_ETHERNET;
  87         default:
  88                 return IB_LINK_LAYER_UNSPECIFIED;
  89         }
  90 }
  91
  92 static enum rdma_link_layer
  93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  94 {
  95         struct mlx5_ib_dev *dev = to_mdev(device);
  96         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  97
  98         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  99 }
 100
 101 static int mlx5_netdev_event(struct notifier_block *this,
 102                              unsigned long event, void *ptr)
 103 {
 104         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 105         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 106                                                  roce.nb);
 107
 108         switch (event) {
 109         case NETDEV_REGISTER:
 110         case NETDEV_UNREGISTER:
 111                 write_lock(&ibdev->roce.netdev_lock);
 112                 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
 113                         ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
 114                                              NULL : ndev;
 115                 write_unlock(&ibdev->roce.netdev_lock);
 116                 break;
 117
 118         case NETDEV_UP:
 119         case NETDEV_DOWN: {
 120                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 121                 struct net_device *upper = NULL;
 122
 123                 if (lag_ndev) {
 124                         upper = netdev_master_upper_dev_get(lag_ndev);
 125                         dev_put(lag_ndev);
 126                 }
 127
 128                 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
 129                     && ibdev->ib_active) {
 130                         struct ib_event ibev = { };
 131
 132                         ibev.device = &ibdev->ib_dev;
 133                         ibev.event = (event == NETDEV_UP) ?
 134                                      IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
 135                         ibev.element.port_num = 1;
 136                         ib_dispatch_event(&ibev);
 137                 }
 138                 break;
 139         }
 140
 141         default:
 142                 break;
 143         }
 144
 145         return NOTIFY_DONE;
 146 }
 147
 148 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 149                                              u8 port_num)
 150 {
 151         struct mlx5_ib_dev *ibdev = to_mdev(device);
 152         struct net_device *ndev;
 153
 154         ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 155         if (ndev)
 156                 return ndev;
 157
 158         /* Ensure ndev does not disappear before we invoke dev_hold()
 159          */
 160         read_lock(&ibdev->roce.netdev_lock);
 161         ndev = ibdev->roce.netdev;
 162         if (ndev)
 163                 dev_hold(ndev);
 164         read_unlock(&ibdev->roce.netdev_lock);
 165
 166         return ndev;
 167 }
 168
 169 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 170                                     u8 *active_width)
 171 {
 172         switch (eth_proto_oper) {
 173         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 174         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 175         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 176         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 177                 *active_width = IB_WIDTH_1X;
 178                 *active_speed = IB_SPEED_SDR;
 179                 break;
 180         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 181         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 182         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 183         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 184         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 185         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 186         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 187                 *active_width = IB_WIDTH_1X;
 188                 *active_speed = IB_SPEED_QDR;
 189                 break;
 190         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 191         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 192         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 193                 *active_width = IB_WIDTH_1X;
 194                 *active_speed = IB_SPEED_EDR;
 195                 break;
 196         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 197         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 198         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 199         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 200                 *active_width = IB_WIDTH_4X;
 201                 *active_speed = IB_SPEED_QDR;
 202                 break;
 203         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 204         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 205         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 206                 *active_width = IB_WIDTH_1X;
 207                 *active_speed = IB_SPEED_HDR;
 208                 break;
 209         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 210                 *active_width = IB_WIDTH_4X;
 211                 *active_speed = IB_SPEED_FDR;
 212                 break;
 213         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 214         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 215         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 216         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 217                 *active_width = IB_WIDTH_4X;
 218                 *active_speed = IB_SPEED_EDR;
 219                 break;
 220         default:
 221                 return -EINVAL;
 222         }
 223
 224         return 0;
 225 }
 226
 227 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 228                                 struct ib_port_attr *props)
 229 {
 230         struct mlx5_ib_dev *dev = to_mdev(device);
 231         struct mlx5_core_dev *mdev = dev->mdev;
 232         struct net_device *ndev, *upper;
 233         enum ib_mtu ndev_ib_mtu;
 234         u16 qkey_viol_cntr;
 235         u32 eth_prot_oper;
 236         int err;
 237
 238         /* Possible bad flows are checked before filling out props so in case
 239          * of an error it will still be zeroed out.
 240          */
 241         err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
 242         if (err)
 243                 return err;
 244
 245         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 246                                  &props->active_width);
 247
 248         props->port_cap_flags  |= IB_PORT_CM_SUP;
 249         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 250
 251         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 252                                                 roce_address_table_size);
 253         props->max_mtu          = IB_MTU_4096;
 254         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 255         props->pkey_tbl_len     = 1;
 256         props->state            = IB_PORT_DOWN;
 257         props->phys_state       = 3;
 258
 259         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 260         props->qkey_viol_cntr = qkey_viol_cntr;
 261
 262         ndev = mlx5_ib_get_netdev(device, port_num);
 263         if (!ndev)
 264                 return 0;
 265
 266         if (mlx5_lag_is_active(dev->mdev)) {
 267                 rcu_read_lock();
 268                 upper = netdev_master_upper_dev_get_rcu(ndev);
 269                 if (upper) {
 270                         dev_put(ndev);
 271                         ndev = upper;
 272                         dev_hold(ndev);
 273                 }
 274                 rcu_read_unlock();
 275         }
 276
 277         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 278                 props->state      = IB_PORT_ACTIVE;
 279                 props->phys_state = 5;
 280         }
 281
 282         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 283
 284         dev_put(ndev);
 285
 286         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 287         return 0;
 288 }
 289
 290 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 291                          unsigned int index, const union ib_gid *gid,
 292                          const struct ib_gid_attr *attr)
 293 {
 294         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 295         u8 roce_version = 0;
 296         u8 roce_l3_type = 0;
 297         bool vlan = false;
 298         u8 mac[ETH_ALEN];
 299         u16 vlan_id = 0;
 300
 301         if (gid) {
 302                 gid_type = attr->gid_type;
 303                 ether_addr_copy(mac, attr->ndev->dev_addr);
 304
 305                 if (is_vlan_dev(attr->ndev)) {
 306                         vlan = true;
 307                         vlan_id = vlan_dev_vlan_id(attr->ndev);
 308                 }
 309         }
 310
 311         switch (gid_type) {
 312         case IB_GID_TYPE_IB:
 313                 roce_version = MLX5_ROCE_VERSION_1;
 314                 break;
 315         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 316                 roce_version = MLX5_ROCE_VERSION_2;
 317                 if (ipv6_addr_v4mapped((void *)gid))
 318                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 319                 else
 320                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 321                 break;
 322
 323         default:
 324                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 325         }
 326
 327         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 328                                       roce_l3_type, gid->raw, mac, vlan,
 329                                       vlan_id);
 330 }
 331
 332 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 333                            unsigned int index, const union ib_gid *gid,
 334                            const struct ib_gid_attr *attr,
 335                            __always_unused void **context)
 336 {
 337         return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
 338 }
 339
 340 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 341                            unsigned int index, __always_unused void **context)
 342 {
 343         return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
 344 }
 345
 346 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 347                                int index)
 348 {
 349         struct ib_gid_attr attr;
 350         union ib_gid gid;
 351
 352         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 353                 return 0;
 354
 355         if (!attr.ndev)
 356                 return 0;
 357
 358         dev_put(attr.ndev);
 359
 360         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 361                 return 0;
 362
 363         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 364 }
 365
 366 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
 367                            int index, enum ib_gid_type *gid_type)
 368 {
 369         struct ib_gid_attr attr;
 370         union ib_gid gid;
 371         int ret;
 372
 373         ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
 374         if (ret)
 375                 return ret;
 376
 377         if (!attr.ndev)
 378                 return -ENODEV;
 379
 380         dev_put(attr.ndev);
 381
 382         *gid_type = attr.gid_type;
 383
 384         return 0;
 385 }
 386
 387 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 388 {
 389         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 390                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 391         return 0;
 392 }
 393
 394 enum {
 395         MLX5_VPORT_ACCESS_METHOD_MAD,
 396         MLX5_VPORT_ACCESS_METHOD_HCA,
 397         MLX5_VPORT_ACCESS_METHOD_NIC,
 398 };
 399
 400 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 401 {
 402         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 403                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 404
 405         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 406             IB_LINK_LAYER_ETHERNET)
 407                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 408
 409         return MLX5_VPORT_ACCESS_METHOD_HCA;
 410 }
 411
 412 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 413                             struct ib_device_attr *props)
 414 {
 415         u8 tmp;
 416         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 417         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 418         u8 atomic_req_8B_endianness_mode =
 419                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 420
 421         /* Check if HW supports 8 bytes standard atomic operations and capable
 422          * of host endianness respond
 423          */
 424         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 425         if (((atomic_operations & tmp) == tmp) &&
 426             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 427             (atomic_req_8B_endianness_mode)) {
 428                 props->atomic_cap = IB_ATOMIC_HCA;
 429         } else {
 430                 props->atomic_cap = IB_ATOMIC_NONE;
 431         }
 432 }
 433
 434 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 435                                         __be64 *sys_image_guid)
 436 {
 437         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 438         struct mlx5_core_dev *mdev = dev->mdev;
 439         u64 tmp;
 440         int err;
 441
 442         switch (mlx5_get_vport_access_method(ibdev)) {
 443         case MLX5_VPORT_ACCESS_METHOD_MAD:
 444                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 445                                                             sys_image_guid);
 446
 447         case MLX5_VPORT_ACCESS_METHOD_HCA:
 448                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 449                 break;
 450
 451         case MLX5_VPORT_ACCESS_METHOD_NIC:
 452                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 453                 break;
 454
 455         default:
 456                 return -EINVAL;
 457         }
 458
 459         if (!err)
 460                 *sys_image_guid = cpu_to_be64(tmp);
 461
 462         return err;
 463
 464 }
 465
 466 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 467                                 u16 *max_pkeys)
 468 {
 469         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 470         struct mlx5_core_dev *mdev = dev->mdev;
 471
 472         switch (mlx5_get_vport_access_method(ibdev)) {
 473         case MLX5_VPORT_ACCESS_METHOD_MAD:
 474                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 475
 476         case MLX5_VPORT_ACCESS_METHOD_HCA:
 477         case MLX5_VPORT_ACCESS_METHOD_NIC:
 478                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 479                                                 pkey_table_size));
 480                 return 0;
 481
 482         default:
 483                 return -EINVAL;
 484         }
 485 }
 486
 487 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 488                                 u32 *vendor_id)
 489 {
 490         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 491
 492         switch (mlx5_get_vport_access_method(ibdev)) {
 493         case MLX5_VPORT_ACCESS_METHOD_MAD:
 494                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 495
 496         case MLX5_VPORT_ACCESS_METHOD_HCA:
 497         case MLX5_VPORT_ACCESS_METHOD_NIC:
 498                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 499
 500         default:
 501                 return -EINVAL;
 502         }
 503 }
 504
 505 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 506                                 __be64 *node_guid)
 507 {
 508         u64 tmp;
 509         int err;
 510
 511         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 512         case MLX5_VPORT_ACCESS_METHOD_MAD:
 513                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 514
 515         case MLX5_VPORT_ACCESS_METHOD_HCA:
 516                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 517                 break;
 518
 519         case MLX5_VPORT_ACCESS_METHOD_NIC:
 520                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 521                 break;
 522
 523         default:
 524                 return -EINVAL;
 525         }
 526
 527         if (!err)
 528                 *node_guid = cpu_to_be64(tmp);
 529
 530         return err;
 531 }
 532
 533 struct mlx5_reg_node_desc {
 534         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 535 };
 536
 537 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 538 {
 539         struct mlx5_reg_node_desc in;
 540
 541         if (mlx5_use_mad_ifc(dev))
 542                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 543
 544         memset(&in, 0, sizeof(in));
 545
 546         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 547                                     sizeof(struct mlx5_reg_node_desc),
 548                                     MLX5_REG_NODE_DESC, 0, 0);
 549 }
 550
 551 static int mlx5_ib_query_device(struct ib_device *ibdev,
 552                                 struct ib_device_attr *props,
 553                                 struct ib_udata *uhw)
 554 {
 555         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 556         struct mlx5_core_dev *mdev = dev->mdev;
 557         int err = -ENOMEM;
 558         int max_sq_desc;
 559         int max_rq_sg;
 560         int max_sq_sg;
 561         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 562         struct mlx5_ib_query_device_resp resp = {};
 563         size_t resp_len;
 564         u64 max_tso;
 565
 566         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 567         if (uhw->outlen && uhw->outlen < resp_len)
 568                 return -EINVAL;
 569         else
 570                 resp.response_length = resp_len;
 571
 572         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 573                 return -EINVAL;
 574
 575         memset(props, 0, sizeof(*props));
 576         err = mlx5_query_system_image_guid(ibdev,
 577                                            &props->sys_image_guid);
 578         if (err)
 579                 return err;
 580
 581         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 582         if (err)
 583                 return err;
 584
 585         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 586         if (err)
 587                 return err;
 588
 589         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 590                 (fw_rev_min(dev->mdev) << 16) |
 591                 fw_rev_sub(dev->mdev);
 592         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 593                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 594                 IB_DEVICE_SYS_IMAGE_GUID                |
 595                 IB_DEVICE_RC_RNR_NAK_GEN;
 596
 597         if (MLX5_CAP_GEN(mdev, pkv))
 598                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 599         if (MLX5_CAP_GEN(mdev, qkv))
 600                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 601         if (MLX5_CAP_GEN(mdev, apm))
 602                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 603         if (MLX5_CAP_GEN(mdev, xrc))
 604                 props->device_cap_flags |= IB_DEVICE_XRC;
 605         if (MLX5_CAP_GEN(mdev, imaicl)) {
 606                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 607                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 608                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 609                 /* We support 'Gappy' memory registration too */
 610                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 611         }
 612         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 613         if (MLX5_CAP_GEN(mdev, sho)) {
 614                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 615                 /* At this stage no support for signature handover */
 616                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 617                                       IB_PROT_T10DIF_TYPE_2 |
 618                                       IB_PROT_T10DIF_TYPE_3;
 619                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 620                                        IB_GUARD_T10DIF_CSUM;
 621         }
 622         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 623                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 624
 625         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
 626                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 627                         /* Legacy bit to support old userspace libraries */
 628                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 629                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 630                 }
 631
 632                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 633                         props->raw_packet_caps |=
 634                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 635
 636                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 637                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 638                         if (max_tso) {
 639                                 resp.tso_caps.max_tso = 1 << max_tso;
 640                                 resp.tso_caps.supported_qpts |=
 641                                         1 << IB_QPT_RAW_PACKET;
 642                                 resp.response_length += sizeof(resp.tso_caps);
 643                         }
 644                 }
 645
 646                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 647                         resp.rss_caps.rx_hash_function =
 648                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 649                         resp.rss_caps.rx_hash_fields_mask =
 650                                                 MLX5_RX_HASH_SRC_IPV4 |
 651                                                 MLX5_RX_HASH_DST_IPV4 |
 652                                                 MLX5_RX_HASH_SRC_IPV6 |
 653                                                 MLX5_RX_HASH_DST_IPV6 |
 654                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 655                                                 MLX5_RX_HASH_DST_PORT_TCP |
 656                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 657                                                 MLX5_RX_HASH_DST_PORT_UDP;
 658                         resp.response_length += sizeof(resp.rss_caps);
 659                 }
 660         } else {
 661                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 662                         resp.response_length += sizeof(resp.tso_caps);
 663                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 664                         resp.response_length += sizeof(resp.rss_caps);
 665         }
 666
 667         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 668                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 669                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 670         }
 671
 672         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 673             MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
 674                 /* Legacy bit to support old userspace libraries */
 675                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 676                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 677         }
 678
 679         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 680                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 681
 682         props->vendor_part_id      = mdev->pdev->device;
 683         props->hw_ver              = mdev->pdev->revision;
 684
 685         props->max_mr_size         = ~0ull;
 686         props->page_size_cap       = ~(min_page_size - 1);
 687         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 688         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 689         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 690                      sizeof(struct mlx5_wqe_data_seg);
 691         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 692         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 693                      sizeof(struct mlx5_wqe_raddr_seg)) /
 694                 sizeof(struct mlx5_wqe_data_seg);
 695         props->max_sge = min(max_rq_sg, max_sq_sg);
 696         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 697         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 698         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 699         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 700         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 701         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 702         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 703         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 704         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 705         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 706         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 707         props->max_srq_sge         = max_rq_sg - 1;
 708         props->max_fast_reg_page_list_len =
 709                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 710         get_atomic_caps(dev, props);
 711         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 712         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 713         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 714         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 715                                            props->max_mcast_grp;
 716         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 717         props->max_ah = INT_MAX;
 718         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 719         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 720
 721 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 722         if (MLX5_CAP_GEN(mdev, pg))
 723                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 724         props->odp_caps = dev->odp_caps;
 725 #endif
 726
 727         if (MLX5_CAP_GEN(mdev, cd))
 728                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 729
 730         if (!mlx5_core_is_pf(mdev))
 731                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 732
 733         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 734             IB_LINK_LAYER_ETHERNET) {
 735                 props->rss_caps.max_rwq_indirection_tables =
 736                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 737                 props->rss_caps.max_rwq_indirection_table_size =
 738                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 739                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 740                 props->max_wq_type_rq =
 741                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 742         }
 743
 744         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
 745                 resp.cqe_comp_caps.max_num =
 746                         MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
 747                         MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
 748                 resp.cqe_comp_caps.supported_format =
 749                         MLX5_IB_CQE_RES_FORMAT_HASH |
 750                         MLX5_IB_CQE_RES_FORMAT_CSUM;
 751                 resp.response_length += sizeof(resp.cqe_comp_caps);
 752         }
 753
 754         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
 755                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
 756                     MLX5_CAP_GEN(mdev, qos)) {
 757                         resp.packet_pacing_caps.qp_rate_limit_max =
 758                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
 759                         resp.packet_pacing_caps.qp_rate_limit_min =
 760                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
 761                         resp.packet_pacing_caps.supported_qpts |=
 762                                 1 << IB_QPT_RAW_PACKET;
 763                 }
 764                 resp.response_length += sizeof(resp.packet_pacing_caps);
 765         }
 766
 767         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
 768                         uhw->outlen)) {
 769                 resp.mlx5_ib_support_multi_pkt_send_wqes =
 770                         MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
 771                 resp.response_length +=
 772                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
 773         }
 774
 775         if (field_avail(typeof(resp), reserved, uhw->outlen))
 776                 resp.response_length += sizeof(resp.reserved);
 777
 778         if (uhw->outlen) {
 779                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
 780
 781                 if (err)
 782                         return err;
 783         }
 784
 785         return 0;
 786 }
 787
 788 enum mlx5_ib_width {
 789         MLX5_IB_WIDTH_1X        = 1 << 0,
 790         MLX5_IB_WIDTH_2X        = 1 << 1,
 791         MLX5_IB_WIDTH_4X        = 1 << 2,
 792         MLX5_IB_WIDTH_8X        = 1 << 3,
 793         MLX5_IB_WIDTH_12X       = 1 << 4
 794 };
 795
 796 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 797                                   u8 *ib_width)
 798 {
 799         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 800         int err = 0;
 801
 802         if (active_width & MLX5_IB_WIDTH_1X) {
 803                 *ib_width = IB_WIDTH_1X;
 804         } else if (active_width & MLX5_IB_WIDTH_2X) {
 805                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 806                             (int)active_width);
 807                 err = -EINVAL;
 808         } else if (active_width & MLX5_IB_WIDTH_4X) {
 809                 *ib_width = IB_WIDTH_4X;
 810         } else if (active_width & MLX5_IB_WIDTH_8X) {
 811                 *ib_width = IB_WIDTH_8X;
 812         } else if (active_width & MLX5_IB_WIDTH_12X) {
 813                 *ib_width = IB_WIDTH_12X;
 814         } else {
 815                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 816                             (int)active_width);
 817                 err = -EINVAL;
 818         }
 819
 820         return err;
 821 }
 822
 823 static int mlx5_mtu_to_ib_mtu(int mtu)
 824 {
 825         switch (mtu) {
 826         case 256: return 1;
 827         case 512: return 2;
 828         case 1024: return 3;
 829         case 2048: return 4;
 830         case 4096: return 5;
 831         default:
 832                 pr_warn("invalid mtu\n");
 833                 return -1;
 834         }
 835 }
 836
 837 enum ib_max_vl_num {
 838         __IB_MAX_VL_0           = 1,
 839         __IB_MAX_VL_0_1         = 2,
 840         __IB_MAX_VL_0_3         = 3,
 841         __IB_MAX_VL_0_7         = 4,
 842         __IB_MAX_VL_0_14        = 5,
 843 };
 844
 845 enum mlx5_vl_hw_cap {
 846         MLX5_VL_HW_0    = 1,
 847         MLX5_VL_HW_0_1  = 2,
 848         MLX5_VL_HW_0_2  = 3,
 849         MLX5_VL_HW_0_3  = 4,
 850         MLX5_VL_HW_0_4  = 5,
 851         MLX5_VL_HW_0_5  = 6,
 852         MLX5_VL_HW_0_6  = 7,
 853         MLX5_VL_HW_0_7  = 8,
 854         MLX5_VL_HW_0_14 = 15
 855 };
 856
 857 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 858                                 u8 *max_vl_num)
 859 {
 860         switch (vl_hw_cap) {
 861         case MLX5_VL_HW_0:
 862                 *max_vl_num = __IB_MAX_VL_0;
 863                 break;
 864         case MLX5_VL_HW_0_1:
 865                 *max_vl_num = __IB_MAX_VL_0_1;
 866                 break;
 867         case MLX5_VL_HW_0_3:
 868                 *max_vl_num = __IB_MAX_VL_0_3;
 869                 break;
 870         case MLX5_VL_HW_0_7:
 871                 *max_vl_num = __IB_MAX_VL_0_7;
 872                 break;
 873         case MLX5_VL_HW_0_14:
 874                 *max_vl_num = __IB_MAX_VL_0_14;
 875                 break;
 876
 877         default:
 878                 return -EINVAL;
 879         }
 880
 881         return 0;
 882 }
 883
 884 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
 885                                struct ib_port_attr *props)
 886 {
 887         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 888         struct mlx5_core_dev *mdev = dev->mdev;
 889         struct mlx5_hca_vport_context *rep;
 890         u16 max_mtu;
 891         u16 oper_mtu;
 892         int err;
 893         u8 ib_link_width_oper;
 894         u8 vl_hw_cap;
 895
 896         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
 897         if (!rep) {
 898                 err = -ENOMEM;
 899                 goto out;
 900         }
 901
 902         /* props being zeroed by the caller, avoid zeroing it here */
 903
 904         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
 905         if (err)
 906                 goto out;
 907
 908         props->lid              = rep->lid;
 909         props->lmc              = rep->lmc;
 910         props->sm_lid           = rep->sm_lid;
 911         props->sm_sl            = rep->sm_sl;
 912         props->state            = rep->vport_state;
 913         props->phys_state       = rep->port_physical_state;
 914         props->port_cap_flags   = rep->cap_mask1;
 915         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
 916         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
 917         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
 918         props->bad_pkey_cntr    = rep->pkey_violation_counter;
 919         props->qkey_viol_cntr   = rep->qkey_violation_counter;
 920         props->subnet_timeout   = rep->subnet_timeout;
 921         props->init_type_reply  = rep->init_type_reply;
 922         props->grh_required     = rep->grh_required;
 923
 924         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
 925         if (err)
 926                 goto out;
 927
 928         err = translate_active_width(ibdev, ib_link_width_oper,
 929                                      &props->active_width);
 930         if (err)
 931                 goto out;
 932         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
 933         if (err)
 934                 goto out;
 935
 936         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
 937
 938         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
 939
 940         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
 941
 942         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
 943
 944         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
 945         if (err)
 946                 goto out;
 947
 948         err = translate_max_vl_num(ibdev, vl_hw_cap,
 949                                    &props->max_vl_num);
 950 out:
 951         kfree(rep);
 952         return err;
 953 }
 954
 955 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 956                        struct ib_port_attr *props)
 957 {
 958         unsigned int count;
 959         int ret;
 960
 961         switch (mlx5_get_vport_access_method(ibdev)) {
 962         case MLX5_VPORT_ACCESS_METHOD_MAD:
 963                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
 964                 break;
 965
 966         case MLX5_VPORT_ACCESS_METHOD_HCA:
 967                 ret = mlx5_query_hca_port(ibdev, port, props);
 968                 break;
 969
 970         case MLX5_VPORT_ACCESS_METHOD_NIC:
 971                 ret = mlx5_query_port_roce(ibdev, port, props);
 972                 break;
 973
 974         default:
 975                 ret = -EINVAL;
 976         }
 977
 978         if (!ret && props) {
 979                 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
 980                 props->gid_tbl_len -= count;
 981         }
 982         return ret;
 983 }
 984
 985 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
 986                              union ib_gid *gid)
 987 {
 988         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 989         struct mlx5_core_dev *mdev = dev->mdev;
 990
 991         switch (mlx5_get_vport_access_method(ibdev)) {
 992         case MLX5_VPORT_ACCESS_METHOD_MAD:
 993                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
 994
 995         case MLX5_VPORT_ACCESS_METHOD_HCA:
 996                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
 997
 998         default:
 999                 return -EINVAL;
1000         }
1001
1002 }
1003
1004 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1005                               u16 *pkey)
1006 {
1007         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1008         struct mlx5_core_dev *mdev = dev->mdev;
1009
1010         switch (mlx5_get_vport_access_method(ibdev)) {
1011         case MLX5_VPORT_ACCESS_METHOD_MAD:
1012                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1013
1014         case MLX5_VPORT_ACCESS_METHOD_HCA:
1015         case MLX5_VPORT_ACCESS_METHOD_NIC:
1016                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
1017                                                  pkey);
1018         default:
1019                 return -EINVAL;
1020         }
1021 }
1022
1023 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1024                                  struct ib_device_modify *props)
1025 {
1026         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1027         struct mlx5_reg_node_desc in;
1028         struct mlx5_reg_node_desc out;
1029         int err;
1030
1031         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1032                 return -EOPNOTSUPP;
1033
1034         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1035                 return 0;
1036
1037         /*
1038          * If possible, pass node desc to FW, so it can generate
1039          * a 144 trap.  If cmd fails, just ignore.
1040          */
1041         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1042         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1043                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1044         if (err)
1045                 return err;
1046
1047         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1048
1049         return err;
1050 }
1051
1052 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1053                                 u32 value)
1054 {
1055         struct mlx5_hca_vport_context ctx = {};
1056         int err;
1057
1058         err = mlx5_query_hca_vport_context(dev->mdev, 0,
1059                                            port_num, 0, &ctx);
1060         if (err)
1061                 return err;
1062
1063         if (~ctx.cap_mask1_perm & mask) {
1064                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1065                              mask, ctx.cap_mask1_perm);
1066                 return -EINVAL;
1067         }
1068
1069         ctx.cap_mask1 = value;
1070         ctx.cap_mask1_perm = mask;
1071         err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1072                                                  port_num, 0, &ctx);
1073
1074         return err;
1075 }
1076
1077 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1078                                struct ib_port_modify *props)
1079 {
1080         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1081         struct ib_port_attr attr;
1082         u32 tmp;
1083         int err;
1084         u32 change_mask;
1085         u32 value;
1086         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1087                       IB_LINK_LAYER_INFINIBAND);
1088
1089         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1090                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1091                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1092                 return set_port_caps_atomic(dev, port, change_mask, value);
1093         }
1094
1095         mutex_lock(&dev->cap_mask_mutex);
1096
1097         err = ib_query_port(ibdev, port, &attr);
1098         if (err)
1099                 goto out;
1100
1101         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1102                 ~props->clr_port_cap_mask;
1103
1104         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1105
1106 out:
1107         mutex_unlock(&dev->cap_mask_mutex);
1108         return err;
1109 }
1110
1111 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1112 {
1113         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1114                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1115 }
1116
1117 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1118                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1119                              u32 *num_sys_pages)
1120 {
1121         int uars_per_sys_page;
1122         int bfregs_per_sys_page;
1123         int ref_bfregs = req->total_num_bfregs;
1124
1125         if (req->total_num_bfregs == 0)
1126                 return -EINVAL;
1127
1128         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1129         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1130
1131         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1132                 return -ENOMEM;
1133
1134         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1135         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1136         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1137         *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1138
1139         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1140                 return -EINVAL;
1141
1142         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n",
1143                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1144                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1145                     req->total_num_bfregs, *num_sys_pages);
1146
1147         return 0;
1148 }
1149
1150 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1151 {
1152         struct mlx5_bfreg_info *bfregi;
1153         int err;
1154         int i;
1155
1156         bfregi = &context->bfregi;
1157         for (i = 0; i < bfregi->num_sys_pages; i++) {
1158                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1159                 if (err)
1160                         goto error;
1161
1162                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1163         }
1164         return 0;
1165
1166 error:
1167         for (--i; i >= 0; i--)
1168                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1169                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1170
1171         return err;
1172 }
1173
1174 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1175 {
1176         struct mlx5_bfreg_info *bfregi;
1177         int err;
1178         int i;
1179
1180         bfregi = &context->bfregi;
1181         for (i = 0; i < bfregi->num_sys_pages; i++) {
1182                 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1183                 if (err) {
1184                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1185                         return err;
1186                 }
1187         }
1188         return 0;
1189 }
1190
1191 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1192 {
1193         int err;
1194
1195         err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1196         if (err)
1197                 return err;
1198
1199         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1200             !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1201                 return err;
1202
1203         mutex_lock(&dev->lb_mutex);
1204         dev->user_td++;
1205
1206         if (dev->user_td == 2)
1207                 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1208
1209         mutex_unlock(&dev->lb_mutex);
1210         return err;
1211 }
1212
1213 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1214 {
1215         mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1216
1217         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1218             !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1219                 return;
1220
1221         mutex_lock(&dev->lb_mutex);
1222         dev->user_td--;
1223
1224         if (dev->user_td < 2)
1225                 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1226
1227         mutex_unlock(&dev->lb_mutex);
1228 }
1229
1230 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1231                                                   struct ib_udata *udata)
1232 {
1233         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1234         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1235         struct mlx5_ib_alloc_ucontext_resp resp = {};
1236         struct mlx5_ib_ucontext *context;
1237         struct mlx5_bfreg_info *bfregi;
1238         int ver;
1239         int err;
1240         size_t reqlen;
1241         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1242                                      max_cqe_version);
1243         bool lib_uar_4k;
1244
1245         if (!dev->ib_active)
1246                 return ERR_PTR(-EAGAIN);
1247
1248         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1249                 return ERR_PTR(-EINVAL);
1250
1251         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1252         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1253                 ver = 0;
1254         else if (reqlen >= min_req_v2)
1255                 ver = 2;
1256         else
1257                 return ERR_PTR(-EINVAL);
1258
1259         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
1260         if (err)
1261                 return ERR_PTR(err);
1262
1263         if (req.flags)
1264                 return ERR_PTR(-EINVAL);
1265
1266         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1267                 return ERR_PTR(-EOPNOTSUPP);
1268
1269         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1270                                     MLX5_NON_FP_BFREGS_PER_UAR);
1271         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1272                 return ERR_PTR(-EINVAL);
1273
1274         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1275         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1276                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1277         resp.cache_line_size = cache_line_size();
1278         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1279         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1280         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1281         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1282         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1283         resp.cqe_version = min_t(__u8,
1284                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1285                                  req.max_cqe_version);
1286         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1287                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1288         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1289                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1290         resp.response_length = min(offsetof(typeof(resp), response_length) +
1291                                    sizeof(resp.response_length), udata->outlen);
1292
1293         context = kzalloc(sizeof(*context), GFP_KERNEL);
1294         if (!context)
1295                 return ERR_PTR(-ENOMEM);
1296
1297         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1298         bfregi = &context->bfregi;
1299
1300         /* updates req->total_num_bfregs */
1301         err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1302         if (err)
1303                 goto out_ctx;
1304
1305         mutex_init(&bfregi->lock);
1306         bfregi->lib_uar_4k = lib_uar_4k;
1307         bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
1308                                 GFP_KERNEL);
1309         if (!bfregi->count) {
1310                 err = -ENOMEM;
1311                 goto out_ctx;
1312         }
1313
1314         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1315                                     sizeof(*bfregi->sys_pages),
1316                                     GFP_KERNEL);
1317         if (!bfregi->sys_pages) {
1318                 err = -ENOMEM;
1319                 goto out_count;
1320         }
1321
1322         err = allocate_uars(dev, context);
1323         if (err)
1324                 goto out_sys_pages;
1325
1326 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1327         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1328 #endif
1329
1330         context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1331         if (!context->upd_xlt_page) {
1332                 err = -ENOMEM;
1333                 goto out_uars;
1334         }
1335         mutex_init(&context->upd_xlt_page_mutex);
1336
1337         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1338                 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1339                 if (err)
1340                         goto out_page;
1341         }
1342
1343         INIT_LIST_HEAD(&context->vma_private_list);
1344         INIT_LIST_HEAD(&context->db_page_list);
1345         mutex_init(&context->db_page_mutex);
1346
1347         resp.tot_bfregs = req.total_num_bfregs;
1348         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1349
1350         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1351                 resp.response_length += sizeof(resp.cqe_version);
1352
1353         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1354                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1355                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1356                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1357         }
1358
1359         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1360                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1361                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1362                         resp.eth_min_inline++;
1363                 }
1364                 resp.response_length += sizeof(resp.eth_min_inline);
1365         }
1366
1367         /*
1368          * We don't want to expose information from the PCI bar that is located
1369          * after 4096 bytes, so if the arch only supports larger pages, let's
1370          * pretend we don't support reading the HCA's core clock. This is also
1371          * forced by mmap function.
1372          */
1373         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1374                 if (PAGE_SIZE <= 4096) {
1375                         resp.comp_mask |=
1376                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1377                         resp.hca_core_clock_offset =
1378                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1379                 }
1380                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1381                                         sizeof(resp.reserved2);
1382         }
1383
1384         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1385                 resp.response_length += sizeof(resp.log_uar_size);
1386
1387         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1388                 resp.response_length += sizeof(resp.num_uars_per_page);
1389
1390         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1391         if (err)
1392                 goto out_td;
1393
1394         bfregi->ver = ver;
1395         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1396         context->cqe_version = resp.cqe_version;
1397         context->lib_caps = req.lib_caps;
1398         print_lib_caps(dev, context->lib_caps);
1399
1400         return &context->ibucontext;
1401
1402 out_td:
1403         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1404                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1405
1406 out_page:
1407         free_page(context->upd_xlt_page);
1408
1409 out_uars:
1410         deallocate_uars(dev, context);
1411
1412 out_sys_pages:
1413         kfree(bfregi->sys_pages);
1414
1415 out_count:
1416         kfree(bfregi->count);
1417
1418 out_ctx:
1419         kfree(context);
1420
1421         return ERR_PTR(err);
1422 }
1423
1424 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1425 {
1426         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1427         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1428         struct mlx5_bfreg_info *bfregi;
1429
1430         bfregi = &context->bfregi;
1431         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1432                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1433
1434         free_page(context->upd_xlt_page);
1435         deallocate_uars(dev, context);
1436         kfree(bfregi->sys_pages);
1437         kfree(bfregi->count);
1438         kfree(context);
1439
1440         return 0;
1441 }
1442
1443 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1444                                  struct mlx5_bfreg_info *bfregi,
1445                                  int idx)
1446 {
1447         int fw_uars_per_page;
1448
1449         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1450
1451         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1452                         bfregi->sys_pages[idx] / fw_uars_per_page;
1453 }
1454
1455 static int get_command(unsigned long offset)
1456 {
1457         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1458 }
1459
1460 static int get_arg(unsigned long offset)
1461 {
1462         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1463 }
1464
1465 static int get_index(unsigned long offset)
1466 {
1467         return get_arg(offset);
1468 }
1469
1470 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1471 {
1472         /* vma_open is called when a new VMA is created on top of our VMA.  This
1473          * is done through either mremap flow or split_vma (usually due to
1474          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1475          * as this VMA is strongly hardware related.  Therefore we set the
1476          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1477          * calling us again and trying to do incorrect actions.  We assume that
1478          * the original VMA size is exactly a single page, and therefore all
1479          * "splitting" operation will not happen to it.
1480          */
1481         area->vm_ops = NULL;
1482 }
1483
1484 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1485 {
1486         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1487
1488         /* It's guaranteed that all VMAs opened on a FD are closed before the
1489          * file itself is closed, therefore no sync is needed with the regular
1490          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1491          * However need a sync with accessing the vma as part of
1492          * mlx5_ib_disassociate_ucontext.
1493          * The close operation is usually called under mm->mmap_sem except when
1494          * process is exiting.
1495          * The exiting case is handled explicitly as part of
1496          * mlx5_ib_disassociate_ucontext.
1497          */
1498         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1499
1500         /* setting the vma context pointer to null in the mlx5_ib driver's
1501          * private data, to protect a race condition in
1502          * mlx5_ib_disassociate_ucontext().
1503          */
1504         mlx5_ib_vma_priv_data->vma = NULL;
1505         list_del(&mlx5_ib_vma_priv_data->list);
1506         kfree(mlx5_ib_vma_priv_data);
1507 }
1508
1509 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1510         .open = mlx5_ib_vma_open,
1511         .close = mlx5_ib_vma_close
1512 };
1513
1514 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1515                                 struct mlx5_ib_ucontext *ctx)
1516 {
1517         struct mlx5_ib_vma_private_data *vma_prv;
1518         struct list_head *vma_head = &ctx->vma_private_list;
1519
1520         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1521         if (!vma_prv)
1522                 return -ENOMEM;
1523
1524         vma_prv->vma = vma;
1525         vma->vm_private_data = vma_prv;
1526         vma->vm_ops =  &mlx5_ib_vm_ops;
1527
1528         list_add(&vma_prv->list, vma_head);
1529
1530         return 0;
1531 }
1532
1533 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1534 {
1535         int ret;
1536         struct vm_area_struct *vma;
1537         struct mlx5_ib_vma_private_data *vma_private, *n;
1538         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1539         struct task_struct *owning_process  = NULL;
1540         struct mm_struct   *owning_mm       = NULL;
1541
1542         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1543         if (!owning_process)
1544                 return;
1545
1546         owning_mm = get_task_mm(owning_process);
1547         if (!owning_mm) {
1548                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1549                 while (1) {
1550                         put_task_struct(owning_process);
1551                         usleep_range(1000, 2000);
1552                         owning_process = get_pid_task(ibcontext->tgid,
1553                                                       PIDTYPE_PID);
1554                         if (!owning_process ||
1555                             owning_process->state == TASK_DEAD) {
1556                                 pr_info("disassociate ucontext done, task was terminated\n");
1557                                 /* in case task was dead need to release the
1558                                  * task struct.
1559                                  */
1560                                 if (owning_process)
1561                                         put_task_struct(owning_process);
1562                                 return;
1563                         }
1564                 }
1565         }
1566
1567         /* need to protect from a race on closing the vma as part of
1568          * mlx5_ib_vma_close.
1569          */
1570         down_write(&owning_mm->mmap_sem);
1571         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1572                                  list) {
1573                 vma = vma_private->vma;
1574                 ret = zap_vma_ptes(vma, vma->vm_start,
1575                                    PAGE_SIZE);
1576                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1577                 /* context going to be destroyed, should
1578                  * not access ops any more.
1579                  */
1580                 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1581                 vma->vm_ops = NULL;
1582                 list_del(&vma_private->list);
1583                 kfree(vma_private);
1584         }
1585         up_write(&owning_mm->mmap_sem);
1586         mmput(owning_mm);
1587         put_task_struct(owning_process);
1588 }
1589
1590 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1591 {
1592         switch (cmd) {
1593         case MLX5_IB_MMAP_WC_PAGE:
1594                 return "WC";
1595         case MLX5_IB_MMAP_REGULAR_PAGE:
1596                 return "best effort WC";
1597         case MLX5_IB_MMAP_NC_PAGE:
1598                 return "NC";
1599         default:
1600                 return NULL;
1601         }
1602 }
1603
1604 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1605                     struct vm_area_struct *vma,
1606                     struct mlx5_ib_ucontext *context)
1607 {
1608         struct mlx5_bfreg_info *bfregi = &context->bfregi;
1609         int err;
1610         unsigned long idx;
1611         phys_addr_t pfn, pa;
1612         pgprot_t prot;
1613         int uars_per_page;
1614
1615         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1616                 return -EINVAL;
1617
1618         uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1619         idx = get_index(vma->vm_pgoff);
1620         if (idx % uars_per_page ||
1621             idx * uars_per_page >= bfregi->num_sys_pages) {
1622                 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1623                 return -EINVAL;
1624         }
1625
1626         switch (cmd) {
1627         case MLX5_IB_MMAP_WC_PAGE:
1628 /* Some architectures don't support WC memory */
1629 #if defined(CONFIG_X86)
1630                 if (!pat_enabled())
1631                         return -EPERM;
1632 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1633                         return -EPERM;
1634 #endif
1635         /* fall through */
1636         case MLX5_IB_MMAP_REGULAR_PAGE:
1637                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1638                 prot = pgprot_writecombine(vma->vm_page_prot);
1639                 break;
1640         case MLX5_IB_MMAP_NC_PAGE:
1641                 prot = pgprot_noncached(vma->vm_page_prot);
1642                 break;
1643         default:
1644                 return -EINVAL;
1645         }
1646
1647         pfn = uar_index2pfn(dev, bfregi, idx);
1648         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1649
1650         vma->vm_page_prot = prot;
1651         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1652                                  PAGE_SIZE, vma->vm_page_prot);
1653         if (err) {
1654                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1655                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1656                 return -EAGAIN;
1657         }
1658
1659         pa = pfn << PAGE_SHIFT;
1660         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1661                     vma->vm_start, &pa);
1662
1663         return mlx5_ib_set_vma_data(vma, context);
1664 }
1665
1666 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1667 {
1668         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1669         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1670         unsigned long command;
1671         phys_addr_t pfn;
1672
1673         command = get_command(vma->vm_pgoff);
1674         switch (command) {
1675         case MLX5_IB_MMAP_WC_PAGE:
1676         case MLX5_IB_MMAP_NC_PAGE:
1677         case MLX5_IB_MMAP_REGULAR_PAGE:
1678                 return uar_mmap(dev, command, vma, context);
1679
1680         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1681                 return -ENOSYS;
1682
1683         case MLX5_IB_MMAP_CORE_CLOCK:
1684                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1685                         return -EINVAL;
1686
1687                 if (vma->vm_flags & VM_WRITE)
1688                         return -EPERM;
1689
1690                 /* Don't expose to user-space information it shouldn't have */
1691                 if (PAGE_SIZE > 4096)
1692                         return -EOPNOTSUPP;
1693
1694                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1695                 pfn = (dev->mdev->iseg_base +
1696                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1697                         PAGE_SHIFT;
1698                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1699                                        PAGE_SIZE, vma->vm_page_prot))
1700                         return -EAGAIN;
1701
1702                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1703                             vma->vm_start,
1704                             (unsigned long long)pfn << PAGE_SHIFT);
1705                 break;
1706
1707         default:
1708                 return -EINVAL;
1709         }
1710
1711         return 0;
1712 }
1713
1714 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1715                                       struct ib_ucontext *context,
1716                                       struct ib_udata *udata)
1717 {
1718         struct mlx5_ib_alloc_pd_resp resp;
1719         struct mlx5_ib_pd *pd;
1720         int err;
1721
1722         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1723         if (!pd)
1724                 return ERR_PTR(-ENOMEM);
1725
1726         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1727         if (err) {
1728                 kfree(pd);
1729                 return ERR_PTR(err);
1730         }
1731
1732         if (context) {
1733                 resp.pdn = pd->pdn;
1734                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1735                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1736                         kfree(pd);
1737                         return ERR_PTR(-EFAULT);
1738                 }
1739         }
1740
1741         return &pd->ibpd;
1742 }
1743
1744 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1745 {
1746         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1747         struct mlx5_ib_pd *mpd = to_mpd(pd);
1748
1749         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1750         kfree(mpd);
1751
1752         return 0;
1753 }
1754
1755 enum {
1756         MATCH_CRITERIA_ENABLE_OUTER_BIT,
1757         MATCH_CRITERIA_ENABLE_MISC_BIT,
1758         MATCH_CRITERIA_ENABLE_INNER_BIT
1759 };
1760
1761 #define HEADER_IS_ZERO(match_criteria, headers)                            \
1762         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1763                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
1764
1765 static u8 get_match_criteria_enable(u32 *match_criteria)
1766 {
1767         u8 match_criteria_enable;
1768
1769         match_criteria_enable =
1770                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1771                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1772         match_criteria_enable |=
1773                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1774                 MATCH_CRITERIA_ENABLE_MISC_BIT;
1775         match_criteria_enable |=
1776                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1777                 MATCH_CRITERIA_ENABLE_INNER_BIT;
1778
1779         return match_criteria_enable;
1780 }
1781
1782 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1783 {
1784         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1785         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1786 }
1787
1788 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1789                            bool inner)
1790 {
1791         if (inner) {
1792                 MLX5_SET(fte_match_set_misc,
1793                          misc_c, inner_ipv6_flow_label, mask);
1794                 MLX5_SET(fte_match_set_misc,
1795                          misc_v, inner_ipv6_flow_label, val);
1796         } else {
1797                 MLX5_SET(fte_match_set_misc,
1798                          misc_c, outer_ipv6_flow_label, mask);
1799                 MLX5_SET(fte_match_set_misc,
1800                          misc_v, outer_ipv6_flow_label, val);
1801         }
1802 }
1803
1804 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1805 {
1806         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1807         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1808         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1809         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1810 }
1811
1812 #define LAST_ETH_FIELD vlan_tag
1813 #define LAST_IB_FIELD sl
1814 #define LAST_IPV4_FIELD tos
1815 #define LAST_IPV6_FIELD traffic_class
1816 #define LAST_TCP_UDP_FIELD src_port
1817 #define LAST_TUNNEL_FIELD tunnel_id
1818 #define LAST_FLOW_TAG_FIELD tag_id
1819 #define LAST_DROP_FIELD size
1820
1821 /* Field is the last supported field */
1822 #define FIELDS_NOT_SUPPORTED(filter, field)\
1823         memchr_inv((void *)&filter.field  +\
1824                    sizeof(filter.field), 0,\
1825                    sizeof(filter) -\
1826                    offsetof(typeof(filter), field) -\
1827                    sizeof(filter.field))
1828
1829 #define IPV4_VERSION 4
1830 #define IPV6_VERSION 6
1831 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
1832                            u32 *match_v, const union ib_flow_spec *ib_spec,
1833                            u32 *tag_id, bool *is_drop)
1834 {
1835         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1836                                            misc_parameters);
1837         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1838                                            misc_parameters);
1839         void *headers_c;
1840         void *headers_v;
1841         int match_ipv;
1842
1843         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1844                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1845                                          inner_headers);
1846                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1847                                          inner_headers);
1848                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1849                                         ft_field_support.inner_ip_version);
1850         } else {
1851                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1852                                          outer_headers);
1853                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1854                                          outer_headers);
1855                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1856                                         ft_field_support.outer_ip_version);
1857         }
1858
1859         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
1860         case IB_FLOW_SPEC_ETH:
1861                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1862                         return -EOPNOTSUPP;
1863
1864                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1865                                              dmac_47_16),
1866                                 ib_spec->eth.mask.dst_mac);
1867                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1868                                              dmac_47_16),
1869                                 ib_spec->eth.val.dst_mac);
1870
1871                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1872                                              smac_47_16),
1873                                 ib_spec->eth.mask.src_mac);
1874                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1875                                              smac_47_16),
1876                                 ib_spec->eth.val.src_mac);
1877
1878                 if (ib_spec->eth.mask.vlan_tag) {
1879                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1880                                  cvlan_tag, 1);
1881                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1882                                  cvlan_tag, 1);
1883
1884                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1885                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1886                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1887                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1888
1889                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1890                                  first_cfi,
1891                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1892                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1893                                  first_cfi,
1894                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1895
1896                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1897                                  first_prio,
1898                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1899                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1900                                  first_prio,
1901                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1902                 }
1903                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1904                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1905                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1906                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1907                 break;
1908         case IB_FLOW_SPEC_IPV4:
1909                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1910                         return -EOPNOTSUPP;
1911
1912                 if (match_ipv) {
1913                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1914                                  ip_version, 0xf);
1915                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1916                                  ip_version, IPV4_VERSION);
1917                 } else {
1918                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1919                                  ethertype, 0xffff);
1920                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1921                                  ethertype, ETH_P_IP);
1922                 }
1923
1924                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1925                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1926                        &ib_spec->ipv4.mask.src_ip,
1927                        sizeof(ib_spec->ipv4.mask.src_ip));
1928                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1929                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1930                        &ib_spec->ipv4.val.src_ip,
1931                        sizeof(ib_spec->ipv4.val.src_ip));
1932                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1933                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1934                        &ib_spec->ipv4.mask.dst_ip,
1935                        sizeof(ib_spec->ipv4.mask.dst_ip));
1936                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1937                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1938                        &ib_spec->ipv4.val.dst_ip,
1939                        sizeof(ib_spec->ipv4.val.dst_ip));
1940
1941                 set_tos(headers_c, headers_v,
1942                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1943
1944                 set_proto(headers_c, headers_v,
1945                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1946                 break;
1947         case IB_FLOW_SPEC_IPV6:
1948                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1949                         return -EOPNOTSUPP;
1950
1951                 if (match_ipv) {
1952                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1953                                  ip_version, 0xf);
1954                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1955                                  ip_version, IPV6_VERSION);
1956                 } else {
1957                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1958                                  ethertype, 0xffff);
1959                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1960                                  ethertype, ETH_P_IPV6);
1961                 }
1962
1963                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1964                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1965                        &ib_spec->ipv6.mask.src_ip,
1966                        sizeof(ib_spec->ipv6.mask.src_ip));
1967                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1968                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1969                        &ib_spec->ipv6.val.src_ip,
1970                        sizeof(ib_spec->ipv6.val.src_ip));
1971                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1972                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1973                        &ib_spec->ipv6.mask.dst_ip,
1974                        sizeof(ib_spec->ipv6.mask.dst_ip));
1975                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1976                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1977                        &ib_spec->ipv6.val.dst_ip,
1978                        sizeof(ib_spec->ipv6.val.dst_ip));
1979
1980                 set_tos(headers_c, headers_v,
1981                         ib_spec->ipv6.mask.traffic_class,
1982                         ib_spec->ipv6.val.traffic_class);
1983
1984                 set_proto(headers_c, headers_v,
1985                           ib_spec->ipv6.mask.next_hdr,
1986                           ib_spec->ipv6.val.next_hdr);
1987
1988                 set_flow_label(misc_params_c, misc_params_v,
1989                                ntohl(ib_spec->ipv6.mask.flow_label),
1990                                ntohl(ib_spec->ipv6.val.flow_label),
1991                                ib_spec->type & IB_FLOW_SPEC_INNER);
1992
1993                 break;
1994         case IB_FLOW_SPEC_TCP:
1995                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1996                                          LAST_TCP_UDP_FIELD))
1997                         return -EOPNOTSUPP;
1998
1999                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2000                          0xff);
2001                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2002                          IPPROTO_TCP);
2003
2004                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2005                          ntohs(ib_spec->tcp_udp.mask.src_port));
2006                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2007                          ntohs(ib_spec->tcp_udp.val.src_port));
2008
2009                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2010                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2011                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2012                          ntohs(ib_spec->tcp_udp.val.dst_port));
2013                 break;
2014         case IB_FLOW_SPEC_UDP:
2015                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2016                                          LAST_TCP_UDP_FIELD))
2017                         return -EOPNOTSUPP;
2018
2019                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2020                          0xff);
2021                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2022                          IPPROTO_UDP);
2023
2024                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2025                          ntohs(ib_spec->tcp_udp.mask.src_port));
2026                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2027                          ntohs(ib_spec->tcp_udp.val.src_port));
2028
2029                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2030                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2031                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2032                          ntohs(ib_spec->tcp_udp.val.dst_port));
2033                 break;
2034         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2035                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2036                                          LAST_TUNNEL_FIELD))
2037                         return -EOPNOTSUPP;
2038
2039                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2040                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2041                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2042                          ntohl(ib_spec->tunnel.val.tunnel_id));
2043                 break;
2044         case IB_FLOW_SPEC_ACTION_TAG:
2045                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2046                                          LAST_FLOW_TAG_FIELD))
2047                         return -EOPNOTSUPP;
2048                 if (ib_spec->flow_tag.tag_id >= BIT(24))
2049                         return -EINVAL;
2050
2051                 *tag_id = ib_spec->flow_tag.tag_id;
2052                 break;
2053         case IB_FLOW_SPEC_ACTION_DROP:
2054                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2055                                          LAST_DROP_FIELD))
2056                         return -EOPNOTSUPP;
2057                 *is_drop = true;
2058                 break;
2059         default:
2060                 return -EINVAL;
2061         }
2062
2063         return 0;
2064 }
2065
2066 /* If a flow could catch both multicast and unicast packets,
2067  * it won't fall into the multicast flow steering table and this rule
2068  * could steal other multicast packets.
2069  */
2070 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
2071 {
2072         struct ib_flow_spec_eth *eth_spec;
2073
2074         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2075             ib_attr->size < sizeof(struct ib_flow_attr) +
2076             sizeof(struct ib_flow_spec_eth) ||
2077             ib_attr->num_of_specs < 1)
2078                 return false;
2079
2080         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
2081         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
2082             eth_spec->size != sizeof(*eth_spec))
2083                 return false;
2084
2085         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2086                is_multicast_ether_addr(eth_spec->val.dst_mac);
2087 }
2088
2089 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2090                                const struct ib_flow_attr *flow_attr,
2091                                bool check_inner)
2092 {
2093         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2094         int match_ipv = check_inner ?
2095                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2096                                         ft_field_support.inner_ip_version) :
2097                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2098                                         ft_field_support.outer_ip_version);
2099         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2100         bool ipv4_spec_valid, ipv6_spec_valid;
2101         unsigned int ip_spec_type = 0;
2102         bool has_ethertype = false;
2103         unsigned int spec_index;
2104         bool mask_valid = true;
2105         u16 eth_type = 0;
2106         bool type_valid;
2107
2108         /* Validate that ethertype is correct */
2109         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2110                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2111                     ib_spec->eth.mask.ether_type) {
2112                         mask_valid = (ib_spec->eth.mask.ether_type ==
2113                                       htons(0xffff));
2114                         has_ethertype = true;
2115                         eth_type = ntohs(ib_spec->eth.val.ether_type);
2116                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2117                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2118                         ip_spec_type = ib_spec->type;
2119                 }
2120                 ib_spec = (void *)ib_spec + ib_spec->size;
2121         }
2122
2123         type_valid = (!has_ethertype) || (!ip_spec_type);
2124         if (!type_valid && mask_valid) {
2125                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2126                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2127                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2128                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2129
2130                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2131                              (((eth_type == ETH_P_MPLS_UC) ||
2132                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2133         }
2134
2135         return type_valid;
2136 }
2137
2138 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2139                           const struct ib_flow_attr *flow_attr)
2140 {
2141         return is_valid_ethertype(mdev, flow_attr, false) &&
2142                is_valid_ethertype(mdev, flow_attr, true);
2143 }
2144
2145 static void put_flow_table(struct mlx5_ib_dev *dev,
2146                            struct mlx5_ib_flow_prio *prio, bool ft_added)
2147 {
2148         prio->refcount -= !!ft_added;
2149         if (!prio->refcount) {
2150                 mlx5_destroy_flow_table(prio->flow_table);
2151                 prio->flow_table = NULL;
2152         }
2153 }
2154
2155 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2156 {
2157         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2158         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2159                                                           struct mlx5_ib_flow_handler,
2160                                                           ibflow);
2161         struct mlx5_ib_flow_handler *iter, *tmp;
2162
2163         mutex_lock(&dev->flow_db.lock);
2164
2165         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2166                 mlx5_del_flow_rules(iter->rule);
2167                 put_flow_table(dev, iter->prio, true);
2168                 list_del(&iter->list);
2169                 kfree(iter);
2170         }
2171
2172         mlx5_del_flow_rules(handler->rule);
2173         put_flow_table(dev, handler->prio, true);
2174         mutex_unlock(&dev->flow_db.lock);
2175
2176         kfree(handler);
2177
2178         return 0;
2179 }
2180
2181 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2182 {
2183         priority *= 2;
2184         if (!dont_trap)
2185                 priority++;
2186         return priority;
2187 }
2188
2189 enum flow_table_type {
2190         MLX5_IB_FT_RX,
2191         MLX5_IB_FT_TX
2192 };
2193
2194 #define MLX5_FS_MAX_TYPES        6
2195 #define MLX5_FS_MAX_ENTRIES      BIT(16)
2196 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2197                                                 struct ib_flow_attr *flow_attr,
2198                                                 enum flow_table_type ft_type)
2199 {
2200         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2201         struct mlx5_flow_namespace *ns = NULL;
2202         struct mlx5_ib_flow_prio *prio;
2203         struct mlx5_flow_table *ft;
2204         int max_table_size;
2205         int num_entries;
2206         int num_groups;
2207         int priority;
2208         int err = 0;
2209
2210         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2211                                                        log_max_ft_size));
2212         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2213                 if (flow_is_multicast_only(flow_attr) &&
2214                     !dont_trap)
2215                         priority = MLX5_IB_FLOW_MCAST_PRIO;
2216                 else
2217                         priority = ib_prio_to_core_prio(flow_attr->priority,
2218                                                         dont_trap);
2219                 ns = mlx5_get_flow_namespace(dev->mdev,
2220                                              MLX5_FLOW_NAMESPACE_BYPASS);
2221                 num_entries = MLX5_FS_MAX_ENTRIES;
2222                 num_groups = MLX5_FS_MAX_TYPES;
2223                 prio = &dev->flow_db.prios[priority];
2224         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2225                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2226                 ns = mlx5_get_flow_namespace(dev->mdev,
2227                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
2228                 build_leftovers_ft_param(&priority,
2229                                          &num_entries,
2230                                          &num_groups);
2231                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2232         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2233                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2234                                         allow_sniffer_and_nic_rx_shared_tir))
2235                         return ERR_PTR(-ENOTSUPP);
2236
2237                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2238                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2239                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2240
2241                 prio = &dev->flow_db.sniffer[ft_type];
2242                 priority = 0;
2243                 num_entries = 1;
2244                 num_groups = 1;
2245         }
2246
2247         if (!ns)
2248                 return ERR_PTR(-ENOTSUPP);
2249
2250         if (num_entries > max_table_size)
2251                 return ERR_PTR(-ENOMEM);
2252
2253         ft = prio->flow_table;
2254         if (!ft) {
2255                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2256                                                          num_entries,
2257                                                          num_groups,
2258                                                          0, 0);
2259
2260                 if (!IS_ERR(ft)) {
2261                         prio->refcount = 0;
2262                         prio->flow_table = ft;
2263                 } else {
2264                         err = PTR_ERR(ft);
2265                 }
2266         }
2267
2268         return err ? ERR_PTR(err) : prio;
2269 }
2270
2271 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2272                                                      struct mlx5_ib_flow_prio *ft_prio,
2273                                                      const struct ib_flow_attr *flow_attr,
2274                                                      struct mlx5_flow_destination *dst)
2275 {
2276         struct mlx5_flow_table  *ft = ft_prio->flow_table;
2277         struct mlx5_ib_flow_handler *handler;
2278         struct mlx5_flow_act flow_act = {0};
2279         struct mlx5_flow_spec *spec;
2280         struct mlx5_flow_destination *rule_dst = dst;
2281         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2282         unsigned int spec_index;
2283         u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2284         bool is_drop = false;
2285         int err = 0;
2286         int dest_num = 1;
2287
2288         if (!is_valid_attr(dev->mdev, flow_attr))
2289                 return ERR_PTR(-EINVAL);
2290
2291         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2292         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2293         if (!handler || !spec) {
2294                 err = -ENOMEM;
2295                 goto free;
2296         }
2297
2298         INIT_LIST_HEAD(&handler->list);
2299
2300         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2301                 err = parse_flow_attr(dev->mdev, spec->match_criteria,
2302                                       spec->match_value,
2303                                       ib_flow, &flow_tag, &is_drop);
2304                 if (err < 0)
2305                         goto free;
2306
2307                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2308         }
2309
2310         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2311         if (is_drop) {
2312                 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2313                 rule_dst = NULL;
2314                 dest_num = 0;
2315         } else {
2316                 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2317                     MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2318         }
2319
2320         if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2321             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2322              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2323                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2324                              flow_tag, flow_attr->type);
2325                 err = -EINVAL;
2326                 goto free;
2327         }
2328         flow_act.flow_tag = flow_tag;
2329         handler->rule = mlx5_add_flow_rules(ft, spec,
2330                                             &flow_act,
2331                                             rule_dst, dest_num);
2332
2333         if (IS_ERR(handler->rule)) {
2334                 err = PTR_ERR(handler->rule);
2335                 goto free;
2336         }
2337
2338         ft_prio->refcount++;
2339         handler->prio = ft_prio;
2340
2341         ft_prio->flow_table = ft;
2342 free:
2343         if (err)
2344                 kfree(handler);
2345         kvfree(spec);
2346         return err ? ERR_PTR(err) : handler;
2347 }
2348
2349 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2350                                                           struct mlx5_ib_flow_prio *ft_prio,
2351                                                           struct ib_flow_attr *flow_attr,
2352                                                           struct mlx5_flow_destination *dst)
2353 {
2354         struct mlx5_ib_flow_handler *handler_dst = NULL;
2355         struct mlx5_ib_flow_handler *handler = NULL;
2356
2357         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2358         if (!IS_ERR(handler)) {
2359                 handler_dst = create_flow_rule(dev, ft_prio,
2360                                                flow_attr, dst);
2361                 if (IS_ERR(handler_dst)) {
2362                         mlx5_del_flow_rules(handler->rule);
2363                         ft_prio->refcount--;
2364                         kfree(handler);
2365                         handler = handler_dst;
2366                 } else {
2367                         list_add(&handler_dst->list, &handler->list);
2368                 }
2369         }
2370
2371         return handler;
2372 }
2373 enum {
2374         LEFTOVERS_MC,
2375         LEFTOVERS_UC,
2376 };
2377
2378 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2379                                                           struct mlx5_ib_flow_prio *ft_prio,
2380                                                           struct ib_flow_attr *flow_attr,
2381                                                           struct mlx5_flow_destination *dst)
2382 {
2383         struct mlx5_ib_flow_handler *handler_ucast = NULL;
2384         struct mlx5_ib_flow_handler *handler = NULL;
2385
2386         static struct {
2387                 struct ib_flow_attr     flow_attr;
2388                 struct ib_flow_spec_eth eth_flow;
2389         } leftovers_specs[] = {
2390                 [LEFTOVERS_MC] = {
2391                         .flow_attr = {
2392                                 .num_of_specs = 1,
2393                                 .size = sizeof(leftovers_specs[0])
2394                         },
2395                         .eth_flow = {
2396                                 .type = IB_FLOW_SPEC_ETH,
2397                                 .size = sizeof(struct ib_flow_spec_eth),
2398                                 .mask = {.dst_mac = {0x1} },
2399                                 .val =  {.dst_mac = {0x1} }
2400                         }
2401                 },
2402                 [LEFTOVERS_UC] = {
2403                         .flow_attr = {
2404                                 .num_of_specs = 1,
2405                                 .size = sizeof(leftovers_specs[0])
2406                         },
2407                         .eth_flow = {
2408                                 .type = IB_FLOW_SPEC_ETH,
2409                                 .size = sizeof(struct ib_flow_spec_eth),
2410                                 .mask = {.dst_mac = {0x1} },
2411                                 .val = {.dst_mac = {} }
2412                         }
2413                 }
2414         };
2415
2416         handler = create_flow_rule(dev, ft_prio,
2417                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
2418                                    dst);
2419         if (!IS_ERR(handler) &&
2420             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2421                 handler_ucast = create_flow_rule(dev, ft_prio,
2422                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
2423                                                  dst);
2424                 if (IS_ERR(handler_ucast)) {
2425                         mlx5_del_flow_rules(handler->rule);
2426                         ft_prio->refcount--;
2427                         kfree(handler);
2428                         handler = handler_ucast;
2429                 } else {
2430                         list_add(&handler_ucast->list, &handler->list);
2431                 }
2432         }
2433
2434         return handler;
2435 }
2436
2437 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2438                                                         struct mlx5_ib_flow_prio *ft_rx,
2439                                                         struct mlx5_ib_flow_prio *ft_tx,
2440                                                         struct mlx5_flow_destination *dst)
2441 {
2442         struct mlx5_ib_flow_handler *handler_rx;
2443         struct mlx5_ib_flow_handler *handler_tx;
2444         int err;
2445         static const struct ib_flow_attr flow_attr  = {
2446                 .num_of_specs = 0,
2447                 .size = sizeof(flow_attr)
2448         };
2449
2450         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2451         if (IS_ERR(handler_rx)) {
2452                 err = PTR_ERR(handler_rx);
2453                 goto err;
2454         }
2455
2456         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2457         if (IS_ERR(handler_tx)) {
2458                 err = PTR_ERR(handler_tx);
2459                 goto err_tx;
2460         }
2461
2462         list_add(&handler_tx->list, &handler_rx->list);
2463
2464         return handler_rx;
2465
2466 err_tx:
2467         mlx5_del_flow_rules(handler_rx->rule);
2468         ft_rx->refcount--;
2469         kfree(handler_rx);
2470 err:
2471         return ERR_PTR(err);
2472 }
2473
2474 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2475                                            struct ib_flow_attr *flow_attr,
2476                                            int domain)
2477 {
2478         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2479         struct mlx5_ib_qp *mqp = to_mqp(qp);
2480         struct mlx5_ib_flow_handler *handler = NULL;
2481         struct mlx5_flow_destination *dst = NULL;
2482         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2483         struct mlx5_ib_flow_prio *ft_prio;
2484         int err;
2485
2486         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2487                 return ERR_PTR(-ENOMEM);
2488
2489         if (domain != IB_FLOW_DOMAIN_USER ||
2490             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2491             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2492                 return ERR_PTR(-EINVAL);
2493
2494         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2495         if (!dst)
2496                 return ERR_PTR(-ENOMEM);
2497
2498         mutex_lock(&dev->flow_db.lock);
2499
2500         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2501         if (IS_ERR(ft_prio)) {
2502                 err = PTR_ERR(ft_prio);
2503                 goto unlock;
2504         }
2505         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2506                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2507                 if (IS_ERR(ft_prio_tx)) {
2508                         err = PTR_ERR(ft_prio_tx);
2509                         ft_prio_tx = NULL;
2510                         goto destroy_ft;
2511                 }
2512         }
2513
2514         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2515         if (mqp->flags & MLX5_IB_QP_RSS)
2516                 dst->tir_num = mqp->rss_qp.tirn;
2517         else
2518                 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2519
2520         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2521                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
2522                         handler = create_dont_trap_rule(dev, ft_prio,
2523                                                         flow_attr, dst);
2524                 } else {
2525                         handler = create_flow_rule(dev, ft_prio, flow_attr,
2526                                                    dst);
2527                 }
2528         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2529                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2530                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2531                                                 dst);
2532         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2533                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2534         } else {
2535                 err = -EINVAL;
2536                 goto destroy_ft;
2537         }
2538
2539         if (IS_ERR(handler)) {
2540                 err = PTR_ERR(handler);
2541                 handler = NULL;
2542                 goto destroy_ft;
2543         }
2544
2545         mutex_unlock(&dev->flow_db.lock);
2546         kfree(dst);
2547
2548         return &handler->ibflow;
2549
2550 destroy_ft:
2551         put_flow_table(dev, ft_prio, false);
2552         if (ft_prio_tx)
2553                 put_flow_table(dev, ft_prio_tx, false);
2554 unlock:
2555         mutex_unlock(&dev->flow_db.lock);
2556         kfree(dst);
2557         kfree(handler);
2558         return ERR_PTR(err);
2559 }
2560
2561 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2562 {
2563         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2564         int err;
2565
2566         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2567         if (err)
2568                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2569                              ibqp->qp_num, gid->raw);
2570
2571         return err;
2572 }
2573
2574 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2575 {
2576         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2577         int err;
2578
2579         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2580         if (err)
2581                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2582                              ibqp->qp_num, gid->raw);
2583
2584         return err;
2585 }
2586
2587 static int init_node_data(struct mlx5_ib_dev *dev)
2588 {
2589         int err;
2590
2591         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2592         if (err)
2593                 return err;
2594
2595         dev->mdev->rev_id = dev->mdev->pdev->revision;
2596
2597         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2598 }
2599
2600 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2601                              char *buf)
2602 {
2603         struct mlx5_ib_dev *dev =
2604                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2605
2606         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2607 }
2608
2609 static ssize_t show_reg_pages(struct device *device,
2610                               struct device_attribute *attr, char *buf)
2611 {
2612         struct mlx5_ib_dev *dev =
2613                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2614
2615         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2616 }
2617
2618 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2619                         char *buf)
2620 {
2621         struct mlx5_ib_dev *dev =
2622                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2623         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2624 }
2625
2626 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2627                         char *buf)
2628 {
2629         struct mlx5_ib_dev *dev =
2630                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2631         return sprintf(buf, "%x\n", dev->mdev->rev_id);
2632 }
2633
2634 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2635                           char *buf)
2636 {
2637         struct mlx5_ib_dev *dev =
2638                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2639         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2640                        dev->mdev->board_id);
2641 }
2642
2643 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
2644 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
2645 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
2646 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2647 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2648
2649 static struct device_attribute *mlx5_class_attributes[] = {
2650         &dev_attr_hw_rev,
2651         &dev_attr_hca_type,
2652         &dev_attr_board_id,
2653         &dev_attr_fw_pages,
2654         &dev_attr_reg_pages,
2655 };
2656
2657 static void pkey_change_handler(struct work_struct *work)
2658 {
2659         struct mlx5_ib_port_resources *ports =
2660                 container_of(work, struct mlx5_ib_port_resources,
2661                              pkey_change_work);
2662
2663         mutex_lock(&ports->devr->mutex);
2664         mlx5_ib_gsi_pkey_change(ports->gsi);
2665         mutex_unlock(&ports->devr->mutex);
2666 }
2667
2668 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2669 {
2670         struct mlx5_ib_qp *mqp;
2671         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2672         struct mlx5_core_cq *mcq;
2673         struct list_head cq_armed_list;
2674         unsigned long flags_qp;
2675         unsigned long flags_cq;
2676         unsigned long flags;
2677
2678         INIT_LIST_HEAD(&cq_armed_list);
2679
2680         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2681         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2682         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2683                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2684                 if (mqp->sq.tail != mqp->sq.head) {
2685                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2686                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2687                         if (send_mcq->mcq.comp &&
2688                             mqp->ibqp.send_cq->comp_handler) {
2689                                 if (!send_mcq->mcq.reset_notify_added) {
2690                                         send_mcq->mcq.reset_notify_added = 1;
2691                                         list_add_tail(&send_mcq->mcq.reset_notify,
2692                                                       &cq_armed_list);
2693                                 }
2694                         }
2695                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2696                 }
2697                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2698                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2699                 /* no handling is needed for SRQ */
2700                 if (!mqp->ibqp.srq) {
2701                         if (mqp->rq.tail != mqp->rq.head) {
2702                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2703                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2704                                 if (recv_mcq->mcq.comp &&
2705                                     mqp->ibqp.recv_cq->comp_handler) {
2706                                         if (!recv_mcq->mcq.reset_notify_added) {
2707                                                 recv_mcq->mcq.reset_notify_added = 1;
2708                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2709                                                               &cq_armed_list);
2710                                         }
2711                                 }
2712                                 spin_unlock_irqrestore(&recv_mcq->lock,
2713                                                        flags_cq);
2714                         }
2715                 }
2716                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2717         }
2718         /*At that point all inflight post send were put to be executed as of we
2719          * lock/unlock above locks Now need to arm all involved CQs.
2720          */
2721         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2722                 mcq->comp(mcq);
2723         }
2724         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2725 }
2726
2727 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2728                           enum mlx5_dev_event event, unsigned long param)
2729 {
2730         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2731         struct ib_event ibev;
2732         bool fatal = false;
2733         u8 port = 0;
2734
2735         switch (event) {
2736         case MLX5_DEV_EVENT_SYS_ERROR:
2737                 ibev.event = IB_EVENT_DEVICE_FATAL;
2738                 mlx5_ib_handle_internal_error(ibdev);
2739                 fatal = true;
2740                 break;
2741
2742         case MLX5_DEV_EVENT_PORT_UP:
2743         case MLX5_DEV_EVENT_PORT_DOWN:
2744         case MLX5_DEV_EVENT_PORT_INITIALIZED:
2745                 port = (u8)param;
2746
2747                 /* In RoCE, port up/down events are handled in
2748                  * mlx5_netdev_event().
2749                  */
2750                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2751                         IB_LINK_LAYER_ETHERNET)
2752                         return;
2753
2754                 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2755                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2756                 break;
2757
2758         case MLX5_DEV_EVENT_LID_CHANGE:
2759                 ibev.event = IB_EVENT_LID_CHANGE;
2760                 port = (u8)param;
2761                 break;
2762
2763         case MLX5_DEV_EVENT_PKEY_CHANGE:
2764                 ibev.event = IB_EVENT_PKEY_CHANGE;
2765                 port = (u8)param;
2766
2767                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2768                 break;
2769
2770         case MLX5_DEV_EVENT_GUID_CHANGE:
2771                 ibev.event = IB_EVENT_GID_CHANGE;
2772                 port = (u8)param;
2773                 break;
2774
2775         case MLX5_DEV_EVENT_CLIENT_REREG:
2776                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2777                 port = (u8)param;
2778                 break;
2779         default:
2780                 return;
2781         }
2782
2783         ibev.device           = &ibdev->ib_dev;
2784         ibev.element.port_num = port;
2785
2786         if (port < 1 || port > ibdev->num_ports) {
2787                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2788                 return;
2789         }
2790
2791         if (ibdev->ib_active)
2792                 ib_dispatch_event(&ibev);
2793
2794         if (fatal)
2795                 ibdev->ib_active = false;
2796 }
2797
2798 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2799 {
2800         struct mlx5_hca_vport_context vport_ctx;
2801         int err;
2802         int port;
2803
2804         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2805                 dev->mdev->port_caps[port - 1].has_smi = false;
2806                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2807                     MLX5_CAP_PORT_TYPE_IB) {
2808                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2809                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2810                                                                    port, 0,
2811                                                                    &vport_ctx);
2812                                 if (err) {
2813                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2814                                                     port, err);
2815                                         return err;
2816                                 }
2817                                 dev->mdev->port_caps[port - 1].has_smi =
2818                                         vport_ctx.has_smi;
2819                         } else {
2820                                 dev->mdev->port_caps[port - 1].has_smi = true;
2821                         }
2822                 }
2823         }
2824         return 0;
2825 }
2826
2827 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2828 {
2829         int port;
2830
2831         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2832                 mlx5_query_ext_port_caps(dev, port);
2833 }
2834
2835 static int get_port_caps(struct mlx5_ib_dev *dev)
2836 {
2837         struct ib_device_attr *dprops = NULL;
2838         struct ib_port_attr *pprops = NULL;
2839         int err = -ENOMEM;
2840         int port;
2841         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2842
2843         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2844         if (!pprops)
2845                 goto out;
2846
2847         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2848         if (!dprops)
2849                 goto out;
2850
2851         err = set_has_smi_cap(dev);
2852         if (err)
2853                 goto out;
2854
2855         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2856         if (err) {
2857                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2858                 goto out;
2859         }
2860
2861         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2862                 memset(pprops, 0, sizeof(*pprops));
2863                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2864                 if (err) {
2865                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
2866                                      port, err);
2867                         break;
2868                 }
2869                 dev->mdev->port_caps[port - 1].pkey_table_len =
2870                                                 dprops->max_pkeys;
2871                 dev->mdev->port_caps[port - 1].gid_table_len =
2872                                                 pprops->gid_tbl_len;
2873                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2874                             dprops->max_pkeys, pprops->gid_tbl_len);
2875         }
2876
2877 out:
2878         kfree(pprops);
2879         kfree(dprops);
2880
2881         return err;
2882 }
2883
2884 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2885 {
2886         int err;
2887
2888         err = mlx5_mr_cache_cleanup(dev);
2889         if (err)
2890                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2891
2892         mlx5_ib_destroy_qp(dev->umrc.qp);
2893         ib_free_cq(dev->umrc.cq);
2894         ib_dealloc_pd(dev->umrc.pd);
2895 }
2896
2897 enum {
2898         MAX_UMR_WR = 128,
2899 };
2900
2901 static int create_umr_res(struct mlx5_ib_dev *dev)
2902 {
2903         struct ib_qp_init_attr *init_attr = NULL;
2904         struct ib_qp_attr *attr = NULL;
2905         struct ib_pd *pd;
2906         struct ib_cq *cq;
2907         struct ib_qp *qp;
2908         int ret;
2909
2910         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2911         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2912         if (!attr || !init_attr) {
2913                 ret = -ENOMEM;
2914                 goto error_0;
2915         }
2916
2917         pd = ib_alloc_pd(&dev->ib_dev, 0);
2918         if (IS_ERR(pd)) {
2919                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2920                 ret = PTR_ERR(pd);
2921                 goto error_0;
2922         }
2923
2924         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2925         if (IS_ERR(cq)) {
2926                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2927                 ret = PTR_ERR(cq);
2928                 goto error_2;
2929         }
2930
2931         init_attr->send_cq = cq;
2932         init_attr->recv_cq = cq;
2933         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2934         init_attr->cap.max_send_wr = MAX_UMR_WR;
2935         init_attr->cap.max_send_sge = 1;
2936         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2937         init_attr->port_num = 1;
2938         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2939         if (IS_ERR(qp)) {
2940                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2941                 ret = PTR_ERR(qp);
2942                 goto error_3;
2943         }
2944         qp->device     = &dev->ib_dev;
2945         qp->real_qp    = qp;
2946         qp->uobject    = NULL;
2947         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
2948
2949         attr->qp_state = IB_QPS_INIT;
2950         attr->port_num = 1;
2951         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2952                                 IB_QP_PORT, NULL);
2953         if (ret) {
2954                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2955                 goto error_4;
2956         }
2957
2958         memset(attr, 0, sizeof(*attr));
2959         attr->qp_state = IB_QPS_RTR;
2960         attr->path_mtu = IB_MTU_256;
2961
2962         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2963         if (ret) {
2964                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2965                 goto error_4;
2966         }
2967
2968         memset(attr, 0, sizeof(*attr));
2969         attr->qp_state = IB_QPS_RTS;
2970         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2971         if (ret) {
2972                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2973                 goto error_4;
2974         }
2975
2976         dev->umrc.qp = qp;
2977         dev->umrc.cq = cq;
2978         dev->umrc.pd = pd;
2979
2980         sema_init(&dev->umrc.sem, MAX_UMR_WR);
2981         ret = mlx5_mr_cache_init(dev);
2982         if (ret) {
2983                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2984                 goto error_4;
2985         }
2986
2987         kfree(attr);
2988         kfree(init_attr);
2989
2990         return 0;
2991
2992 error_4:
2993         mlx5_ib_destroy_qp(qp);
2994
2995 error_3:
2996         ib_free_cq(cq);
2997
2998 error_2:
2999         ib_dealloc_pd(pd);
3000
3001 error_0:
3002         kfree(attr);
3003         kfree(init_attr);
3004         return ret;
3005 }
3006
3007 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3008 {
3009         switch (umr_fence_cap) {
3010         case MLX5_CAP_UMR_FENCE_NONE:
3011                 return MLX5_FENCE_MODE_NONE;
3012         case MLX5_CAP_UMR_FENCE_SMALL:
3013                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3014         default:
3015                 return MLX5_FENCE_MODE_STRONG_ORDERING;
3016         }
3017 }
3018
3019 static int create_dev_resources(struct mlx5_ib_resources *devr)
3020 {
3021         struct ib_srq_init_attr attr;
3022         struct mlx5_ib_dev *dev;
3023         struct ib_cq_init_attr cq_attr = {.cqe = 1};
3024         int port;
3025         int ret = 0;
3026
3027         dev = container_of(devr, struct mlx5_ib_dev, devr);
3028
3029         mutex_init(&devr->mutex);
3030
3031         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3032         if (IS_ERR(devr->p0)) {
3033                 ret = PTR_ERR(devr->p0);
3034                 goto error0;
3035         }
3036         devr->p0->device  = &dev->ib_dev;
3037         devr->p0->uobject = NULL;
3038         atomic_set(&devr->p0->usecnt, 0);
3039
3040         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
3041         if (IS_ERR(devr->c0)) {
3042                 ret = PTR_ERR(devr->c0);
3043                 goto error1;
3044         }
3045         devr->c0->device        = &dev->ib_dev;
3046         devr->c0->uobject       = NULL;
3047         devr->c0->comp_handler  = NULL;
3048         devr->c0->event_handler = NULL;
3049         devr->c0->cq_context    = NULL;
3050         atomic_set(&devr->c0->usecnt, 0);
3051
3052         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3053         if (IS_ERR(devr->x0)) {
3054                 ret = PTR_ERR(devr->x0);
3055                 goto error2;
3056         }
3057         devr->x0->device = &dev->ib_dev;
3058         devr->x0->inode = NULL;
3059         atomic_set(&devr->x0->usecnt, 0);
3060         mutex_init(&devr->x0->tgt_qp_mutex);
3061         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3062
3063         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3064         if (IS_ERR(devr->x1)) {
3065                 ret = PTR_ERR(devr->x1);
3066                 goto error3;
3067         }
3068         devr->x1->device = &dev->ib_dev;
3069         devr->x1->inode = NULL;
3070         atomic_set(&devr->x1->usecnt, 0);
3071         mutex_init(&devr->x1->tgt_qp_mutex);
3072         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3073
3074         memset(&attr, 0, sizeof(attr));
3075         attr.attr.max_sge = 1;
3076         attr.attr.max_wr = 1;
3077         attr.srq_type = IB_SRQT_XRC;
3078         attr.ext.xrc.cq = devr->c0;
3079         attr.ext.xrc.xrcd = devr->x0;
3080
3081         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3082         if (IS_ERR(devr->s0)) {
3083                 ret = PTR_ERR(devr->s0);
3084                 goto error4;
3085         }
3086         devr->s0->device        = &dev->ib_dev;
3087         devr->s0->pd            = devr->p0;
3088         devr->s0->uobject       = NULL;
3089         devr->s0->event_handler = NULL;
3090         devr->s0->srq_context   = NULL;
3091         devr->s0->srq_type      = IB_SRQT_XRC;
3092         devr->s0->ext.xrc.xrcd  = devr->x0;
3093         devr->s0->ext.xrc.cq    = devr->c0;
3094         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3095         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
3096         atomic_inc(&devr->p0->usecnt);
3097         atomic_set(&devr->s0->usecnt, 0);
3098
3099         memset(&attr, 0, sizeof(attr));
3100         attr.attr.max_sge = 1;
3101         attr.attr.max_wr = 1;
3102         attr.srq_type = IB_SRQT_BASIC;
3103         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3104         if (IS_ERR(devr->s1)) {
3105                 ret = PTR_ERR(devr->s1);
3106                 goto error5;
3107         }
3108         devr->s1->device        = &dev->ib_dev;
3109         devr->s1->pd            = devr->p0;
3110         devr->s1->uobject       = NULL;
3111         devr->s1->event_handler = NULL;
3112         devr->s1->srq_context   = NULL;
3113         devr->s1->srq_type      = IB_SRQT_BASIC;
3114         devr->s1->ext.xrc.cq    = devr->c0;
3115         atomic_inc(&devr->p0->usecnt);
3116         atomic_set(&devr->s0->usecnt, 0);
3117
3118         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3119                 INIT_WORK(&devr->ports[port].pkey_change_work,
3120                           pkey_change_handler);
3121                 devr->ports[port].devr = devr;
3122         }
3123
3124         return 0;
3125
3126 error5:
3127         mlx5_ib_destroy_srq(devr->s0);
3128 error4:
3129         mlx5_ib_dealloc_xrcd(devr->x1);
3130 error3:
3131         mlx5_ib_dealloc_xrcd(devr->x0);
3132 error2:
3133         mlx5_ib_destroy_cq(devr->c0);
3134 error1:
3135         mlx5_ib_dealloc_pd(devr->p0);
3136 error0:
3137         return ret;
3138 }
3139
3140 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3141 {
3142         struct mlx5_ib_dev *dev =
3143                 container_of(devr, struct mlx5_ib_dev, devr);
3144         int port;
3145
3146         mlx5_ib_destroy_srq(devr->s1);
3147         mlx5_ib_destroy_srq(devr->s0);
3148         mlx5_ib_dealloc_xrcd(devr->x0);
3149         mlx5_ib_dealloc_xrcd(devr->x1);
3150         mlx5_ib_destroy_cq(devr->c0);
3151         mlx5_ib_dealloc_pd(devr->p0);
3152
3153         /* Make sure no change P_Key work items are still executing */
3154         for (port = 0; port < dev->num_ports; ++port)
3155                 cancel_work_sync(&devr->ports[port].pkey_change_work);
3156 }
3157
3158 static u32 get_core_cap_flags(struct ib_device *ibdev)
3159 {
3160         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3161         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3162         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3163         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3164         u32 ret = 0;
3165
3166         if (ll == IB_LINK_LAYER_INFINIBAND)
3167                 return RDMA_CORE_PORT_IBA_IB;
3168
3169         ret = RDMA_CORE_PORT_RAW_PACKET;
3170
3171         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3172                 return ret;
3173
3174         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3175                 return ret;
3176
3177         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3178                 ret |= RDMA_CORE_PORT_IBA_ROCE;
3179
3180         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3181                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3182
3183         return ret;
3184 }
3185
3186 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3187                                struct ib_port_immutable *immutable)
3188 {
3189         struct ib_port_attr attr;
3190         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3191         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3192         int err;
3193
3194         immutable->core_cap_flags = get_core_cap_flags(ibdev);
3195
3196         err = ib_query_port(ibdev, port_num, &attr);
3197         if (err)
3198                 return err;
3199
3200         immutable->pkey_tbl_len = attr.pkey_tbl_len;
3201         immutable->gid_tbl_len = attr.gid_tbl_len;
3202         immutable->core_cap_flags = get_core_cap_flags(ibdev);
3203         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3204                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3205
3206         return 0;
3207 }
3208
3209 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
3210                            size_t str_len)
3211 {
3212         struct mlx5_ib_dev *dev =
3213                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3214         snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
3215                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
3216 }
3217
3218 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3219 {
3220         struct mlx5_core_dev *mdev = dev->mdev;
3221         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3222                                                                  MLX5_FLOW_NAMESPACE_LAG);
3223         struct mlx5_flow_table *ft;
3224         int err;
3225
3226         if (!ns || !mlx5_lag_is_active(mdev))
3227                 return 0;
3228
3229         err = mlx5_cmd_create_vport_lag(mdev);
3230         if (err)
3231                 return err;
3232
3233         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3234         if (IS_ERR(ft)) {
3235                 err = PTR_ERR(ft);
3236                 goto err_destroy_vport_lag;
3237         }
3238
3239         dev->flow_db.lag_demux_ft = ft;
3240         return 0;
3241
3242 err_destroy_vport_lag:
3243         mlx5_cmd_destroy_vport_lag(mdev);
3244         return err;
3245 }
3246
3247 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3248 {
3249         struct mlx5_core_dev *mdev = dev->mdev;
3250
3251         if (dev->flow_db.lag_demux_ft) {
3252                 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3253                 dev->flow_db.lag_demux_ft = NULL;
3254
3255                 mlx5_cmd_destroy_vport_lag(mdev);
3256         }
3257 }
3258
3259 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3260 {
3261         int err;
3262
3263         dev->roce.nb.notifier_call = mlx5_netdev_event;
3264         err = register_netdevice_notifier(&dev->roce.nb);
3265         if (err) {
3266                 dev->roce.nb.notifier_call = NULL;
3267                 return err;
3268         }
3269
3270         return 0;
3271 }
3272
3273 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
3274 {
3275         if (dev->roce.nb.notifier_call) {
3276                 unregister_netdevice_notifier(&dev->roce.nb);
3277                 dev->roce.nb.notifier_call = NULL;
3278         }
3279 }
3280
3281 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3282 {
3283         int err;
3284
3285         err = mlx5_add_netdev_notifier(dev);
3286         if (err)
3287                 return err;
3288
3289         if (MLX5_CAP_GEN(dev->mdev, roce)) {
3290                 err = mlx5_nic_vport_enable_roce(dev->mdev);
3291                 if (err)
3292                         goto err_unregister_netdevice_notifier;
3293         }
3294
3295         err = mlx5_eth_lag_init(dev);
3296         if (err)
3297                 goto err_disable_roce;
3298
3299         return 0;
3300
3301 err_disable_roce:
3302         if (MLX5_CAP_GEN(dev->mdev, roce))
3303                 mlx5_nic_vport_disable_roce(dev->mdev);
3304
3305 err_unregister_netdevice_notifier:
3306         mlx5_remove_netdev_notifier(dev);
3307         return err;
3308 }
3309
3310 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3311 {
3312         mlx5_eth_lag_cleanup(dev);
3313         if (MLX5_CAP_GEN(dev->mdev, roce))
3314                 mlx5_nic_vport_disable_roce(dev->mdev);
3315 }
3316
3317 struct mlx5_ib_counter {
3318         const char *name;
3319         size_t offset;
3320 };
3321
3322 #define INIT_Q_COUNTER(_name)           \
3323         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3324
3325 static const struct mlx5_ib_counter basic_q_cnts[] = {
3326         INIT_Q_COUNTER(rx_write_requests),
3327         INIT_Q_COUNTER(rx_read_requests),
3328         INIT_Q_COUNTER(rx_atomic_requests),
3329         INIT_Q_COUNTER(out_of_buffer),
3330 };
3331
3332 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
3333         INIT_Q_COUNTER(out_of_sequence),
3334 };
3335
3336 static const struct mlx5_ib_counter retrans_q_cnts[] = {
3337         INIT_Q_COUNTER(duplicate_request),
3338         INIT_Q_COUNTER(rnr_nak_retry_err),
3339         INIT_Q_COUNTER(packet_seq_err),
3340         INIT_Q_COUNTER(implied_nak_seq_err),
3341         INIT_Q_COUNTER(local_ack_timeout_err),
3342 };
3343
3344 #define INIT_CONG_COUNTER(_name)                \
3345         { .name = #_name, .offset =     \
3346                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3347
3348 static const struct mlx5_ib_counter cong_cnts[] = {
3349         INIT_CONG_COUNTER(rp_cnp_ignored),
3350         INIT_CONG_COUNTER(rp_cnp_handled),
3351         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3352         INIT_CONG_COUNTER(np_cnp_sent),
3353 };
3354
3355 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
3356 {
3357         unsigned int i;
3358
3359         for (i = 0; i < dev->num_ports; i++) {
3360                 mlx5_core_dealloc_q_counter(dev->mdev,
3361                                             dev->port[i].cnts.set_id);
3362                 kfree(dev->port[i].cnts.names);
3363                 kfree(dev->port[i].cnts.offsets);
3364         }
3365 }
3366
3367 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3368                                     struct mlx5_ib_counters *cnts)
3369 {
3370         u32 num_counters;
3371
3372         num_counters = ARRAY_SIZE(basic_q_cnts);
3373
3374         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3375                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3376
3377         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3378                 num_counters += ARRAY_SIZE(retrans_q_cnts);
3379         cnts->num_q_counters = num_counters;
3380
3381         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3382                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3383                 num_counters += ARRAY_SIZE(cong_cnts);
3384         }
3385
3386         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3387         if (!cnts->names)
3388                 return -ENOMEM;
3389
3390         cnts->offsets = kcalloc(num_counters,
3391                                 sizeof(cnts->offsets), GFP_KERNEL);
3392         if (!cnts->offsets)
3393                 goto err_names;
3394
3395         return 0;
3396
3397 err_names:
3398         kfree(cnts->names);
3399         return -ENOMEM;
3400 }
3401
3402 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3403                                   const char **names,
3404                                   size_t *offsets)
3405 {
3406         int i;
3407         int j = 0;
3408
3409         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3410                 names[j] = basic_q_cnts[i].name;
3411                 offsets[j] = basic_q_cnts[i].offset;
3412         }
3413
3414         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3415                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3416                         names[j] = out_of_seq_q_cnts[i].name;
3417                         offsets[j] = out_of_seq_q_cnts[i].offset;
3418                 }
3419         }
3420
3421         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3422                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3423                         names[j] = retrans_q_cnts[i].name;
3424                         offsets[j] = retrans_q_cnts[i].offset;
3425                 }
3426         }
3427
3428         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3429                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3430                         names[j] = cong_cnts[i].name;
3431                         offsets[j] = cong_cnts[i].offset;
3432                 }
3433         }
3434 }
3435
3436 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
3437 {
3438         int i;
3439         int ret;
3440
3441         for (i = 0; i < dev->num_ports; i++) {
3442                 struct mlx5_ib_port *port = &dev->port[i];
3443
3444                 ret = mlx5_core_alloc_q_counter(dev->mdev,
3445                                                 &port->cnts.set_id);
3446                 if (ret) {
3447                         mlx5_ib_warn(dev,
3448                                      "couldn't allocate queue counter for port %d, err %d\n",
3449                                      i + 1, ret);
3450                         goto dealloc_counters;
3451                 }
3452
3453                 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
3454                 if (ret)
3455                         goto dealloc_counters;
3456
3457                 mlx5_ib_fill_counters(dev, port->cnts.names,
3458                                       port->cnts.offsets);
3459         }
3460
3461         return 0;
3462
3463 dealloc_counters:
3464         while (--i >= 0)
3465                 mlx5_core_dealloc_q_counter(dev->mdev,
3466                                             dev->port[i].cnts.set_id);
3467
3468         return ret;
3469 }
3470
3471 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3472                                                     u8 port_num)
3473 {
3474         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3475         struct mlx5_ib_port *port = &dev->port[port_num - 1];
3476
3477         /* We support only per port stats */
3478         if (port_num == 0)
3479                 return NULL;
3480
3481         return rdma_alloc_hw_stats_struct(port->cnts.names,
3482                                           port->cnts.num_q_counters +
3483                                           port->cnts.num_cong_counters,
3484                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
3485 }
3486
3487 static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3488                                     struct mlx5_ib_port *port,
3489                                     struct rdma_hw_stats *stats)
3490 {
3491         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3492         void *out;
3493         __be32 val;
3494         int ret, i;
3495
3496         out = kvzalloc(outlen, GFP_KERNEL);
3497         if (!out)
3498                 return -ENOMEM;
3499
3500         ret = mlx5_core_query_q_counter(dev->mdev,
3501                                         port->cnts.set_id, 0,
3502                                         out, outlen);
3503         if (ret)
3504                 goto free;
3505
3506         for (i = 0; i < port->cnts.num_q_counters; i++) {
3507                 val = *(__be32 *)(out + port->cnts.offsets[i]);
3508                 stats->value[i] = (u64)be32_to_cpu(val);
3509         }
3510
3511 free:
3512         kvfree(out);
3513         return ret;
3514 }
3515
3516 static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev,
3517                                        struct mlx5_ib_port *port,
3518                                        struct rdma_hw_stats *stats)
3519 {
3520         int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3521         void *out;
3522         int ret, i;
3523         int offset = port->cnts.num_q_counters;
3524
3525         out = kvzalloc(outlen, GFP_KERNEL);
3526         if (!out)
3527                 return -ENOMEM;
3528
3529         ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3530         if (ret)
3531                 goto free;
3532
3533         for (i = 0; i < port->cnts.num_cong_counters; i++) {
3534                 stats->value[i + offset] =
3535                         be64_to_cpup((__be64 *)(out +
3536                                      port->cnts.offsets[i + offset]));
3537         }
3538
3539 free:
3540         kvfree(out);
3541         return ret;
3542 }
3543
3544 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3545                                 struct rdma_hw_stats *stats,
3546                                 u8 port_num, int index)
3547 {
3548         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3549         struct mlx5_ib_port *port = &dev->port[port_num - 1];
3550         int ret, num_counters;
3551
3552         if (!stats)
3553                 return -EINVAL;
3554
3555         ret = mlx5_ib_query_q_counters(dev, port, stats);
3556         if (ret)
3557                 return ret;
3558         num_counters = port->cnts.num_q_counters;
3559
3560         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3561                 ret = mlx5_ib_query_cong_counters(dev, port, stats);
3562                 if (ret)
3563                         return ret;
3564                 num_counters += port->cnts.num_cong_counters;
3565         }
3566
3567         return num_counters;
3568 }
3569
3570 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3571 {
3572         return mlx5_rdma_netdev_free(netdev);
3573 }
3574
3575 static struct net_device*
3576 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3577                           u8 port_num,
3578                           enum rdma_netdev_t type,
3579                           const char *name,
3580                           unsigned char name_assign_type,
3581                           void (*setup)(struct net_device *))
3582 {
3583         struct net_device *netdev;
3584         struct rdma_netdev *rn;
3585
3586         if (type != RDMA_NETDEV_IPOIB)
3587                 return ERR_PTR(-EOPNOTSUPP);
3588
3589         netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3590                                         name, setup);
3591         if (likely(!IS_ERR_OR_NULL(netdev))) {
3592                 rn = netdev_priv(netdev);
3593                 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3594         }
3595         return netdev;
3596 }
3597
3598 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3599 {
3600         struct mlx5_ib_dev *dev;
3601         enum rdma_link_layer ll;
3602         int port_type_cap;
3603         const char *name;
3604         int err;
3605         int i;
3606
3607         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3608         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3609
3610         printk_once(KERN_INFO "%s", mlx5_version);
3611
3612         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3613         if (!dev)
3614                 return NULL;
3615
3616         dev->mdev = mdev;
3617
3618         dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3619                             GFP_KERNEL);
3620         if (!dev->port)
3621                 goto err_dealloc;
3622
3623         rwlock_init(&dev->roce.netdev_lock);
3624         err = get_port_caps(dev);
3625         if (err)
3626                 goto err_free_port;
3627
3628         if (mlx5_use_mad_ifc(dev))
3629                 get_ext_port_caps(dev);
3630
3631         if (!mlx5_lag_is_active(mdev))
3632                 name = "mlx5_%d";
3633         else
3634                 name = "mlx5_bond_%d";
3635
3636         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
3637         dev->ib_dev.owner               = THIS_MODULE;
3638         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
3639         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
3640         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
3641         dev->ib_dev.phys_port_cnt     = dev->num_ports;
3642         dev->ib_dev.num_comp_vectors    =
3643                 dev->mdev->priv.eq_table.num_comp_vectors;
3644         dev->ib_dev.dev.parent          = &mdev->pdev->dev;
3645
3646         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
3647         dev->ib_dev.uverbs_cmd_mask     =
3648                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
3649                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
3650                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
3651                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
3652                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
3653                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
3654                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
3655                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
3656                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
3657                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
3658                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3659                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
3660                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
3661                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
3662                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
3663                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
3664                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
3665                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
3666                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
3667                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
3668                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
3669                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
3670                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
3671                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
3672                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
3673                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3674         dev->ib_dev.uverbs_ex_cmd_mask =
3675                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
3676                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
3677                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
3678                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
3679
3680         dev->ib_dev.query_device        = mlx5_ib_query_device;
3681         dev->ib_dev.query_port          = mlx5_ib_query_port;
3682         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
3683         if (ll == IB_LINK_LAYER_ETHERNET)
3684                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
3685         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
3686         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
3687         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
3688         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
3689         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
3690         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
3691         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
3692         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
3693         dev->ib_dev.mmap                = mlx5_ib_mmap;
3694         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
3695         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
3696         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
3697         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
3698         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
3699         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
3700         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
3701         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
3702         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
3703         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
3704         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
3705         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
3706         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
3707         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
3708         dev->ib_dev.post_send           = mlx5_ib_post_send;
3709         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
3710         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
3711         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
3712         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
3713         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
3714         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
3715         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
3716         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
3717         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
3718         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
3719         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
3720         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
3721         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
3722         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
3723         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
3724         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
3725         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
3726         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
3727         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
3728         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
3729                 dev->ib_dev.alloc_rdma_netdev   = mlx5_ib_alloc_rdma_netdev;
3730
3731         if (mlx5_core_is_pf(mdev)) {
3732                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
3733                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
3734                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
3735                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
3736         }
3737
3738         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3739
3740         mlx5_ib_internal_fill_odp_caps(dev);
3741
3742         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3743
3744         if (MLX5_CAP_GEN(mdev, imaicl)) {
3745                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
3746                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
3747                 dev->ib_dev.uverbs_cmd_mask |=
3748                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
3749                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3750         }
3751
3752         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3753                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
3754                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
3755         }
3756
3757         if (MLX5_CAP_GEN(mdev, xrc)) {
3758                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3759                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3760                 dev->ib_dev.uverbs_cmd_mask |=
3761                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3762                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3763         }
3764
3765         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3766             IB_LINK_LAYER_ETHERNET) {
3767                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3768                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3769                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
3770                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
3771                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
3772                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3773                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3774                 dev->ib_dev.uverbs_ex_cmd_mask |=
3775                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3776                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3777                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3778                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3779                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3780                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3781                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3782         }
3783         err = init_node_data(dev);
3784         if (err)
3785                 goto err_free_port;
3786
3787         mutex_init(&dev->flow_db.lock);
3788         mutex_init(&dev->cap_mask_mutex);
3789         INIT_LIST_HEAD(&dev->qp_list);
3790         spin_lock_init(&dev->reset_flow_resource_lock);
3791
3792         if (ll == IB_LINK_LAYER_ETHERNET) {
3793                 err = mlx5_enable_eth(dev);
3794                 if (err)
3795                         goto err_free_port;
3796         }
3797
3798         err = create_dev_resources(&dev->devr);
3799         if (err)
3800                 goto err_disable_eth;
3801
3802         err = mlx5_ib_odp_init_one(dev);
3803         if (err)
3804                 goto err_rsrc;
3805
3806         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3807                 err = mlx5_ib_alloc_counters(dev);
3808                 if (err)
3809                         goto err_odp;
3810         }
3811
3812         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
3813         if (!dev->mdev->priv.uar)
3814                 goto err_cnt;
3815
3816         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
3817         if (err)
3818                 goto err_uar_page;
3819
3820         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
3821         if (err)
3822                 goto err_bfreg;
3823
3824         err = ib_register_device(&dev->ib_dev, NULL);
3825         if (err)
3826                 goto err_fp_bfreg;
3827
3828         err = create_umr_res(dev);
3829         if (err)
3830                 goto err_dev;
3831
3832         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3833                 err = device_create_file(&dev->ib_dev.dev,
3834                                          mlx5_class_attributes[i]);
3835                 if (err)
3836                         goto err_umrc;
3837         }
3838
3839         if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
3840             MLX5_CAP_GEN(mdev, disable_local_lb))
3841                 mutex_init(&dev->lb_mutex);
3842
3843         dev->ib_active = true;
3844
3845         return dev;
3846
3847 err_umrc:
3848         destroy_umrc_res(dev);
3849
3850 err_dev:
3851         ib_unregister_device(&dev->ib_dev);
3852
3853 err_fp_bfreg:
3854         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3855
3856 err_bfreg:
3857         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3858
3859 err_uar_page:
3860         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
3861
3862 err_cnt:
3863         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3864                 mlx5_ib_dealloc_counters(dev);
3865
3866 err_odp:
3867         mlx5_ib_odp_remove_one(dev);
3868
3869 err_rsrc:
3870         destroy_dev_resources(&dev->devr);
3871
3872 err_disable_eth:
3873         if (ll == IB_LINK_LAYER_ETHERNET) {
3874                 mlx5_disable_eth(dev);
3875                 mlx5_remove_netdev_notifier(dev);
3876         }
3877
3878 err_free_port:
3879         kfree(dev->port);
3880
3881 err_dealloc:
3882         ib_dealloc_device((struct ib_device *)dev);
3883
3884         return NULL;
3885 }
3886
3887 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3888 {
3889         struct mlx5_ib_dev *dev = context;
3890         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3891
3892         mlx5_remove_netdev_notifier(dev);
3893         ib_unregister_device(&dev->ib_dev);
3894         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3895         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3896         mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
3897         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3898                 mlx5_ib_dealloc_counters(dev);
3899         destroy_umrc_res(dev);
3900         mlx5_ib_odp_remove_one(dev);
3901         destroy_dev_resources(&dev->devr);
3902         if (ll == IB_LINK_LAYER_ETHERNET)
3903                 mlx5_disable_eth(dev);
3904         kfree(dev->port);
3905         ib_dealloc_device(&dev->ib_dev);
3906 }
3907
3908 static struct mlx5_interface mlx5_ib_interface = {
3909         .add            = mlx5_ib_add,
3910         .remove         = mlx5_ib_remove,
3911         .event          = mlx5_ib_event,
3912 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3913         .pfault         = mlx5_ib_pfault,
3914 #endif
3915         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
3916 };
3917
3918 static int __init mlx5_ib_init(void)
3919 {
3920         int err;
3921
3922         mlx5_ib_odp_init();
3923
3924         err = mlx5_register_interface(&mlx5_ib_interface);
3925
3926         return err;
3927 }
3928
3929 static void __exit mlx5_ib_cleanup(void)
3930 {
3931         mlx5_unregister_interface(&mlx5_ib_interface);
3932 }
3933
3934 module_init(mlx5_ib_init);
3935 module_exit(mlx5_ib_cleanup);