1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
4 * Copyright (c) 2020, Intel Corporation. All rights reserved.
7 #include <linux/debugfs.h>
8 #include <linux/highmem.h>
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/errno.h>
12 #include <linux/pci.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/slab.h>
15 #include <linux/bitmap.h>
16 #include <linux/sched.h>
17 #include <linux/sched/mm.h>
18 #include <linux/sched/task.h>
19 #include <linux/delay.h>
20 #include <rdma/ib_user_verbs.h>
21 #include <rdma/ib_addr.h>
22 #include <rdma/ib_cache.h>
23 #include <linux/mlx5/port.h>
24 #include <linux/mlx5/vport.h>
25 #include <linux/mlx5/fs.h>
26 #include <linux/mlx5/eswitch.h>
27 #include <linux/list.h>
28 #include <rdma/ib_smi.h>
29 #include <rdma/ib_umem.h>
32 #include <linux/etherdevice.h>
45 #include <rdma/uverbs_std_types.h>
46 #include <rdma/uverbs_ioctl.h>
47 #include <rdma/mlx5_user_ioctl_verbs.h>
48 #include <rdma/mlx5_user_ioctl_cmds.h>
49 #include <rdma/ib_umem_odp.h>
51 #define UVERBS_MODULE_NAME mlx5_ib
52 #include <rdma/uverbs_named_ioctl.h>
54 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
55 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver");
56 MODULE_LICENSE("Dual BSD/GPL");
58 struct mlx5_ib_event_work {
59 struct work_struct work;
61 struct mlx5_ib_dev *dev;
62 struct mlx5_ib_multiport_info *mpi;
70 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
73 static struct workqueue_struct *mlx5_ib_event_wq;
74 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
75 static LIST_HEAD(mlx5_ib_dev_list);
77 * This mutex should be held when accessing either of the above lists
79 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
81 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
83 struct mlx5_ib_dev *dev;
85 mutex_lock(&mlx5_ib_multiport_mutex);
87 mutex_unlock(&mlx5_ib_multiport_mutex);
91 static enum rdma_link_layer
92 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
94 switch (port_type_cap) {
95 case MLX5_CAP_PORT_TYPE_IB:
96 return IB_LINK_LAYER_INFINIBAND;
97 case MLX5_CAP_PORT_TYPE_ETH:
98 return IB_LINK_LAYER_ETHERNET;
100 return IB_LINK_LAYER_UNSPECIFIED;
104 static enum rdma_link_layer
105 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num)
107 struct mlx5_ib_dev *dev = to_mdev(device);
108 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
110 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
113 static int get_port_state(struct ib_device *ibdev,
115 enum ib_port_state *state)
117 struct ib_port_attr attr;
120 memset(&attr, 0, sizeof(attr));
121 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
127 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
128 struct net_device *ndev,
129 struct net_device *upper,
132 struct net_device *rep_ndev;
133 struct mlx5_ib_port *port;
136 for (i = 0; i < dev->num_ports; i++) {
137 port = &dev->port[i];
141 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) {
146 if (upper && port->rep->vport == MLX5_VPORT_UPLINK)
149 read_lock(&port->roce.netdev_lock);
150 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw,
152 if (rep_ndev == ndev) {
153 read_unlock(&port->roce.netdev_lock);
157 read_unlock(&port->roce.netdev_lock);
163 static int mlx5_netdev_event(struct notifier_block *this,
164 unsigned long event, void *ptr)
166 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
167 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
168 u32 port_num = roce->native_port_num;
169 struct mlx5_core_dev *mdev;
170 struct mlx5_ib_dev *ibdev;
173 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
178 case NETDEV_REGISTER:
179 /* Should already be registered during the load */
182 write_lock(&roce->netdev_lock);
183 if (ndev->dev.parent == mdev->device)
185 write_unlock(&roce->netdev_lock);
188 case NETDEV_UNREGISTER:
189 /* In case of reps, ib device goes away before the netdevs */
190 write_lock(&roce->netdev_lock);
191 if (roce->netdev == ndev)
193 write_unlock(&roce->netdev_lock);
199 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
200 struct net_device *upper = NULL;
203 upper = netdev_master_upper_dev_get(lag_ndev);
208 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num);
211 if ((upper == ndev ||
212 ((!upper || ibdev->is_rep) && ndev == roce->netdev)) &&
214 struct ib_event ibev = { };
215 enum ib_port_state port_state;
217 if (get_port_state(&ibdev->ib_dev, port_num,
221 if (roce->last_port_state == port_state)
224 roce->last_port_state = port_state;
225 ibev.device = &ibdev->ib_dev;
226 if (port_state == IB_PORT_DOWN)
227 ibev.event = IB_EVENT_PORT_ERR;
228 else if (port_state == IB_PORT_ACTIVE)
229 ibev.event = IB_EVENT_PORT_ACTIVE;
233 ibev.element.port_num = port_num;
234 ib_dispatch_event(&ibev);
243 mlx5_ib_put_native_port_mdev(ibdev, port_num);
247 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
250 struct mlx5_ib_dev *ibdev = to_mdev(device);
251 struct net_device *ndev;
252 struct mlx5_core_dev *mdev;
254 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
258 ndev = mlx5_lag_get_roce_netdev(mdev);
262 /* Ensure ndev does not disappear before we invoke dev_hold()
264 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
265 ndev = ibdev->port[port_num - 1].roce.netdev;
268 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
271 mlx5_ib_put_native_port_mdev(ibdev, port_num);
275 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
277 u32 *native_port_num)
279 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
281 struct mlx5_core_dev *mdev = NULL;
282 struct mlx5_ib_multiport_info *mpi;
283 struct mlx5_ib_port *port;
285 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
286 ll != IB_LINK_LAYER_ETHERNET) {
288 *native_port_num = ib_port_num;
293 *native_port_num = 1;
295 port = &ibdev->port[ib_port_num - 1];
296 spin_lock(&port->mp.mpi_lock);
297 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
298 if (mpi && !mpi->unaffiliate) {
300 /* If it's the master no need to refcount, it'll exist
301 * as long as the ib_dev exists.
306 spin_unlock(&port->mp.mpi_lock);
311 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num)
313 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
315 struct mlx5_ib_multiport_info *mpi;
316 struct mlx5_ib_port *port;
318 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
321 port = &ibdev->port[port_num - 1];
323 spin_lock(&port->mp.mpi_lock);
324 mpi = ibdev->port[port_num - 1].mp.mpi;
329 if (mpi->unaffiliate)
330 complete(&mpi->unref_comp);
332 spin_unlock(&port->mp.mpi_lock);
335 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper,
336 u16 *active_speed, u8 *active_width)
338 switch (eth_proto_oper) {
339 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
340 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
341 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
342 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
343 *active_width = IB_WIDTH_1X;
344 *active_speed = IB_SPEED_SDR;
346 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
347 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
348 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
349 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
350 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
351 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
352 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
353 *active_width = IB_WIDTH_1X;
354 *active_speed = IB_SPEED_QDR;
356 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
357 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
358 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
359 *active_width = IB_WIDTH_1X;
360 *active_speed = IB_SPEED_EDR;
362 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
363 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
364 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
365 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
366 *active_width = IB_WIDTH_4X;
367 *active_speed = IB_SPEED_QDR;
369 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
370 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
371 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
372 *active_width = IB_WIDTH_1X;
373 *active_speed = IB_SPEED_HDR;
375 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
376 *active_width = IB_WIDTH_4X;
377 *active_speed = IB_SPEED_FDR;
379 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
380 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
381 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
382 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
383 *active_width = IB_WIDTH_4X;
384 *active_speed = IB_SPEED_EDR;
393 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
396 switch (eth_proto_oper) {
397 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
398 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
399 *active_width = IB_WIDTH_1X;
400 *active_speed = IB_SPEED_SDR;
402 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
403 *active_width = IB_WIDTH_1X;
404 *active_speed = IB_SPEED_DDR;
406 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
407 *active_width = IB_WIDTH_1X;
408 *active_speed = IB_SPEED_QDR;
410 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
411 *active_width = IB_WIDTH_4X;
412 *active_speed = IB_SPEED_QDR;
414 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
415 *active_width = IB_WIDTH_1X;
416 *active_speed = IB_SPEED_EDR;
418 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
419 *active_width = IB_WIDTH_2X;
420 *active_speed = IB_SPEED_EDR;
422 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
423 *active_width = IB_WIDTH_1X;
424 *active_speed = IB_SPEED_HDR;
426 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
427 *active_width = IB_WIDTH_4X;
428 *active_speed = IB_SPEED_EDR;
430 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
431 *active_width = IB_WIDTH_2X;
432 *active_speed = IB_SPEED_HDR;
434 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR):
435 *active_width = IB_WIDTH_1X;
436 *active_speed = IB_SPEED_NDR;
438 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
439 *active_width = IB_WIDTH_4X;
440 *active_speed = IB_SPEED_HDR;
442 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2):
443 *active_width = IB_WIDTH_2X;
444 *active_speed = IB_SPEED_NDR;
446 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4):
447 *active_width = IB_WIDTH_4X;
448 *active_speed = IB_SPEED_NDR;
457 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed,
458 u8 *active_width, bool ext)
461 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
463 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
467 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num,
468 struct ib_port_attr *props)
470 struct mlx5_ib_dev *dev = to_mdev(device);
471 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
472 struct mlx5_core_dev *mdev;
473 struct net_device *ndev, *upper;
474 enum ib_mtu ndev_ib_mtu;
475 bool put_mdev = true;
481 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
483 /* This means the port isn't affiliated yet. Get the
484 * info for the master port instead.
492 /* Possible bad flows are checked before filling out props so in case
493 * of an error it will still be zeroed out.
494 * Use native port in case of reps
497 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
500 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
504 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
505 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
507 props->active_width = IB_WIDTH_4X;
508 props->active_speed = IB_SPEED_QDR;
510 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
511 &props->active_width, ext);
513 if (!dev->is_rep && dev->mdev->roce.roce_en) {
516 props->port_cap_flags |= IB_PORT_CM_SUP;
517 props->ip_gids = true;
518 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
519 roce_address_table_size);
520 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
521 props->qkey_viol_cntr = qkey_viol_cntr;
523 props->max_mtu = IB_MTU_4096;
524 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
525 props->pkey_tbl_len = 1;
526 props->state = IB_PORT_DOWN;
527 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
529 /* If this is a stub query for an unaffiliated port stop here */
533 ndev = mlx5_ib_get_netdev(device, port_num);
537 if (dev->lag_active) {
539 upper = netdev_master_upper_dev_get_rcu(ndev);
548 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
549 props->state = IB_PORT_ACTIVE;
550 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
553 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
557 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
560 mlx5_ib_put_native_port_mdev(dev, port_num);
564 static int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num,
565 unsigned int index, const union ib_gid *gid,
566 const struct ib_gid_attr *attr)
568 enum ib_gid_type gid_type;
569 u16 vlan_id = 0xffff;
575 gid_type = attr->gid_type;
577 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
583 case IB_GID_TYPE_ROCE:
584 roce_version = MLX5_ROCE_VERSION_1;
586 case IB_GID_TYPE_ROCE_UDP_ENCAP:
587 roce_version = MLX5_ROCE_VERSION_2;
588 if (gid && ipv6_addr_v4mapped((void *)gid))
589 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
591 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
595 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
598 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
599 roce_l3_type, gid->raw, mac,
600 vlan_id < VLAN_CFI_MASK, vlan_id,
604 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
605 __always_unused void **context)
607 return set_roce_addr(to_mdev(attr->device), attr->port_num,
608 attr->index, &attr->gid, attr);
611 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
612 __always_unused void **context)
614 return set_roce_addr(to_mdev(attr->device), attr->port_num,
615 attr->index, NULL, attr);
618 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
619 const struct ib_gid_attr *attr)
621 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
624 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
627 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
629 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
630 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
635 MLX5_VPORT_ACCESS_METHOD_MAD,
636 MLX5_VPORT_ACCESS_METHOD_HCA,
637 MLX5_VPORT_ACCESS_METHOD_NIC,
640 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
642 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
643 return MLX5_VPORT_ACCESS_METHOD_MAD;
645 if (mlx5_ib_port_link_layer(ibdev, 1) ==
646 IB_LINK_LAYER_ETHERNET)
647 return MLX5_VPORT_ACCESS_METHOD_NIC;
649 return MLX5_VPORT_ACCESS_METHOD_HCA;
652 static void get_atomic_caps(struct mlx5_ib_dev *dev,
654 struct ib_device_attr *props)
657 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
658 u8 atomic_req_8B_endianness_mode =
659 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
661 /* Check if HW supports 8 bytes standard atomic operations and capable
662 * of host endianness respond
664 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
665 if (((atomic_operations & tmp) == tmp) &&
666 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
667 (atomic_req_8B_endianness_mode)) {
668 props->atomic_cap = IB_ATOMIC_HCA;
670 props->atomic_cap = IB_ATOMIC_NONE;
674 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
675 struct ib_device_attr *props)
677 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
679 get_atomic_caps(dev, atomic_size_qp, props);
682 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
683 __be64 *sys_image_guid)
685 struct mlx5_ib_dev *dev = to_mdev(ibdev);
686 struct mlx5_core_dev *mdev = dev->mdev;
690 switch (mlx5_get_vport_access_method(ibdev)) {
691 case MLX5_VPORT_ACCESS_METHOD_MAD:
692 return mlx5_query_mad_ifc_system_image_guid(ibdev,
695 case MLX5_VPORT_ACCESS_METHOD_HCA:
696 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
699 case MLX5_VPORT_ACCESS_METHOD_NIC:
700 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
708 *sys_image_guid = cpu_to_be64(tmp);
714 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
717 struct mlx5_ib_dev *dev = to_mdev(ibdev);
718 struct mlx5_core_dev *mdev = dev->mdev;
720 switch (mlx5_get_vport_access_method(ibdev)) {
721 case MLX5_VPORT_ACCESS_METHOD_MAD:
722 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
724 case MLX5_VPORT_ACCESS_METHOD_HCA:
725 case MLX5_VPORT_ACCESS_METHOD_NIC:
726 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
735 static int mlx5_query_vendor_id(struct ib_device *ibdev,
738 struct mlx5_ib_dev *dev = to_mdev(ibdev);
740 switch (mlx5_get_vport_access_method(ibdev)) {
741 case MLX5_VPORT_ACCESS_METHOD_MAD:
742 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
744 case MLX5_VPORT_ACCESS_METHOD_HCA:
745 case MLX5_VPORT_ACCESS_METHOD_NIC:
746 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
753 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
759 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
760 case MLX5_VPORT_ACCESS_METHOD_MAD:
761 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
763 case MLX5_VPORT_ACCESS_METHOD_HCA:
764 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
767 case MLX5_VPORT_ACCESS_METHOD_NIC:
768 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
776 *node_guid = cpu_to_be64(tmp);
781 struct mlx5_reg_node_desc {
782 u8 desc[IB_DEVICE_NODE_DESC_MAX];
785 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
787 struct mlx5_reg_node_desc in;
789 if (mlx5_use_mad_ifc(dev))
790 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
792 memset(&in, 0, sizeof(in));
794 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
795 sizeof(struct mlx5_reg_node_desc),
796 MLX5_REG_NODE_DESC, 0, 0);
799 static int mlx5_ib_query_device(struct ib_device *ibdev,
800 struct ib_device_attr *props,
801 struct ib_udata *uhw)
803 size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
804 struct mlx5_ib_dev *dev = to_mdev(ibdev);
805 struct mlx5_core_dev *mdev = dev->mdev;
810 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
811 bool raw_support = !mlx5_core_mp_enabled(mdev);
812 struct mlx5_ib_query_device_resp resp = {};
816 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
817 if (uhw_outlen && uhw_outlen < resp_len)
820 resp.response_length = resp_len;
822 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
825 memset(props, 0, sizeof(*props));
826 err = mlx5_query_system_image_guid(ibdev,
827 &props->sys_image_guid);
831 props->max_pkeys = dev->pkey_table_len;
833 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
837 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
838 (fw_rev_min(dev->mdev) << 16) |
839 fw_rev_sub(dev->mdev);
840 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
841 IB_DEVICE_PORT_ACTIVE_EVENT |
842 IB_DEVICE_SYS_IMAGE_GUID |
843 IB_DEVICE_RC_RNR_NAK_GEN;
845 if (MLX5_CAP_GEN(mdev, pkv))
846 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
847 if (MLX5_CAP_GEN(mdev, qkv))
848 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
849 if (MLX5_CAP_GEN(mdev, apm))
850 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
851 if (MLX5_CAP_GEN(mdev, xrc))
852 props->device_cap_flags |= IB_DEVICE_XRC;
853 if (MLX5_CAP_GEN(mdev, imaicl)) {
854 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
855 IB_DEVICE_MEM_WINDOW_TYPE_2B;
856 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
857 /* We support 'Gappy' memory registration too */
858 props->kernel_cap_flags |= IBK_SG_GAPS_REG;
860 /* IB_WR_REG_MR always requires changing the entity size with UMR */
861 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
862 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
863 if (MLX5_CAP_GEN(mdev, sho)) {
864 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER;
865 /* At this stage no support for signature handover */
866 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
867 IB_PROT_T10DIF_TYPE_2 |
868 IB_PROT_T10DIF_TYPE_3;
869 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
870 IB_GUARD_T10DIF_CSUM;
872 if (MLX5_CAP_GEN(mdev, block_lb_mc))
873 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK;
875 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
876 if (MLX5_CAP_ETH(mdev, csum_cap)) {
877 /* Legacy bit to support old userspace libraries */
878 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
879 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
882 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
883 props->raw_packet_caps |=
884 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
886 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
887 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
889 resp.tso_caps.max_tso = 1 << max_tso;
890 resp.tso_caps.supported_qpts |=
891 1 << IB_QPT_RAW_PACKET;
892 resp.response_length += sizeof(resp.tso_caps);
896 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
897 resp.rss_caps.rx_hash_function =
898 MLX5_RX_HASH_FUNC_TOEPLITZ;
899 resp.rss_caps.rx_hash_fields_mask =
900 MLX5_RX_HASH_SRC_IPV4 |
901 MLX5_RX_HASH_DST_IPV4 |
902 MLX5_RX_HASH_SRC_IPV6 |
903 MLX5_RX_HASH_DST_IPV6 |
904 MLX5_RX_HASH_SRC_PORT_TCP |
905 MLX5_RX_HASH_DST_PORT_TCP |
906 MLX5_RX_HASH_SRC_PORT_UDP |
907 MLX5_RX_HASH_DST_PORT_UDP |
909 resp.response_length += sizeof(resp.rss_caps);
912 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
913 resp.response_length += sizeof(resp.tso_caps);
914 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
915 resp.response_length += sizeof(resp.rss_caps);
918 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
919 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
920 props->kernel_cap_flags |= IBK_UD_TSO;
923 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
924 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
926 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
928 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
929 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
930 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
932 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
933 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
935 /* Legacy bit to support old userspace libraries */
936 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
937 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
940 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
942 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
945 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
946 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
948 if (MLX5_CAP_GEN(mdev, end_pad))
949 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
951 props->vendor_part_id = mdev->pdev->device;
952 props->hw_ver = mdev->pdev->revision;
954 props->max_mr_size = ~0ull;
955 props->page_size_cap = ~(min_page_size - 1);
956 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
957 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
958 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
959 sizeof(struct mlx5_wqe_data_seg);
960 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
961 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
962 sizeof(struct mlx5_wqe_raddr_seg)) /
963 sizeof(struct mlx5_wqe_data_seg);
964 props->max_send_sge = max_sq_sg;
965 props->max_recv_sge = max_rq_sg;
966 props->max_sge_rd = MLX5_MAX_SGE_RD;
967 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
968 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
969 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
970 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
971 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
972 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
973 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
974 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
975 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
976 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
977 props->max_srq_sge = max_rq_sg - 1;
978 props->max_fast_reg_page_list_len =
979 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
980 props->max_pi_fast_reg_page_list_len =
981 props->max_fast_reg_page_list_len / 2;
983 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
984 get_atomic_caps_qp(dev, props);
985 props->masked_atomic_cap = IB_ATOMIC_NONE;
986 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
987 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
988 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
989 props->max_mcast_grp;
990 props->max_ah = INT_MAX;
991 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
992 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
994 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
995 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
996 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING;
997 props->odp_caps = dev->odp_caps;
999 /* ODP for kernel QPs is not implemented for receive
1002 props->odp_caps.per_transport_caps.rc_odp_caps &=
1003 ~(IB_ODP_SUPPORT_READ |
1004 IB_ODP_SUPPORT_SRQ_RECV);
1005 props->odp_caps.per_transport_caps.uc_odp_caps &=
1006 ~(IB_ODP_SUPPORT_READ |
1007 IB_ODP_SUPPORT_SRQ_RECV);
1008 props->odp_caps.per_transport_caps.ud_odp_caps &=
1009 ~(IB_ODP_SUPPORT_READ |
1010 IB_ODP_SUPPORT_SRQ_RECV);
1011 props->odp_caps.per_transport_caps.xrc_odp_caps &=
1012 ~(IB_ODP_SUPPORT_READ |
1013 IB_ODP_SUPPORT_SRQ_RECV);
1017 if (mlx5_core_is_vf(mdev))
1018 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION;
1020 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1021 IB_LINK_LAYER_ETHERNET && raw_support) {
1022 props->rss_caps.max_rwq_indirection_tables =
1023 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1024 props->rss_caps.max_rwq_indirection_table_size =
1025 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1026 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1027 props->max_wq_type_rq =
1028 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1031 if (MLX5_CAP_GEN(mdev, tag_matching)) {
1032 props->tm_caps.max_num_tags =
1033 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1034 props->tm_caps.max_ops =
1035 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1036 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1039 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1040 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1041 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1042 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1045 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1046 props->cq_caps.max_cq_moderation_count =
1048 props->cq_caps.max_cq_moderation_period =
1052 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
1053 resp.response_length += sizeof(resp.cqe_comp_caps);
1055 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1056 resp.cqe_comp_caps.max_num =
1057 MLX5_CAP_GEN(dev->mdev,
1058 cqe_compression_max_num);
1060 resp.cqe_comp_caps.supported_format =
1061 MLX5_IB_CQE_RES_FORMAT_HASH |
1062 MLX5_IB_CQE_RES_FORMAT_CSUM;
1064 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1065 resp.cqe_comp_caps.supported_format |=
1066 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1070 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
1072 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1073 MLX5_CAP_GEN(mdev, qos)) {
1074 resp.packet_pacing_caps.qp_rate_limit_max =
1075 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1076 resp.packet_pacing_caps.qp_rate_limit_min =
1077 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1078 resp.packet_pacing_caps.supported_qpts |=
1079 1 << IB_QPT_RAW_PACKET;
1080 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1081 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1082 resp.packet_pacing_caps.cap_flags |=
1083 MLX5_IB_PP_SUPPORT_BURST;
1085 resp.response_length += sizeof(resp.packet_pacing_caps);
1088 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1090 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1091 resp.mlx5_ib_support_multi_pkt_send_wqes =
1094 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1095 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1096 MLX5_IB_SUPPORT_EMPW;
1098 resp.response_length +=
1099 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1102 if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
1103 resp.response_length += sizeof(resp.flags);
1105 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1107 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1109 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1110 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1111 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1113 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1115 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1118 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
1119 resp.response_length += sizeof(resp.sw_parsing_caps);
1120 if (MLX5_CAP_ETH(mdev, swp)) {
1121 resp.sw_parsing_caps.sw_parsing_offloads |=
1124 if (MLX5_CAP_ETH(mdev, swp_csum))
1125 resp.sw_parsing_caps.sw_parsing_offloads |=
1126 MLX5_IB_SW_PARSING_CSUM;
1128 if (MLX5_CAP_ETH(mdev, swp_lso))
1129 resp.sw_parsing_caps.sw_parsing_offloads |=
1130 MLX5_IB_SW_PARSING_LSO;
1132 if (resp.sw_parsing_caps.sw_parsing_offloads)
1133 resp.sw_parsing_caps.supported_qpts =
1134 BIT(IB_QPT_RAW_PACKET);
1138 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
1140 resp.response_length += sizeof(resp.striding_rq_caps);
1141 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1142 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1143 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1144 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1145 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1146 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1147 resp.striding_rq_caps
1148 .min_single_wqe_log_num_of_strides =
1149 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1151 resp.striding_rq_caps
1152 .min_single_wqe_log_num_of_strides =
1153 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1154 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1155 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1156 resp.striding_rq_caps.supported_qpts =
1157 BIT(IB_QPT_RAW_PACKET);
1161 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
1162 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1163 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1164 resp.tunnel_offloads_caps |=
1165 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1166 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1167 resp.tunnel_offloads_caps |=
1168 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1169 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1170 resp.tunnel_offloads_caps |=
1171 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1172 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1173 resp.tunnel_offloads_caps |=
1174 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1175 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1176 resp.tunnel_offloads_caps |=
1177 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1180 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) {
1181 resp.response_length += sizeof(resp.dci_streams_caps);
1183 resp.dci_streams_caps.max_log_num_concurent =
1184 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels);
1186 resp.dci_streams_caps.max_log_num_errored =
1187 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams);
1191 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1200 static void translate_active_width(struct ib_device *ibdev, u16 active_width,
1203 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1205 if (active_width & MLX5_PTYS_WIDTH_1X)
1206 *ib_width = IB_WIDTH_1X;
1207 else if (active_width & MLX5_PTYS_WIDTH_2X)
1208 *ib_width = IB_WIDTH_2X;
1209 else if (active_width & MLX5_PTYS_WIDTH_4X)
1210 *ib_width = IB_WIDTH_4X;
1211 else if (active_width & MLX5_PTYS_WIDTH_8X)
1212 *ib_width = IB_WIDTH_8X;
1213 else if (active_width & MLX5_PTYS_WIDTH_12X)
1214 *ib_width = IB_WIDTH_12X;
1216 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1218 *ib_width = IB_WIDTH_4X;
1224 static int mlx5_mtu_to_ib_mtu(int mtu)
1229 case 1024: return 3;
1230 case 2048: return 4;
1231 case 4096: return 5;
1233 pr_warn("invalid mtu\n");
1238 enum ib_max_vl_num {
1240 __IB_MAX_VL_0_1 = 2,
1241 __IB_MAX_VL_0_3 = 3,
1242 __IB_MAX_VL_0_7 = 4,
1243 __IB_MAX_VL_0_14 = 5,
1246 enum mlx5_vl_hw_cap {
1255 MLX5_VL_HW_0_14 = 15
1258 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1261 switch (vl_hw_cap) {
1263 *max_vl_num = __IB_MAX_VL_0;
1265 case MLX5_VL_HW_0_1:
1266 *max_vl_num = __IB_MAX_VL_0_1;
1268 case MLX5_VL_HW_0_3:
1269 *max_vl_num = __IB_MAX_VL_0_3;
1271 case MLX5_VL_HW_0_7:
1272 *max_vl_num = __IB_MAX_VL_0_7;
1274 case MLX5_VL_HW_0_14:
1275 *max_vl_num = __IB_MAX_VL_0_14;
1285 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port,
1286 struct ib_port_attr *props)
1288 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1289 struct mlx5_core_dev *mdev = dev->mdev;
1290 struct mlx5_hca_vport_context *rep;
1294 u16 ib_link_width_oper;
1297 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1303 /* props being zeroed by the caller, avoid zeroing it here */
1305 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1309 props->lid = rep->lid;
1310 props->lmc = rep->lmc;
1311 props->sm_lid = rep->sm_lid;
1312 props->sm_sl = rep->sm_sl;
1313 props->state = rep->vport_state;
1314 props->phys_state = rep->port_physical_state;
1315 props->port_cap_flags = rep->cap_mask1;
1316 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1317 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1318 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1319 props->bad_pkey_cntr = rep->pkey_violation_counter;
1320 props->qkey_viol_cntr = rep->qkey_violation_counter;
1321 props->subnet_timeout = rep->subnet_timeout;
1322 props->init_type_reply = rep->init_type_reply;
1324 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1325 props->port_cap_flags2 = rep->cap_mask2;
1327 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper,
1328 &props->active_speed, port);
1332 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1334 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1336 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1338 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1340 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1342 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1346 err = translate_max_vl_num(ibdev, vl_hw_cap,
1347 &props->max_vl_num);
1353 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1354 struct ib_port_attr *props)
1359 switch (mlx5_get_vport_access_method(ibdev)) {
1360 case MLX5_VPORT_ACCESS_METHOD_MAD:
1361 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1364 case MLX5_VPORT_ACCESS_METHOD_HCA:
1365 ret = mlx5_query_hca_port(ibdev, port, props);
1368 case MLX5_VPORT_ACCESS_METHOD_NIC:
1369 ret = mlx5_query_port_roce(ibdev, port, props);
1376 if (!ret && props) {
1377 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1378 struct mlx5_core_dev *mdev;
1379 bool put_mdev = true;
1381 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1383 /* If the port isn't affiliated yet query the master.
1384 * The master and slave will have the same values.
1390 count = mlx5_core_reserved_gids_count(mdev);
1392 mlx5_ib_put_native_port_mdev(dev, port);
1393 props->gid_tbl_len -= count;
1398 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port,
1399 struct ib_port_attr *props)
1401 return mlx5_query_port_roce(ibdev, port, props);
1404 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1407 /* Default special Pkey for representor device port as per the
1408 * IB specification 1.3 section 10.9.1.2.
1414 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index,
1417 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1418 struct mlx5_core_dev *mdev = dev->mdev;
1420 switch (mlx5_get_vport_access_method(ibdev)) {
1421 case MLX5_VPORT_ACCESS_METHOD_MAD:
1422 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1424 case MLX5_VPORT_ACCESS_METHOD_HCA:
1425 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1433 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port,
1434 u16 index, u16 *pkey)
1436 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1437 struct mlx5_core_dev *mdev;
1438 bool put_mdev = true;
1442 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1444 /* The port isn't affiliated yet, get the PKey from the master
1445 * port. For RoCE the PKey tables will be the same.
1452 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1455 mlx5_ib_put_native_port_mdev(dev, port);
1460 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1463 switch (mlx5_get_vport_access_method(ibdev)) {
1464 case MLX5_VPORT_ACCESS_METHOD_MAD:
1465 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1467 case MLX5_VPORT_ACCESS_METHOD_HCA:
1468 case MLX5_VPORT_ACCESS_METHOD_NIC:
1469 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1475 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1476 struct ib_device_modify *props)
1478 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1479 struct mlx5_reg_node_desc in;
1480 struct mlx5_reg_node_desc out;
1483 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1486 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1490 * If possible, pass node desc to FW, so it can generate
1491 * a 144 trap. If cmd fails, just ignore.
1493 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1494 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1495 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1499 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1504 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask,
1507 struct mlx5_hca_vport_context ctx = {};
1508 struct mlx5_core_dev *mdev;
1512 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1516 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1520 if (~ctx.cap_mask1_perm & mask) {
1521 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1522 mask, ctx.cap_mask1_perm);
1527 ctx.cap_mask1 = value;
1528 ctx.cap_mask1_perm = mask;
1529 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1533 mlx5_ib_put_native_port_mdev(dev, port_num);
1538 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask,
1539 struct ib_port_modify *props)
1541 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1542 struct ib_port_attr attr;
1547 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1548 IB_LINK_LAYER_INFINIBAND);
1550 /* CM layer calls ib_modify_port() regardless of the link layer. For
1551 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1556 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1557 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1558 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1559 return set_port_caps_atomic(dev, port, change_mask, value);
1562 mutex_lock(&dev->cap_mask_mutex);
1564 err = ib_query_port(ibdev, port, &attr);
1568 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1569 ~props->clr_port_cap_mask;
1571 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1574 mutex_unlock(&dev->cap_mask_mutex);
1578 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1580 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1581 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1584 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1586 /* Large page with non 4k uar support might limit the dynamic size */
1587 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1588 return MLX5_MIN_DYN_BFREGS;
1590 return MLX5_MAX_DYN_BFREGS;
1593 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1594 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1595 struct mlx5_bfreg_info *bfregi)
1597 int uars_per_sys_page;
1598 int bfregs_per_sys_page;
1599 int ref_bfregs = req->total_num_bfregs;
1601 if (req->total_num_bfregs == 0)
1604 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1605 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1607 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1610 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1611 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1612 /* This holds the required static allocation asked by the user */
1613 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1614 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1617 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1618 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1619 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1620 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1622 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1623 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1624 lib_uar_4k ? "yes" : "no", ref_bfregs,
1625 req->total_num_bfregs, bfregi->total_num_bfregs,
1626 bfregi->num_sys_pages);
1631 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1633 struct mlx5_bfreg_info *bfregi;
1637 bfregi = &context->bfregi;
1638 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1639 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i],
1644 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1647 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1648 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1653 for (--i; i >= 0; i--)
1654 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i],
1656 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1661 static void deallocate_uars(struct mlx5_ib_dev *dev,
1662 struct mlx5_ib_ucontext *context)
1664 struct mlx5_bfreg_info *bfregi;
1667 bfregi = &context->bfregi;
1668 for (i = 0; i < bfregi->num_sys_pages; i++)
1669 if (i < bfregi->num_static_sys_pages ||
1670 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1671 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i],
1675 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1679 mutex_lock(&dev->lb.mutex);
1685 if (dev->lb.user_td == 2 ||
1687 if (!dev->lb.enabled) {
1688 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1689 dev->lb.enabled = true;
1693 mutex_unlock(&dev->lb.mutex);
1698 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1700 mutex_lock(&dev->lb.mutex);
1706 if (dev->lb.user_td == 1 &&
1708 if (dev->lb.enabled) {
1709 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1710 dev->lb.enabled = false;
1714 mutex_unlock(&dev->lb.mutex);
1717 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1722 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1725 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1729 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1730 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1731 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1734 return mlx5_ib_enable_lb(dev, true, false);
1737 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1740 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1743 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1745 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1746 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1747 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1750 mlx5_ib_disable_lb(dev, true, false);
1753 static int set_ucontext_resp(struct ib_ucontext *uctx,
1754 struct mlx5_ib_alloc_ucontext_resp *resp)
1756 struct ib_device *ibdev = uctx->device;
1757 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1758 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1759 struct mlx5_bfreg_info *bfregi = &context->bfregi;
1762 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1763 err = mlx5_cmd_dump_fill_mkey(dev->mdev,
1764 &resp->dump_fill_mkey);
1768 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1771 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1772 if (dev->wc_support)
1773 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev,
1775 resp->cache_line_size = cache_line_size();
1776 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1777 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1778 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1779 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1780 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1781 resp->cqe_version = context->cqe_version;
1782 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1783 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1784 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1785 MLX5_CAP_GEN(dev->mdev,
1786 num_of_uars_per_page) : 1;
1787 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 :
1788 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs;
1789 resp->num_ports = dev->num_ports;
1790 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1791 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1793 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1794 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline);
1795 resp->eth_min_inline++;
1798 if (dev->mdev->clock_info)
1799 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1802 * We don't want to expose information from the PCI bar that is located
1803 * after 4096 bytes, so if the arch only supports larger pages, let's
1804 * pretend we don't support reading the HCA's core clock. This is also
1805 * forced by mmap function.
1807 if (PAGE_SIZE <= 4096) {
1809 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1810 resp->hca_core_clock_offset =
1811 offsetof(struct mlx5_init_seg,
1812 internal_timer_h) % PAGE_SIZE;
1815 if (MLX5_CAP_GEN(dev->mdev, ece_support))
1816 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
1818 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) &&
1819 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) &&
1820 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format)))
1822 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS;
1824 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
1826 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
1827 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
1832 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1833 struct ib_udata *udata)
1835 struct ib_device *ibdev = uctx->device;
1836 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1837 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1838 struct mlx5_ib_alloc_ucontext_resp resp = {};
1839 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1840 struct mlx5_bfreg_info *bfregi;
1843 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1848 if (!dev->ib_active)
1851 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1853 else if (udata->inlen >= min_req_v2)
1858 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1862 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1865 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1868 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1869 MLX5_NON_FP_BFREGS_PER_UAR);
1870 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1873 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1874 err = mlx5_ib_devx_create(dev, true);
1877 context->devx_uid = err;
1880 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1881 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
1882 bfregi = &context->bfregi;
1885 bfregi->lib_uar_dyn = lib_uar_dyn;
1889 /* updates req->total_num_bfregs */
1890 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1894 mutex_init(&bfregi->lock);
1895 bfregi->lib_uar_4k = lib_uar_4k;
1896 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1898 if (!bfregi->count) {
1903 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1904 sizeof(*bfregi->sys_pages),
1906 if (!bfregi->sys_pages) {
1911 err = allocate_uars(dev, context);
1916 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1921 INIT_LIST_HEAD(&context->db_page_list);
1922 mutex_init(&context->db_page_mutex);
1924 context->cqe_version = min_t(__u8,
1925 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1926 req.max_cqe_version);
1928 err = set_ucontext_resp(uctx, &resp);
1932 resp.response_length = min(udata->outlen, sizeof(resp));
1933 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1938 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1939 context->lib_caps = req.lib_caps;
1940 print_lib_caps(dev, context->lib_caps);
1942 if (mlx5_ib_lag_should_assign_affinity(dev)) {
1943 u32 port = mlx5_core_native_port_num(dev->mdev) - 1;
1945 atomic_set(&context->tx_port_affinity,
1947 1, &dev->port[port].roce.tx_port_affinity));
1953 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1956 deallocate_uars(dev, context);
1959 kfree(bfregi->sys_pages);
1962 kfree(bfregi->count);
1965 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1966 mlx5_ib_devx_destroy(dev, context->devx_uid);
1972 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext,
1973 struct uverbs_attr_bundle *attrs)
1975 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {};
1978 ret = set_ucontext_resp(ibcontext, &uctx_resp);
1982 uctx_resp.response_length =
1984 uverbs_attr_get_len(attrs,
1985 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX),
1988 ret = uverbs_copy_to_struct_or_zero(attrs,
1989 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
1995 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1997 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1998 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1999 struct mlx5_bfreg_info *bfregi;
2001 bfregi = &context->bfregi;
2002 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2004 deallocate_uars(dev, context);
2005 kfree(bfregi->sys_pages);
2006 kfree(bfregi->count);
2008 if (context->devx_uid)
2009 mlx5_ib_devx_destroy(dev, context->devx_uid);
2012 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2015 int fw_uars_per_page;
2017 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2019 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2022 static u64 uar_index2paddress(struct mlx5_ib_dev *dev,
2025 unsigned int fw_uars_per_page;
2027 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2028 MLX5_UARS_IN_PAGE : 1;
2030 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2033 static int get_command(unsigned long offset)
2035 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2038 static int get_arg(unsigned long offset)
2040 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2043 static int get_index(unsigned long offset)
2045 return get_arg(offset);
2048 /* Index resides in an extra byte to enable larger values than 255 */
2049 static int get_extended_index(unsigned long offset)
2051 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2055 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2059 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2062 case MLX5_IB_MMAP_WC_PAGE:
2064 case MLX5_IB_MMAP_REGULAR_PAGE:
2065 return "best effort WC";
2066 case MLX5_IB_MMAP_NC_PAGE:
2068 case MLX5_IB_MMAP_DEVICE_MEM:
2069 return "Device Memory";
2075 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2076 struct vm_area_struct *vma,
2077 struct mlx5_ib_ucontext *context)
2079 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2080 !(vma->vm_flags & VM_SHARED))
2083 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2086 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2088 vma->vm_flags &= ~VM_MAYWRITE;
2090 if (!dev->mdev->clock_info)
2093 return vm_insert_page(vma, vma->vm_start,
2094 virt_to_page(dev->mdev->clock_info));
2097 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2099 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2100 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
2101 struct mlx5_var_table *var_table = &dev->var_table;
2102 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext);
2104 switch (mentry->mmap_flag) {
2105 case MLX5_IB_MMAP_TYPE_MEMIC:
2106 case MLX5_IB_MMAP_TYPE_MEMIC_OP:
2107 mlx5_ib_dm_mmap_free(dev, mentry);
2109 case MLX5_IB_MMAP_TYPE_VAR:
2110 mutex_lock(&var_table->bitmap_lock);
2111 clear_bit(mentry->page_idx, var_table->bitmap);
2112 mutex_unlock(&var_table->bitmap_lock);
2115 case MLX5_IB_MMAP_TYPE_UAR_WC:
2116 case MLX5_IB_MMAP_TYPE_UAR_NC:
2117 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx,
2126 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2127 struct vm_area_struct *vma,
2128 struct mlx5_ib_ucontext *context)
2130 struct mlx5_bfreg_info *bfregi = &context->bfregi;
2135 u32 bfreg_dyn_idx = 0;
2137 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2138 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2139 bfregi->num_static_sys_pages;
2141 if (bfregi->lib_uar_dyn)
2144 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2148 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2150 idx = get_index(vma->vm_pgoff);
2152 if (idx >= max_valid_idx) {
2153 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2154 idx, max_valid_idx);
2159 case MLX5_IB_MMAP_WC_PAGE:
2160 case MLX5_IB_MMAP_ALLOC_WC:
2161 case MLX5_IB_MMAP_REGULAR_PAGE:
2162 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2163 prot = pgprot_writecombine(vma->vm_page_prot);
2165 case MLX5_IB_MMAP_NC_PAGE:
2166 prot = pgprot_noncached(vma->vm_page_prot);
2175 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2176 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2177 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2178 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2179 bfreg_dyn_idx, bfregi->total_num_bfregs);
2183 mutex_lock(&bfregi->lock);
2184 /* Fail if uar already allocated, first bfreg index of each
2185 * page holds its count.
2187 if (bfregi->count[bfreg_dyn_idx]) {
2188 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2189 mutex_unlock(&bfregi->lock);
2193 bfregi->count[bfreg_dyn_idx]++;
2194 mutex_unlock(&bfregi->lock);
2196 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index,
2199 mlx5_ib_warn(dev, "UAR alloc failed\n");
2203 uar_index = bfregi->sys_pages[idx];
2206 pfn = uar_index2pfn(dev, uar_index);
2207 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2209 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2213 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2214 err, mmap_cmd2str(cmd));
2219 bfregi->sys_pages[idx] = uar_index;
2226 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid);
2229 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2234 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2239 command = get_command(vma->vm_pgoff);
2240 idx = get_extended_index(vma->vm_pgoff);
2242 return (command << 16 | idx);
2245 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2246 struct vm_area_struct *vma,
2247 struct ib_ucontext *ucontext)
2249 struct mlx5_user_mmap_entry *mentry;
2250 struct rdma_user_mmap_entry *entry;
2251 unsigned long pgoff;
2256 pgoff = mlx5_vma_to_pgoff(vma);
2257 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2261 mentry = to_mmmap(entry);
2262 pfn = (mentry->address >> PAGE_SHIFT);
2263 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
2264 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
2265 prot = pgprot_noncached(vma->vm_page_prot);
2267 prot = pgprot_writecombine(vma->vm_page_prot);
2268 ret = rdma_user_mmap_io(ucontext, vma, pfn,
2269 entry->npages * PAGE_SIZE,
2272 rdma_user_mmap_entry_put(&mentry->rdma_entry);
2276 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2278 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2279 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
2281 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2282 (index & 0xFF)) << PAGE_SHIFT;
2285 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2287 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2288 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2289 unsigned long command;
2292 command = get_command(vma->vm_pgoff);
2294 case MLX5_IB_MMAP_WC_PAGE:
2295 case MLX5_IB_MMAP_ALLOC_WC:
2296 if (!dev->wc_support)
2299 case MLX5_IB_MMAP_NC_PAGE:
2300 case MLX5_IB_MMAP_REGULAR_PAGE:
2301 return uar_mmap(dev, command, vma, context);
2303 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2306 case MLX5_IB_MMAP_CORE_CLOCK:
2307 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2310 if (vma->vm_flags & VM_WRITE)
2312 vma->vm_flags &= ~VM_MAYWRITE;
2314 /* Don't expose to user-space information it shouldn't have */
2315 if (PAGE_SIZE > 4096)
2318 pfn = (dev->mdev->iseg_base +
2319 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2321 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2323 pgprot_noncached(vma->vm_page_prot),
2325 case MLX5_IB_MMAP_CLOCK_INFO:
2326 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2329 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
2335 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2337 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2338 struct ib_device *ibdev = ibpd->device;
2339 struct mlx5_ib_alloc_pd_resp resp;
2341 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2342 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2344 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2345 udata, struct mlx5_ib_ucontext, ibucontext);
2347 uid = context ? context->devx_uid : 0;
2348 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2349 MLX5_SET(alloc_pd_in, in, uid, uid);
2350 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out);
2354 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2358 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2359 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2367 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2369 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2370 struct mlx5_ib_pd *mpd = to_mpd(pd);
2372 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2375 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2377 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2378 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
2383 to_mpd(ibqp->pd)->uid : 0;
2385 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) {
2386 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2390 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2392 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2393 ibqp->qp_num, gid->raw);
2398 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2400 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2405 to_mpd(ibqp->pd)->uid : 0;
2406 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2408 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2409 ibqp->qp_num, gid->raw);
2414 static int init_node_data(struct mlx5_ib_dev *dev)
2418 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2422 dev->mdev->rev_id = dev->mdev->pdev->revision;
2424 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2427 static ssize_t fw_pages_show(struct device *device,
2428 struct device_attribute *attr, char *buf)
2430 struct mlx5_ib_dev *dev =
2431 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2433 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages);
2435 static DEVICE_ATTR_RO(fw_pages);
2437 static ssize_t reg_pages_show(struct device *device,
2438 struct device_attribute *attr, char *buf)
2440 struct mlx5_ib_dev *dev =
2441 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2443 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2445 static DEVICE_ATTR_RO(reg_pages);
2447 static ssize_t hca_type_show(struct device *device,
2448 struct device_attribute *attr, char *buf)
2450 struct mlx5_ib_dev *dev =
2451 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2453 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device);
2455 static DEVICE_ATTR_RO(hca_type);
2457 static ssize_t hw_rev_show(struct device *device,
2458 struct device_attribute *attr, char *buf)
2460 struct mlx5_ib_dev *dev =
2461 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2463 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id);
2465 static DEVICE_ATTR_RO(hw_rev);
2467 static ssize_t board_id_show(struct device *device,
2468 struct device_attribute *attr, char *buf)
2470 struct mlx5_ib_dev *dev =
2471 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2473 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2474 dev->mdev->board_id);
2476 static DEVICE_ATTR_RO(board_id);
2478 static struct attribute *mlx5_class_attributes[] = {
2479 &dev_attr_hw_rev.attr,
2480 &dev_attr_hca_type.attr,
2481 &dev_attr_board_id.attr,
2482 &dev_attr_fw_pages.attr,
2483 &dev_attr_reg_pages.attr,
2487 static const struct attribute_group mlx5_attr_group = {
2488 .attrs = mlx5_class_attributes,
2491 static void pkey_change_handler(struct work_struct *work)
2493 struct mlx5_ib_port_resources *ports =
2494 container_of(work, struct mlx5_ib_port_resources,
2499 * We got this event before device was fully configured
2500 * and MAD registration code wasn't called/finished yet.
2504 mlx5_ib_gsi_pkey_change(ports->gsi);
2507 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2509 struct mlx5_ib_qp *mqp;
2510 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2511 struct mlx5_core_cq *mcq;
2512 struct list_head cq_armed_list;
2513 unsigned long flags_qp;
2514 unsigned long flags_cq;
2515 unsigned long flags;
2517 INIT_LIST_HEAD(&cq_armed_list);
2519 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2520 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2521 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2522 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2523 if (mqp->sq.tail != mqp->sq.head) {
2524 send_mcq = to_mcq(mqp->ibqp.send_cq);
2525 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2526 if (send_mcq->mcq.comp &&
2527 mqp->ibqp.send_cq->comp_handler) {
2528 if (!send_mcq->mcq.reset_notify_added) {
2529 send_mcq->mcq.reset_notify_added = 1;
2530 list_add_tail(&send_mcq->mcq.reset_notify,
2534 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2536 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2537 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2538 /* no handling is needed for SRQ */
2539 if (!mqp->ibqp.srq) {
2540 if (mqp->rq.tail != mqp->rq.head) {
2541 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2542 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2543 if (recv_mcq->mcq.comp &&
2544 mqp->ibqp.recv_cq->comp_handler) {
2545 if (!recv_mcq->mcq.reset_notify_added) {
2546 recv_mcq->mcq.reset_notify_added = 1;
2547 list_add_tail(&recv_mcq->mcq.reset_notify,
2551 spin_unlock_irqrestore(&recv_mcq->lock,
2555 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2557 /*At that point all inflight post send were put to be executed as of we
2558 * lock/unlock above locks Now need to arm all involved CQs.
2560 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2561 mcq->comp(mcq, NULL);
2563 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2566 static void delay_drop_handler(struct work_struct *work)
2569 struct mlx5_ib_delay_drop *delay_drop =
2570 container_of(work, struct mlx5_ib_delay_drop,
2573 atomic_inc(&delay_drop->events_cnt);
2575 mutex_lock(&delay_drop->lock);
2576 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout);
2578 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2579 delay_drop->timeout);
2580 delay_drop->activate = false;
2582 mutex_unlock(&delay_drop->lock);
2585 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2586 struct ib_event *ibev)
2588 u32 port = (eqe->data.port.port >> 4) & 0xf;
2590 switch (eqe->sub_type) {
2591 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
2592 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2593 IB_LINK_LAYER_ETHERNET)
2594 schedule_work(&ibdev->delay_drop.delay_drop_work);
2596 default: /* do nothing */
2601 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2602 struct ib_event *ibev)
2604 u32 port = (eqe->data.port.port >> 4) & 0xf;
2606 ibev->element.port_num = port;
2608 switch (eqe->sub_type) {
2609 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
2610 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
2611 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
2612 /* In RoCE, port up/down events are handled in
2613 * mlx5_netdev_event().
2615 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2616 IB_LINK_LAYER_ETHERNET)
2619 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
2620 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2623 case MLX5_PORT_CHANGE_SUBTYPE_LID:
2624 ibev->event = IB_EVENT_LID_CHANGE;
2627 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
2628 ibev->event = IB_EVENT_PKEY_CHANGE;
2629 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2632 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
2633 ibev->event = IB_EVENT_GID_CHANGE;
2636 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
2637 ibev->event = IB_EVENT_CLIENT_REREGISTER;
2646 static void mlx5_ib_handle_event(struct work_struct *_work)
2648 struct mlx5_ib_event_work *work =
2649 container_of(_work, struct mlx5_ib_event_work, work);
2650 struct mlx5_ib_dev *ibdev;
2651 struct ib_event ibev;
2654 if (work->is_slave) {
2655 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
2662 switch (work->event) {
2663 case MLX5_DEV_EVENT_SYS_ERROR:
2664 ibev.event = IB_EVENT_DEVICE_FATAL;
2665 mlx5_ib_handle_internal_error(ibdev);
2666 ibev.element.port_num = (u8)(unsigned long)work->param;
2669 case MLX5_EVENT_TYPE_PORT_CHANGE:
2670 if (handle_port_change(ibdev, work->param, &ibev))
2673 case MLX5_EVENT_TYPE_GENERAL_EVENT:
2674 handle_general_event(ibdev, work->param, &ibev);
2680 ibev.device = &ibdev->ib_dev;
2682 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
2683 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
2687 if (ibdev->ib_active)
2688 ib_dispatch_event(&ibev);
2691 ibdev->ib_active = false;
2696 static int mlx5_ib_event(struct notifier_block *nb,
2697 unsigned long event, void *param)
2699 struct mlx5_ib_event_work *work;
2701 work = kmalloc(sizeof(*work), GFP_ATOMIC);
2705 INIT_WORK(&work->work, mlx5_ib_handle_event);
2706 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
2707 work->is_slave = false;
2708 work->param = param;
2709 work->event = event;
2711 queue_work(mlx5_ib_event_wq, &work->work);
2716 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
2717 unsigned long event, void *param)
2719 struct mlx5_ib_event_work *work;
2721 work = kmalloc(sizeof(*work), GFP_ATOMIC);
2725 INIT_WORK(&work->work, mlx5_ib_handle_event);
2726 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
2727 work->is_slave = true;
2728 work->param = param;
2729 work->event = event;
2730 queue_work(mlx5_ib_event_wq, &work->work);
2735 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2737 struct mlx5_hca_vport_context vport_ctx;
2741 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB)
2744 for (port = 1; port <= dev->num_ports; port++) {
2745 if (!MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2746 dev->port_caps[port - 1].has_smi = true;
2749 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0,
2752 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2756 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi;
2762 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2766 rdma_for_each_port (&dev->ib_dev, port)
2767 mlx5_query_ext_port_caps(dev, port);
2770 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2772 switch (umr_fence_cap) {
2773 case MLX5_CAP_UMR_FENCE_NONE:
2774 return MLX5_FENCE_MODE_NONE;
2775 case MLX5_CAP_UMR_FENCE_SMALL:
2776 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2778 return MLX5_FENCE_MODE_STRONG_ORDERING;
2782 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev)
2784 struct mlx5_ib_resources *devr = &dev->devr;
2785 struct ib_srq_init_attr attr;
2786 struct ib_device *ibdev;
2787 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2791 ibdev = &dev->ib_dev;
2793 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2796 devr->p0 = ib_alloc_pd(ibdev, 0);
2797 if (IS_ERR(devr->p0))
2798 return PTR_ERR(devr->p0);
2800 devr->c0 = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr);
2801 if (IS_ERR(devr->c0)) {
2802 ret = PTR_ERR(devr->c0);
2806 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
2810 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
2814 memset(&attr, 0, sizeof(attr));
2815 attr.attr.max_sge = 1;
2816 attr.attr.max_wr = 1;
2817 attr.srq_type = IB_SRQT_XRC;
2818 attr.ext.cq = devr->c0;
2820 devr->s0 = ib_create_srq(devr->p0, &attr);
2821 if (IS_ERR(devr->s0)) {
2822 ret = PTR_ERR(devr->s0);
2826 memset(&attr, 0, sizeof(attr));
2827 attr.attr.max_sge = 1;
2828 attr.attr.max_wr = 1;
2829 attr.srq_type = IB_SRQT_BASIC;
2831 devr->s1 = ib_create_srq(devr->p0, &attr);
2832 if (IS_ERR(devr->s1)) {
2833 ret = PTR_ERR(devr->s1);
2837 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
2838 INIT_WORK(&devr->ports[port].pkey_change_work,
2839 pkey_change_handler);
2844 ib_destroy_srq(devr->s0);
2846 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2848 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2850 ib_destroy_cq(devr->c0);
2852 ib_dealloc_pd(devr->p0);
2856 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev)
2858 struct mlx5_ib_resources *devr = &dev->devr;
2862 * Make sure no change P_Key work items are still executing.
2864 * At this stage, the mlx5_ib_event should be unregistered
2865 * and it ensures that no new works are added.
2867 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
2868 cancel_work_sync(&devr->ports[port].pkey_change_work);
2870 ib_destroy_srq(devr->s1);
2871 ib_destroy_srq(devr->s0);
2872 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2873 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2874 ib_destroy_cq(devr->c0);
2875 ib_dealloc_pd(devr->p0);
2878 static u32 get_core_cap_flags(struct ib_device *ibdev,
2879 struct mlx5_hca_vport_context *rep)
2881 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2882 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2883 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2884 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2885 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
2888 if (rep->grh_required)
2889 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
2891 if (ll == IB_LINK_LAYER_INFINIBAND)
2892 return ret | RDMA_CORE_PORT_IBA_IB;
2895 ret |= RDMA_CORE_PORT_RAW_PACKET;
2897 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2900 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2903 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2904 ret |= RDMA_CORE_PORT_IBA_ROCE;
2906 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2907 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2912 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num,
2913 struct ib_port_immutable *immutable)
2915 struct ib_port_attr attr;
2916 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2917 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
2918 struct mlx5_hca_vport_context rep = {0};
2921 err = ib_query_port(ibdev, port_num, &attr);
2925 if (ll == IB_LINK_LAYER_INFINIBAND) {
2926 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
2932 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2933 immutable->gid_tbl_len = attr.gid_tbl_len;
2934 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
2935 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2940 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num,
2941 struct ib_port_immutable *immutable)
2943 struct ib_port_attr attr;
2946 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
2948 err = ib_query_port(ibdev, port_num, &attr);
2952 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2953 immutable->gid_tbl_len = attr.gid_tbl_len;
2954 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
2959 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
2961 struct mlx5_ib_dev *dev =
2962 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2963 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
2964 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
2965 fw_rev_sub(dev->mdev));
2968 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
2970 struct mlx5_core_dev *mdev = dev->mdev;
2971 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
2972 MLX5_FLOW_NAMESPACE_LAG);
2973 struct mlx5_flow_table *ft;
2976 if (!ns || !mlx5_lag_is_active(mdev))
2979 err = mlx5_cmd_create_vport_lag(mdev);
2983 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
2986 goto err_destroy_vport_lag;
2989 dev->flow_db->lag_demux_ft = ft;
2990 dev->lag_ports = mlx5_lag_get_num_ports(mdev);
2991 dev->lag_active = true;
2994 err_destroy_vport_lag:
2995 mlx5_cmd_destroy_vport_lag(mdev);
2999 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3001 struct mlx5_core_dev *mdev = dev->mdev;
3003 if (dev->lag_active) {
3004 dev->lag_active = false;
3006 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
3007 dev->flow_db->lag_demux_ft = NULL;
3009 mlx5_cmd_destroy_vport_lag(mdev);
3013 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num)
3017 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
3018 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
3020 dev->port[port_num].roce.nb.notifier_call = NULL;
3027 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num)
3029 if (dev->port[port_num].roce.nb.notifier_call) {
3030 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
3031 dev->port[port_num].roce.nb.notifier_call = NULL;
3035 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3039 if (!dev->is_rep && dev->profile != &raw_eth_profile) {
3040 err = mlx5_nic_vport_enable_roce(dev->mdev);
3045 err = mlx5_eth_lag_init(dev);
3047 goto err_disable_roce;
3052 if (!dev->is_rep && dev->profile != &raw_eth_profile)
3053 mlx5_nic_vport_disable_roce(dev->mdev);
3058 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3060 mlx5_eth_lag_cleanup(dev);
3061 if (!dev->is_rep && dev->profile != &raw_eth_profile)
3062 mlx5_nic_vport_disable_roce(dev->mdev);
3065 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num,
3066 enum rdma_netdev_t type,
3067 struct rdma_netdev_alloc_params *params)
3069 if (type != RDMA_NETDEV_IPOIB)
3072 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
3075 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3076 size_t count, loff_t *pos)
3078 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3082 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3083 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3086 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3087 size_t count, loff_t *pos)
3089 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3093 if (kstrtouint_from_user(buf, count, 0, &var))
3096 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3099 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3102 delay_drop->timeout = timeout;
3107 static const struct file_operations fops_delay_drop_timeout = {
3108 .owner = THIS_MODULE,
3109 .open = simple_open,
3110 .write = delay_drop_timeout_write,
3111 .read = delay_drop_timeout_read,
3114 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
3115 struct mlx5_ib_multiport_info *mpi)
3117 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3118 struct mlx5_ib_port *port = &ibdev->port[port_num];
3123 lockdep_assert_held(&mlx5_ib_multiport_mutex);
3125 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
3127 spin_lock(&port->mp.mpi_lock);
3129 spin_unlock(&port->mp.mpi_lock);
3135 spin_unlock(&port->mp.mpi_lock);
3136 if (mpi->mdev_events.notifier_call)
3137 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
3138 mpi->mdev_events.notifier_call = NULL;
3139 mlx5_remove_netdev_notifier(ibdev, port_num);
3140 spin_lock(&port->mp.mpi_lock);
3142 comps = mpi->mdev_refcnt;
3144 mpi->unaffiliate = true;
3145 init_completion(&mpi->unref_comp);
3146 spin_unlock(&port->mp.mpi_lock);
3148 for (i = 0; i < comps; i++)
3149 wait_for_completion(&mpi->unref_comp);
3151 spin_lock(&port->mp.mpi_lock);
3152 mpi->unaffiliate = false;
3155 port->mp.mpi = NULL;
3157 spin_unlock(&port->mp.mpi_lock);
3159 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
3161 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1);
3162 /* Log an error, still needed to cleanup the pointers and add
3163 * it back to the list.
3166 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
3169 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
3172 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
3173 struct mlx5_ib_multiport_info *mpi)
3175 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3178 lockdep_assert_held(&mlx5_ib_multiport_mutex);
3180 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
3181 if (ibdev->port[port_num].mp.mpi) {
3182 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n",
3184 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3188 ibdev->port[port_num].mp.mpi = mpi;
3190 mpi->mdev_events.notifier_call = NULL;
3191 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3193 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
3197 err = mlx5_add_netdev_notifier(ibdev, port_num);
3199 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
3204 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
3205 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
3207 mlx5_ib_init_cong_debugfs(ibdev, port_num);
3212 mlx5_ib_unbind_slave_port(ibdev, mpi);
3216 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
3218 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3219 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3221 struct mlx5_ib_multiport_info *mpi;
3225 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3228 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
3229 &dev->sys_image_guid);
3233 err = mlx5_nic_vport_enable_roce(dev->mdev);
3237 mutex_lock(&mlx5_ib_multiport_mutex);
3238 for (i = 0; i < dev->num_ports; i++) {
3241 /* build a stub multiport info struct for the native port. */
3242 if (i == port_num) {
3243 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
3245 mutex_unlock(&mlx5_ib_multiport_mutex);
3246 mlx5_nic_vport_disable_roce(dev->mdev);
3250 mpi->is_master = true;
3251 mpi->mdev = dev->mdev;
3252 mpi->sys_image_guid = dev->sys_image_guid;
3253 dev->port[i].mp.mpi = mpi;
3259 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
3261 if (dev->sys_image_guid == mpi->sys_image_guid &&
3262 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
3263 bound = mlx5_ib_bind_slave_port(dev, mpi);
3267 dev_dbg(mpi->mdev->device,
3268 "removing port from unaffiliated list.\n");
3269 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
3270 list_del(&mpi->list);
3275 mlx5_ib_dbg(dev, "no free port found for port %d\n",
3279 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
3280 mutex_unlock(&mlx5_ib_multiport_mutex);
3284 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
3286 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3287 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3291 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3294 mutex_lock(&mlx5_ib_multiport_mutex);
3295 for (i = 0; i < dev->num_ports; i++) {
3296 if (dev->port[i].mp.mpi) {
3297 /* Destroy the native port stub */
3298 if (i == port_num) {
3299 kfree(dev->port[i].mp.mpi);
3300 dev->port[i].mp.mpi = NULL;
3302 mlx5_ib_dbg(dev, "unbinding port_num: %u\n",
3304 list_add_tail(&dev->port[i].mp.mpi->list,
3305 &mlx5_ib_unaffiliated_port_list);
3306 mlx5_ib_unbind_slave_port(dev,
3307 dev->port[i].mp.mpi);
3312 mlx5_ib_dbg(dev, "removing from devlist\n");
3313 list_del(&dev->ib_dev_list);
3314 mutex_unlock(&mlx5_ib_multiport_mutex);
3316 mlx5_nic_vport_disable_roce(dev->mdev);
3319 static int mmap_obj_cleanup(struct ib_uobject *uobject,
3320 enum rdma_remove_reason why,
3321 struct uverbs_attr_bundle *attrs)
3323 struct mlx5_user_mmap_entry *obj = uobject->object;
3325 rdma_user_mmap_entry_remove(&obj->rdma_entry);
3329 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
3330 struct mlx5_user_mmap_entry *entry,
3333 return rdma_user_mmap_entry_insert_range(
3334 &c->ibucontext, &entry->rdma_entry, length,
3335 (MLX5_IB_MMAP_OFFSET_START << 16),
3336 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
3339 static struct mlx5_user_mmap_entry *
3340 alloc_var_entry(struct mlx5_ib_ucontext *c)
3342 struct mlx5_user_mmap_entry *entry;
3343 struct mlx5_var_table *var_table;
3347 var_table = &to_mdev(c->ibucontext.device)->var_table;
3348 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3350 return ERR_PTR(-ENOMEM);
3352 mutex_lock(&var_table->bitmap_lock);
3353 page_idx = find_first_zero_bit(var_table->bitmap,
3354 var_table->num_var_hw_entries);
3355 if (page_idx >= var_table->num_var_hw_entries) {
3357 mutex_unlock(&var_table->bitmap_lock);
3361 set_bit(page_idx, var_table->bitmap);
3362 mutex_unlock(&var_table->bitmap_lock);
3364 entry->address = var_table->hw_start_addr +
3365 (page_idx * var_table->stride_size);
3366 entry->page_idx = page_idx;
3367 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
3369 err = mlx5_rdma_user_mmap_entry_insert(c, entry,
3370 var_table->stride_size);
3377 mutex_lock(&var_table->bitmap_lock);
3378 clear_bit(page_idx, var_table->bitmap);
3379 mutex_unlock(&var_table->bitmap_lock);
3382 return ERR_PTR(err);
3385 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
3386 struct uverbs_attr_bundle *attrs)
3388 struct ib_uobject *uobj = uverbs_attr_get_uobject(
3389 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3390 struct mlx5_ib_ucontext *c;
3391 struct mlx5_user_mmap_entry *entry;
3396 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3400 entry = alloc_var_entry(c);
3402 return PTR_ERR(entry);
3404 mmap_offset = mlx5_entry_to_mmap_offset(entry);
3405 length = entry->rdma_entry.npages * PAGE_SIZE;
3406 uobj->object = entry;
3407 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3409 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3410 &mmap_offset, sizeof(mmap_offset));
3414 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3415 &entry->page_idx, sizeof(entry->page_idx));
3419 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3420 &length, sizeof(length));
3424 DECLARE_UVERBS_NAMED_METHOD(
3425 MLX5_IB_METHOD_VAR_OBJ_ALLOC,
3426 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
3430 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3431 UVERBS_ATTR_TYPE(u32),
3433 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3434 UVERBS_ATTR_TYPE(u32),
3436 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3437 UVERBS_ATTR_TYPE(u64),
3440 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3441 MLX5_IB_METHOD_VAR_OBJ_DESTROY,
3442 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
3444 UVERBS_ACCESS_DESTROY,
3447 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
3448 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3449 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
3450 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
3452 static bool var_is_supported(struct ib_device *device)
3454 struct mlx5_ib_dev *dev = to_mdev(device);
3456 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3457 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
3460 static struct mlx5_user_mmap_entry *
3461 alloc_uar_entry(struct mlx5_ib_ucontext *c,
3462 enum mlx5_ib_uapi_uar_alloc_type alloc_type)
3464 struct mlx5_user_mmap_entry *entry;
3465 struct mlx5_ib_dev *dev;
3469 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3471 return ERR_PTR(-ENOMEM);
3473 dev = to_mdev(c->ibucontext.device);
3474 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid);
3478 entry->page_idx = uar_index;
3479 entry->address = uar_index2paddress(dev, uar_index);
3480 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3481 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC;
3483 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC;
3485 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE);
3492 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid);
3495 return ERR_PTR(err);
3498 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
3499 struct uverbs_attr_bundle *attrs)
3501 struct ib_uobject *uobj = uverbs_attr_get_uobject(
3502 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3503 enum mlx5_ib_uapi_uar_alloc_type alloc_type;
3504 struct mlx5_ib_ucontext *c;
3505 struct mlx5_user_mmap_entry *entry;
3510 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3514 err = uverbs_get_const(&alloc_type, attrs,
3515 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
3519 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
3520 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
3523 if (!to_mdev(c->ibucontext.device)->wc_support &&
3524 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3527 entry = alloc_uar_entry(c, alloc_type);
3529 return PTR_ERR(entry);
3531 mmap_offset = mlx5_entry_to_mmap_offset(entry);
3532 length = entry->rdma_entry.npages * PAGE_SIZE;
3533 uobj->object = entry;
3534 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3536 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3537 &mmap_offset, sizeof(mmap_offset));
3541 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3542 &entry->page_idx, sizeof(entry->page_idx));
3546 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3547 &length, sizeof(length));
3551 DECLARE_UVERBS_NAMED_METHOD(
3552 MLX5_IB_METHOD_UAR_OBJ_ALLOC,
3553 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
3557 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
3558 enum mlx5_ib_uapi_uar_alloc_type,
3560 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3561 UVERBS_ATTR_TYPE(u32),
3563 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3564 UVERBS_ATTR_TYPE(u32),
3566 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3567 UVERBS_ATTR_TYPE(u64),
3570 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3571 MLX5_IB_METHOD_UAR_OBJ_DESTROY,
3572 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
3574 UVERBS_ACCESS_DESTROY,
3577 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
3578 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3579 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
3580 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
3582 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3583 mlx5_ib_query_context,
3584 UVERBS_OBJECT_DEVICE,
3585 UVERBS_METHOD_QUERY_CONTEXT,
3586 UVERBS_ATTR_PTR_OUT(
3587 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
3588 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp,
3592 static const struct uapi_definition mlx5_ib_defs[] = {
3593 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
3594 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
3595 UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
3596 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs),
3597 UAPI_DEF_CHAIN(mlx5_ib_dm_defs),
3599 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context),
3600 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
3601 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
3602 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
3606 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
3608 mlx5_ib_cleanup_multiport_master(dev);
3609 WARN_ON(!xa_empty(&dev->odp_mkeys));
3610 mutex_destroy(&dev->cap_mask_mutex);
3611 WARN_ON(!xa_empty(&dev->sig_mrs));
3612 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
3615 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
3617 struct mlx5_core_dev *mdev = dev->mdev;
3621 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3622 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3623 dev->ib_dev.phys_port_cnt = dev->num_ports;
3624 dev->ib_dev.dev.parent = mdev->device;
3625 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES;
3627 for (i = 0; i < dev->num_ports; i++) {
3628 spin_lock_init(&dev->port[i].mp.mpi_lock);
3629 rwlock_init(&dev->port[i].roce.netdev_lock);
3630 dev->port[i].roce.dev = dev;
3631 dev->port[i].roce.native_port_num = i + 1;
3632 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
3635 err = mlx5_ib_init_multiport_master(dev);
3639 err = set_has_smi_cap(dev);
3643 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len);
3647 if (mlx5_use_mad_ifc(dev))
3648 get_ext_port_caps(dev);
3650 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
3652 mutex_init(&dev->cap_mask_mutex);
3653 INIT_LIST_HEAD(&dev->qp_list);
3654 spin_lock_init(&dev->reset_flow_resource_lock);
3655 xa_init(&dev->odp_mkeys);
3656 xa_init(&dev->sig_mrs);
3657 atomic_set(&dev->mkey_var, 0);
3659 spin_lock_init(&dev->dm.lock);
3664 mlx5_ib_cleanup_multiport_master(dev);
3668 static int mlx5_ib_enable_driver(struct ib_device *dev)
3670 struct mlx5_ib_dev *mdev = to_mdev(dev);
3673 ret = mlx5_ib_test_wc(mdev);
3674 mlx5_ib_dbg(mdev, "Write-Combining %s",
3675 mdev->wc_support ? "supported" : "not supported");
3680 static const struct ib_device_ops mlx5_ib_dev_ops = {
3681 .owner = THIS_MODULE,
3682 .driver_id = RDMA_DRIVER_MLX5,
3683 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
3685 .add_gid = mlx5_ib_add_gid,
3686 .alloc_mr = mlx5_ib_alloc_mr,
3687 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
3688 .alloc_pd = mlx5_ib_alloc_pd,
3689 .alloc_ucontext = mlx5_ib_alloc_ucontext,
3690 .attach_mcast = mlx5_ib_mcg_attach,
3691 .check_mr_status = mlx5_ib_check_mr_status,
3692 .create_ah = mlx5_ib_create_ah,
3693 .create_cq = mlx5_ib_create_cq,
3694 .create_qp = mlx5_ib_create_qp,
3695 .create_srq = mlx5_ib_create_srq,
3696 .create_user_ah = mlx5_ib_create_ah,
3697 .dealloc_pd = mlx5_ib_dealloc_pd,
3698 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
3699 .del_gid = mlx5_ib_del_gid,
3700 .dereg_mr = mlx5_ib_dereg_mr,
3701 .destroy_ah = mlx5_ib_destroy_ah,
3702 .destroy_cq = mlx5_ib_destroy_cq,
3703 .destroy_qp = mlx5_ib_destroy_qp,
3704 .destroy_srq = mlx5_ib_destroy_srq,
3705 .detach_mcast = mlx5_ib_mcg_detach,
3706 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
3707 .drain_rq = mlx5_ib_drain_rq,
3708 .drain_sq = mlx5_ib_drain_sq,
3709 .device_group = &mlx5_attr_group,
3710 .enable_driver = mlx5_ib_enable_driver,
3711 .get_dev_fw_str = get_dev_fw_str,
3712 .get_dma_mr = mlx5_ib_get_dma_mr,
3713 .get_link_layer = mlx5_ib_port_link_layer,
3714 .map_mr_sg = mlx5_ib_map_mr_sg,
3715 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
3716 .mmap = mlx5_ib_mmap,
3717 .mmap_free = mlx5_ib_mmap_free,
3718 .modify_cq = mlx5_ib_modify_cq,
3719 .modify_device = mlx5_ib_modify_device,
3720 .modify_port = mlx5_ib_modify_port,
3721 .modify_qp = mlx5_ib_modify_qp,
3722 .modify_srq = mlx5_ib_modify_srq,
3723 .poll_cq = mlx5_ib_poll_cq,
3724 .post_recv = mlx5_ib_post_recv_nodrain,
3725 .post_send = mlx5_ib_post_send_nodrain,
3726 .post_srq_recv = mlx5_ib_post_srq_recv,
3727 .process_mad = mlx5_ib_process_mad,
3728 .query_ah = mlx5_ib_query_ah,
3729 .query_device = mlx5_ib_query_device,
3730 .query_gid = mlx5_ib_query_gid,
3731 .query_pkey = mlx5_ib_query_pkey,
3732 .query_qp = mlx5_ib_query_qp,
3733 .query_srq = mlx5_ib_query_srq,
3734 .query_ucontext = mlx5_ib_query_ucontext,
3735 .reg_user_mr = mlx5_ib_reg_user_mr,
3736 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf,
3737 .req_notify_cq = mlx5_ib_arm_cq,
3738 .rereg_user_mr = mlx5_ib_rereg_user_mr,
3739 .resize_cq = mlx5_ib_resize_cq,
3741 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
3742 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs),
3743 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
3744 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
3745 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp),
3746 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
3747 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
3750 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
3751 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
3754 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
3755 .get_vf_config = mlx5_ib_get_vf_config,
3756 .get_vf_guid = mlx5_ib_get_vf_guid,
3757 .get_vf_stats = mlx5_ib_get_vf_stats,
3758 .set_vf_guid = mlx5_ib_set_vf_guid,
3759 .set_vf_link_state = mlx5_ib_set_vf_link_state,
3762 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
3763 .alloc_mw = mlx5_ib_alloc_mw,
3764 .dealloc_mw = mlx5_ib_dealloc_mw,
3766 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw),
3769 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
3770 .alloc_xrcd = mlx5_ib_alloc_xrcd,
3771 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
3773 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd),
3776 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
3778 struct mlx5_core_dev *mdev = dev->mdev;
3779 struct mlx5_var_table *var_table = &dev->var_table;
3780 u8 log_doorbell_bar_size;
3781 u8 log_doorbell_stride;
3784 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3785 log_doorbell_bar_size);
3786 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3787 log_doorbell_stride);
3788 var_table->hw_start_addr = dev->mdev->bar_addr +
3789 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
3790 doorbell_bar_offset);
3791 bar_size = (1ULL << log_doorbell_bar_size) * 4096;
3792 var_table->stride_size = 1ULL << log_doorbell_stride;
3793 var_table->num_var_hw_entries = div_u64(bar_size,
3794 var_table->stride_size);
3795 mutex_init(&var_table->bitmap_lock);
3796 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
3798 return (var_table->bitmap) ? 0 : -ENOMEM;
3801 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
3803 bitmap_free(dev->var_table.bitmap);
3806 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
3808 struct mlx5_core_dev *mdev = dev->mdev;
3811 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
3812 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
3813 ib_set_device_ops(&dev->ib_dev,
3814 &mlx5_ib_dev_ipoib_enhanced_ops);
3816 if (mlx5_core_is_pf(mdev))
3817 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
3819 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3821 if (MLX5_CAP_GEN(mdev, imaicl))
3822 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
3824 if (MLX5_CAP_GEN(mdev, xrc))
3825 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
3827 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
3828 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3829 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
3830 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
3832 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
3834 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
3835 dev->ib_dev.driver_def = mlx5_ib_defs;
3837 err = init_node_data(dev);
3841 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
3842 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
3843 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
3844 mutex_init(&dev->lb.mutex);
3846 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3847 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
3848 err = mlx5_ib_init_var_table(dev);
3853 dev->ib_dev.use_cq_dim = true;
3858 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
3859 .get_port_immutable = mlx5_port_immutable,
3860 .query_port = mlx5_ib_query_port,
3863 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
3865 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
3869 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
3870 .get_port_immutable = mlx5_port_rep_immutable,
3871 .query_port = mlx5_ib_rep_query_port,
3872 .query_pkey = mlx5_ib_rep_query_pkey,
3875 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
3877 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
3881 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
3882 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
3883 .create_wq = mlx5_ib_create_wq,
3884 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
3885 .destroy_wq = mlx5_ib_destroy_wq,
3886 .get_netdev = mlx5_ib_get_netdev,
3887 .modify_wq = mlx5_ib_modify_wq,
3889 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table,
3893 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev)
3895 struct mlx5_core_dev *mdev = dev->mdev;
3896 enum rdma_link_layer ll;
3901 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3902 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3904 if (ll == IB_LINK_LAYER_ETHERNET) {
3905 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
3907 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3909 /* Register only for native ports */
3910 err = mlx5_add_netdev_notifier(dev, port_num);
3914 err = mlx5_enable_eth(dev);
3921 mlx5_remove_netdev_notifier(dev, port_num);
3925 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev)
3927 struct mlx5_core_dev *mdev = dev->mdev;
3928 enum rdma_link_layer ll;
3932 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3933 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3935 if (ll == IB_LINK_LAYER_ETHERNET) {
3936 mlx5_disable_eth(dev);
3938 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3939 mlx5_remove_netdev_notifier(dev, port_num);
3943 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
3945 mlx5_ib_init_cong_debugfs(dev,
3946 mlx5_core_native_port_num(dev->mdev) - 1);
3950 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
3952 mlx5_ib_cleanup_cong_debugfs(dev,
3953 mlx5_core_native_port_num(dev->mdev) - 1);
3956 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
3958 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
3959 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
3962 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
3964 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
3967 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
3971 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
3975 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
3977 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3982 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
3984 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3985 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3988 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
3992 if (!mlx5_lag_is_active(dev->mdev))
3995 name = "mlx5_bond_%d";
3996 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
3999 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
4003 err = mlx5_mkey_cache_cleanup(dev);
4005 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4007 mlx5r_umr_resource_cleanup(dev);
4010 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4012 ib_unregister_device(&dev->ib_dev);
4015 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
4019 ret = mlx5r_umr_resource_init(dev);
4023 ret = mlx5_mkey_cache_init(dev);
4025 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4026 mlx5r_umr_resource_cleanup(dev);
4031 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4033 struct dentry *root;
4035 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4038 mutex_init(&dev->delay_drop.lock);
4039 dev->delay_drop.dev = dev;
4040 dev->delay_drop.activate = false;
4041 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4042 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4043 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4044 atomic_set(&dev->delay_drop.events_cnt, 0);
4046 if (!mlx5_debugfs_root)
4049 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev));
4050 dev->delay_drop.dir_debugfs = root;
4052 debugfs_create_atomic_t("num_timeout_events", 0400, root,
4053 &dev->delay_drop.events_cnt);
4054 debugfs_create_atomic_t("num_rqs", 0400, root,
4055 &dev->delay_drop.rqs_cnt);
4056 debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
4057 &fops_delay_drop_timeout);
4061 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4063 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4066 cancel_work_sync(&dev->delay_drop.delay_drop_work);
4067 if (!dev->delay_drop.dir_debugfs)
4070 debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
4071 dev->delay_drop.dir_debugfs = NULL;
4074 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
4076 dev->mdev_events.notifier_call = mlx5_ib_event;
4077 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
4081 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
4083 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
4086 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4087 const struct mlx5_ib_profile *profile,
4090 dev->ib_active = false;
4092 /* Number of stages to cleanup */
4095 if (profile->stage[stage].cleanup)
4096 profile->stage[stage].cleanup(dev);
4100 ib_dealloc_device(&dev->ib_dev);
4103 int __mlx5_ib_add(struct mlx5_ib_dev *dev,
4104 const struct mlx5_ib_profile *profile)
4109 dev->profile = profile;
4111 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4112 if (profile->stage[i].init) {
4113 err = profile->stage[i].init(dev);
4119 dev->ib_active = true;
4123 /* Clean up stages which were initialized */
4126 if (profile->stage[i].cleanup)
4127 profile->stage[i].cleanup(dev);
4132 static const struct mlx5_ib_profile pf_profile = {
4133 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4134 mlx5_ib_stage_init_init,
4135 mlx5_ib_stage_init_cleanup),
4136 STAGE_CREATE(MLX5_IB_STAGE_FS,
4138 mlx5_ib_fs_cleanup),
4139 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4140 mlx5_ib_stage_caps_init,
4141 mlx5_ib_stage_caps_cleanup),
4142 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4143 mlx5_ib_stage_non_default_cb,
4145 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4147 mlx5_ib_roce_cleanup),
4148 STAGE_CREATE(MLX5_IB_STAGE_QP,
4150 mlx5_cleanup_qp_table),
4151 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4152 mlx5_init_srq_table,
4153 mlx5_cleanup_srq_table),
4154 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4155 mlx5_ib_dev_res_init,
4156 mlx5_ib_dev_res_cleanup),
4157 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4158 mlx5_ib_stage_dev_notifier_init,
4159 mlx5_ib_stage_dev_notifier_cleanup),
4160 STAGE_CREATE(MLX5_IB_STAGE_ODP,
4161 mlx5_ib_odp_init_one,
4162 mlx5_ib_odp_cleanup_one),
4163 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4164 mlx5_ib_counters_init,
4165 mlx5_ib_counters_cleanup),
4166 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4167 mlx5_ib_stage_cong_debugfs_init,
4168 mlx5_ib_stage_cong_debugfs_cleanup),
4169 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4170 mlx5_ib_stage_uar_init,
4171 mlx5_ib_stage_uar_cleanup),
4172 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4173 mlx5_ib_stage_bfrag_init,
4174 mlx5_ib_stage_bfrag_cleanup),
4175 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4177 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4178 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4180 mlx5_ib_devx_cleanup),
4181 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4182 mlx5_ib_stage_ib_reg_init,
4183 mlx5_ib_stage_ib_reg_cleanup),
4184 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4185 mlx5_ib_stage_post_ib_reg_umr_init,
4187 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4188 mlx5_ib_stage_delay_drop_init,
4189 mlx5_ib_stage_delay_drop_cleanup),
4190 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4191 mlx5_ib_restrack_init,
4195 const struct mlx5_ib_profile raw_eth_profile = {
4196 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4197 mlx5_ib_stage_init_init,
4198 mlx5_ib_stage_init_cleanup),
4199 STAGE_CREATE(MLX5_IB_STAGE_FS,
4201 mlx5_ib_fs_cleanup),
4202 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4203 mlx5_ib_stage_caps_init,
4204 mlx5_ib_stage_caps_cleanup),
4205 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4206 mlx5_ib_stage_raw_eth_non_default_cb,
4208 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4210 mlx5_ib_roce_cleanup),
4211 STAGE_CREATE(MLX5_IB_STAGE_QP,
4213 mlx5_cleanup_qp_table),
4214 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4215 mlx5_init_srq_table,
4216 mlx5_cleanup_srq_table),
4217 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4218 mlx5_ib_dev_res_init,
4219 mlx5_ib_dev_res_cleanup),
4220 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4221 mlx5_ib_stage_dev_notifier_init,
4222 mlx5_ib_stage_dev_notifier_cleanup),
4223 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4224 mlx5_ib_counters_init,
4225 mlx5_ib_counters_cleanup),
4226 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4227 mlx5_ib_stage_cong_debugfs_init,
4228 mlx5_ib_stage_cong_debugfs_cleanup),
4229 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4230 mlx5_ib_stage_uar_init,
4231 mlx5_ib_stage_uar_cleanup),
4232 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4233 mlx5_ib_stage_bfrag_init,
4234 mlx5_ib_stage_bfrag_cleanup),
4235 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4237 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4238 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4240 mlx5_ib_devx_cleanup),
4241 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4242 mlx5_ib_stage_ib_reg_init,
4243 mlx5_ib_stage_ib_reg_cleanup),
4244 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4245 mlx5_ib_stage_post_ib_reg_umr_init,
4247 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4248 mlx5_ib_restrack_init,
4252 static int mlx5r_mp_probe(struct auxiliary_device *adev,
4253 const struct auxiliary_device_id *id)
4255 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4256 struct mlx5_core_dev *mdev = idev->mdev;
4257 struct mlx5_ib_multiport_info *mpi;
4258 struct mlx5_ib_dev *dev;
4262 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4267 err = mlx5_query_nic_vport_system_image_guid(mdev,
4268 &mpi->sys_image_guid);
4274 mutex_lock(&mlx5_ib_multiport_mutex);
4275 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
4276 if (dev->sys_image_guid == mpi->sys_image_guid)
4277 bound = mlx5_ib_bind_slave_port(dev, mpi);
4280 rdma_roce_rescan_device(&dev->ib_dev);
4281 mpi->ibdev->ib_active = true;
4287 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4288 dev_dbg(mdev->device,
4289 "no suitable IB device found to bind to, added to unaffiliated list.\n");
4291 mutex_unlock(&mlx5_ib_multiport_mutex);
4293 auxiliary_set_drvdata(adev, mpi);
4297 static void mlx5r_mp_remove(struct auxiliary_device *adev)
4299 struct mlx5_ib_multiport_info *mpi;
4301 mpi = auxiliary_get_drvdata(adev);
4302 mutex_lock(&mlx5_ib_multiport_mutex);
4304 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
4306 list_del(&mpi->list);
4307 mutex_unlock(&mlx5_ib_multiport_mutex);
4311 static int mlx5r_probe(struct auxiliary_device *adev,
4312 const struct auxiliary_device_id *id)
4314 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4315 struct mlx5_core_dev *mdev = idev->mdev;
4316 const struct mlx5_ib_profile *profile;
4317 int port_type_cap, num_ports, ret;
4318 enum rdma_link_layer ll;
4319 struct mlx5_ib_dev *dev;
4321 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4322 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4324 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4325 MLX5_CAP_GEN(mdev, num_vhca_ports));
4326 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
4329 dev->port = kcalloc(num_ports, sizeof(*dev->port),
4332 ib_dealloc_device(&dev->ib_dev);
4337 dev->num_ports = num_ports;
4339 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_init_enabled(mdev))
4340 profile = &raw_eth_profile;
4342 profile = &pf_profile;
4344 ret = __mlx5_ib_add(dev, profile);
4347 ib_dealloc_device(&dev->ib_dev);
4351 auxiliary_set_drvdata(adev, dev);
4355 static void mlx5r_remove(struct auxiliary_device *adev)
4357 struct mlx5_ib_dev *dev;
4359 dev = auxiliary_get_drvdata(adev);
4360 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
4363 static const struct auxiliary_device_id mlx5r_mp_id_table[] = {
4364 { .name = MLX5_ADEV_NAME ".multiport", },
4368 static const struct auxiliary_device_id mlx5r_id_table[] = {
4369 { .name = MLX5_ADEV_NAME ".rdma", },
4373 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table);
4374 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table);
4376 static struct auxiliary_driver mlx5r_mp_driver = {
4377 .name = "multiport",
4378 .probe = mlx5r_mp_probe,
4379 .remove = mlx5r_mp_remove,
4380 .id_table = mlx5r_mp_id_table,
4383 static struct auxiliary_driver mlx5r_driver = {
4385 .probe = mlx5r_probe,
4386 .remove = mlx5r_remove,
4387 .id_table = mlx5r_id_table,
4390 static int __init mlx5_ib_init(void)
4394 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL);
4395 if (!xlt_emergency_page)
4398 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
4399 if (!mlx5_ib_event_wq) {
4400 free_page((unsigned long)xlt_emergency_page);
4405 ret = mlx5r_rep_init();
4408 ret = auxiliary_driver_register(&mlx5r_mp_driver);
4411 ret = auxiliary_driver_register(&mlx5r_driver);
4417 auxiliary_driver_unregister(&mlx5r_mp_driver);
4419 mlx5r_rep_cleanup();
4421 destroy_workqueue(mlx5_ib_event_wq);
4422 free_page((unsigned long)xlt_emergency_page);
4426 static void __exit mlx5_ib_cleanup(void)
4428 auxiliary_driver_unregister(&mlx5r_driver);
4429 auxiliary_driver_unregister(&mlx5r_mp_driver);
4430 mlx5r_rep_cleanup();
4432 destroy_workqueue(mlx5_ib_event_wq);
4433 free_page((unsigned long)xlt_emergency_page);
4436 module_init(mlx5_ib_init);
4437 module_exit(mlx5_ib_cleanup);