drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/errno.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/slab.h>
  40 #if defined(CONFIG_X86)
  41 #include <asm/pat.h>
  42 #endif
  43 #include <linux/sched.h>
  44 #include <linux/sched/mm.h>
  45 #include <linux/sched/task.h>
  46 #include <linux/delay.h>
  47 #include <rdma/ib_user_verbs.h>
  48 #include <rdma/ib_addr.h>
  49 #include <rdma/ib_cache.h>
  50 #include <linux/mlx5/port.h>
  51 #include <linux/mlx5/vport.h>
  52 #include <linux/list.h>
  53 #include <rdma/ib_smi.h>
  54 #include <rdma/ib_umem.h>
  55 #include <linux/in.h>
  56 #include <linux/etherdevice.h>
  57 #include <linux/mlx5/fs.h>
  58 #include <linux/mlx5/vport.h>
  59 #include "mlx5_ib.h"
  60 #include "cmd.h"
  61 #include <linux/mlx5/vport.h>
  62
  63 #define DRIVER_NAME "mlx5_ib"
  64 #define DRIVER_VERSION "5.0-0"
  65
  66 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  67 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  68 MODULE_LICENSE("Dual BSD/GPL");
  69 MODULE_VERSION(DRIVER_VERSION);
  70
  71 static char mlx5_version[] =
  72         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  73         DRIVER_VERSION "\n";
  74
  75 enum {
  76         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  77 };
  78
  79 static enum rdma_link_layer
  80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  81 {
  82         switch (port_type_cap) {
  83         case MLX5_CAP_PORT_TYPE_IB:
  84                 return IB_LINK_LAYER_INFINIBAND;
  85         case MLX5_CAP_PORT_TYPE_ETH:
  86                 return IB_LINK_LAYER_ETHERNET;
  87         default:
  88                 return IB_LINK_LAYER_UNSPECIFIED;
  89         }
  90 }
  91
  92 static enum rdma_link_layer
  93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  94 {
  95         struct mlx5_ib_dev *dev = to_mdev(device);
  96         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  97
  98         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  99 }
 100
 101 static int get_port_state(struct ib_device *ibdev,
 102                           u8 port_num,
 103                           enum ib_port_state *state)
 104 {
 105         struct ib_port_attr attr;
 106         int ret;
 107
 108         memset(&attr, 0, sizeof(attr));
 109         ret = mlx5_ib_query_port(ibdev, port_num, &attr);
 110         if (!ret)
 111                 *state = attr.state;
 112         return ret;
 113 }
 114
 115 static int mlx5_netdev_event(struct notifier_block *this,
 116                              unsigned long event, void *ptr)
 117 {
 118         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 119         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 120                                                  roce.nb);
 121
 122         switch (event) {
 123         case NETDEV_REGISTER:
 124         case NETDEV_UNREGISTER:
 125                 write_lock(&ibdev->roce.netdev_lock);
 126                 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
 127                         ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
 128                                              NULL : ndev;
 129                 write_unlock(&ibdev->roce.netdev_lock);
 130                 break;
 131
 132         case NETDEV_CHANGE:
 133         case NETDEV_UP:
 134         case NETDEV_DOWN: {
 135                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 136                 struct net_device *upper = NULL;
 137
 138                 if (lag_ndev) {
 139                         upper = netdev_master_upper_dev_get(lag_ndev);
 140                         dev_put(lag_ndev);
 141                 }
 142
 143                 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
 144                     && ibdev->ib_active) {
 145                         struct ib_event ibev = { };
 146                         enum ib_port_state port_state;
 147
 148                         if (get_port_state(&ibdev->ib_dev, 1, &port_state))
 149                                 return NOTIFY_DONE;
 150
 151                         if (ibdev->roce.last_port_state == port_state)
 152                                 return NOTIFY_DONE;
 153
 154                         ibdev->roce.last_port_state = port_state;
 155                         ibev.device = &ibdev->ib_dev;
 156                         if (port_state == IB_PORT_DOWN)
 157                                 ibev.event = IB_EVENT_PORT_ERR;
 158                         else if (port_state == IB_PORT_ACTIVE)
 159                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 160                         else
 161                                 return NOTIFY_DONE;
 162
 163                         ibev.element.port_num = 1;
 164                         ib_dispatch_event(&ibev);
 165                 }
 166                 break;
 167         }
 168
 169         default:
 170                 break;
 171         }
 172
 173         return NOTIFY_DONE;
 174 }
 175
 176 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 177                                              u8 port_num)
 178 {
 179         struct mlx5_ib_dev *ibdev = to_mdev(device);
 180         struct net_device *ndev;
 181
 182         ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 183         if (ndev)
 184                 return ndev;
 185
 186         /* Ensure ndev does not disappear before we invoke dev_hold()
 187          */
 188         read_lock(&ibdev->roce.netdev_lock);
 189         ndev = ibdev->roce.netdev;
 190         if (ndev)
 191                 dev_hold(ndev);
 192         read_unlock(&ibdev->roce.netdev_lock);
 193
 194         return ndev;
 195 }
 196
 197 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 198                                     u8 *active_width)
 199 {
 200         switch (eth_proto_oper) {
 201         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 202         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 203         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 204         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 205                 *active_width = IB_WIDTH_1X;
 206                 *active_speed = IB_SPEED_SDR;
 207                 break;
 208         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 209         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 210         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 211         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 212         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 213         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 214         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 215                 *active_width = IB_WIDTH_1X;
 216                 *active_speed = IB_SPEED_QDR;
 217                 break;
 218         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 219         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 220         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 221                 *active_width = IB_WIDTH_1X;
 222                 *active_speed = IB_SPEED_EDR;
 223                 break;
 224         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 225         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 226         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 227         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 228                 *active_width = IB_WIDTH_4X;
 229                 *active_speed = IB_SPEED_QDR;
 230                 break;
 231         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 232         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 233         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 234                 *active_width = IB_WIDTH_1X;
 235                 *active_speed = IB_SPEED_HDR;
 236                 break;
 237         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 238                 *active_width = IB_WIDTH_4X;
 239                 *active_speed = IB_SPEED_FDR;
 240                 break;
 241         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 242         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 243         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 244         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 245                 *active_width = IB_WIDTH_4X;
 246                 *active_speed = IB_SPEED_EDR;
 247                 break;
 248         default:
 249                 return -EINVAL;
 250         }
 251
 252         return 0;
 253 }
 254
 255 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 256                                 struct ib_port_attr *props)
 257 {
 258         struct mlx5_ib_dev *dev = to_mdev(device);
 259         struct mlx5_core_dev *mdev = dev->mdev;
 260         struct net_device *ndev, *upper;
 261         enum ib_mtu ndev_ib_mtu;
 262         u16 qkey_viol_cntr;
 263         u32 eth_prot_oper;
 264         int err;
 265
 266         /* Possible bad flows are checked before filling out props so in case
 267          * of an error it will still be zeroed out.
 268          */
 269         err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
 270         if (err)
 271                 return err;
 272
 273         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 274                                  &props->active_width);
 275
 276         props->port_cap_flags  |= IB_PORT_CM_SUP;
 277         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 278
 279         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 280                                                 roce_address_table_size);
 281         props->max_mtu          = IB_MTU_4096;
 282         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 283         props->pkey_tbl_len     = 1;
 284         props->state            = IB_PORT_DOWN;
 285         props->phys_state       = 3;
 286
 287         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 288         props->qkey_viol_cntr = qkey_viol_cntr;
 289
 290         ndev = mlx5_ib_get_netdev(device, port_num);
 291         if (!ndev)
 292                 return 0;
 293
 294         if (mlx5_lag_is_active(dev->mdev)) {
 295                 rcu_read_lock();
 296                 upper = netdev_master_upper_dev_get_rcu(ndev);
 297                 if (upper) {
 298                         dev_put(ndev);
 299                         ndev = upper;
 300                         dev_hold(ndev);
 301                 }
 302                 rcu_read_unlock();
 303         }
 304
 305         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 306                 props->state      = IB_PORT_ACTIVE;
 307                 props->phys_state = 5;
 308         }
 309
 310         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 311
 312         dev_put(ndev);
 313
 314         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 315         return 0;
 316 }
 317
 318 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 319                          unsigned int index, const union ib_gid *gid,
 320                          const struct ib_gid_attr *attr)
 321 {
 322         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 323         u8 roce_version = 0;
 324         u8 roce_l3_type = 0;
 325         bool vlan = false;
 326         u8 mac[ETH_ALEN];
 327         u16 vlan_id = 0;
 328
 329         if (gid) {
 330                 gid_type = attr->gid_type;
 331                 ether_addr_copy(mac, attr->ndev->dev_addr);
 332
 333                 if (is_vlan_dev(attr->ndev)) {
 334                         vlan = true;
 335                         vlan_id = vlan_dev_vlan_id(attr->ndev);
 336                 }
 337         }
 338
 339         switch (gid_type) {
 340         case IB_GID_TYPE_IB:
 341                 roce_version = MLX5_ROCE_VERSION_1;
 342                 break;
 343         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 344                 roce_version = MLX5_ROCE_VERSION_2;
 345                 if (ipv6_addr_v4mapped((void *)gid))
 346                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 347                 else
 348                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 349                 break;
 350
 351         default:
 352                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 353         }
 354
 355         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 356                                       roce_l3_type, gid->raw, mac, vlan,
 357                                       vlan_id);
 358 }
 359
 360 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 361                            unsigned int index, const union ib_gid *gid,
 362                            const struct ib_gid_attr *attr,
 363                            __always_unused void **context)
 364 {
 365         return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
 366 }
 367
 368 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 369                            unsigned int index, __always_unused void **context)
 370 {
 371         return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
 372 }
 373
 374 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 375                                int index)
 376 {
 377         struct ib_gid_attr attr;
 378         union ib_gid gid;
 379
 380         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 381                 return 0;
 382
 383         if (!attr.ndev)
 384                 return 0;
 385
 386         dev_put(attr.ndev);
 387
 388         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 389                 return 0;
 390
 391         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 392 }
 393
 394 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
 395                            int index, enum ib_gid_type *gid_type)
 396 {
 397         struct ib_gid_attr attr;
 398         union ib_gid gid;
 399         int ret;
 400
 401         ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
 402         if (ret)
 403                 return ret;
 404
 405         if (!attr.ndev)
 406                 return -ENODEV;
 407
 408         dev_put(attr.ndev);
 409
 410         *gid_type = attr.gid_type;
 411
 412         return 0;
 413 }
 414
 415 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 416 {
 417         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 418                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 419         return 0;
 420 }
 421
 422 enum {
 423         MLX5_VPORT_ACCESS_METHOD_MAD,
 424         MLX5_VPORT_ACCESS_METHOD_HCA,
 425         MLX5_VPORT_ACCESS_METHOD_NIC,
 426 };
 427
 428 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 429 {
 430         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 431                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 432
 433         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 434             IB_LINK_LAYER_ETHERNET)
 435                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 436
 437         return MLX5_VPORT_ACCESS_METHOD_HCA;
 438 }
 439
 440 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 441                             struct ib_device_attr *props)
 442 {
 443         u8 tmp;
 444         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 445         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 446         u8 atomic_req_8B_endianness_mode =
 447                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 448
 449         /* Check if HW supports 8 bytes standard atomic operations and capable
 450          * of host endianness respond
 451          */
 452         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 453         if (((atomic_operations & tmp) == tmp) &&
 454             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 455             (atomic_req_8B_endianness_mode)) {
 456                 props->atomic_cap = IB_ATOMIC_HCA;
 457         } else {
 458                 props->atomic_cap = IB_ATOMIC_NONE;
 459         }
 460 }
 461
 462 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 463                                         __be64 *sys_image_guid)
 464 {
 465         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 466         struct mlx5_core_dev *mdev = dev->mdev;
 467         u64 tmp;
 468         int err;
 469
 470         switch (mlx5_get_vport_access_method(ibdev)) {
 471         case MLX5_VPORT_ACCESS_METHOD_MAD:
 472                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 473                                                             sys_image_guid);
 474
 475         case MLX5_VPORT_ACCESS_METHOD_HCA:
 476                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 477                 break;
 478
 479         case MLX5_VPORT_ACCESS_METHOD_NIC:
 480                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 481                 break;
 482
 483         default:
 484                 return -EINVAL;
 485         }
 486
 487         if (!err)
 488                 *sys_image_guid = cpu_to_be64(tmp);
 489
 490         return err;
 491
 492 }
 493
 494 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 495                                 u16 *max_pkeys)
 496 {
 497         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 498         struct mlx5_core_dev *mdev = dev->mdev;
 499
 500         switch (mlx5_get_vport_access_method(ibdev)) {
 501         case MLX5_VPORT_ACCESS_METHOD_MAD:
 502                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 503
 504         case MLX5_VPORT_ACCESS_METHOD_HCA:
 505         case MLX5_VPORT_ACCESS_METHOD_NIC:
 506                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 507                                                 pkey_table_size));
 508                 return 0;
 509
 510         default:
 511                 return -EINVAL;
 512         }
 513 }
 514
 515 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 516                                 u32 *vendor_id)
 517 {
 518         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 519
 520         switch (mlx5_get_vport_access_method(ibdev)) {
 521         case MLX5_VPORT_ACCESS_METHOD_MAD:
 522                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 523
 524         case MLX5_VPORT_ACCESS_METHOD_HCA:
 525         case MLX5_VPORT_ACCESS_METHOD_NIC:
 526                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 527
 528         default:
 529                 return -EINVAL;
 530         }
 531 }
 532
 533 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 534                                 __be64 *node_guid)
 535 {
 536         u64 tmp;
 537         int err;
 538
 539         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 540         case MLX5_VPORT_ACCESS_METHOD_MAD:
 541                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 542
 543         case MLX5_VPORT_ACCESS_METHOD_HCA:
 544                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 545                 break;
 546
 547         case MLX5_VPORT_ACCESS_METHOD_NIC:
 548                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 549                 break;
 550
 551         default:
 552                 return -EINVAL;
 553         }
 554
 555         if (!err)
 556                 *node_guid = cpu_to_be64(tmp);
 557
 558         return err;
 559 }
 560
 561 struct mlx5_reg_node_desc {
 562         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 563 };
 564
 565 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 566 {
 567         struct mlx5_reg_node_desc in;
 568
 569         if (mlx5_use_mad_ifc(dev))
 570                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 571
 572         memset(&in, 0, sizeof(in));
 573
 574         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 575                                     sizeof(struct mlx5_reg_node_desc),
 576                                     MLX5_REG_NODE_DESC, 0, 0);
 577 }
 578
 579 static int mlx5_ib_query_device(struct ib_device *ibdev,
 580                                 struct ib_device_attr *props,
 581                                 struct ib_udata *uhw)
 582 {
 583         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 584         struct mlx5_core_dev *mdev = dev->mdev;
 585         int err = -ENOMEM;
 586         int max_sq_desc;
 587         int max_rq_sg;
 588         int max_sq_sg;
 589         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 590         struct mlx5_ib_query_device_resp resp = {};
 591         size_t resp_len;
 592         u64 max_tso;
 593
 594         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 595         if (uhw->outlen && uhw->outlen < resp_len)
 596                 return -EINVAL;
 597         else
 598                 resp.response_length = resp_len;
 599
 600         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 601                 return -EINVAL;
 602
 603         memset(props, 0, sizeof(*props));
 604         err = mlx5_query_system_image_guid(ibdev,
 605                                            &props->sys_image_guid);
 606         if (err)
 607                 return err;
 608
 609         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 610         if (err)
 611                 return err;
 612
 613         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 614         if (err)
 615                 return err;
 616
 617         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 618                 (fw_rev_min(dev->mdev) << 16) |
 619                 fw_rev_sub(dev->mdev);
 620         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 621                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 622                 IB_DEVICE_SYS_IMAGE_GUID                |
 623                 IB_DEVICE_RC_RNR_NAK_GEN;
 624
 625         if (MLX5_CAP_GEN(mdev, pkv))
 626                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 627         if (MLX5_CAP_GEN(mdev, qkv))
 628                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 629         if (MLX5_CAP_GEN(mdev, apm))
 630                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 631         if (MLX5_CAP_GEN(mdev, xrc))
 632                 props->device_cap_flags |= IB_DEVICE_XRC;
 633         if (MLX5_CAP_GEN(mdev, imaicl)) {
 634                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 635                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 636                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 637                 /* We support 'Gappy' memory registration too */
 638                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 639         }
 640         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 641         if (MLX5_CAP_GEN(mdev, sho)) {
 642                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 643                 /* At this stage no support for signature handover */
 644                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 645                                       IB_PROT_T10DIF_TYPE_2 |
 646                                       IB_PROT_T10DIF_TYPE_3;
 647                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 648                                        IB_GUARD_T10DIF_CSUM;
 649         }
 650         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 651                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 652
 653         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
 654                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 655                         /* Legacy bit to support old userspace libraries */
 656                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 657                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 658                 }
 659
 660                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 661                         props->raw_packet_caps |=
 662                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 663
 664                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 665                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 666                         if (max_tso) {
 667                                 resp.tso_caps.max_tso = 1 << max_tso;
 668                                 resp.tso_caps.supported_qpts |=
 669                                         1 << IB_QPT_RAW_PACKET;
 670                                 resp.response_length += sizeof(resp.tso_caps);
 671                         }
 672                 }
 673
 674                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 675                         resp.rss_caps.rx_hash_function =
 676                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 677                         resp.rss_caps.rx_hash_fields_mask =
 678                                                 MLX5_RX_HASH_SRC_IPV4 |
 679                                                 MLX5_RX_HASH_DST_IPV4 |
 680                                                 MLX5_RX_HASH_SRC_IPV6 |
 681                                                 MLX5_RX_HASH_DST_IPV6 |
 682                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 683                                                 MLX5_RX_HASH_DST_PORT_TCP |
 684                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 685                                                 MLX5_RX_HASH_DST_PORT_UDP;
 686                         resp.response_length += sizeof(resp.rss_caps);
 687                 }
 688         } else {
 689                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 690                         resp.response_length += sizeof(resp.tso_caps);
 691                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 692                         resp.response_length += sizeof(resp.rss_caps);
 693         }
 694
 695         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 696                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 697                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 698         }
 699
 700         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 701             MLX5_CAP_GEN(dev->mdev, general_notification_event))
 702                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 703
 704         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 705             MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
 706                 /* Legacy bit to support old userspace libraries */
 707                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 708                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 709         }
 710
 711         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 712                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 713
 714         props->vendor_part_id      = mdev->pdev->device;
 715         props->hw_ver              = mdev->pdev->revision;
 716
 717         props->max_mr_size         = ~0ull;
 718         props->page_size_cap       = ~(min_page_size - 1);
 719         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 720         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 721         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 722                      sizeof(struct mlx5_wqe_data_seg);
 723         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 724         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 725                      sizeof(struct mlx5_wqe_raddr_seg)) /
 726                 sizeof(struct mlx5_wqe_data_seg);
 727         props->max_sge = min(max_rq_sg, max_sq_sg);
 728         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 729         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 730         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 731         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 732         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 733         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 734         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 735         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 736         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 737         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 738         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 739         props->max_srq_sge         = max_rq_sg - 1;
 740         props->max_fast_reg_page_list_len =
 741                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 742         get_atomic_caps(dev, props);
 743         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 744         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 745         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 746         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 747                                            props->max_mcast_grp;
 748         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 749         props->max_ah = INT_MAX;
 750         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 751         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 752
 753 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 754         if (MLX5_CAP_GEN(mdev, pg))
 755                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 756         props->odp_caps = dev->odp_caps;
 757 #endif
 758
 759         if (MLX5_CAP_GEN(mdev, cd))
 760                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 761
 762         if (!mlx5_core_is_pf(mdev))
 763                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 764
 765         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 766             IB_LINK_LAYER_ETHERNET) {
 767                 props->rss_caps.max_rwq_indirection_tables =
 768                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 769                 props->rss_caps.max_rwq_indirection_table_size =
 770                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 771                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 772                 props->max_wq_type_rq =
 773                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 774         }
 775
 776         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
 777                 resp.cqe_comp_caps.max_num =
 778                         MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
 779                         MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
 780                 resp.cqe_comp_caps.supported_format =
 781                         MLX5_IB_CQE_RES_FORMAT_HASH |
 782                         MLX5_IB_CQE_RES_FORMAT_CSUM;
 783                 resp.response_length += sizeof(resp.cqe_comp_caps);
 784         }
 785
 786         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
 787                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
 788                     MLX5_CAP_GEN(mdev, qos)) {
 789                         resp.packet_pacing_caps.qp_rate_limit_max =
 790                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
 791                         resp.packet_pacing_caps.qp_rate_limit_min =
 792                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
 793                         resp.packet_pacing_caps.supported_qpts |=
 794                                 1 << IB_QPT_RAW_PACKET;
 795                 }
 796                 resp.response_length += sizeof(resp.packet_pacing_caps);
 797         }
 798
 799         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
 800                         uhw->outlen)) {
 801                 resp.mlx5_ib_support_multi_pkt_send_wqes =
 802                         MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
 803                 resp.response_length +=
 804                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
 805         }
 806
 807         if (field_avail(typeof(resp), reserved, uhw->outlen))
 808                 resp.response_length += sizeof(resp.reserved);
 809
 810         if (uhw->outlen) {
 811                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
 812
 813                 if (err)
 814                         return err;
 815         }
 816
 817         return 0;
 818 }
 819
 820 enum mlx5_ib_width {
 821         MLX5_IB_WIDTH_1X        = 1 << 0,
 822         MLX5_IB_WIDTH_2X        = 1 << 1,
 823         MLX5_IB_WIDTH_4X        = 1 << 2,
 824         MLX5_IB_WIDTH_8X        = 1 << 3,
 825         MLX5_IB_WIDTH_12X       = 1 << 4
 826 };
 827
 828 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 829                                   u8 *ib_width)
 830 {
 831         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 832         int err = 0;
 833
 834         if (active_width & MLX5_IB_WIDTH_1X) {
 835                 *ib_width = IB_WIDTH_1X;
 836         } else if (active_width & MLX5_IB_WIDTH_2X) {
 837                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 838                             (int)active_width);
 839                 err = -EINVAL;
 840         } else if (active_width & MLX5_IB_WIDTH_4X) {
 841                 *ib_width = IB_WIDTH_4X;
 842         } else if (active_width & MLX5_IB_WIDTH_8X) {
 843                 *ib_width = IB_WIDTH_8X;
 844         } else if (active_width & MLX5_IB_WIDTH_12X) {
 845                 *ib_width = IB_WIDTH_12X;
 846         } else {
 847                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 848                             (int)active_width);
 849                 err = -EINVAL;
 850         }
 851
 852         return err;
 853 }
 854
 855 static int mlx5_mtu_to_ib_mtu(int mtu)
 856 {
 857         switch (mtu) {
 858         case 256: return 1;
 859         case 512: return 2;
 860         case 1024: return 3;
 861         case 2048: return 4;
 862         case 4096: return 5;
 863         default:
 864                 pr_warn("invalid mtu\n");
 865                 return -1;
 866         }
 867 }
 868
 869 enum ib_max_vl_num {
 870         __IB_MAX_VL_0           = 1,
 871         __IB_MAX_VL_0_1         = 2,
 872         __IB_MAX_VL_0_3         = 3,
 873         __IB_MAX_VL_0_7         = 4,
 874         __IB_MAX_VL_0_14        = 5,
 875 };
 876
 877 enum mlx5_vl_hw_cap {
 878         MLX5_VL_HW_0    = 1,
 879         MLX5_VL_HW_0_1  = 2,
 880         MLX5_VL_HW_0_2  = 3,
 881         MLX5_VL_HW_0_3  = 4,
 882         MLX5_VL_HW_0_4  = 5,
 883         MLX5_VL_HW_0_5  = 6,
 884         MLX5_VL_HW_0_6  = 7,
 885         MLX5_VL_HW_0_7  = 8,
 886         MLX5_VL_HW_0_14 = 15
 887 };
 888
 889 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 890                                 u8 *max_vl_num)
 891 {
 892         switch (vl_hw_cap) {
 893         case MLX5_VL_HW_0:
 894                 *max_vl_num = __IB_MAX_VL_0;
 895                 break;
 896         case MLX5_VL_HW_0_1:
 897                 *max_vl_num = __IB_MAX_VL_0_1;
 898                 break;
 899         case MLX5_VL_HW_0_3:
 900                 *max_vl_num = __IB_MAX_VL_0_3;
 901                 break;
 902         case MLX5_VL_HW_0_7:
 903                 *max_vl_num = __IB_MAX_VL_0_7;
 904                 break;
 905         case MLX5_VL_HW_0_14:
 906                 *max_vl_num = __IB_MAX_VL_0_14;
 907                 break;
 908
 909         default:
 910                 return -EINVAL;
 911         }
 912
 913         return 0;
 914 }
 915
 916 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
 917                                struct ib_port_attr *props)
 918 {
 919         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 920         struct mlx5_core_dev *mdev = dev->mdev;
 921         struct mlx5_hca_vport_context *rep;
 922         u16 max_mtu;
 923         u16 oper_mtu;
 924         int err;
 925         u8 ib_link_width_oper;
 926         u8 vl_hw_cap;
 927
 928         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
 929         if (!rep) {
 930                 err = -ENOMEM;
 931                 goto out;
 932         }
 933
 934         /* props being zeroed by the caller, avoid zeroing it here */
 935
 936         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
 937         if (err)
 938                 goto out;
 939
 940         props->lid              = rep->lid;
 941         props->lmc              = rep->lmc;
 942         props->sm_lid           = rep->sm_lid;
 943         props->sm_sl            = rep->sm_sl;
 944         props->state            = rep->vport_state;
 945         props->phys_state       = rep->port_physical_state;
 946         props->port_cap_flags   = rep->cap_mask1;
 947         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
 948         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
 949         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
 950         props->bad_pkey_cntr    = rep->pkey_violation_counter;
 951         props->qkey_viol_cntr   = rep->qkey_violation_counter;
 952         props->subnet_timeout   = rep->subnet_timeout;
 953         props->init_type_reply  = rep->init_type_reply;
 954         props->grh_required     = rep->grh_required;
 955
 956         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
 957         if (err)
 958                 goto out;
 959
 960         err = translate_active_width(ibdev, ib_link_width_oper,
 961                                      &props->active_width);
 962         if (err)
 963                 goto out;
 964         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
 965         if (err)
 966                 goto out;
 967
 968         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
 969
 970         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
 971
 972         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
 973
 974         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
 975
 976         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
 977         if (err)
 978                 goto out;
 979
 980         err = translate_max_vl_num(ibdev, vl_hw_cap,
 981                                    &props->max_vl_num);
 982 out:
 983         kfree(rep);
 984         return err;
 985 }
 986
 987 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 988                        struct ib_port_attr *props)
 989 {
 990         unsigned int count;
 991         int ret;
 992
 993         switch (mlx5_get_vport_access_method(ibdev)) {
 994         case MLX5_VPORT_ACCESS_METHOD_MAD:
 995                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
 996                 break;
 997
 998         case MLX5_VPORT_ACCESS_METHOD_HCA:
 999                 ret = mlx5_query_hca_port(ibdev, port, props);
1000                 break;
1001
1002         case MLX5_VPORT_ACCESS_METHOD_NIC:
1003                 ret = mlx5_query_port_roce(ibdev, port, props);
1004                 break;
1005
1006         default:
1007                 ret = -EINVAL;
1008         }
1009
1010         if (!ret && props) {
1011                 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
1012                 props->gid_tbl_len -= count;
1013         }
1014         return ret;
1015 }
1016
1017 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1018                              union ib_gid *gid)
1019 {
1020         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1021         struct mlx5_core_dev *mdev = dev->mdev;
1022
1023         switch (mlx5_get_vport_access_method(ibdev)) {
1024         case MLX5_VPORT_ACCESS_METHOD_MAD:
1025                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1026
1027         case MLX5_VPORT_ACCESS_METHOD_HCA:
1028                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1029
1030         default:
1031                 return -EINVAL;
1032         }
1033
1034 }
1035
1036 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1037                               u16 *pkey)
1038 {
1039         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1040         struct mlx5_core_dev *mdev = dev->mdev;
1041
1042         switch (mlx5_get_vport_access_method(ibdev)) {
1043         case MLX5_VPORT_ACCESS_METHOD_MAD:
1044                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1045
1046         case MLX5_VPORT_ACCESS_METHOD_HCA:
1047         case MLX5_VPORT_ACCESS_METHOD_NIC:
1048                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
1049                                                  pkey);
1050         default:
1051                 return -EINVAL;
1052         }
1053 }
1054
1055 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1056                                  struct ib_device_modify *props)
1057 {
1058         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1059         struct mlx5_reg_node_desc in;
1060         struct mlx5_reg_node_desc out;
1061         int err;
1062
1063         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1064                 return -EOPNOTSUPP;
1065
1066         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1067                 return 0;
1068
1069         /*
1070          * If possible, pass node desc to FW, so it can generate
1071          * a 144 trap.  If cmd fails, just ignore.
1072          */
1073         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1074         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1075                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1076         if (err)
1077                 return err;
1078
1079         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1080
1081         return err;
1082 }
1083
1084 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1085                                 u32 value)
1086 {
1087         struct mlx5_hca_vport_context ctx = {};
1088         int err;
1089
1090         err = mlx5_query_hca_vport_context(dev->mdev, 0,
1091                                            port_num, 0, &ctx);
1092         if (err)
1093                 return err;
1094
1095         if (~ctx.cap_mask1_perm & mask) {
1096                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1097                              mask, ctx.cap_mask1_perm);
1098                 return -EINVAL;
1099         }
1100
1101         ctx.cap_mask1 = value;
1102         ctx.cap_mask1_perm = mask;
1103         err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1104                                                  port_num, 0, &ctx);
1105
1106         return err;
1107 }
1108
1109 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1110                                struct ib_port_modify *props)
1111 {
1112         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1113         struct ib_port_attr attr;
1114         u32 tmp;
1115         int err;
1116         u32 change_mask;
1117         u32 value;
1118         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1119                       IB_LINK_LAYER_INFINIBAND);
1120
1121         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1122                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1123                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1124                 return set_port_caps_atomic(dev, port, change_mask, value);
1125         }
1126
1127         mutex_lock(&dev->cap_mask_mutex);
1128
1129         err = ib_query_port(ibdev, port, &attr);
1130         if (err)
1131                 goto out;
1132
1133         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1134                 ~props->clr_port_cap_mask;
1135
1136         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1137
1138 out:
1139         mutex_unlock(&dev->cap_mask_mutex);
1140         return err;
1141 }
1142
1143 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1144 {
1145         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1146                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1147 }
1148
1149 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1150                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1151                              u32 *num_sys_pages)
1152 {
1153         int uars_per_sys_page;
1154         int bfregs_per_sys_page;
1155         int ref_bfregs = req->total_num_bfregs;
1156
1157         if (req->total_num_bfregs == 0)
1158                 return -EINVAL;
1159
1160         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1161         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1162
1163         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1164                 return -ENOMEM;
1165
1166         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1167         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1168         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1169         *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1170
1171         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1172                 return -EINVAL;
1173
1174         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n",
1175                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1176                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1177                     req->total_num_bfregs, *num_sys_pages);
1178
1179         return 0;
1180 }
1181
1182 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1183 {
1184         struct mlx5_bfreg_info *bfregi;
1185         int err;
1186         int i;
1187
1188         bfregi = &context->bfregi;
1189         for (i = 0; i < bfregi->num_sys_pages; i++) {
1190                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1191                 if (err)
1192                         goto error;
1193
1194                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1195         }
1196         return 0;
1197
1198 error:
1199         for (--i; i >= 0; i--)
1200                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1201                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1202
1203         return err;
1204 }
1205
1206 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1207 {
1208         struct mlx5_bfreg_info *bfregi;
1209         int err;
1210         int i;
1211
1212         bfregi = &context->bfregi;
1213         for (i = 0; i < bfregi->num_sys_pages; i++) {
1214                 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1215                 if (err) {
1216                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1217                         return err;
1218                 }
1219         }
1220         return 0;
1221 }
1222
1223 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1224 {
1225         int err;
1226
1227         err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1228         if (err)
1229                 return err;
1230
1231         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1232             !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1233                 return err;
1234
1235         mutex_lock(&dev->lb_mutex);
1236         dev->user_td++;
1237
1238         if (dev->user_td == 2)
1239                 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1240
1241         mutex_unlock(&dev->lb_mutex);
1242         return err;
1243 }
1244
1245 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1246 {
1247         mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1248
1249         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1250             !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1251                 return;
1252
1253         mutex_lock(&dev->lb_mutex);
1254         dev->user_td--;
1255
1256         if (dev->user_td < 2)
1257                 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1258
1259         mutex_unlock(&dev->lb_mutex);
1260 }
1261
1262 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1263                                                   struct ib_udata *udata)
1264 {
1265         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1266         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1267         struct mlx5_ib_alloc_ucontext_resp resp = {};
1268         struct mlx5_ib_ucontext *context;
1269         struct mlx5_bfreg_info *bfregi;
1270         int ver;
1271         int err;
1272         size_t reqlen;
1273         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1274                                      max_cqe_version);
1275         bool lib_uar_4k;
1276
1277         if (!dev->ib_active)
1278                 return ERR_PTR(-EAGAIN);
1279
1280         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1281                 return ERR_PTR(-EINVAL);
1282
1283         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1284         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1285                 ver = 0;
1286         else if (reqlen >= min_req_v2)
1287                 ver = 2;
1288         else
1289                 return ERR_PTR(-EINVAL);
1290
1291         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
1292         if (err)
1293                 return ERR_PTR(err);
1294
1295         if (req.flags)
1296                 return ERR_PTR(-EINVAL);
1297
1298         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1299                 return ERR_PTR(-EOPNOTSUPP);
1300
1301         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1302                                     MLX5_NON_FP_BFREGS_PER_UAR);
1303         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1304                 return ERR_PTR(-EINVAL);
1305
1306         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1307         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1308                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1309         resp.cache_line_size = cache_line_size();
1310         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1311         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1312         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1313         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1314         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1315         resp.cqe_version = min_t(__u8,
1316                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1317                                  req.max_cqe_version);
1318         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1319                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1320         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1321                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1322         resp.response_length = min(offsetof(typeof(resp), response_length) +
1323                                    sizeof(resp.response_length), udata->outlen);
1324
1325         context = kzalloc(sizeof(*context), GFP_KERNEL);
1326         if (!context)
1327                 return ERR_PTR(-ENOMEM);
1328
1329         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1330         bfregi = &context->bfregi;
1331
1332         /* updates req->total_num_bfregs */
1333         err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1334         if (err)
1335                 goto out_ctx;
1336
1337         mutex_init(&bfregi->lock);
1338         bfregi->lib_uar_4k = lib_uar_4k;
1339         bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
1340                                 GFP_KERNEL);
1341         if (!bfregi->count) {
1342                 err = -ENOMEM;
1343                 goto out_ctx;
1344         }
1345
1346         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1347                                     sizeof(*bfregi->sys_pages),
1348                                     GFP_KERNEL);
1349         if (!bfregi->sys_pages) {
1350                 err = -ENOMEM;
1351                 goto out_count;
1352         }
1353
1354         err = allocate_uars(dev, context);
1355         if (err)
1356                 goto out_sys_pages;
1357
1358 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1359         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1360 #endif
1361
1362         context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1363         if (!context->upd_xlt_page) {
1364                 err = -ENOMEM;
1365                 goto out_uars;
1366         }
1367         mutex_init(&context->upd_xlt_page_mutex);
1368
1369         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1370                 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1371                 if (err)
1372                         goto out_page;
1373         }
1374
1375         INIT_LIST_HEAD(&context->vma_private_list);
1376         INIT_LIST_HEAD(&context->db_page_list);
1377         mutex_init(&context->db_page_mutex);
1378
1379         resp.tot_bfregs = req.total_num_bfregs;
1380         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1381
1382         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1383                 resp.response_length += sizeof(resp.cqe_version);
1384
1385         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1386                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1387                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1388                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1389         }
1390
1391         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1392                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1393                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1394                         resp.eth_min_inline++;
1395                 }
1396                 resp.response_length += sizeof(resp.eth_min_inline);
1397         }
1398
1399         /*
1400          * We don't want to expose information from the PCI bar that is located
1401          * after 4096 bytes, so if the arch only supports larger pages, let's
1402          * pretend we don't support reading the HCA's core clock. This is also
1403          * forced by mmap function.
1404          */
1405         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1406                 if (PAGE_SIZE <= 4096) {
1407                         resp.comp_mask |=
1408                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1409                         resp.hca_core_clock_offset =
1410                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1411                 }
1412                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1413                                         sizeof(resp.reserved2);
1414         }
1415
1416         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1417                 resp.response_length += sizeof(resp.log_uar_size);
1418
1419         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1420                 resp.response_length += sizeof(resp.num_uars_per_page);
1421
1422         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1423         if (err)
1424                 goto out_td;
1425
1426         bfregi->ver = ver;
1427         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1428         context->cqe_version = resp.cqe_version;
1429         context->lib_caps = req.lib_caps;
1430         print_lib_caps(dev, context->lib_caps);
1431
1432         return &context->ibucontext;
1433
1434 out_td:
1435         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1436                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1437
1438 out_page:
1439         free_page(context->upd_xlt_page);
1440
1441 out_uars:
1442         deallocate_uars(dev, context);
1443
1444 out_sys_pages:
1445         kfree(bfregi->sys_pages);
1446
1447 out_count:
1448         kfree(bfregi->count);
1449
1450 out_ctx:
1451         kfree(context);
1452
1453         return ERR_PTR(err);
1454 }
1455
1456 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1457 {
1458         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1459         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1460         struct mlx5_bfreg_info *bfregi;
1461
1462         bfregi = &context->bfregi;
1463         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1464                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1465
1466         free_page(context->upd_xlt_page);
1467         deallocate_uars(dev, context);
1468         kfree(bfregi->sys_pages);
1469         kfree(bfregi->count);
1470         kfree(context);
1471
1472         return 0;
1473 }
1474
1475 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1476                                  struct mlx5_bfreg_info *bfregi,
1477                                  int idx)
1478 {
1479         int fw_uars_per_page;
1480
1481         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1482
1483         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1484                         bfregi->sys_pages[idx] / fw_uars_per_page;
1485 }
1486
1487 static int get_command(unsigned long offset)
1488 {
1489         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1490 }
1491
1492 static int get_arg(unsigned long offset)
1493 {
1494         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1495 }
1496
1497 static int get_index(unsigned long offset)
1498 {
1499         return get_arg(offset);
1500 }
1501
1502 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1503 {
1504         /* vma_open is called when a new VMA is created on top of our VMA.  This
1505          * is done through either mremap flow or split_vma (usually due to
1506          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1507          * as this VMA is strongly hardware related.  Therefore we set the
1508          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1509          * calling us again and trying to do incorrect actions.  We assume that
1510          * the original VMA size is exactly a single page, and therefore all
1511          * "splitting" operation will not happen to it.
1512          */
1513         area->vm_ops = NULL;
1514 }
1515
1516 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1517 {
1518         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1519
1520         /* It's guaranteed that all VMAs opened on a FD are closed before the
1521          * file itself is closed, therefore no sync is needed with the regular
1522          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1523          * However need a sync with accessing the vma as part of
1524          * mlx5_ib_disassociate_ucontext.
1525          * The close operation is usually called under mm->mmap_sem except when
1526          * process is exiting.
1527          * The exiting case is handled explicitly as part of
1528          * mlx5_ib_disassociate_ucontext.
1529          */
1530         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1531
1532         /* setting the vma context pointer to null in the mlx5_ib driver's
1533          * private data, to protect a race condition in
1534          * mlx5_ib_disassociate_ucontext().
1535          */
1536         mlx5_ib_vma_priv_data->vma = NULL;
1537         list_del(&mlx5_ib_vma_priv_data->list);
1538         kfree(mlx5_ib_vma_priv_data);
1539 }
1540
1541 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1542         .open = mlx5_ib_vma_open,
1543         .close = mlx5_ib_vma_close
1544 };
1545
1546 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1547                                 struct mlx5_ib_ucontext *ctx)
1548 {
1549         struct mlx5_ib_vma_private_data *vma_prv;
1550         struct list_head *vma_head = &ctx->vma_private_list;
1551
1552         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1553         if (!vma_prv)
1554                 return -ENOMEM;
1555
1556         vma_prv->vma = vma;
1557         vma->vm_private_data = vma_prv;
1558         vma->vm_ops =  &mlx5_ib_vm_ops;
1559
1560         list_add(&vma_prv->list, vma_head);
1561
1562         return 0;
1563 }
1564
1565 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1566 {
1567         int ret;
1568         struct vm_area_struct *vma;
1569         struct mlx5_ib_vma_private_data *vma_private, *n;
1570         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1571         struct task_struct *owning_process  = NULL;
1572         struct mm_struct   *owning_mm       = NULL;
1573
1574         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1575         if (!owning_process)
1576                 return;
1577
1578         owning_mm = get_task_mm(owning_process);
1579         if (!owning_mm) {
1580                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1581                 while (1) {
1582                         put_task_struct(owning_process);
1583                         usleep_range(1000, 2000);
1584                         owning_process = get_pid_task(ibcontext->tgid,
1585                                                       PIDTYPE_PID);
1586                         if (!owning_process ||
1587                             owning_process->state == TASK_DEAD) {
1588                                 pr_info("disassociate ucontext done, task was terminated\n");
1589                                 /* in case task was dead need to release the
1590                                  * task struct.
1591                                  */
1592                                 if (owning_process)
1593                                         put_task_struct(owning_process);
1594                                 return;
1595                         }
1596                 }
1597         }
1598
1599         /* need to protect from a race on closing the vma as part of
1600          * mlx5_ib_vma_close.
1601          */
1602         down_write(&owning_mm->mmap_sem);
1603         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1604                                  list) {
1605                 vma = vma_private->vma;
1606                 ret = zap_vma_ptes(vma, vma->vm_start,
1607                                    PAGE_SIZE);
1608                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1609                 /* context going to be destroyed, should
1610                  * not access ops any more.
1611                  */
1612                 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1613                 vma->vm_ops = NULL;
1614                 list_del(&vma_private->list);
1615                 kfree(vma_private);
1616         }
1617         up_write(&owning_mm->mmap_sem);
1618         mmput(owning_mm);
1619         put_task_struct(owning_process);
1620 }
1621
1622 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1623 {
1624         switch (cmd) {
1625         case MLX5_IB_MMAP_WC_PAGE:
1626                 return "WC";
1627         case MLX5_IB_MMAP_REGULAR_PAGE:
1628                 return "best effort WC";
1629         case MLX5_IB_MMAP_NC_PAGE:
1630                 return "NC";
1631         default:
1632                 return NULL;
1633         }
1634 }
1635
1636 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1637                     struct vm_area_struct *vma,
1638                     struct mlx5_ib_ucontext *context)
1639 {
1640         struct mlx5_bfreg_info *bfregi = &context->bfregi;
1641         int err;
1642         unsigned long idx;
1643         phys_addr_t pfn, pa;
1644         pgprot_t prot;
1645         int uars_per_page;
1646
1647         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1648                 return -EINVAL;
1649
1650         uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1651         idx = get_index(vma->vm_pgoff);
1652         if (idx % uars_per_page ||
1653             idx * uars_per_page >= bfregi->num_sys_pages) {
1654                 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1655                 return -EINVAL;
1656         }
1657
1658         switch (cmd) {
1659         case MLX5_IB_MMAP_WC_PAGE:
1660 /* Some architectures don't support WC memory */
1661 #if defined(CONFIG_X86)
1662                 if (!pat_enabled())
1663                         return -EPERM;
1664 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1665                         return -EPERM;
1666 #endif
1667         /* fall through */
1668         case MLX5_IB_MMAP_REGULAR_PAGE:
1669                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1670                 prot = pgprot_writecombine(vma->vm_page_prot);
1671                 break;
1672         case MLX5_IB_MMAP_NC_PAGE:
1673                 prot = pgprot_noncached(vma->vm_page_prot);
1674                 break;
1675         default:
1676                 return -EINVAL;
1677         }
1678
1679         pfn = uar_index2pfn(dev, bfregi, idx);
1680         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1681
1682         vma->vm_page_prot = prot;
1683         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1684                                  PAGE_SIZE, vma->vm_page_prot);
1685         if (err) {
1686                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1687                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1688                 return -EAGAIN;
1689         }
1690
1691         pa = pfn << PAGE_SHIFT;
1692         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1693                     vma->vm_start, &pa);
1694
1695         return mlx5_ib_set_vma_data(vma, context);
1696 }
1697
1698 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1699 {
1700         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1701         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1702         unsigned long command;
1703         phys_addr_t pfn;
1704
1705         command = get_command(vma->vm_pgoff);
1706         switch (command) {
1707         case MLX5_IB_MMAP_WC_PAGE:
1708         case MLX5_IB_MMAP_NC_PAGE:
1709         case MLX5_IB_MMAP_REGULAR_PAGE:
1710                 return uar_mmap(dev, command, vma, context);
1711
1712         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1713                 return -ENOSYS;
1714
1715         case MLX5_IB_MMAP_CORE_CLOCK:
1716                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1717                         return -EINVAL;
1718
1719                 if (vma->vm_flags & VM_WRITE)
1720                         return -EPERM;
1721
1722                 /* Don't expose to user-space information it shouldn't have */
1723                 if (PAGE_SIZE > 4096)
1724                         return -EOPNOTSUPP;
1725
1726                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1727                 pfn = (dev->mdev->iseg_base +
1728                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1729                         PAGE_SHIFT;
1730                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1731                                        PAGE_SIZE, vma->vm_page_prot))
1732                         return -EAGAIN;
1733
1734                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1735                             vma->vm_start,
1736                             (unsigned long long)pfn << PAGE_SHIFT);
1737                 break;
1738
1739         default:
1740                 return -EINVAL;
1741         }
1742
1743         return 0;
1744 }
1745
1746 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1747                                       struct ib_ucontext *context,
1748                                       struct ib_udata *udata)
1749 {
1750         struct mlx5_ib_alloc_pd_resp resp;
1751         struct mlx5_ib_pd *pd;
1752         int err;
1753
1754         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1755         if (!pd)
1756                 return ERR_PTR(-ENOMEM);
1757
1758         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1759         if (err) {
1760                 kfree(pd);
1761                 return ERR_PTR(err);
1762         }
1763
1764         if (context) {
1765                 resp.pdn = pd->pdn;
1766                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1767                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1768                         kfree(pd);
1769                         return ERR_PTR(-EFAULT);
1770                 }
1771         }
1772
1773         return &pd->ibpd;
1774 }
1775
1776 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1777 {
1778         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1779         struct mlx5_ib_pd *mpd = to_mpd(pd);
1780
1781         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1782         kfree(mpd);
1783
1784         return 0;
1785 }
1786
1787 enum {
1788         MATCH_CRITERIA_ENABLE_OUTER_BIT,
1789         MATCH_CRITERIA_ENABLE_MISC_BIT,
1790         MATCH_CRITERIA_ENABLE_INNER_BIT
1791 };
1792
1793 #define HEADER_IS_ZERO(match_criteria, headers)                            \
1794         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1795                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
1796
1797 static u8 get_match_criteria_enable(u32 *match_criteria)
1798 {
1799         u8 match_criteria_enable;
1800
1801         match_criteria_enable =
1802                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1803                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1804         match_criteria_enable |=
1805                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1806                 MATCH_CRITERIA_ENABLE_MISC_BIT;
1807         match_criteria_enable |=
1808                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1809                 MATCH_CRITERIA_ENABLE_INNER_BIT;
1810
1811         return match_criteria_enable;
1812 }
1813
1814 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1815 {
1816         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1817         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1818 }
1819
1820 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1821                            bool inner)
1822 {
1823         if (inner) {
1824                 MLX5_SET(fte_match_set_misc,
1825                          misc_c, inner_ipv6_flow_label, mask);
1826                 MLX5_SET(fte_match_set_misc,
1827                          misc_v, inner_ipv6_flow_label, val);
1828         } else {
1829                 MLX5_SET(fte_match_set_misc,
1830                          misc_c, outer_ipv6_flow_label, mask);
1831                 MLX5_SET(fte_match_set_misc,
1832                          misc_v, outer_ipv6_flow_label, val);
1833         }
1834 }
1835
1836 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1837 {
1838         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1839         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1840         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1841         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1842 }
1843
1844 #define LAST_ETH_FIELD vlan_tag
1845 #define LAST_IB_FIELD sl
1846 #define LAST_IPV4_FIELD tos
1847 #define LAST_IPV6_FIELD traffic_class
1848 #define LAST_TCP_UDP_FIELD src_port
1849 #define LAST_TUNNEL_FIELD tunnel_id
1850 #define LAST_FLOW_TAG_FIELD tag_id
1851 #define LAST_DROP_FIELD size
1852
1853 /* Field is the last supported field */
1854 #define FIELDS_NOT_SUPPORTED(filter, field)\
1855         memchr_inv((void *)&filter.field  +\
1856                    sizeof(filter.field), 0,\
1857                    sizeof(filter) -\
1858                    offsetof(typeof(filter), field) -\
1859                    sizeof(filter.field))
1860
1861 #define IPV4_VERSION 4
1862 #define IPV6_VERSION 6
1863 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
1864                            u32 *match_v, const union ib_flow_spec *ib_spec,
1865                            u32 *tag_id, bool *is_drop)
1866 {
1867         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1868                                            misc_parameters);
1869         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1870                                            misc_parameters);
1871         void *headers_c;
1872         void *headers_v;
1873         int match_ipv;
1874
1875         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1876                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1877                                          inner_headers);
1878                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1879                                          inner_headers);
1880                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1881                                         ft_field_support.inner_ip_version);
1882         } else {
1883                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1884                                          outer_headers);
1885                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1886                                          outer_headers);
1887                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1888                                         ft_field_support.outer_ip_version);
1889         }
1890
1891         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
1892         case IB_FLOW_SPEC_ETH:
1893                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1894                         return -EOPNOTSUPP;
1895
1896                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1897                                              dmac_47_16),
1898                                 ib_spec->eth.mask.dst_mac);
1899                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1900                                              dmac_47_16),
1901                                 ib_spec->eth.val.dst_mac);
1902
1903                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1904                                              smac_47_16),
1905                                 ib_spec->eth.mask.src_mac);
1906                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1907                                              smac_47_16),
1908                                 ib_spec->eth.val.src_mac);
1909
1910                 if (ib_spec->eth.mask.vlan_tag) {
1911                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1912                                  cvlan_tag, 1);
1913                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1914                                  cvlan_tag, 1);
1915
1916                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1917                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1918                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1919                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1920
1921                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1922                                  first_cfi,
1923                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1924                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1925                                  first_cfi,
1926                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1927
1928                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1929                                  first_prio,
1930                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1931                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1932                                  first_prio,
1933                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1934                 }
1935                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1936                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1937                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1938                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1939                 break;
1940         case IB_FLOW_SPEC_IPV4:
1941                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1942                         return -EOPNOTSUPP;
1943
1944                 if (match_ipv) {
1945                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1946                                  ip_version, 0xf);
1947                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1948                                  ip_version, IPV4_VERSION);
1949                 } else {
1950                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1951                                  ethertype, 0xffff);
1952                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1953                                  ethertype, ETH_P_IP);
1954                 }
1955
1956                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1957                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1958                        &ib_spec->ipv4.mask.src_ip,
1959                        sizeof(ib_spec->ipv4.mask.src_ip));
1960                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1961                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1962                        &ib_spec->ipv4.val.src_ip,
1963                        sizeof(ib_spec->ipv4.val.src_ip));
1964                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1965                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1966                        &ib_spec->ipv4.mask.dst_ip,
1967                        sizeof(ib_spec->ipv4.mask.dst_ip));
1968                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1969                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1970                        &ib_spec->ipv4.val.dst_ip,
1971                        sizeof(ib_spec->ipv4.val.dst_ip));
1972
1973                 set_tos(headers_c, headers_v,
1974                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1975
1976                 set_proto(headers_c, headers_v,
1977                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1978                 break;
1979         case IB_FLOW_SPEC_IPV6:
1980                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1981                         return -EOPNOTSUPP;
1982
1983                 if (match_ipv) {
1984                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1985                                  ip_version, 0xf);
1986                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1987                                  ip_version, IPV6_VERSION);
1988                 } else {
1989                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1990                                  ethertype, 0xffff);
1991                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1992                                  ethertype, ETH_P_IPV6);
1993                 }
1994
1995                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1996                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1997                        &ib_spec->ipv6.mask.src_ip,
1998                        sizeof(ib_spec->ipv6.mask.src_ip));
1999                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2000                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2001                        &ib_spec->ipv6.val.src_ip,
2002                        sizeof(ib_spec->ipv6.val.src_ip));
2003                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2004                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2005                        &ib_spec->ipv6.mask.dst_ip,
2006                        sizeof(ib_spec->ipv6.mask.dst_ip));
2007                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2008                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2009                        &ib_spec->ipv6.val.dst_ip,
2010                        sizeof(ib_spec->ipv6.val.dst_ip));
2011
2012                 set_tos(headers_c, headers_v,
2013                         ib_spec->ipv6.mask.traffic_class,
2014                         ib_spec->ipv6.val.traffic_class);
2015
2016                 set_proto(headers_c, headers_v,
2017                           ib_spec->ipv6.mask.next_hdr,
2018                           ib_spec->ipv6.val.next_hdr);
2019
2020                 set_flow_label(misc_params_c, misc_params_v,
2021                                ntohl(ib_spec->ipv6.mask.flow_label),
2022                                ntohl(ib_spec->ipv6.val.flow_label),
2023                                ib_spec->type & IB_FLOW_SPEC_INNER);
2024
2025                 break;
2026         case IB_FLOW_SPEC_TCP:
2027                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2028                                          LAST_TCP_UDP_FIELD))
2029                         return -EOPNOTSUPP;
2030
2031                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2032                          0xff);
2033                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2034                          IPPROTO_TCP);
2035
2036                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2037                          ntohs(ib_spec->tcp_udp.mask.src_port));
2038                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2039                          ntohs(ib_spec->tcp_udp.val.src_port));
2040
2041                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2042                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2043                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2044                          ntohs(ib_spec->tcp_udp.val.dst_port));
2045                 break;
2046         case IB_FLOW_SPEC_UDP:
2047                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2048                                          LAST_TCP_UDP_FIELD))
2049                         return -EOPNOTSUPP;
2050
2051                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2052                          0xff);
2053                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2054                          IPPROTO_UDP);
2055
2056                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2057                          ntohs(ib_spec->tcp_udp.mask.src_port));
2058                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2059                          ntohs(ib_spec->tcp_udp.val.src_port));
2060
2061                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2062                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2063                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2064                          ntohs(ib_spec->tcp_udp.val.dst_port));
2065                 break;
2066         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2067                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2068                                          LAST_TUNNEL_FIELD))
2069                         return -EOPNOTSUPP;
2070
2071                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2072                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2073                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2074                          ntohl(ib_spec->tunnel.val.tunnel_id));
2075                 break;
2076         case IB_FLOW_SPEC_ACTION_TAG:
2077                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2078                                          LAST_FLOW_TAG_FIELD))
2079                         return -EOPNOTSUPP;
2080                 if (ib_spec->flow_tag.tag_id >= BIT(24))
2081                         return -EINVAL;
2082
2083                 *tag_id = ib_spec->flow_tag.tag_id;
2084                 break;
2085         case IB_FLOW_SPEC_ACTION_DROP:
2086                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2087                                          LAST_DROP_FIELD))
2088                         return -EOPNOTSUPP;
2089                 *is_drop = true;
2090                 break;
2091         default:
2092                 return -EINVAL;
2093         }
2094
2095         return 0;
2096 }
2097
2098 /* If a flow could catch both multicast and unicast packets,
2099  * it won't fall into the multicast flow steering table and this rule
2100  * could steal other multicast packets.
2101  */
2102 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
2103 {
2104         struct ib_flow_spec_eth *eth_spec;
2105
2106         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2107             ib_attr->size < sizeof(struct ib_flow_attr) +
2108             sizeof(struct ib_flow_spec_eth) ||
2109             ib_attr->num_of_specs < 1)
2110                 return false;
2111
2112         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
2113         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
2114             eth_spec->size != sizeof(*eth_spec))
2115                 return false;
2116
2117         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2118                is_multicast_ether_addr(eth_spec->val.dst_mac);
2119 }
2120
2121 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2122                                const struct ib_flow_attr *flow_attr,
2123                                bool check_inner)
2124 {
2125         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2126         int match_ipv = check_inner ?
2127                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2128                                         ft_field_support.inner_ip_version) :
2129                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2130                                         ft_field_support.outer_ip_version);
2131         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2132         bool ipv4_spec_valid, ipv6_spec_valid;
2133         unsigned int ip_spec_type = 0;
2134         bool has_ethertype = false;
2135         unsigned int spec_index;
2136         bool mask_valid = true;
2137         u16 eth_type = 0;
2138         bool type_valid;
2139
2140         /* Validate that ethertype is correct */
2141         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2142                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2143                     ib_spec->eth.mask.ether_type) {
2144                         mask_valid = (ib_spec->eth.mask.ether_type ==
2145                                       htons(0xffff));
2146                         has_ethertype = true;
2147                         eth_type = ntohs(ib_spec->eth.val.ether_type);
2148                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2149                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2150                         ip_spec_type = ib_spec->type;
2151                 }
2152                 ib_spec = (void *)ib_spec + ib_spec->size;
2153         }
2154
2155         type_valid = (!has_ethertype) || (!ip_spec_type);
2156         if (!type_valid && mask_valid) {
2157                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2158                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2159                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2160                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2161
2162                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2163                              (((eth_type == ETH_P_MPLS_UC) ||
2164                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2165         }
2166
2167         return type_valid;
2168 }
2169
2170 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2171                           const struct ib_flow_attr *flow_attr)
2172 {
2173         return is_valid_ethertype(mdev, flow_attr, false) &&
2174                is_valid_ethertype(mdev, flow_attr, true);
2175 }
2176
2177 static void put_flow_table(struct mlx5_ib_dev *dev,
2178                            struct mlx5_ib_flow_prio *prio, bool ft_added)
2179 {
2180         prio->refcount -= !!ft_added;
2181         if (!prio->refcount) {
2182                 mlx5_destroy_flow_table(prio->flow_table);
2183                 prio->flow_table = NULL;
2184         }
2185 }
2186
2187 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2188 {
2189         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2190         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2191                                                           struct mlx5_ib_flow_handler,
2192                                                           ibflow);
2193         struct mlx5_ib_flow_handler *iter, *tmp;
2194
2195         mutex_lock(&dev->flow_db.lock);
2196
2197         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2198                 mlx5_del_flow_rules(iter->rule);
2199                 put_flow_table(dev, iter->prio, true);
2200                 list_del(&iter->list);
2201                 kfree(iter);
2202         }
2203
2204         mlx5_del_flow_rules(handler->rule);
2205         put_flow_table(dev, handler->prio, true);
2206         mutex_unlock(&dev->flow_db.lock);
2207
2208         kfree(handler);
2209
2210         return 0;
2211 }
2212
2213 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2214 {
2215         priority *= 2;
2216         if (!dont_trap)
2217                 priority++;
2218         return priority;
2219 }
2220
2221 enum flow_table_type {
2222         MLX5_IB_FT_RX,
2223         MLX5_IB_FT_TX
2224 };
2225
2226 #define MLX5_FS_MAX_TYPES        6
2227 #define MLX5_FS_MAX_ENTRIES      BIT(16)
2228 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2229                                                 struct ib_flow_attr *flow_attr,
2230                                                 enum flow_table_type ft_type)
2231 {
2232         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2233         struct mlx5_flow_namespace *ns = NULL;
2234         struct mlx5_ib_flow_prio *prio;
2235         struct mlx5_flow_table *ft;
2236         int max_table_size;
2237         int num_entries;
2238         int num_groups;
2239         int priority;
2240         int err = 0;
2241
2242         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2243                                                        log_max_ft_size));
2244         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2245                 if (flow_is_multicast_only(flow_attr) &&
2246                     !dont_trap)
2247                         priority = MLX5_IB_FLOW_MCAST_PRIO;
2248                 else
2249                         priority = ib_prio_to_core_prio(flow_attr->priority,
2250                                                         dont_trap);
2251                 ns = mlx5_get_flow_namespace(dev->mdev,
2252                                              MLX5_FLOW_NAMESPACE_BYPASS);
2253                 num_entries = MLX5_FS_MAX_ENTRIES;
2254                 num_groups = MLX5_FS_MAX_TYPES;
2255                 prio = &dev->flow_db.prios[priority];
2256         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2257                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2258                 ns = mlx5_get_flow_namespace(dev->mdev,
2259                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
2260                 build_leftovers_ft_param(&priority,
2261                                          &num_entries,
2262                                          &num_groups);
2263                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2264         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2265                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2266                                         allow_sniffer_and_nic_rx_shared_tir))
2267                         return ERR_PTR(-ENOTSUPP);
2268
2269                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2270                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2271                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2272
2273                 prio = &dev->flow_db.sniffer[ft_type];
2274                 priority = 0;
2275                 num_entries = 1;
2276                 num_groups = 1;
2277         }
2278
2279         if (!ns)
2280                 return ERR_PTR(-ENOTSUPP);
2281
2282         if (num_entries > max_table_size)
2283                 return ERR_PTR(-ENOMEM);
2284
2285         ft = prio->flow_table;
2286         if (!ft) {
2287                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2288                                                          num_entries,
2289                                                          num_groups,
2290                                                          0, 0);
2291
2292                 if (!IS_ERR(ft)) {
2293                         prio->refcount = 0;
2294                         prio->flow_table = ft;
2295                 } else {
2296                         err = PTR_ERR(ft);
2297                 }
2298         }
2299
2300         return err ? ERR_PTR(err) : prio;
2301 }
2302
2303 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2304                                                      struct mlx5_ib_flow_prio *ft_prio,
2305                                                      const struct ib_flow_attr *flow_attr,
2306                                                      struct mlx5_flow_destination *dst)
2307 {
2308         struct mlx5_flow_table  *ft = ft_prio->flow_table;
2309         struct mlx5_ib_flow_handler *handler;
2310         struct mlx5_flow_act flow_act = {0};
2311         struct mlx5_flow_spec *spec;
2312         struct mlx5_flow_destination *rule_dst = dst;
2313         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2314         unsigned int spec_index;
2315         u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2316         bool is_drop = false;
2317         int err = 0;
2318         int dest_num = 1;
2319
2320         if (!is_valid_attr(dev->mdev, flow_attr))
2321                 return ERR_PTR(-EINVAL);
2322
2323         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2324         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2325         if (!handler || !spec) {
2326                 err = -ENOMEM;
2327                 goto free;
2328         }
2329
2330         INIT_LIST_HEAD(&handler->list);
2331
2332         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2333                 err = parse_flow_attr(dev->mdev, spec->match_criteria,
2334                                       spec->match_value,
2335                                       ib_flow, &flow_tag, &is_drop);
2336                 if (err < 0)
2337                         goto free;
2338
2339                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2340         }
2341
2342         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2343         if (is_drop) {
2344                 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2345                 rule_dst = NULL;
2346                 dest_num = 0;
2347         } else {
2348                 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2349                     MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2350         }
2351
2352         if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2353             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2354              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2355                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2356                              flow_tag, flow_attr->type);
2357                 err = -EINVAL;
2358                 goto free;
2359         }
2360         flow_act.flow_tag = flow_tag;
2361         handler->rule = mlx5_add_flow_rules(ft, spec,
2362                                             &flow_act,
2363                                             rule_dst, dest_num);
2364
2365         if (IS_ERR(handler->rule)) {
2366                 err = PTR_ERR(handler->rule);
2367                 goto free;
2368         }
2369
2370         ft_prio->refcount++;
2371         handler->prio = ft_prio;
2372
2373         ft_prio->flow_table = ft;
2374 free:
2375         if (err)
2376                 kfree(handler);
2377         kvfree(spec);
2378         return err ? ERR_PTR(err) : handler;
2379 }
2380
2381 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2382                                                           struct mlx5_ib_flow_prio *ft_prio,
2383                                                           struct ib_flow_attr *flow_attr,
2384                                                           struct mlx5_flow_destination *dst)
2385 {
2386         struct mlx5_ib_flow_handler *handler_dst = NULL;
2387         struct mlx5_ib_flow_handler *handler = NULL;
2388
2389         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2390         if (!IS_ERR(handler)) {
2391                 handler_dst = create_flow_rule(dev, ft_prio,
2392                                                flow_attr, dst);
2393                 if (IS_ERR(handler_dst)) {
2394                         mlx5_del_flow_rules(handler->rule);
2395                         ft_prio->refcount--;
2396                         kfree(handler);
2397                         handler = handler_dst;
2398                 } else {
2399                         list_add(&handler_dst->list, &handler->list);
2400                 }
2401         }
2402
2403         return handler;
2404 }
2405 enum {
2406         LEFTOVERS_MC,
2407         LEFTOVERS_UC,
2408 };
2409
2410 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2411                                                           struct mlx5_ib_flow_prio *ft_prio,
2412                                                           struct ib_flow_attr *flow_attr,
2413                                                           struct mlx5_flow_destination *dst)
2414 {
2415         struct mlx5_ib_flow_handler *handler_ucast = NULL;
2416         struct mlx5_ib_flow_handler *handler = NULL;
2417
2418         static struct {
2419                 struct ib_flow_attr     flow_attr;
2420                 struct ib_flow_spec_eth eth_flow;
2421         } leftovers_specs[] = {
2422                 [LEFTOVERS_MC] = {
2423                         .flow_attr = {
2424                                 .num_of_specs = 1,
2425                                 .size = sizeof(leftovers_specs[0])
2426                         },
2427                         .eth_flow = {
2428                                 .type = IB_FLOW_SPEC_ETH,
2429                                 .size = sizeof(struct ib_flow_spec_eth),
2430                                 .mask = {.dst_mac = {0x1} },
2431                                 .val =  {.dst_mac = {0x1} }
2432                         }
2433                 },
2434                 [LEFTOVERS_UC] = {
2435                         .flow_attr = {
2436                                 .num_of_specs = 1,
2437                                 .size = sizeof(leftovers_specs[0])
2438                         },
2439                         .eth_flow = {
2440                                 .type = IB_FLOW_SPEC_ETH,
2441                                 .size = sizeof(struct ib_flow_spec_eth),
2442                                 .mask = {.dst_mac = {0x1} },
2443                                 .val = {.dst_mac = {} }
2444                         }
2445                 }
2446         };
2447
2448         handler = create_flow_rule(dev, ft_prio,
2449                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
2450                                    dst);
2451         if (!IS_ERR(handler) &&
2452             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2453                 handler_ucast = create_flow_rule(dev, ft_prio,
2454                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
2455                                                  dst);
2456                 if (IS_ERR(handler_ucast)) {
2457                         mlx5_del_flow_rules(handler->rule);
2458                         ft_prio->refcount--;
2459                         kfree(handler);
2460                         handler = handler_ucast;
2461                 } else {
2462                         list_add(&handler_ucast->list, &handler->list);
2463                 }
2464         }
2465
2466         return handler;
2467 }
2468
2469 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2470                                                         struct mlx5_ib_flow_prio *ft_rx,
2471                                                         struct mlx5_ib_flow_prio *ft_tx,
2472                                                         struct mlx5_flow_destination *dst)
2473 {
2474         struct mlx5_ib_flow_handler *handler_rx;
2475         struct mlx5_ib_flow_handler *handler_tx;
2476         int err;
2477         static const struct ib_flow_attr flow_attr  = {
2478                 .num_of_specs = 0,
2479                 .size = sizeof(flow_attr)
2480         };
2481
2482         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2483         if (IS_ERR(handler_rx)) {
2484                 err = PTR_ERR(handler_rx);
2485                 goto err;
2486         }
2487
2488         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2489         if (IS_ERR(handler_tx)) {
2490                 err = PTR_ERR(handler_tx);
2491                 goto err_tx;
2492         }
2493
2494         list_add(&handler_tx->list, &handler_rx->list);
2495
2496         return handler_rx;
2497
2498 err_tx:
2499         mlx5_del_flow_rules(handler_rx->rule);
2500         ft_rx->refcount--;
2501         kfree(handler_rx);
2502 err:
2503         return ERR_PTR(err);
2504 }
2505
2506 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2507                                            struct ib_flow_attr *flow_attr,
2508                                            int domain)
2509 {
2510         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2511         struct mlx5_ib_qp *mqp = to_mqp(qp);
2512         struct mlx5_ib_flow_handler *handler = NULL;
2513         struct mlx5_flow_destination *dst = NULL;
2514         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2515         struct mlx5_ib_flow_prio *ft_prio;
2516         int err;
2517
2518         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2519                 return ERR_PTR(-ENOMEM);
2520
2521         if (domain != IB_FLOW_DOMAIN_USER ||
2522             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2523             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2524                 return ERR_PTR(-EINVAL);
2525
2526         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2527         if (!dst)
2528                 return ERR_PTR(-ENOMEM);
2529
2530         mutex_lock(&dev->flow_db.lock);
2531
2532         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2533         if (IS_ERR(ft_prio)) {
2534                 err = PTR_ERR(ft_prio);
2535                 goto unlock;
2536         }
2537         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2538                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2539                 if (IS_ERR(ft_prio_tx)) {
2540                         err = PTR_ERR(ft_prio_tx);
2541                         ft_prio_tx = NULL;
2542                         goto destroy_ft;
2543                 }
2544         }
2545
2546         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2547         if (mqp->flags & MLX5_IB_QP_RSS)
2548                 dst->tir_num = mqp->rss_qp.tirn;
2549         else
2550                 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2551
2552         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2553                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
2554                         handler = create_dont_trap_rule(dev, ft_prio,
2555                                                         flow_attr, dst);
2556                 } else {
2557                         handler = create_flow_rule(dev, ft_prio, flow_attr,
2558                                                    dst);
2559                 }
2560         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2561                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2562                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2563                                                 dst);
2564         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2565                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2566         } else {
2567                 err = -EINVAL;
2568                 goto destroy_ft;
2569         }
2570
2571         if (IS_ERR(handler)) {
2572                 err = PTR_ERR(handler);
2573                 handler = NULL;
2574                 goto destroy_ft;
2575         }
2576
2577         mutex_unlock(&dev->flow_db.lock);
2578         kfree(dst);
2579
2580         return &handler->ibflow;
2581
2582 destroy_ft:
2583         put_flow_table(dev, ft_prio, false);
2584         if (ft_prio_tx)
2585                 put_flow_table(dev, ft_prio_tx, false);
2586 unlock:
2587         mutex_unlock(&dev->flow_db.lock);
2588         kfree(dst);
2589         kfree(handler);
2590         return ERR_PTR(err);
2591 }
2592
2593 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2594 {
2595         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2596         int err;
2597
2598         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2599         if (err)
2600                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2601                              ibqp->qp_num, gid->raw);
2602
2603         return err;
2604 }
2605
2606 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2607 {
2608         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2609         int err;
2610
2611         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2612         if (err)
2613                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2614                              ibqp->qp_num, gid->raw);
2615
2616         return err;
2617 }
2618
2619 static int init_node_data(struct mlx5_ib_dev *dev)
2620 {
2621         int err;
2622
2623         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2624         if (err)
2625                 return err;
2626
2627         dev->mdev->rev_id = dev->mdev->pdev->revision;
2628
2629         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2630 }
2631
2632 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2633                              char *buf)
2634 {
2635         struct mlx5_ib_dev *dev =
2636                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2637
2638         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2639 }
2640
2641 static ssize_t show_reg_pages(struct device *device,
2642                               struct device_attribute *attr, char *buf)
2643 {
2644         struct mlx5_ib_dev *dev =
2645                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2646
2647         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2648 }
2649
2650 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2651                         char *buf)
2652 {
2653         struct mlx5_ib_dev *dev =
2654                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2655         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2656 }
2657
2658 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2659                         char *buf)
2660 {
2661         struct mlx5_ib_dev *dev =
2662                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2663         return sprintf(buf, "%x\n", dev->mdev->rev_id);
2664 }
2665
2666 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2667                           char *buf)
2668 {
2669         struct mlx5_ib_dev *dev =
2670                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2671         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2672                        dev->mdev->board_id);
2673 }
2674
2675 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
2676 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
2677 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
2678 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2679 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2680
2681 static struct device_attribute *mlx5_class_attributes[] = {
2682         &dev_attr_hw_rev,
2683         &dev_attr_hca_type,
2684         &dev_attr_board_id,
2685         &dev_attr_fw_pages,
2686         &dev_attr_reg_pages,
2687 };
2688
2689 static void pkey_change_handler(struct work_struct *work)
2690 {
2691         struct mlx5_ib_port_resources *ports =
2692                 container_of(work, struct mlx5_ib_port_resources,
2693                              pkey_change_work);
2694
2695         mutex_lock(&ports->devr->mutex);
2696         mlx5_ib_gsi_pkey_change(ports->gsi);
2697         mutex_unlock(&ports->devr->mutex);
2698 }
2699
2700 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2701 {
2702         struct mlx5_ib_qp *mqp;
2703         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2704         struct mlx5_core_cq *mcq;
2705         struct list_head cq_armed_list;
2706         unsigned long flags_qp;
2707         unsigned long flags_cq;
2708         unsigned long flags;
2709
2710         INIT_LIST_HEAD(&cq_armed_list);
2711
2712         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2713         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2714         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2715                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2716                 if (mqp->sq.tail != mqp->sq.head) {
2717                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2718                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2719                         if (send_mcq->mcq.comp &&
2720                             mqp->ibqp.send_cq->comp_handler) {
2721                                 if (!send_mcq->mcq.reset_notify_added) {
2722                                         send_mcq->mcq.reset_notify_added = 1;
2723                                         list_add_tail(&send_mcq->mcq.reset_notify,
2724                                                       &cq_armed_list);
2725                                 }
2726                         }
2727                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2728                 }
2729                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2730                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2731                 /* no handling is needed for SRQ */
2732                 if (!mqp->ibqp.srq) {
2733                         if (mqp->rq.tail != mqp->rq.head) {
2734                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2735                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2736                                 if (recv_mcq->mcq.comp &&
2737                                     mqp->ibqp.recv_cq->comp_handler) {
2738                                         if (!recv_mcq->mcq.reset_notify_added) {
2739                                                 recv_mcq->mcq.reset_notify_added = 1;
2740                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2741                                                               &cq_armed_list);
2742                                         }
2743                                 }
2744                                 spin_unlock_irqrestore(&recv_mcq->lock,
2745                                                        flags_cq);
2746                         }
2747                 }
2748                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2749         }
2750         /*At that point all inflight post send were put to be executed as of we
2751          * lock/unlock above locks Now need to arm all involved CQs.
2752          */
2753         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2754                 mcq->comp(mcq);
2755         }
2756         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2757 }
2758
2759 static void delay_drop_handler(struct work_struct *work)
2760 {
2761         int err;
2762         struct mlx5_ib_delay_drop *delay_drop =
2763                 container_of(work, struct mlx5_ib_delay_drop,
2764                              delay_drop_work);
2765
2766         mutex_lock(&delay_drop->lock);
2767         err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
2768                                        delay_drop->timeout);
2769         if (err) {
2770                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2771                              delay_drop->timeout);
2772                 delay_drop->activate = false;
2773         }
2774         mutex_unlock(&delay_drop->lock);
2775 }
2776
2777 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2778                           enum mlx5_dev_event event, unsigned long param)
2779 {
2780         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2781         struct ib_event ibev;
2782         bool fatal = false;
2783         u8 port = 0;
2784
2785         switch (event) {
2786         case MLX5_DEV_EVENT_SYS_ERROR:
2787                 ibev.event = IB_EVENT_DEVICE_FATAL;
2788                 mlx5_ib_handle_internal_error(ibdev);
2789                 fatal = true;
2790                 break;
2791
2792         case MLX5_DEV_EVENT_PORT_UP:
2793         case MLX5_DEV_EVENT_PORT_DOWN:
2794         case MLX5_DEV_EVENT_PORT_INITIALIZED:
2795                 port = (u8)param;
2796
2797                 /* In RoCE, port up/down events are handled in
2798                  * mlx5_netdev_event().
2799                  */
2800                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2801                         IB_LINK_LAYER_ETHERNET)
2802                         return;
2803
2804                 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2805                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2806                 break;
2807
2808         case MLX5_DEV_EVENT_LID_CHANGE:
2809                 ibev.event = IB_EVENT_LID_CHANGE;
2810                 port = (u8)param;
2811                 break;
2812
2813         case MLX5_DEV_EVENT_PKEY_CHANGE:
2814                 ibev.event = IB_EVENT_PKEY_CHANGE;
2815                 port = (u8)param;
2816
2817                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2818                 break;
2819
2820         case MLX5_DEV_EVENT_GUID_CHANGE:
2821                 ibev.event = IB_EVENT_GID_CHANGE;
2822                 port = (u8)param;
2823                 break;
2824
2825         case MLX5_DEV_EVENT_CLIENT_REREG:
2826                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2827                 port = (u8)param;
2828                 break;
2829         case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
2830                 schedule_work(&ibdev->delay_drop.delay_drop_work);
2831                 goto out;
2832         default:
2833                 goto out;
2834         }
2835
2836         ibev.device           = &ibdev->ib_dev;
2837         ibev.element.port_num = port;
2838
2839         if (port < 1 || port > ibdev->num_ports) {
2840                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2841                 goto out;
2842         }
2843
2844         if (ibdev->ib_active)
2845                 ib_dispatch_event(&ibev);
2846
2847         if (fatal)
2848                 ibdev->ib_active = false;
2849
2850 out:
2851         return;
2852 }
2853
2854 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2855 {
2856         struct mlx5_hca_vport_context vport_ctx;
2857         int err;
2858         int port;
2859
2860         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2861                 dev->mdev->port_caps[port - 1].has_smi = false;
2862                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2863                     MLX5_CAP_PORT_TYPE_IB) {
2864                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2865                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2866                                                                    port, 0,
2867                                                                    &vport_ctx);
2868                                 if (err) {
2869                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2870                                                     port, err);
2871                                         return err;
2872                                 }
2873                                 dev->mdev->port_caps[port - 1].has_smi =
2874                                         vport_ctx.has_smi;
2875                         } else {
2876                                 dev->mdev->port_caps[port - 1].has_smi = true;
2877                         }
2878                 }
2879         }
2880         return 0;
2881 }
2882
2883 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2884 {
2885         int port;
2886
2887         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2888                 mlx5_query_ext_port_caps(dev, port);
2889 }
2890
2891 static int get_port_caps(struct mlx5_ib_dev *dev)
2892 {
2893         struct ib_device_attr *dprops = NULL;
2894         struct ib_port_attr *pprops = NULL;
2895         int err = -ENOMEM;
2896         int port;
2897         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2898
2899         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2900         if (!pprops)
2901                 goto out;
2902
2903         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2904         if (!dprops)
2905                 goto out;
2906
2907         err = set_has_smi_cap(dev);
2908         if (err)
2909                 goto out;
2910
2911         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2912         if (err) {
2913                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2914                 goto out;
2915         }
2916
2917         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2918                 memset(pprops, 0, sizeof(*pprops));
2919                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2920                 if (err) {
2921                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
2922                                      port, err);
2923                         break;
2924                 }
2925                 dev->mdev->port_caps[port - 1].pkey_table_len =
2926                                                 dprops->max_pkeys;
2927                 dev->mdev->port_caps[port - 1].gid_table_len =
2928                                                 pprops->gid_tbl_len;
2929                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2930                             dprops->max_pkeys, pprops->gid_tbl_len);
2931         }
2932
2933 out:
2934         kfree(pprops);
2935         kfree(dprops);
2936
2937         return err;
2938 }
2939
2940 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2941 {
2942         int err;
2943
2944         err = mlx5_mr_cache_cleanup(dev);
2945         if (err)
2946                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2947
2948         mlx5_ib_destroy_qp(dev->umrc.qp);
2949         ib_free_cq(dev->umrc.cq);
2950         ib_dealloc_pd(dev->umrc.pd);
2951 }
2952
2953 enum {
2954         MAX_UMR_WR = 128,
2955 };
2956
2957 static int create_umr_res(struct mlx5_ib_dev *dev)
2958 {
2959         struct ib_qp_init_attr *init_attr = NULL;
2960         struct ib_qp_attr *attr = NULL;
2961         struct ib_pd *pd;
2962         struct ib_cq *cq;
2963         struct ib_qp *qp;
2964         int ret;
2965
2966         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2967         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2968         if (!attr || !init_attr) {
2969                 ret = -ENOMEM;
2970                 goto error_0;
2971         }
2972
2973         pd = ib_alloc_pd(&dev->ib_dev, 0);
2974         if (IS_ERR(pd)) {
2975                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2976                 ret = PTR_ERR(pd);
2977                 goto error_0;
2978         }
2979
2980         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2981         if (IS_ERR(cq)) {
2982                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2983                 ret = PTR_ERR(cq);
2984                 goto error_2;
2985         }
2986
2987         init_attr->send_cq = cq;
2988         init_attr->recv_cq = cq;
2989         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2990         init_attr->cap.max_send_wr = MAX_UMR_WR;
2991         init_attr->cap.max_send_sge = 1;
2992         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2993         init_attr->port_num = 1;
2994         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2995         if (IS_ERR(qp)) {
2996                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2997                 ret = PTR_ERR(qp);
2998                 goto error_3;
2999         }
3000         qp->device     = &dev->ib_dev;
3001         qp->real_qp    = qp;
3002         qp->uobject    = NULL;
3003         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
3004
3005         attr->qp_state = IB_QPS_INIT;
3006         attr->port_num = 1;
3007         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3008                                 IB_QP_PORT, NULL);
3009         if (ret) {
3010                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3011                 goto error_4;
3012         }
3013
3014         memset(attr, 0, sizeof(*attr));
3015         attr->qp_state = IB_QPS_RTR;
3016         attr->path_mtu = IB_MTU_256;
3017
3018         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3019         if (ret) {
3020                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3021                 goto error_4;
3022         }
3023
3024         memset(attr, 0, sizeof(*attr));
3025         attr->qp_state = IB_QPS_RTS;
3026         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3027         if (ret) {
3028                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3029                 goto error_4;
3030         }
3031
3032         dev->umrc.qp = qp;
3033         dev->umrc.cq = cq;
3034         dev->umrc.pd = pd;
3035
3036         sema_init(&dev->umrc.sem, MAX_UMR_WR);
3037         ret = mlx5_mr_cache_init(dev);
3038         if (ret) {
3039                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3040                 goto error_4;
3041         }
3042
3043         kfree(attr);
3044         kfree(init_attr);
3045
3046         return 0;
3047
3048 error_4:
3049         mlx5_ib_destroy_qp(qp);
3050
3051 error_3:
3052         ib_free_cq(cq);
3053
3054 error_2:
3055         ib_dealloc_pd(pd);
3056
3057 error_0:
3058         kfree(attr);
3059         kfree(init_attr);
3060         return ret;
3061 }
3062
3063 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3064 {
3065         switch (umr_fence_cap) {
3066         case MLX5_CAP_UMR_FENCE_NONE:
3067                 return MLX5_FENCE_MODE_NONE;
3068         case MLX5_CAP_UMR_FENCE_SMALL:
3069                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3070         default:
3071                 return MLX5_FENCE_MODE_STRONG_ORDERING;
3072         }
3073 }
3074
3075 static int create_dev_resources(struct mlx5_ib_resources *devr)
3076 {
3077         struct ib_srq_init_attr attr;
3078         struct mlx5_ib_dev *dev;
3079         struct ib_cq_init_attr cq_attr = {.cqe = 1};
3080         int port;
3081         int ret = 0;
3082
3083         dev = container_of(devr, struct mlx5_ib_dev, devr);
3084
3085         mutex_init(&devr->mutex);
3086
3087         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3088         if (IS_ERR(devr->p0)) {
3089                 ret = PTR_ERR(devr->p0);
3090                 goto error0;
3091         }
3092         devr->p0->device  = &dev->ib_dev;
3093         devr->p0->uobject = NULL;
3094         atomic_set(&devr->p0->usecnt, 0);
3095
3096         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
3097         if (IS_ERR(devr->c0)) {
3098                 ret = PTR_ERR(devr->c0);
3099                 goto error1;
3100         }
3101         devr->c0->device        = &dev->ib_dev;
3102         devr->c0->uobject       = NULL;
3103         devr->c0->comp_handler  = NULL;
3104         devr->c0->event_handler = NULL;
3105         devr->c0->cq_context    = NULL;
3106         atomic_set(&devr->c0->usecnt, 0);
3107
3108         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3109         if (IS_ERR(devr->x0)) {
3110                 ret = PTR_ERR(devr->x0);
3111                 goto error2;
3112         }
3113         devr->x0->device = &dev->ib_dev;
3114         devr->x0->inode = NULL;
3115         atomic_set(&devr->x0->usecnt, 0);
3116         mutex_init(&devr->x0->tgt_qp_mutex);
3117         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3118
3119         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3120         if (IS_ERR(devr->x1)) {
3121                 ret = PTR_ERR(devr->x1);
3122                 goto error3;
3123         }
3124         devr->x1->device = &dev->ib_dev;
3125         devr->x1->inode = NULL;
3126         atomic_set(&devr->x1->usecnt, 0);
3127         mutex_init(&devr->x1->tgt_qp_mutex);
3128         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3129
3130         memset(&attr, 0, sizeof(attr));
3131         attr.attr.max_sge = 1;
3132         attr.attr.max_wr = 1;
3133         attr.srq_type = IB_SRQT_XRC;
3134         attr.ext.xrc.cq = devr->c0;
3135         attr.ext.xrc.xrcd = devr->x0;
3136
3137         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3138         if (IS_ERR(devr->s0)) {
3139                 ret = PTR_ERR(devr->s0);
3140                 goto error4;
3141         }
3142         devr->s0->device        = &dev->ib_dev;
3143         devr->s0->pd            = devr->p0;
3144         devr->s0->uobject       = NULL;
3145         devr->s0->event_handler = NULL;
3146         devr->s0->srq_context   = NULL;
3147         devr->s0->srq_type      = IB_SRQT_XRC;
3148         devr->s0->ext.xrc.xrcd  = devr->x0;
3149         devr->s0->ext.xrc.cq    = devr->c0;
3150         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3151         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
3152         atomic_inc(&devr->p0->usecnt);
3153         atomic_set(&devr->s0->usecnt, 0);
3154
3155         memset(&attr, 0, sizeof(attr));
3156         attr.attr.max_sge = 1;
3157         attr.attr.max_wr = 1;
3158         attr.srq_type = IB_SRQT_BASIC;
3159         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3160         if (IS_ERR(devr->s1)) {
3161                 ret = PTR_ERR(devr->s1);
3162                 goto error5;
3163         }
3164         devr->s1->device        = &dev->ib_dev;
3165         devr->s1->pd            = devr->p0;
3166         devr->s1->uobject       = NULL;
3167         devr->s1->event_handler = NULL;
3168         devr->s1->srq_context   = NULL;
3169         devr->s1->srq_type      = IB_SRQT_BASIC;
3170         devr->s1->ext.xrc.cq    = devr->c0;
3171         atomic_inc(&devr->p0->usecnt);
3172         atomic_set(&devr->s0->usecnt, 0);
3173
3174         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3175                 INIT_WORK(&devr->ports[port].pkey_change_work,
3176                           pkey_change_handler);
3177                 devr->ports[port].devr = devr;
3178         }
3179
3180         return 0;
3181
3182 error5:
3183         mlx5_ib_destroy_srq(devr->s0);
3184 error4:
3185         mlx5_ib_dealloc_xrcd(devr->x1);
3186 error3:
3187         mlx5_ib_dealloc_xrcd(devr->x0);
3188 error2:
3189         mlx5_ib_destroy_cq(devr->c0);
3190 error1:
3191         mlx5_ib_dealloc_pd(devr->p0);
3192 error0:
3193         return ret;
3194 }
3195
3196 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3197 {
3198         struct mlx5_ib_dev *dev =
3199                 container_of(devr, struct mlx5_ib_dev, devr);
3200         int port;
3201
3202         mlx5_ib_destroy_srq(devr->s1);
3203         mlx5_ib_destroy_srq(devr->s0);
3204         mlx5_ib_dealloc_xrcd(devr->x0);
3205         mlx5_ib_dealloc_xrcd(devr->x1);
3206         mlx5_ib_destroy_cq(devr->c0);
3207         mlx5_ib_dealloc_pd(devr->p0);
3208
3209         /* Make sure no change P_Key work items are still executing */
3210         for (port = 0; port < dev->num_ports; ++port)
3211                 cancel_work_sync(&devr->ports[port].pkey_change_work);
3212 }
3213
3214 static u32 get_core_cap_flags(struct ib_device *ibdev)
3215 {
3216         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3217         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3218         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3219         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3220         u32 ret = 0;
3221
3222         if (ll == IB_LINK_LAYER_INFINIBAND)
3223                 return RDMA_CORE_PORT_IBA_IB;
3224
3225         ret = RDMA_CORE_PORT_RAW_PACKET;
3226
3227         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3228                 return ret;
3229
3230         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3231                 return ret;
3232
3233         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3234                 ret |= RDMA_CORE_PORT_IBA_ROCE;
3235
3236         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3237                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3238
3239         return ret;
3240 }
3241
3242 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3243                                struct ib_port_immutable *immutable)
3244 {
3245         struct ib_port_attr attr;
3246         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3247         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3248         int err;
3249
3250         immutable->core_cap_flags = get_core_cap_flags(ibdev);
3251
3252         err = ib_query_port(ibdev, port_num, &attr);
3253         if (err)
3254                 return err;
3255
3256         immutable->pkey_tbl_len = attr.pkey_tbl_len;
3257         immutable->gid_tbl_len = attr.gid_tbl_len;
3258         immutable->core_cap_flags = get_core_cap_flags(ibdev);
3259         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3260                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3261
3262         return 0;
3263 }
3264
3265 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
3266                            size_t str_len)
3267 {
3268         struct mlx5_ib_dev *dev =
3269                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3270         snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
3271                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
3272 }
3273
3274 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3275 {
3276         struct mlx5_core_dev *mdev = dev->mdev;
3277         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3278                                                                  MLX5_FLOW_NAMESPACE_LAG);
3279         struct mlx5_flow_table *ft;
3280         int err;
3281
3282         if (!ns || !mlx5_lag_is_active(mdev))
3283                 return 0;
3284
3285         err = mlx5_cmd_create_vport_lag(mdev);
3286         if (err)
3287                 return err;
3288
3289         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3290         if (IS_ERR(ft)) {
3291                 err = PTR_ERR(ft);
3292                 goto err_destroy_vport_lag;
3293         }
3294
3295         dev->flow_db.lag_demux_ft = ft;
3296         return 0;
3297
3298 err_destroy_vport_lag:
3299         mlx5_cmd_destroy_vport_lag(mdev);
3300         return err;
3301 }
3302
3303 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3304 {
3305         struct mlx5_core_dev *mdev = dev->mdev;
3306
3307         if (dev->flow_db.lag_demux_ft) {
3308                 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3309                 dev->flow_db.lag_demux_ft = NULL;
3310
3311                 mlx5_cmd_destroy_vport_lag(mdev);
3312         }
3313 }
3314
3315 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3316 {
3317         int err;
3318
3319         dev->roce.nb.notifier_call = mlx5_netdev_event;
3320         err = register_netdevice_notifier(&dev->roce.nb);
3321         if (err) {
3322                 dev->roce.nb.notifier_call = NULL;
3323                 return err;
3324         }
3325
3326         return 0;
3327 }
3328
3329 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
3330 {
3331         if (dev->roce.nb.notifier_call) {
3332                 unregister_netdevice_notifier(&dev->roce.nb);
3333                 dev->roce.nb.notifier_call = NULL;
3334         }
3335 }
3336
3337 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3338 {
3339         int err;
3340
3341         err = mlx5_add_netdev_notifier(dev);
3342         if (err)
3343                 return err;
3344
3345         if (MLX5_CAP_GEN(dev->mdev, roce)) {
3346                 err = mlx5_nic_vport_enable_roce(dev->mdev);
3347                 if (err)
3348                         goto err_unregister_netdevice_notifier;
3349         }
3350
3351         err = mlx5_eth_lag_init(dev);
3352         if (err)
3353                 goto err_disable_roce;
3354
3355         return 0;
3356
3357 err_disable_roce:
3358         if (MLX5_CAP_GEN(dev->mdev, roce))
3359                 mlx5_nic_vport_disable_roce(dev->mdev);
3360
3361 err_unregister_netdevice_notifier:
3362         mlx5_remove_netdev_notifier(dev);
3363         return err;
3364 }
3365
3366 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3367 {
3368         mlx5_eth_lag_cleanup(dev);
3369         if (MLX5_CAP_GEN(dev->mdev, roce))
3370                 mlx5_nic_vport_disable_roce(dev->mdev);
3371 }
3372
3373 struct mlx5_ib_counter {
3374         const char *name;
3375         size_t offset;
3376 };
3377
3378 #define INIT_Q_COUNTER(_name)           \
3379         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3380
3381 static const struct mlx5_ib_counter basic_q_cnts[] = {
3382         INIT_Q_COUNTER(rx_write_requests),
3383         INIT_Q_COUNTER(rx_read_requests),
3384         INIT_Q_COUNTER(rx_atomic_requests),
3385         INIT_Q_COUNTER(out_of_buffer),
3386 };
3387
3388 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
3389         INIT_Q_COUNTER(out_of_sequence),
3390 };
3391
3392 static const struct mlx5_ib_counter retrans_q_cnts[] = {
3393         INIT_Q_COUNTER(duplicate_request),
3394         INIT_Q_COUNTER(rnr_nak_retry_err),
3395         INIT_Q_COUNTER(packet_seq_err),
3396         INIT_Q_COUNTER(implied_nak_seq_err),
3397         INIT_Q_COUNTER(local_ack_timeout_err),
3398 };
3399
3400 #define INIT_CONG_COUNTER(_name)                \
3401         { .name = #_name, .offset =     \
3402                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3403
3404 static const struct mlx5_ib_counter cong_cnts[] = {
3405         INIT_CONG_COUNTER(rp_cnp_ignored),
3406         INIT_CONG_COUNTER(rp_cnp_handled),
3407         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3408         INIT_CONG_COUNTER(np_cnp_sent),
3409 };
3410
3411 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
3412 {
3413         unsigned int i;
3414
3415         for (i = 0; i < dev->num_ports; i++) {
3416                 mlx5_core_dealloc_q_counter(dev->mdev,
3417                                             dev->port[i].cnts.set_id);
3418                 kfree(dev->port[i].cnts.names);
3419                 kfree(dev->port[i].cnts.offsets);
3420         }
3421 }
3422
3423 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3424                                     struct mlx5_ib_counters *cnts)
3425 {
3426         u32 num_counters;
3427
3428         num_counters = ARRAY_SIZE(basic_q_cnts);
3429
3430         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3431                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3432
3433         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3434                 num_counters += ARRAY_SIZE(retrans_q_cnts);
3435         cnts->num_q_counters = num_counters;
3436
3437         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3438                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3439                 num_counters += ARRAY_SIZE(cong_cnts);
3440         }
3441
3442         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3443         if (!cnts->names)
3444                 return -ENOMEM;
3445
3446         cnts->offsets = kcalloc(num_counters,
3447                                 sizeof(cnts->offsets), GFP_KERNEL);
3448         if (!cnts->offsets)
3449                 goto err_names;
3450
3451         return 0;
3452
3453 err_names:
3454         kfree(cnts->names);
3455         return -ENOMEM;
3456 }
3457
3458 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3459                                   const char **names,
3460                                   size_t *offsets)
3461 {
3462         int i;
3463         int j = 0;
3464
3465         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3466                 names[j] = basic_q_cnts[i].name;
3467                 offsets[j] = basic_q_cnts[i].offset;
3468         }
3469
3470         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3471                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3472                         names[j] = out_of_seq_q_cnts[i].name;
3473                         offsets[j] = out_of_seq_q_cnts[i].offset;
3474                 }
3475         }
3476
3477         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3478                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3479                         names[j] = retrans_q_cnts[i].name;
3480                         offsets[j] = retrans_q_cnts[i].offset;
3481                 }
3482         }
3483
3484         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3485                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3486                         names[j] = cong_cnts[i].name;
3487                         offsets[j] = cong_cnts[i].offset;
3488                 }
3489         }
3490 }
3491
3492 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
3493 {
3494         int i;
3495         int ret;
3496
3497         for (i = 0; i < dev->num_ports; i++) {
3498                 struct mlx5_ib_port *port = &dev->port[i];
3499
3500                 ret = mlx5_core_alloc_q_counter(dev->mdev,
3501                                                 &port->cnts.set_id);
3502                 if (ret) {
3503                         mlx5_ib_warn(dev,
3504                                      "couldn't allocate queue counter for port %d, err %d\n",
3505                                      i + 1, ret);
3506                         goto dealloc_counters;
3507                 }
3508
3509                 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
3510                 if (ret)
3511                         goto dealloc_counters;
3512
3513                 mlx5_ib_fill_counters(dev, port->cnts.names,
3514                                       port->cnts.offsets);
3515         }
3516
3517         return 0;
3518
3519 dealloc_counters:
3520         while (--i >= 0)
3521                 mlx5_core_dealloc_q_counter(dev->mdev,
3522                                             dev->port[i].cnts.set_id);
3523
3524         return ret;
3525 }
3526
3527 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3528                                                     u8 port_num)
3529 {
3530         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3531         struct mlx5_ib_port *port = &dev->port[port_num - 1];
3532
3533         /* We support only per port stats */
3534         if (port_num == 0)
3535                 return NULL;
3536
3537         return rdma_alloc_hw_stats_struct(port->cnts.names,
3538                                           port->cnts.num_q_counters +
3539                                           port->cnts.num_cong_counters,
3540                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
3541 }
3542
3543 static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3544                                     struct mlx5_ib_port *port,
3545                                     struct rdma_hw_stats *stats)
3546 {
3547         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3548         void *out;
3549         __be32 val;
3550         int ret, i;
3551
3552         out = kvzalloc(outlen, GFP_KERNEL);
3553         if (!out)
3554                 return -ENOMEM;
3555
3556         ret = mlx5_core_query_q_counter(dev->mdev,
3557                                         port->cnts.set_id, 0,
3558                                         out, outlen);
3559         if (ret)
3560                 goto free;
3561
3562         for (i = 0; i < port->cnts.num_q_counters; i++) {
3563                 val = *(__be32 *)(out + port->cnts.offsets[i]);
3564                 stats->value[i] = (u64)be32_to_cpu(val);
3565         }
3566
3567 free:
3568         kvfree(out);
3569         return ret;
3570 }
3571
3572 static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev,
3573                                        struct mlx5_ib_port *port,
3574                                        struct rdma_hw_stats *stats)
3575 {
3576         int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3577         void *out;
3578         int ret, i;
3579         int offset = port->cnts.num_q_counters;
3580
3581         out = kvzalloc(outlen, GFP_KERNEL);
3582         if (!out)
3583                 return -ENOMEM;
3584
3585         ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3586         if (ret)
3587                 goto free;
3588
3589         for (i = 0; i < port->cnts.num_cong_counters; i++) {
3590                 stats->value[i + offset] =
3591                         be64_to_cpup((__be64 *)(out +
3592                                      port->cnts.offsets[i + offset]));
3593         }
3594
3595 free:
3596         kvfree(out);
3597         return ret;
3598 }
3599
3600 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3601                                 struct rdma_hw_stats *stats,
3602                                 u8 port_num, int index)
3603 {
3604         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3605         struct mlx5_ib_port *port = &dev->port[port_num - 1];
3606         int ret, num_counters;
3607
3608         if (!stats)
3609                 return -EINVAL;
3610
3611         ret = mlx5_ib_query_q_counters(dev, port, stats);
3612         if (ret)
3613                 return ret;
3614         num_counters = port->cnts.num_q_counters;
3615
3616         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3617                 ret = mlx5_ib_query_cong_counters(dev, port, stats);
3618                 if (ret)
3619                         return ret;
3620                 num_counters += port->cnts.num_cong_counters;
3621         }
3622
3623         return num_counters;
3624 }
3625
3626 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3627 {
3628         return mlx5_rdma_netdev_free(netdev);
3629 }
3630
3631 static struct net_device*
3632 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3633                           u8 port_num,
3634                           enum rdma_netdev_t type,
3635                           const char *name,
3636                           unsigned char name_assign_type,
3637                           void (*setup)(struct net_device *))
3638 {
3639         struct net_device *netdev;
3640         struct rdma_netdev *rn;
3641
3642         if (type != RDMA_NETDEV_IPOIB)
3643                 return ERR_PTR(-EOPNOTSUPP);
3644
3645         netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3646                                         name, setup);
3647         if (likely(!IS_ERR_OR_NULL(netdev))) {
3648                 rn = netdev_priv(netdev);
3649                 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3650         }
3651         return netdev;
3652 }
3653
3654 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
3655 {
3656         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3657                 return;
3658
3659         cancel_work_sync(&dev->delay_drop.delay_drop_work);
3660 }
3661
3662 static void init_delay_drop(struct mlx5_ib_dev *dev)
3663 {
3664         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3665                 return;
3666
3667         mutex_init(&dev->delay_drop.lock);
3668         dev->delay_drop.dev = dev;
3669         dev->delay_drop.activate = false;
3670         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
3671         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
3672 }
3673
3674 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3675 {
3676         struct mlx5_ib_dev *dev;
3677         enum rdma_link_layer ll;
3678         int port_type_cap;
3679         const char *name;
3680         int err;
3681         int i;
3682
3683         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3684         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3685
3686         printk_once(KERN_INFO "%s", mlx5_version);
3687
3688         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3689         if (!dev)
3690                 return NULL;
3691
3692         dev->mdev = mdev;
3693
3694         dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3695                             GFP_KERNEL);
3696         if (!dev->port)
3697                 goto err_dealloc;
3698
3699         rwlock_init(&dev->roce.netdev_lock);
3700         err = get_port_caps(dev);
3701         if (err)
3702                 goto err_free_port;
3703
3704         if (mlx5_use_mad_ifc(dev))
3705                 get_ext_port_caps(dev);
3706
3707         if (!mlx5_lag_is_active(mdev))
3708                 name = "mlx5_%d";
3709         else
3710                 name = "mlx5_bond_%d";
3711
3712         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
3713         dev->ib_dev.owner               = THIS_MODULE;
3714         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
3715         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
3716         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
3717         dev->ib_dev.phys_port_cnt     = dev->num_ports;
3718         dev->ib_dev.num_comp_vectors    =
3719                 dev->mdev->priv.eq_table.num_comp_vectors;
3720         dev->ib_dev.dev.parent          = &mdev->pdev->dev;
3721
3722         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
3723         dev->ib_dev.uverbs_cmd_mask     =
3724                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
3725                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
3726                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
3727                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
3728                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
3729                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
3730                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
3731                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
3732                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
3733                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
3734                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3735                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
3736                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
3737                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
3738                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
3739                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
3740                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
3741                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
3742                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
3743                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
3744                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
3745                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
3746                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
3747                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
3748                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
3749                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3750         dev->ib_dev.uverbs_ex_cmd_mask =
3751                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
3752                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
3753                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
3754                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
3755
3756         dev->ib_dev.query_device        = mlx5_ib_query_device;
3757         dev->ib_dev.query_port          = mlx5_ib_query_port;
3758         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
3759         if (ll == IB_LINK_LAYER_ETHERNET)
3760                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
3761         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
3762         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
3763         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
3764         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
3765         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
3766         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
3767         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
3768         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
3769         dev->ib_dev.mmap                = mlx5_ib_mmap;
3770         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
3771         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
3772         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
3773         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
3774         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
3775         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
3776         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
3777         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
3778         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
3779         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
3780         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
3781         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
3782         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
3783         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
3784         dev->ib_dev.post_send           = mlx5_ib_post_send;
3785         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
3786         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
3787         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
3788         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
3789         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
3790         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
3791         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
3792         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
3793         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
3794         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
3795         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
3796         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
3797         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
3798         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
3799         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
3800         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
3801         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
3802         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
3803         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
3804         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
3805                 dev->ib_dev.alloc_rdma_netdev   = mlx5_ib_alloc_rdma_netdev;
3806
3807         if (mlx5_core_is_pf(mdev)) {
3808                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
3809                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
3810                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
3811                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
3812         }
3813
3814         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3815
3816         mlx5_ib_internal_fill_odp_caps(dev);
3817
3818         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3819
3820         if (MLX5_CAP_GEN(mdev, imaicl)) {
3821                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
3822                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
3823                 dev->ib_dev.uverbs_cmd_mask |=
3824                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
3825                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3826         }
3827
3828         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3829                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
3830                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
3831         }
3832
3833         if (MLX5_CAP_GEN(mdev, xrc)) {
3834                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3835                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3836                 dev->ib_dev.uverbs_cmd_mask |=
3837                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3838                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3839         }
3840
3841         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3842             IB_LINK_LAYER_ETHERNET) {
3843                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3844                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3845                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
3846                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
3847                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
3848                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3849                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3850                 dev->ib_dev.uverbs_ex_cmd_mask |=
3851                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3852                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3853                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3854                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3855                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3856                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3857                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3858         }
3859         err = init_node_data(dev);
3860         if (err)
3861                 goto err_free_port;
3862
3863         mutex_init(&dev->flow_db.lock);
3864         mutex_init(&dev->cap_mask_mutex);
3865         INIT_LIST_HEAD(&dev->qp_list);
3866         spin_lock_init(&dev->reset_flow_resource_lock);
3867
3868         if (ll == IB_LINK_LAYER_ETHERNET) {
3869                 err = mlx5_enable_eth(dev);
3870                 if (err)
3871                         goto err_free_port;
3872                 dev->roce.last_port_state = IB_PORT_DOWN;
3873         }
3874
3875         err = create_dev_resources(&dev->devr);
3876         if (err)
3877                 goto err_disable_eth;
3878
3879         err = mlx5_ib_odp_init_one(dev);
3880         if (err)
3881                 goto err_rsrc;
3882
3883         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3884                 err = mlx5_ib_alloc_counters(dev);
3885                 if (err)
3886                         goto err_odp;
3887         }
3888
3889         err = mlx5_ib_init_cong_debugfs(dev);
3890         if (err)
3891                 goto err_cnt;
3892
3893         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
3894         if (!dev->mdev->priv.uar)
3895                 goto err_cong;
3896
3897         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
3898         if (err)
3899                 goto err_uar_page;
3900
3901         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
3902         if (err)
3903                 goto err_bfreg;
3904
3905         err = ib_register_device(&dev->ib_dev, NULL);
3906         if (err)
3907                 goto err_fp_bfreg;
3908
3909         err = create_umr_res(dev);
3910         if (err)
3911                 goto err_dev;
3912
3913         init_delay_drop(dev);
3914
3915         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3916                 err = device_create_file(&dev->ib_dev.dev,
3917                                          mlx5_class_attributes[i]);
3918                 if (err)
3919                         goto err_delay_drop;
3920         }
3921
3922         if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
3923             MLX5_CAP_GEN(mdev, disable_local_lb))
3924                 mutex_init(&dev->lb_mutex);
3925
3926         dev->ib_active = true;
3927
3928         return dev;
3929
3930 err_delay_drop:
3931         cancel_delay_drop(dev);
3932         destroy_umrc_res(dev);
3933
3934 err_dev:
3935         ib_unregister_device(&dev->ib_dev);
3936
3937 err_fp_bfreg:
3938         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3939
3940 err_bfreg:
3941         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3942
3943 err_uar_page:
3944         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
3945
3946 err_cnt:
3947         mlx5_ib_cleanup_cong_debugfs(dev);
3948 err_cong:
3949         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3950                 mlx5_ib_dealloc_counters(dev);
3951
3952 err_odp:
3953         mlx5_ib_odp_remove_one(dev);
3954
3955 err_rsrc:
3956         destroy_dev_resources(&dev->devr);
3957
3958 err_disable_eth:
3959         if (ll == IB_LINK_LAYER_ETHERNET) {
3960                 mlx5_disable_eth(dev);
3961                 mlx5_remove_netdev_notifier(dev);
3962         }
3963
3964 err_free_port:
3965         kfree(dev->port);
3966
3967 err_dealloc:
3968         ib_dealloc_device((struct ib_device *)dev);
3969
3970         return NULL;
3971 }
3972
3973 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3974 {
3975         struct mlx5_ib_dev *dev = context;
3976         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3977
3978         cancel_delay_drop(dev);
3979         mlx5_remove_netdev_notifier(dev);
3980         ib_unregister_device(&dev->ib_dev);
3981         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3982         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3983         mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
3984         mlx5_ib_cleanup_cong_debugfs(dev);
3985         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3986                 mlx5_ib_dealloc_counters(dev);
3987         destroy_umrc_res(dev);
3988         mlx5_ib_odp_remove_one(dev);
3989         destroy_dev_resources(&dev->devr);
3990         if (ll == IB_LINK_LAYER_ETHERNET)
3991                 mlx5_disable_eth(dev);
3992         kfree(dev->port);
3993         ib_dealloc_device(&dev->ib_dev);
3994 }
3995
3996 static struct mlx5_interface mlx5_ib_interface = {
3997         .add            = mlx5_ib_add,
3998         .remove         = mlx5_ib_remove,
3999         .event          = mlx5_ib_event,
4000 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4001         .pfault         = mlx5_ib_pfault,
4002 #endif
4003         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
4004 };
4005
4006 static int __init mlx5_ib_init(void)
4007 {
4008         int err;
4009
4010         mlx5_ib_odp_init();
4011
4012         err = mlx5_register_interface(&mlx5_ib_interface);
4013
4014         return err;
4015 }
4016
4017 static void __exit mlx5_ib_cleanup(void)
4018 {
4019         mlx5_unregister_interface(&mlx5_ib_interface);
4020 }
4021
4022 module_init(mlx5_ib_init);
4023 module_exit(mlx5_ib_cleanup);