drivers/infiniband/hw/mlx5/main.c

   1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
   2 /*
   3  * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
   4  * Copyright (c) 2020, Intel Corporation. All rights reserved.
   5  */
   6
   7 #include <linux/debugfs.h>
   8 #include <linux/highmem.h>
   9 #include <linux/module.h>
  10 #include <linux/init.h>
  11 #include <linux/errno.h>
  12 #include <linux/pci.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/slab.h>
  15 #include <linux/bitmap.h>
  16 #include <linux/sched.h>
  17 #include <linux/sched/mm.h>
  18 #include <linux/sched/task.h>
  19 #include <linux/delay.h>
  20 #include <rdma/ib_user_verbs.h>
  21 #include <rdma/ib_addr.h>
  22 #include <rdma/ib_cache.h>
  23 #include <linux/mlx5/port.h>
  24 #include <linux/mlx5/vport.h>
  25 #include <linux/mlx5/fs.h>
  26 #include <linux/mlx5/eswitch.h>
  27 #include <linux/list.h>
  28 #include <rdma/ib_smi.h>
  29 #include <rdma/ib_umem.h>
  30 #include <rdma/lag.h>
  31 #include <linux/in.h>
  32 #include <linux/etherdevice.h>
  33 #include "mlx5_ib.h"
  34 #include "ib_rep.h"
  35 #include "cmd.h"
  36 #include "devx.h"
  37 #include "dm.h"
  38 #include "fs.h"
  39 #include "srq.h"
  40 #include "qp.h"
  41 #include "wr.h"
  42 #include "restrack.h"
  43 #include "counters.h"
  44 #include "umr.h"
  45 #include <rdma/uverbs_std_types.h>
  46 #include <rdma/uverbs_ioctl.h>
  47 #include <rdma/mlx5_user_ioctl_verbs.h>
  48 #include <rdma/mlx5_user_ioctl_cmds.h>
  49 #include <rdma/ib_umem_odp.h>
  50
  51 #define UVERBS_MODULE_NAME mlx5_ib
  52 #include <rdma/uverbs_named_ioctl.h>
  53
  54 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  55 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver");
  56 MODULE_LICENSE("Dual BSD/GPL");
  57
  58 struct mlx5_ib_event_work {
  59         struct work_struct      work;
  60         union {
  61                 struct mlx5_ib_dev            *dev;
  62                 struct mlx5_ib_multiport_info *mpi;
  63         };
  64         bool                    is_slave;
  65         unsigned int            event;
  66         void                    *param;
  67 };
  68
  69 enum {
  70         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  71 };
  72
  73 static struct workqueue_struct *mlx5_ib_event_wq;
  74 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
  75 static LIST_HEAD(mlx5_ib_dev_list);
  76 /*
  77  * This mutex should be held when accessing either of the above lists
  78  */
  79 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
  80
  81 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
  82 {
  83         struct mlx5_ib_dev *dev;
  84
  85         mutex_lock(&mlx5_ib_multiport_mutex);
  86         dev = mpi->ibdev;
  87         mutex_unlock(&mlx5_ib_multiport_mutex);
  88         return dev;
  89 }
  90
  91 static enum rdma_link_layer
  92 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  93 {
  94         switch (port_type_cap) {
  95         case MLX5_CAP_PORT_TYPE_IB:
  96                 return IB_LINK_LAYER_INFINIBAND;
  97         case MLX5_CAP_PORT_TYPE_ETH:
  98                 return IB_LINK_LAYER_ETHERNET;
  99         default:
 100                 return IB_LINK_LAYER_UNSPECIFIED;
 101         }
 102 }
 103
 104 static enum rdma_link_layer
 105 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num)
 106 {
 107         struct mlx5_ib_dev *dev = to_mdev(device);
 108         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 109
 110         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 111 }
 112
 113 static int get_port_state(struct ib_device *ibdev,
 114                           u32 port_num,
 115                           enum ib_port_state *state)
 116 {
 117         struct ib_port_attr attr;
 118         int ret;
 119
 120         memset(&attr, 0, sizeof(attr));
 121         ret = ibdev->ops.query_port(ibdev, port_num, &attr);
 122         if (!ret)
 123                 *state = attr.state;
 124         return ret;
 125 }
 126
 127 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
 128                                            struct net_device *ndev,
 129                                            struct net_device *upper,
 130                                            u32 *port_num)
 131 {
 132         struct net_device *rep_ndev;
 133         struct mlx5_ib_port *port;
 134         int i;
 135
 136         for (i = 0; i < dev->num_ports; i++) {
 137                 port  = &dev->port[i];
 138                 if (!port->rep)
 139                         continue;
 140
 141                 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) {
 142                         *port_num = i + 1;
 143                         return &port->roce;
 144                 }
 145
 146                 if (upper && port->rep->vport == MLX5_VPORT_UPLINK)
 147                         continue;
 148
 149                 read_lock(&port->roce.netdev_lock);
 150                 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw,
 151                                                   port->rep->vport);
 152                 if (rep_ndev == ndev) {
 153                         read_unlock(&port->roce.netdev_lock);
 154                         *port_num = i + 1;
 155                         return &port->roce;
 156                 }
 157                 read_unlock(&port->roce.netdev_lock);
 158         }
 159
 160         return NULL;
 161 }
 162
 163 static int mlx5_netdev_event(struct notifier_block *this,
 164                              unsigned long event, void *ptr)
 165 {
 166         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 167         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 168         u32 port_num = roce->native_port_num;
 169         struct mlx5_core_dev *mdev;
 170         struct mlx5_ib_dev *ibdev;
 171
 172         ibdev = roce->dev;
 173         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 174         if (!mdev)
 175                 return NOTIFY_DONE;
 176
 177         switch (event) {
 178         case NETDEV_REGISTER:
 179                 /* Should already be registered during the load */
 180                 if (ibdev->is_rep)
 181                         break;
 182                 write_lock(&roce->netdev_lock);
 183                 if (ndev->dev.parent == mdev->device)
 184                         roce->netdev = ndev;
 185                 write_unlock(&roce->netdev_lock);
 186                 break;
 187
 188         case NETDEV_UNREGISTER:
 189                 /* In case of reps, ib device goes away before the netdevs */
 190                 write_lock(&roce->netdev_lock);
 191                 if (roce->netdev == ndev)
 192                         roce->netdev = NULL;
 193                 write_unlock(&roce->netdev_lock);
 194                 break;
 195
 196         case NETDEV_CHANGE:
 197         case NETDEV_UP:
 198         case NETDEV_DOWN: {
 199                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 200                 struct net_device *upper = NULL;
 201
 202                 if (lag_ndev) {
 203                         upper = netdev_master_upper_dev_get(lag_ndev);
 204                         dev_put(lag_ndev);
 205                 }
 206
 207                 if (ibdev->is_rep)
 208                         roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num);
 209                 if (!roce)
 210                         return NOTIFY_DONE;
 211                 if ((upper == ndev ||
 212                      ((!upper || ibdev->is_rep) && ndev == roce->netdev)) &&
 213                     ibdev->ib_active) {
 214                         struct ib_event ibev = { };
 215                         enum ib_port_state port_state;
 216
 217                         if (get_port_state(&ibdev->ib_dev, port_num,
 218                                            &port_state))
 219                                 goto done;
 220
 221                         if (roce->last_port_state == port_state)
 222                                 goto done;
 223
 224                         roce->last_port_state = port_state;
 225                         ibev.device = &ibdev->ib_dev;
 226                         if (port_state == IB_PORT_DOWN)
 227                                 ibev.event = IB_EVENT_PORT_ERR;
 228                         else if (port_state == IB_PORT_ACTIVE)
 229                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 230                         else
 231                                 goto done;
 232
 233                         ibev.element.port_num = port_num;
 234                         ib_dispatch_event(&ibev);
 235                 }
 236                 break;
 237         }
 238
 239         default:
 240                 break;
 241         }
 242 done:
 243         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 244         return NOTIFY_DONE;
 245 }
 246
 247 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 248                                              u32 port_num)
 249 {
 250         struct mlx5_ib_dev *ibdev = to_mdev(device);
 251         struct net_device *ndev;
 252         struct mlx5_core_dev *mdev;
 253
 254         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 255         if (!mdev)
 256                 return NULL;
 257
 258         ndev = mlx5_lag_get_roce_netdev(mdev);
 259         if (ndev)
 260                 goto out;
 261
 262         /* Ensure ndev does not disappear before we invoke dev_hold()
 263          */
 264         read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
 265         ndev = ibdev->port[port_num - 1].roce.netdev;
 266         if (ndev)
 267                 dev_hold(ndev);
 268         read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
 269
 270 out:
 271         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 272         return ndev;
 273 }
 274
 275 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 276                                                    u32 ib_port_num,
 277                                                    u32 *native_port_num)
 278 {
 279         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 280                                                           ib_port_num);
 281         struct mlx5_core_dev *mdev = NULL;
 282         struct mlx5_ib_multiport_info *mpi;
 283         struct mlx5_ib_port *port;
 284
 285         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 286             ll != IB_LINK_LAYER_ETHERNET) {
 287                 if (native_port_num)
 288                         *native_port_num = ib_port_num;
 289                 return ibdev->mdev;
 290         }
 291
 292         if (native_port_num)
 293                 *native_port_num = 1;
 294
 295         port = &ibdev->port[ib_port_num - 1];
 296         spin_lock(&port->mp.mpi_lock);
 297         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 298         if (mpi && !mpi->unaffiliate) {
 299                 mdev = mpi->mdev;
 300                 /* If it's the master no need to refcount, it'll exist
 301                  * as long as the ib_dev exists.
 302                  */
 303                 if (!mpi->is_master)
 304                         mpi->mdev_refcnt++;
 305         }
 306         spin_unlock(&port->mp.mpi_lock);
 307
 308         return mdev;
 309 }
 310
 311 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num)
 312 {
 313         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 314                                                           port_num);
 315         struct mlx5_ib_multiport_info *mpi;
 316         struct mlx5_ib_port *port;
 317
 318         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 319                 return;
 320
 321         port = &ibdev->port[port_num - 1];
 322
 323         spin_lock(&port->mp.mpi_lock);
 324         mpi = ibdev->port[port_num - 1].mp.mpi;
 325         if (mpi->is_master)
 326                 goto out;
 327
 328         mpi->mdev_refcnt--;
 329         if (mpi->unaffiliate)
 330                 complete(&mpi->unref_comp);
 331 out:
 332         spin_unlock(&port->mp.mpi_lock);
 333 }
 334
 335 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper,
 336                                            u16 *active_speed, u8 *active_width)
 337 {
 338         switch (eth_proto_oper) {
 339         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 340         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 341         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 342         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 343                 *active_width = IB_WIDTH_1X;
 344                 *active_speed = IB_SPEED_SDR;
 345                 break;
 346         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 347         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 348         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 349         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 350         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 351         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 352         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 353                 *active_width = IB_WIDTH_1X;
 354                 *active_speed = IB_SPEED_QDR;
 355                 break;
 356         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 357         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 358         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 359                 *active_width = IB_WIDTH_1X;
 360                 *active_speed = IB_SPEED_EDR;
 361                 break;
 362         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 363         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 364         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 365         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 366                 *active_width = IB_WIDTH_4X;
 367                 *active_speed = IB_SPEED_QDR;
 368                 break;
 369         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 370         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 371         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 372                 *active_width = IB_WIDTH_1X;
 373                 *active_speed = IB_SPEED_HDR;
 374                 break;
 375         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 376                 *active_width = IB_WIDTH_4X;
 377                 *active_speed = IB_SPEED_FDR;
 378                 break;
 379         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 380         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 381         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 382         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 383                 *active_width = IB_WIDTH_4X;
 384                 *active_speed = IB_SPEED_EDR;
 385                 break;
 386         default:
 387                 return -EINVAL;
 388         }
 389
 390         return 0;
 391 }
 392
 393 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
 394                                         u8 *active_width)
 395 {
 396         switch (eth_proto_oper) {
 397         case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
 398         case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
 399                 *active_width = IB_WIDTH_1X;
 400                 *active_speed = IB_SPEED_SDR;
 401                 break;
 402         case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
 403                 *active_width = IB_WIDTH_1X;
 404                 *active_speed = IB_SPEED_DDR;
 405                 break;
 406         case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
 407                 *active_width = IB_WIDTH_1X;
 408                 *active_speed = IB_SPEED_QDR;
 409                 break;
 410         case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
 411                 *active_width = IB_WIDTH_4X;
 412                 *active_speed = IB_SPEED_QDR;
 413                 break;
 414         case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
 415                 *active_width = IB_WIDTH_1X;
 416                 *active_speed = IB_SPEED_EDR;
 417                 break;
 418         case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
 419                 *active_width = IB_WIDTH_2X;
 420                 *active_speed = IB_SPEED_EDR;
 421                 break;
 422         case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
 423                 *active_width = IB_WIDTH_1X;
 424                 *active_speed = IB_SPEED_HDR;
 425                 break;
 426         case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
 427                 *active_width = IB_WIDTH_4X;
 428                 *active_speed = IB_SPEED_EDR;
 429                 break;
 430         case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
 431                 *active_width = IB_WIDTH_2X;
 432                 *active_speed = IB_SPEED_HDR;
 433                 break;
 434         case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR):
 435                 *active_width = IB_WIDTH_1X;
 436                 *active_speed = IB_SPEED_NDR;
 437                 break;
 438         case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
 439                 *active_width = IB_WIDTH_4X;
 440                 *active_speed = IB_SPEED_HDR;
 441                 break;
 442         case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2):
 443                 *active_width = IB_WIDTH_2X;
 444                 *active_speed = IB_SPEED_NDR;
 445                 break;
 446         case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4):
 447                 *active_width = IB_WIDTH_4X;
 448                 *active_speed = IB_SPEED_NDR;
 449                 break;
 450         default:
 451                 return -EINVAL;
 452         }
 453
 454         return 0;
 455 }
 456
 457 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed,
 458                                     u8 *active_width, bool ext)
 459 {
 460         return ext ?
 461                 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
 462                                              active_width) :
 463                 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
 464                                                 active_width);
 465 }
 466
 467 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num,
 468                                 struct ib_port_attr *props)
 469 {
 470         struct mlx5_ib_dev *dev = to_mdev(device);
 471         u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
 472         struct mlx5_core_dev *mdev;
 473         struct net_device *ndev, *upper;
 474         enum ib_mtu ndev_ib_mtu;
 475         bool put_mdev = true;
 476         u32 eth_prot_oper;
 477         u32 mdev_port_num;
 478         bool ext;
 479         int err;
 480
 481         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 482         if (!mdev) {
 483                 /* This means the port isn't affiliated yet. Get the
 484                  * info for the master port instead.
 485                  */
 486                 put_mdev = false;
 487                 mdev = dev->mdev;
 488                 mdev_port_num = 1;
 489                 port_num = 1;
 490         }
 491
 492         /* Possible bad flows are checked before filling out props so in case
 493          * of an error it will still be zeroed out.
 494          * Use native port in case of reps
 495          */
 496         if (dev->is_rep)
 497                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 498                                            1);
 499         else
 500                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 501                                            mdev_port_num);
 502         if (err)
 503                 goto out;
 504         ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
 505         eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
 506
 507         props->active_width     = IB_WIDTH_4X;
 508         props->active_speed     = IB_SPEED_QDR;
 509
 510         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 511                                  &props->active_width, ext);
 512
 513         if (!dev->is_rep && dev->mdev->roce.roce_en) {
 514                 u16 qkey_viol_cntr;
 515
 516                 props->port_cap_flags |= IB_PORT_CM_SUP;
 517                 props->ip_gids = true;
 518                 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
 519                                                    roce_address_table_size);
 520                 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 521                 props->qkey_viol_cntr = qkey_viol_cntr;
 522         }
 523         props->max_mtu          = IB_MTU_4096;
 524         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 525         props->pkey_tbl_len     = 1;
 526         props->state            = IB_PORT_DOWN;
 527         props->phys_state       = IB_PORT_PHYS_STATE_DISABLED;
 528
 529         /* If this is a stub query for an unaffiliated port stop here */
 530         if (!put_mdev)
 531                 goto out;
 532
 533         ndev = mlx5_ib_get_netdev(device, port_num);
 534         if (!ndev)
 535                 goto out;
 536
 537         if (dev->lag_active) {
 538                 rcu_read_lock();
 539                 upper = netdev_master_upper_dev_get_rcu(ndev);
 540                 if (upper) {
 541                         dev_put(ndev);
 542                         ndev = upper;
 543                         dev_hold(ndev);
 544                 }
 545                 rcu_read_unlock();
 546         }
 547
 548         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 549                 props->state      = IB_PORT_ACTIVE;
 550                 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
 551         }
 552
 553         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 554
 555         dev_put(ndev);
 556
 557         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 558 out:
 559         if (put_mdev)
 560                 mlx5_ib_put_native_port_mdev(dev, port_num);
 561         return err;
 562 }
 563
 564 static int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num,
 565                          unsigned int index, const union ib_gid *gid,
 566                          const struct ib_gid_attr *attr)
 567 {
 568         enum ib_gid_type gid_type;
 569         u16 vlan_id = 0xffff;
 570         u8 roce_version = 0;
 571         u8 roce_l3_type = 0;
 572         u8 mac[ETH_ALEN];
 573         int ret;
 574
 575         gid_type = attr->gid_type;
 576         if (gid) {
 577                 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
 578                 if (ret)
 579                         return ret;
 580         }
 581
 582         switch (gid_type) {
 583         case IB_GID_TYPE_ROCE:
 584                 roce_version = MLX5_ROCE_VERSION_1;
 585                 break;
 586         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 587                 roce_version = MLX5_ROCE_VERSION_2;
 588                 if (gid && ipv6_addr_v4mapped((void *)gid))
 589                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 590                 else
 591                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 592                 break;
 593
 594         default:
 595                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 596         }
 597
 598         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 599                                       roce_l3_type, gid->raw, mac,
 600                                       vlan_id < VLAN_CFI_MASK, vlan_id,
 601                                       port_num);
 602 }
 603
 604 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
 605                            __always_unused void **context)
 606 {
 607         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 608                              attr->index, &attr->gid, attr);
 609 }
 610
 611 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 612                            __always_unused void **context)
 613 {
 614         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 615                              attr->index, NULL, attr);
 616 }
 617
 618 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
 619                                    const struct ib_gid_attr *attr)
 620 {
 621         if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 622                 return 0;
 623
 624         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 625 }
 626
 627 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 628 {
 629         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 630                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 631         return 0;
 632 }
 633
 634 enum {
 635         MLX5_VPORT_ACCESS_METHOD_MAD,
 636         MLX5_VPORT_ACCESS_METHOD_HCA,
 637         MLX5_VPORT_ACCESS_METHOD_NIC,
 638 };
 639
 640 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 641 {
 642         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 643                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 644
 645         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 646             IB_LINK_LAYER_ETHERNET)
 647                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 648
 649         return MLX5_VPORT_ACCESS_METHOD_HCA;
 650 }
 651
 652 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 653                             u8 atomic_size_qp,
 654                             struct ib_device_attr *props)
 655 {
 656         u8 tmp;
 657         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 658         u8 atomic_req_8B_endianness_mode =
 659                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 660
 661         /* Check if HW supports 8 bytes standard atomic operations and capable
 662          * of host endianness respond
 663          */
 664         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 665         if (((atomic_operations & tmp) == tmp) &&
 666             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 667             (atomic_req_8B_endianness_mode)) {
 668                 props->atomic_cap = IB_ATOMIC_HCA;
 669         } else {
 670                 props->atomic_cap = IB_ATOMIC_NONE;
 671         }
 672 }
 673
 674 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 675                                struct ib_device_attr *props)
 676 {
 677         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 678
 679         get_atomic_caps(dev, atomic_size_qp, props);
 680 }
 681
 682 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 683                                         __be64 *sys_image_guid)
 684 {
 685         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 686         struct mlx5_core_dev *mdev = dev->mdev;
 687         u64 tmp;
 688         int err;
 689
 690         switch (mlx5_get_vport_access_method(ibdev)) {
 691         case MLX5_VPORT_ACCESS_METHOD_MAD:
 692                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 693                                                             sys_image_guid);
 694
 695         case MLX5_VPORT_ACCESS_METHOD_HCA:
 696                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 697                 break;
 698
 699         case MLX5_VPORT_ACCESS_METHOD_NIC:
 700                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 701                 break;
 702
 703         default:
 704                 return -EINVAL;
 705         }
 706
 707         if (!err)
 708                 *sys_image_guid = cpu_to_be64(tmp);
 709
 710         return err;
 711
 712 }
 713
 714 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 715                                 u16 *max_pkeys)
 716 {
 717         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 718         struct mlx5_core_dev *mdev = dev->mdev;
 719
 720         switch (mlx5_get_vport_access_method(ibdev)) {
 721         case MLX5_VPORT_ACCESS_METHOD_MAD:
 722                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 723
 724         case MLX5_VPORT_ACCESS_METHOD_HCA:
 725         case MLX5_VPORT_ACCESS_METHOD_NIC:
 726                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 727                                                 pkey_table_size));
 728                 return 0;
 729
 730         default:
 731                 return -EINVAL;
 732         }
 733 }
 734
 735 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 736                                 u32 *vendor_id)
 737 {
 738         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 739
 740         switch (mlx5_get_vport_access_method(ibdev)) {
 741         case MLX5_VPORT_ACCESS_METHOD_MAD:
 742                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 743
 744         case MLX5_VPORT_ACCESS_METHOD_HCA:
 745         case MLX5_VPORT_ACCESS_METHOD_NIC:
 746                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 747
 748         default:
 749                 return -EINVAL;
 750         }
 751 }
 752
 753 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 754                                 __be64 *node_guid)
 755 {
 756         u64 tmp;
 757         int err;
 758
 759         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 760         case MLX5_VPORT_ACCESS_METHOD_MAD:
 761                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 762
 763         case MLX5_VPORT_ACCESS_METHOD_HCA:
 764                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 765                 break;
 766
 767         case MLX5_VPORT_ACCESS_METHOD_NIC:
 768                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 769                 break;
 770
 771         default:
 772                 return -EINVAL;
 773         }
 774
 775         if (!err)
 776                 *node_guid = cpu_to_be64(tmp);
 777
 778         return err;
 779 }
 780
 781 struct mlx5_reg_node_desc {
 782         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 783 };
 784
 785 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 786 {
 787         struct mlx5_reg_node_desc in;
 788
 789         if (mlx5_use_mad_ifc(dev))
 790                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 791
 792         memset(&in, 0, sizeof(in));
 793
 794         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 795                                     sizeof(struct mlx5_reg_node_desc),
 796                                     MLX5_REG_NODE_DESC, 0, 0);
 797 }
 798
 799 static int mlx5_ib_query_device(struct ib_device *ibdev,
 800                                 struct ib_device_attr *props,
 801                                 struct ib_udata *uhw)
 802 {
 803         size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
 804         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 805         struct mlx5_core_dev *mdev = dev->mdev;
 806         int err = -ENOMEM;
 807         int max_sq_desc;
 808         int max_rq_sg;
 809         int max_sq_sg;
 810         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 811         bool raw_support = !mlx5_core_mp_enabled(mdev);
 812         struct mlx5_ib_query_device_resp resp = {};
 813         size_t resp_len;
 814         u64 max_tso;
 815
 816         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 817         if (uhw_outlen && uhw_outlen < resp_len)
 818                 return -EINVAL;
 819
 820         resp.response_length = resp_len;
 821
 822         if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 823                 return -EINVAL;
 824
 825         memset(props, 0, sizeof(*props));
 826         err = mlx5_query_system_image_guid(ibdev,
 827                                            &props->sys_image_guid);
 828         if (err)
 829                 return err;
 830
 831         props->max_pkeys = dev->pkey_table_len;
 832
 833         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 834         if (err)
 835                 return err;
 836
 837         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 838                 (fw_rev_min(dev->mdev) << 16) |
 839                 fw_rev_sub(dev->mdev);
 840         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 841                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 842                 IB_DEVICE_SYS_IMAGE_GUID                |
 843                 IB_DEVICE_RC_RNR_NAK_GEN;
 844
 845         if (MLX5_CAP_GEN(mdev, pkv))
 846                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 847         if (MLX5_CAP_GEN(mdev, qkv))
 848                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 849         if (MLX5_CAP_GEN(mdev, apm))
 850                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 851         if (MLX5_CAP_GEN(mdev, xrc))
 852                 props->device_cap_flags |= IB_DEVICE_XRC;
 853         if (MLX5_CAP_GEN(mdev, imaicl)) {
 854                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 855                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 856                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 857                 /* We support 'Gappy' memory registration too */
 858                 props->kernel_cap_flags |= IBK_SG_GAPS_REG;
 859         }
 860         /* IB_WR_REG_MR always requires changing the entity size with UMR */
 861         if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
 862                 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 863         if (MLX5_CAP_GEN(mdev, sho)) {
 864                 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER;
 865                 /* At this stage no support for signature handover */
 866                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 867                                       IB_PROT_T10DIF_TYPE_2 |
 868                                       IB_PROT_T10DIF_TYPE_3;
 869                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 870                                        IB_GUARD_T10DIF_CSUM;
 871         }
 872         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 873                 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK;
 874
 875         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 876                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 877                         /* Legacy bit to support old userspace libraries */
 878                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 879                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 880                 }
 881
 882                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 883                         props->raw_packet_caps |=
 884                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 885
 886                 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
 887                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 888                         if (max_tso) {
 889                                 resp.tso_caps.max_tso = 1 << max_tso;
 890                                 resp.tso_caps.supported_qpts |=
 891                                         1 << IB_QPT_RAW_PACKET;
 892                                 resp.response_length += sizeof(resp.tso_caps);
 893                         }
 894                 }
 895
 896                 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
 897                         resp.rss_caps.rx_hash_function =
 898                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 899                         resp.rss_caps.rx_hash_fields_mask =
 900                                                 MLX5_RX_HASH_SRC_IPV4 |
 901                                                 MLX5_RX_HASH_DST_IPV4 |
 902                                                 MLX5_RX_HASH_SRC_IPV6 |
 903                                                 MLX5_RX_HASH_DST_IPV6 |
 904                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 905                                                 MLX5_RX_HASH_DST_PORT_TCP |
 906                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 907                                                 MLX5_RX_HASH_DST_PORT_UDP |
 908                                                 MLX5_RX_HASH_INNER;
 909                         resp.response_length += sizeof(resp.rss_caps);
 910                 }
 911         } else {
 912                 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
 913                         resp.response_length += sizeof(resp.tso_caps);
 914                 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
 915                         resp.response_length += sizeof(resp.rss_caps);
 916         }
 917
 918         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 919                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 920                 props->kernel_cap_flags |= IBK_UD_TSO;
 921         }
 922
 923         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 924             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 925             raw_support)
 926                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 927
 928         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 929             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 930                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 931
 932         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 933             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 934             raw_support) {
 935                 /* Legacy bit to support old userspace libraries */
 936                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 937                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 938         }
 939
 940         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
 941                 props->max_dm_size =
 942                         MLX5_CAP_DEV_MEM(mdev, max_memic_size);
 943         }
 944
 945         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 946                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 947
 948         if (MLX5_CAP_GEN(mdev, end_pad))
 949                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 950
 951         props->vendor_part_id      = mdev->pdev->device;
 952         props->hw_ver              = mdev->pdev->revision;
 953
 954         props->max_mr_size         = ~0ull;
 955         props->page_size_cap       = ~(min_page_size - 1);
 956         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 957         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 958         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 959                      sizeof(struct mlx5_wqe_data_seg);
 960         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 961         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 962                      sizeof(struct mlx5_wqe_raddr_seg)) /
 963                 sizeof(struct mlx5_wqe_data_seg);
 964         props->max_send_sge = max_sq_sg;
 965         props->max_recv_sge = max_rq_sg;
 966         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 967         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 968         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 969         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 970         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 971         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 972         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 973         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 974         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 975         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 976         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 977         props->max_srq_sge         = max_rq_sg - 1;
 978         props->max_fast_reg_page_list_len =
 979                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 980         props->max_pi_fast_reg_page_list_len =
 981                 props->max_fast_reg_page_list_len / 2;
 982         props->max_sgl_rd =
 983                 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
 984         get_atomic_caps_qp(dev, props);
 985         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 986         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 987         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 988         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 989                                            props->max_mcast_grp;
 990         props->max_ah = INT_MAX;
 991         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 992         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 993
 994         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
 995                 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
 996                         props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING;
 997                 props->odp_caps = dev->odp_caps;
 998                 if (!uhw) {
 999                         /* ODP for kernel QPs is not implemented for receive
1000                          * WQEs and SRQ WQEs
1001                          */
1002                         props->odp_caps.per_transport_caps.rc_odp_caps &=
1003                                 ~(IB_ODP_SUPPORT_READ |
1004                                   IB_ODP_SUPPORT_SRQ_RECV);
1005                         props->odp_caps.per_transport_caps.uc_odp_caps &=
1006                                 ~(IB_ODP_SUPPORT_READ |
1007                                   IB_ODP_SUPPORT_SRQ_RECV);
1008                         props->odp_caps.per_transport_caps.ud_odp_caps &=
1009                                 ~(IB_ODP_SUPPORT_READ |
1010                                   IB_ODP_SUPPORT_SRQ_RECV);
1011                         props->odp_caps.per_transport_caps.xrc_odp_caps &=
1012                                 ~(IB_ODP_SUPPORT_READ |
1013                                   IB_ODP_SUPPORT_SRQ_RECV);
1014                 }
1015         }
1016
1017         if (mlx5_core_is_vf(mdev))
1018                 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION;
1019
1020         if (mlx5_ib_port_link_layer(ibdev, 1) ==
1021             IB_LINK_LAYER_ETHERNET && raw_support) {
1022                 props->rss_caps.max_rwq_indirection_tables =
1023                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1024                 props->rss_caps.max_rwq_indirection_table_size =
1025                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1026                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1027                 props->max_wq_type_rq =
1028                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1029         }
1030
1031         if (MLX5_CAP_GEN(mdev, tag_matching)) {
1032                 props->tm_caps.max_num_tags =
1033                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1034                 props->tm_caps.max_ops =
1035                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1036                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1037         }
1038
1039         if (MLX5_CAP_GEN(mdev, tag_matching) &&
1040             MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1041                 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1042                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1043         }
1044
1045         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1046                 props->cq_caps.max_cq_moderation_count =
1047                                                 MLX5_MAX_CQ_COUNT;
1048                 props->cq_caps.max_cq_moderation_period =
1049                                                 MLX5_MAX_CQ_PERIOD;
1050         }
1051
1052         if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
1053                 resp.response_length += sizeof(resp.cqe_comp_caps);
1054
1055                 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1056                         resp.cqe_comp_caps.max_num =
1057                                 MLX5_CAP_GEN(dev->mdev,
1058                                              cqe_compression_max_num);
1059
1060                         resp.cqe_comp_caps.supported_format =
1061                                 MLX5_IB_CQE_RES_FORMAT_HASH |
1062                                 MLX5_IB_CQE_RES_FORMAT_CSUM;
1063
1064                         if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1065                                 resp.cqe_comp_caps.supported_format |=
1066                                         MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1067                 }
1068         }
1069
1070         if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
1071             raw_support) {
1072                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1073                     MLX5_CAP_GEN(mdev, qos)) {
1074                         resp.packet_pacing_caps.qp_rate_limit_max =
1075                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1076                         resp.packet_pacing_caps.qp_rate_limit_min =
1077                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1078                         resp.packet_pacing_caps.supported_qpts |=
1079                                 1 << IB_QPT_RAW_PACKET;
1080                         if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1081                             MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1082                                 resp.packet_pacing_caps.cap_flags |=
1083                                         MLX5_IB_PP_SUPPORT_BURST;
1084                 }
1085                 resp.response_length += sizeof(resp.packet_pacing_caps);
1086         }
1087
1088         if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1089             uhw_outlen) {
1090                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1091                         resp.mlx5_ib_support_multi_pkt_send_wqes =
1092                                 MLX5_IB_ALLOW_MPW;
1093
1094                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1095                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
1096                                 MLX5_IB_SUPPORT_EMPW;
1097
1098                 resp.response_length +=
1099                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1100         }
1101
1102         if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
1103                 resp.response_length += sizeof(resp.flags);
1104
1105                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1106                         resp.flags |=
1107                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1108
1109                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1110                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1111                 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1112                         resp.flags |=
1113                                 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1114
1115                 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1116         }
1117
1118         if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
1119                 resp.response_length += sizeof(resp.sw_parsing_caps);
1120                 if (MLX5_CAP_ETH(mdev, swp)) {
1121                         resp.sw_parsing_caps.sw_parsing_offloads |=
1122                                 MLX5_IB_SW_PARSING;
1123
1124                         if (MLX5_CAP_ETH(mdev, swp_csum))
1125                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1126                                         MLX5_IB_SW_PARSING_CSUM;
1127
1128                         if (MLX5_CAP_ETH(mdev, swp_lso))
1129                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1130                                         MLX5_IB_SW_PARSING_LSO;
1131
1132                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1133                                 resp.sw_parsing_caps.supported_qpts =
1134                                         BIT(IB_QPT_RAW_PACKET);
1135                 }
1136         }
1137
1138         if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
1139             raw_support) {
1140                 resp.response_length += sizeof(resp.striding_rq_caps);
1141                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1142                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1143                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1144                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1145                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1146                         if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1147                                 resp.striding_rq_caps
1148                                         .min_single_wqe_log_num_of_strides =
1149                                         MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1150                         else
1151                                 resp.striding_rq_caps
1152                                         .min_single_wqe_log_num_of_strides =
1153                                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1154                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1155                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1156                         resp.striding_rq_caps.supported_qpts =
1157                                 BIT(IB_QPT_RAW_PACKET);
1158                 }
1159         }
1160
1161         if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
1162                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1163                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1164                         resp.tunnel_offloads_caps |=
1165                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1166                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1167                         resp.tunnel_offloads_caps |=
1168                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1169                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1170                         resp.tunnel_offloads_caps |=
1171                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1172                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1173                         resp.tunnel_offloads_caps |=
1174                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1175                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1176                         resp.tunnel_offloads_caps |=
1177                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1178         }
1179
1180         if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) {
1181                 resp.response_length += sizeof(resp.dci_streams_caps);
1182
1183                 resp.dci_streams_caps.max_log_num_concurent =
1184                         MLX5_CAP_GEN(mdev, log_max_dci_stream_channels);
1185
1186                 resp.dci_streams_caps.max_log_num_errored =
1187                         MLX5_CAP_GEN(mdev, log_max_dci_errored_streams);
1188         }
1189
1190         if (uhw_outlen) {
1191                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1192
1193                 if (err)
1194                         return err;
1195         }
1196
1197         return 0;
1198 }
1199
1200 static void translate_active_width(struct ib_device *ibdev, u16 active_width,
1201                                    u8 *ib_width)
1202 {
1203         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1204
1205         if (active_width & MLX5_PTYS_WIDTH_1X)
1206                 *ib_width = IB_WIDTH_1X;
1207         else if (active_width & MLX5_PTYS_WIDTH_2X)
1208                 *ib_width = IB_WIDTH_2X;
1209         else if (active_width & MLX5_PTYS_WIDTH_4X)
1210                 *ib_width = IB_WIDTH_4X;
1211         else if (active_width & MLX5_PTYS_WIDTH_8X)
1212                 *ib_width = IB_WIDTH_8X;
1213         else if (active_width & MLX5_PTYS_WIDTH_12X)
1214                 *ib_width = IB_WIDTH_12X;
1215         else {
1216                 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1217                             active_width);
1218                 *ib_width = IB_WIDTH_4X;
1219         }
1220
1221         return;
1222 }
1223
1224 static int mlx5_mtu_to_ib_mtu(int mtu)
1225 {
1226         switch (mtu) {
1227         case 256: return 1;
1228         case 512: return 2;
1229         case 1024: return 3;
1230         case 2048: return 4;
1231         case 4096: return 5;
1232         default:
1233                 pr_warn("invalid mtu\n");
1234                 return -1;
1235         }
1236 }
1237
1238 enum ib_max_vl_num {
1239         __IB_MAX_VL_0           = 1,
1240         __IB_MAX_VL_0_1         = 2,
1241         __IB_MAX_VL_0_3         = 3,
1242         __IB_MAX_VL_0_7         = 4,
1243         __IB_MAX_VL_0_14        = 5,
1244 };
1245
1246 enum mlx5_vl_hw_cap {
1247         MLX5_VL_HW_0    = 1,
1248         MLX5_VL_HW_0_1  = 2,
1249         MLX5_VL_HW_0_2  = 3,
1250         MLX5_VL_HW_0_3  = 4,
1251         MLX5_VL_HW_0_4  = 5,
1252         MLX5_VL_HW_0_5  = 6,
1253         MLX5_VL_HW_0_6  = 7,
1254         MLX5_VL_HW_0_7  = 8,
1255         MLX5_VL_HW_0_14 = 15
1256 };
1257
1258 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1259                                 u8 *max_vl_num)
1260 {
1261         switch (vl_hw_cap) {
1262         case MLX5_VL_HW_0:
1263                 *max_vl_num = __IB_MAX_VL_0;
1264                 break;
1265         case MLX5_VL_HW_0_1:
1266                 *max_vl_num = __IB_MAX_VL_0_1;
1267                 break;
1268         case MLX5_VL_HW_0_3:
1269                 *max_vl_num = __IB_MAX_VL_0_3;
1270                 break;
1271         case MLX5_VL_HW_0_7:
1272                 *max_vl_num = __IB_MAX_VL_0_7;
1273                 break;
1274         case MLX5_VL_HW_0_14:
1275                 *max_vl_num = __IB_MAX_VL_0_14;
1276                 break;
1277
1278         default:
1279                 return -EINVAL;
1280         }
1281
1282         return 0;
1283 }
1284
1285 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port,
1286                                struct ib_port_attr *props)
1287 {
1288         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1289         struct mlx5_core_dev *mdev = dev->mdev;
1290         struct mlx5_hca_vport_context *rep;
1291         u16 max_mtu;
1292         u16 oper_mtu;
1293         int err;
1294         u16 ib_link_width_oper;
1295         u8 vl_hw_cap;
1296
1297         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1298         if (!rep) {
1299                 err = -ENOMEM;
1300                 goto out;
1301         }
1302
1303         /* props being zeroed by the caller, avoid zeroing it here */
1304
1305         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1306         if (err)
1307                 goto out;
1308
1309         props->lid              = rep->lid;
1310         props->lmc              = rep->lmc;
1311         props->sm_lid           = rep->sm_lid;
1312         props->sm_sl            = rep->sm_sl;
1313         props->state            = rep->vport_state;
1314         props->phys_state       = rep->port_physical_state;
1315         props->port_cap_flags   = rep->cap_mask1;
1316         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1317         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1318         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1319         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1320         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1321         props->subnet_timeout   = rep->subnet_timeout;
1322         props->init_type_reply  = rep->init_type_reply;
1323
1324         if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1325                 props->port_cap_flags2 = rep->cap_mask2;
1326
1327         err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper,
1328                                       &props->active_speed, port);
1329         if (err)
1330                 goto out;
1331
1332         translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1333
1334         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1335
1336         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1337
1338         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1339
1340         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1341
1342         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1343         if (err)
1344                 goto out;
1345
1346         err = translate_max_vl_num(ibdev, vl_hw_cap,
1347                                    &props->max_vl_num);
1348 out:
1349         kfree(rep);
1350         return err;
1351 }
1352
1353 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1354                        struct ib_port_attr *props)
1355 {
1356         unsigned int count;
1357         int ret;
1358
1359         switch (mlx5_get_vport_access_method(ibdev)) {
1360         case MLX5_VPORT_ACCESS_METHOD_MAD:
1361                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1362                 break;
1363
1364         case MLX5_VPORT_ACCESS_METHOD_HCA:
1365                 ret = mlx5_query_hca_port(ibdev, port, props);
1366                 break;
1367
1368         case MLX5_VPORT_ACCESS_METHOD_NIC:
1369                 ret = mlx5_query_port_roce(ibdev, port, props);
1370                 break;
1371
1372         default:
1373                 ret = -EINVAL;
1374         }
1375
1376         if (!ret && props) {
1377                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1378                 struct mlx5_core_dev *mdev;
1379                 bool put_mdev = true;
1380
1381                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1382                 if (!mdev) {
1383                         /* If the port isn't affiliated yet query the master.
1384                          * The master and slave will have the same values.
1385                          */
1386                         mdev = dev->mdev;
1387                         port = 1;
1388                         put_mdev = false;
1389                 }
1390                 count = mlx5_core_reserved_gids_count(mdev);
1391                 if (put_mdev)
1392                         mlx5_ib_put_native_port_mdev(dev, port);
1393                 props->gid_tbl_len -= count;
1394         }
1395         return ret;
1396 }
1397
1398 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port,
1399                                   struct ib_port_attr *props)
1400 {
1401         return mlx5_query_port_roce(ibdev, port, props);
1402 }
1403
1404 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1405                                   u16 *pkey)
1406 {
1407         /* Default special Pkey for representor device port as per the
1408          * IB specification 1.3 section 10.9.1.2.
1409          */
1410         *pkey = 0xffff;
1411         return 0;
1412 }
1413
1414 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index,
1415                              union ib_gid *gid)
1416 {
1417         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1418         struct mlx5_core_dev *mdev = dev->mdev;
1419
1420         switch (mlx5_get_vport_access_method(ibdev)) {
1421         case MLX5_VPORT_ACCESS_METHOD_MAD:
1422                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1423
1424         case MLX5_VPORT_ACCESS_METHOD_HCA:
1425                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1426
1427         default:
1428                 return -EINVAL;
1429         }
1430
1431 }
1432
1433 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port,
1434                                    u16 index, u16 *pkey)
1435 {
1436         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1437         struct mlx5_core_dev *mdev;
1438         bool put_mdev = true;
1439         u32 mdev_port_num;
1440         int err;
1441
1442         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1443         if (!mdev) {
1444                 /* The port isn't affiliated yet, get the PKey from the master
1445                  * port. For RoCE the PKey tables will be the same.
1446                  */
1447                 put_mdev = false;
1448                 mdev = dev->mdev;
1449                 mdev_port_num = 1;
1450         }
1451
1452         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1453                                         index, pkey);
1454         if (put_mdev)
1455                 mlx5_ib_put_native_port_mdev(dev, port);
1456
1457         return err;
1458 }
1459
1460 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1461                               u16 *pkey)
1462 {
1463         switch (mlx5_get_vport_access_method(ibdev)) {
1464         case MLX5_VPORT_ACCESS_METHOD_MAD:
1465                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1466
1467         case MLX5_VPORT_ACCESS_METHOD_HCA:
1468         case MLX5_VPORT_ACCESS_METHOD_NIC:
1469                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1470         default:
1471                 return -EINVAL;
1472         }
1473 }
1474
1475 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1476                                  struct ib_device_modify *props)
1477 {
1478         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1479         struct mlx5_reg_node_desc in;
1480         struct mlx5_reg_node_desc out;
1481         int err;
1482
1483         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1484                 return -EOPNOTSUPP;
1485
1486         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1487                 return 0;
1488
1489         /*
1490          * If possible, pass node desc to FW, so it can generate
1491          * a 144 trap.  If cmd fails, just ignore.
1492          */
1493         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1494         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1495                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1496         if (err)
1497                 return err;
1498
1499         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1500
1501         return err;
1502 }
1503
1504 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask,
1505                                 u32 value)
1506 {
1507         struct mlx5_hca_vport_context ctx = {};
1508         struct mlx5_core_dev *mdev;
1509         u32 mdev_port_num;
1510         int err;
1511
1512         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1513         if (!mdev)
1514                 return -ENODEV;
1515
1516         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1517         if (err)
1518                 goto out;
1519
1520         if (~ctx.cap_mask1_perm & mask) {
1521                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1522                              mask, ctx.cap_mask1_perm);
1523                 err = -EINVAL;
1524                 goto out;
1525         }
1526
1527         ctx.cap_mask1 = value;
1528         ctx.cap_mask1_perm = mask;
1529         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1530                                                  0, &ctx);
1531
1532 out:
1533         mlx5_ib_put_native_port_mdev(dev, port_num);
1534
1535         return err;
1536 }
1537
1538 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask,
1539                                struct ib_port_modify *props)
1540 {
1541         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1542         struct ib_port_attr attr;
1543         u32 tmp;
1544         int err;
1545         u32 change_mask;
1546         u32 value;
1547         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1548                       IB_LINK_LAYER_INFINIBAND);
1549
1550         /* CM layer calls ib_modify_port() regardless of the link layer. For
1551          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1552          */
1553         if (!is_ib)
1554                 return 0;
1555
1556         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1557                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1558                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1559                 return set_port_caps_atomic(dev, port, change_mask, value);
1560         }
1561
1562         mutex_lock(&dev->cap_mask_mutex);
1563
1564         err = ib_query_port(ibdev, port, &attr);
1565         if (err)
1566                 goto out;
1567
1568         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1569                 ~props->clr_port_cap_mask;
1570
1571         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1572
1573 out:
1574         mutex_unlock(&dev->cap_mask_mutex);
1575         return err;
1576 }
1577
1578 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1579 {
1580         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1581                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1582 }
1583
1584 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1585 {
1586         /* Large page with non 4k uar support might limit the dynamic size */
1587         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1588                 return MLX5_MIN_DYN_BFREGS;
1589
1590         return MLX5_MAX_DYN_BFREGS;
1591 }
1592
1593 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1594                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1595                              struct mlx5_bfreg_info *bfregi)
1596 {
1597         int uars_per_sys_page;
1598         int bfregs_per_sys_page;
1599         int ref_bfregs = req->total_num_bfregs;
1600
1601         if (req->total_num_bfregs == 0)
1602                 return -EINVAL;
1603
1604         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1605         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1606
1607         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1608                 return -ENOMEM;
1609
1610         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1611         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1612         /* This holds the required static allocation asked by the user */
1613         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1614         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1615                 return -EINVAL;
1616
1617         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1618         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1619         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1620         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1621
1622         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1623                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1624                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1625                     req->total_num_bfregs, bfregi->total_num_bfregs,
1626                     bfregi->num_sys_pages);
1627
1628         return 0;
1629 }
1630
1631 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1632 {
1633         struct mlx5_bfreg_info *bfregi;
1634         int err;
1635         int i;
1636
1637         bfregi = &context->bfregi;
1638         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1639                 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i],
1640                                          context->devx_uid);
1641                 if (err)
1642                         goto error;
1643
1644                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1645         }
1646
1647         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1648                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1649
1650         return 0;
1651
1652 error:
1653         for (--i; i >= 0; i--)
1654                 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i],
1655                                          context->devx_uid))
1656                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1657
1658         return err;
1659 }
1660
1661 static void deallocate_uars(struct mlx5_ib_dev *dev,
1662                             struct mlx5_ib_ucontext *context)
1663 {
1664         struct mlx5_bfreg_info *bfregi;
1665         int i;
1666
1667         bfregi = &context->bfregi;
1668         for (i = 0; i < bfregi->num_sys_pages; i++)
1669                 if (i < bfregi->num_static_sys_pages ||
1670                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1671                         mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i],
1672                                              context->devx_uid);
1673 }
1674
1675 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1676 {
1677         int err = 0;
1678
1679         mutex_lock(&dev->lb.mutex);
1680         if (td)
1681                 dev->lb.user_td++;
1682         if (qp)
1683                 dev->lb.qps++;
1684
1685         if (dev->lb.user_td == 2 ||
1686             dev->lb.qps == 1) {
1687                 if (!dev->lb.enabled) {
1688                         err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1689                         dev->lb.enabled = true;
1690                 }
1691         }
1692
1693         mutex_unlock(&dev->lb.mutex);
1694
1695         return err;
1696 }
1697
1698 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1699 {
1700         mutex_lock(&dev->lb.mutex);
1701         if (td)
1702                 dev->lb.user_td--;
1703         if (qp)
1704                 dev->lb.qps--;
1705
1706         if (dev->lb.user_td == 1 &&
1707             dev->lb.qps == 0) {
1708                 if (dev->lb.enabled) {
1709                         mlx5_nic_vport_update_local_lb(dev->mdev, false);
1710                         dev->lb.enabled = false;
1711                 }
1712         }
1713
1714         mutex_unlock(&dev->lb.mutex);
1715 }
1716
1717 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1718                                           u16 uid)
1719 {
1720         int err;
1721
1722         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1723                 return 0;
1724
1725         err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1726         if (err)
1727                 return err;
1728
1729         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1730             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1731              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1732                 return err;
1733
1734         return mlx5_ib_enable_lb(dev, true, false);
1735 }
1736
1737 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1738                                              u16 uid)
1739 {
1740         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1741                 return;
1742
1743         mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1744
1745         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1746             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1747              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1748                 return;
1749
1750         mlx5_ib_disable_lb(dev, true, false);
1751 }
1752
1753 static int set_ucontext_resp(struct ib_ucontext *uctx,
1754                              struct mlx5_ib_alloc_ucontext_resp *resp)
1755 {
1756         struct ib_device *ibdev = uctx->device;
1757         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1758         struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1759         struct mlx5_bfreg_info *bfregi = &context->bfregi;
1760         int err;
1761
1762         if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1763                 err = mlx5_cmd_dump_fill_mkey(dev->mdev,
1764                                               &resp->dump_fill_mkey);
1765                 if (err)
1766                         return err;
1767                 resp->comp_mask |=
1768                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1769         }
1770
1771         resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1772         if (dev->wc_support)
1773                 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev,
1774                                                       log_bf_reg_size);
1775         resp->cache_line_size = cache_line_size();
1776         resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1777         resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1778         resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1779         resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1780         resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1781         resp->cqe_version = context->cqe_version;
1782         resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1783                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1784         resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1785                                         MLX5_CAP_GEN(dev->mdev,
1786                                                      num_of_uars_per_page) : 1;
1787         resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 :
1788                         bfregi->total_num_bfregs - bfregi->num_dyn_bfregs;
1789         resp->num_ports = dev->num_ports;
1790         resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1791                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1792
1793         if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1794                 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline);
1795                 resp->eth_min_inline++;
1796         }
1797
1798         if (dev->mdev->clock_info)
1799                 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1800
1801         /*
1802          * We don't want to expose information from the PCI bar that is located
1803          * after 4096 bytes, so if the arch only supports larger pages, let's
1804          * pretend we don't support reading the HCA's core clock. This is also
1805          * forced by mmap function.
1806          */
1807         if (PAGE_SIZE <= 4096) {
1808                 resp->comp_mask |=
1809                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1810                 resp->hca_core_clock_offset =
1811                         offsetof(struct mlx5_init_seg,
1812                                  internal_timer_h) % PAGE_SIZE;
1813         }
1814
1815         if (MLX5_CAP_GEN(dev->mdev, ece_support))
1816                 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
1817
1818         if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) &&
1819             rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) &&
1820             rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format)))
1821                 resp->comp_mask |=
1822                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS;
1823
1824         resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
1825
1826         if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
1827                 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
1828
1829         return 0;
1830 }
1831
1832 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1833                                   struct ib_udata *udata)
1834 {
1835         struct ib_device *ibdev = uctx->device;
1836         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1837         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1838         struct mlx5_ib_alloc_ucontext_resp resp = {};
1839         struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1840         struct mlx5_bfreg_info *bfregi;
1841         int ver;
1842         int err;
1843         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1844                                      max_cqe_version);
1845         bool lib_uar_4k;
1846         bool lib_uar_dyn;
1847
1848         if (!dev->ib_active)
1849                 return -EAGAIN;
1850
1851         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1852                 ver = 0;
1853         else if (udata->inlen >= min_req_v2)
1854                 ver = 2;
1855         else
1856                 return -EINVAL;
1857
1858         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1859         if (err)
1860                 return err;
1861
1862         if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1863                 return -EOPNOTSUPP;
1864
1865         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1866                 return -EOPNOTSUPP;
1867
1868         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1869                                     MLX5_NON_FP_BFREGS_PER_UAR);
1870         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1871                 return -EINVAL;
1872
1873         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1874                 err = mlx5_ib_devx_create(dev, true);
1875                 if (err < 0)
1876                         goto out_ctx;
1877                 context->devx_uid = err;
1878         }
1879
1880         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1881         lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
1882         bfregi = &context->bfregi;
1883
1884         if (lib_uar_dyn) {
1885                 bfregi->lib_uar_dyn = lib_uar_dyn;
1886                 goto uar_done;
1887         }
1888
1889         /* updates req->total_num_bfregs */
1890         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1891         if (err)
1892                 goto out_devx;
1893
1894         mutex_init(&bfregi->lock);
1895         bfregi->lib_uar_4k = lib_uar_4k;
1896         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1897                                 GFP_KERNEL);
1898         if (!bfregi->count) {
1899                 err = -ENOMEM;
1900                 goto out_devx;
1901         }
1902
1903         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1904                                     sizeof(*bfregi->sys_pages),
1905                                     GFP_KERNEL);
1906         if (!bfregi->sys_pages) {
1907                 err = -ENOMEM;
1908                 goto out_count;
1909         }
1910
1911         err = allocate_uars(dev, context);
1912         if (err)
1913                 goto out_sys_pages;
1914
1915 uar_done:
1916         err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1917                                              context->devx_uid);
1918         if (err)
1919                 goto out_uars;
1920
1921         INIT_LIST_HEAD(&context->db_page_list);
1922         mutex_init(&context->db_page_mutex);
1923
1924         context->cqe_version = min_t(__u8,
1925                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1926                                  req.max_cqe_version);
1927
1928         err = set_ucontext_resp(uctx, &resp);
1929         if (err)
1930                 goto out_mdev;
1931
1932         resp.response_length = min(udata->outlen, sizeof(resp));
1933         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1934         if (err)
1935                 goto out_mdev;
1936
1937         bfregi->ver = ver;
1938         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1939         context->lib_caps = req.lib_caps;
1940         print_lib_caps(dev, context->lib_caps);
1941
1942         if (mlx5_ib_lag_should_assign_affinity(dev)) {
1943                 u32 port = mlx5_core_native_port_num(dev->mdev) - 1;
1944
1945                 atomic_set(&context->tx_port_affinity,
1946                            atomic_add_return(
1947                                    1, &dev->port[port].roce.tx_port_affinity));
1948         }
1949
1950         return 0;
1951
1952 out_mdev:
1953         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1954
1955 out_uars:
1956         deallocate_uars(dev, context);
1957
1958 out_sys_pages:
1959         kfree(bfregi->sys_pages);
1960
1961 out_count:
1962         kfree(bfregi->count);
1963
1964 out_devx:
1965         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1966                 mlx5_ib_devx_destroy(dev, context->devx_uid);
1967
1968 out_ctx:
1969         return err;
1970 }
1971
1972 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext,
1973                                   struct uverbs_attr_bundle *attrs)
1974 {
1975         struct mlx5_ib_alloc_ucontext_resp uctx_resp = {};
1976         int ret;
1977
1978         ret = set_ucontext_resp(ibcontext, &uctx_resp);
1979         if (ret)
1980                 return ret;
1981
1982         uctx_resp.response_length =
1983                 min_t(size_t,
1984                       uverbs_attr_get_len(attrs,
1985                                 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX),
1986                       sizeof(uctx_resp));
1987
1988         ret = uverbs_copy_to_struct_or_zero(attrs,
1989                                         MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
1990                                         &uctx_resp,
1991                                         sizeof(uctx_resp));
1992         return ret;
1993 }
1994
1995 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1996 {
1997         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1998         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1999         struct mlx5_bfreg_info *bfregi;
2000
2001         bfregi = &context->bfregi;
2002         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2003
2004         deallocate_uars(dev, context);
2005         kfree(bfregi->sys_pages);
2006         kfree(bfregi->count);
2007
2008         if (context->devx_uid)
2009                 mlx5_ib_devx_destroy(dev, context->devx_uid);
2010 }
2011
2012 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2013                                  int uar_idx)
2014 {
2015         int fw_uars_per_page;
2016
2017         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2018
2019         return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2020 }
2021
2022 static u64 uar_index2paddress(struct mlx5_ib_dev *dev,
2023                                  int uar_idx)
2024 {
2025         unsigned int fw_uars_per_page;
2026
2027         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2028                                 MLX5_UARS_IN_PAGE : 1;
2029
2030         return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2031 }
2032
2033 static int get_command(unsigned long offset)
2034 {
2035         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2036 }
2037
2038 static int get_arg(unsigned long offset)
2039 {
2040         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2041 }
2042
2043 static int get_index(unsigned long offset)
2044 {
2045         return get_arg(offset);
2046 }
2047
2048 /* Index resides in an extra byte to enable larger values than 255 */
2049 static int get_extended_index(unsigned long offset)
2050 {
2051         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2052 }
2053
2054
2055 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2056 {
2057 }
2058
2059 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2060 {
2061         switch (cmd) {
2062         case MLX5_IB_MMAP_WC_PAGE:
2063                 return "WC";
2064         case MLX5_IB_MMAP_REGULAR_PAGE:
2065                 return "best effort WC";
2066         case MLX5_IB_MMAP_NC_PAGE:
2067                 return "NC";
2068         case MLX5_IB_MMAP_DEVICE_MEM:
2069                 return "Device Memory";
2070         default:
2071                 return NULL;
2072         }
2073 }
2074
2075 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2076                                         struct vm_area_struct *vma,
2077                                         struct mlx5_ib_ucontext *context)
2078 {
2079         if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2080             !(vma->vm_flags & VM_SHARED))
2081                 return -EINVAL;
2082
2083         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2084                 return -EOPNOTSUPP;
2085
2086         if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2087                 return -EPERM;
2088         vma->vm_flags &= ~VM_MAYWRITE;
2089
2090         if (!dev->mdev->clock_info)
2091                 return -EOPNOTSUPP;
2092
2093         return vm_insert_page(vma, vma->vm_start,
2094                               virt_to_page(dev->mdev->clock_info));
2095 }
2096
2097 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2098 {
2099         struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2100         struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
2101         struct mlx5_var_table *var_table = &dev->var_table;
2102         struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext);
2103
2104         switch (mentry->mmap_flag) {
2105         case MLX5_IB_MMAP_TYPE_MEMIC:
2106         case MLX5_IB_MMAP_TYPE_MEMIC_OP:
2107                 mlx5_ib_dm_mmap_free(dev, mentry);
2108                 break;
2109         case MLX5_IB_MMAP_TYPE_VAR:
2110                 mutex_lock(&var_table->bitmap_lock);
2111                 clear_bit(mentry->page_idx, var_table->bitmap);
2112                 mutex_unlock(&var_table->bitmap_lock);
2113                 kfree(mentry);
2114                 break;
2115         case MLX5_IB_MMAP_TYPE_UAR_WC:
2116         case MLX5_IB_MMAP_TYPE_UAR_NC:
2117                 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx,
2118                                      context->devx_uid);
2119                 kfree(mentry);
2120                 break;
2121         default:
2122                 WARN_ON(true);
2123         }
2124 }
2125
2126 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2127                     struct vm_area_struct *vma,
2128                     struct mlx5_ib_ucontext *context)
2129 {
2130         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2131         int err;
2132         unsigned long idx;
2133         phys_addr_t pfn;
2134         pgprot_t prot;
2135         u32 bfreg_dyn_idx = 0;
2136         u32 uar_index;
2137         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2138         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2139                                 bfregi->num_static_sys_pages;
2140
2141         if (bfregi->lib_uar_dyn)
2142                 return -EINVAL;
2143
2144         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2145                 return -EINVAL;
2146
2147         if (dyn_uar)
2148                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2149         else
2150                 idx = get_index(vma->vm_pgoff);
2151
2152         if (idx >= max_valid_idx) {
2153                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2154                              idx, max_valid_idx);
2155                 return -EINVAL;
2156         }
2157
2158         switch (cmd) {
2159         case MLX5_IB_MMAP_WC_PAGE:
2160         case MLX5_IB_MMAP_ALLOC_WC:
2161         case MLX5_IB_MMAP_REGULAR_PAGE:
2162                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2163                 prot = pgprot_writecombine(vma->vm_page_prot);
2164                 break;
2165         case MLX5_IB_MMAP_NC_PAGE:
2166                 prot = pgprot_noncached(vma->vm_page_prot);
2167                 break;
2168         default:
2169                 return -EINVAL;
2170         }
2171
2172         if (dyn_uar) {
2173                 int uars_per_page;
2174
2175                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2176                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2177                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2178                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2179                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2180                         return -EINVAL;
2181                 }
2182
2183                 mutex_lock(&bfregi->lock);
2184                 /* Fail if uar already allocated, first bfreg index of each
2185                  * page holds its count.
2186                  */
2187                 if (bfregi->count[bfreg_dyn_idx]) {
2188                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2189                         mutex_unlock(&bfregi->lock);
2190                         return -EINVAL;
2191                 }
2192
2193                 bfregi->count[bfreg_dyn_idx]++;
2194                 mutex_unlock(&bfregi->lock);
2195
2196                 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index,
2197                                          context->devx_uid);
2198                 if (err) {
2199                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2200                         goto free_bfreg;
2201                 }
2202         } else {
2203                 uar_index = bfregi->sys_pages[idx];
2204         }
2205
2206         pfn = uar_index2pfn(dev, uar_index);
2207         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2208
2209         err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2210                                 prot, NULL);
2211         if (err) {
2212                 mlx5_ib_err(dev,
2213                             "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2214                             err, mmap_cmd2str(cmd));
2215                 goto err;
2216         }
2217
2218         if (dyn_uar)
2219                 bfregi->sys_pages[idx] = uar_index;
2220         return 0;
2221
2222 err:
2223         if (!dyn_uar)
2224                 return err;
2225
2226         mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid);
2227
2228 free_bfreg:
2229         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2230
2231         return err;
2232 }
2233
2234 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2235 {
2236         unsigned long idx;
2237         u8 command;
2238
2239         command = get_command(vma->vm_pgoff);
2240         idx = get_extended_index(vma->vm_pgoff);
2241
2242         return (command << 16 | idx);
2243 }
2244
2245 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2246                                struct vm_area_struct *vma,
2247                                struct ib_ucontext *ucontext)
2248 {
2249         struct mlx5_user_mmap_entry *mentry;
2250         struct rdma_user_mmap_entry *entry;
2251         unsigned long pgoff;
2252         pgprot_t prot;
2253         phys_addr_t pfn;
2254         int ret;
2255
2256         pgoff = mlx5_vma_to_pgoff(vma);
2257         entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2258         if (!entry)
2259                 return -EINVAL;
2260
2261         mentry = to_mmmap(entry);
2262         pfn = (mentry->address >> PAGE_SHIFT);
2263         if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
2264             mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
2265                 prot = pgprot_noncached(vma->vm_page_prot);
2266         else
2267                 prot = pgprot_writecombine(vma->vm_page_prot);
2268         ret = rdma_user_mmap_io(ucontext, vma, pfn,
2269                                 entry->npages * PAGE_SIZE,
2270                                 prot,
2271                                 entry);
2272         rdma_user_mmap_entry_put(&mentry->rdma_entry);
2273         return ret;
2274 }
2275
2276 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2277 {
2278         u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2279         u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
2280
2281         return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2282                 (index & 0xFF)) << PAGE_SHIFT;
2283 }
2284
2285 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2286 {
2287         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2288         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2289         unsigned long command;
2290         phys_addr_t pfn;
2291
2292         command = get_command(vma->vm_pgoff);
2293         switch (command) {
2294         case MLX5_IB_MMAP_WC_PAGE:
2295         case MLX5_IB_MMAP_ALLOC_WC:
2296                 if (!dev->wc_support)
2297                         return -EPERM;
2298                 fallthrough;
2299         case MLX5_IB_MMAP_NC_PAGE:
2300         case MLX5_IB_MMAP_REGULAR_PAGE:
2301                 return uar_mmap(dev, command, vma, context);
2302
2303         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2304                 return -ENOSYS;
2305
2306         case MLX5_IB_MMAP_CORE_CLOCK:
2307                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2308                         return -EINVAL;
2309
2310                 if (vma->vm_flags & VM_WRITE)
2311                         return -EPERM;
2312                 vma->vm_flags &= ~VM_MAYWRITE;
2313
2314                 /* Don't expose to user-space information it shouldn't have */
2315                 if (PAGE_SIZE > 4096)
2316                         return -EOPNOTSUPP;
2317
2318                 pfn = (dev->mdev->iseg_base +
2319                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2320                         PAGE_SHIFT;
2321                 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2322                                          PAGE_SIZE,
2323                                          pgprot_noncached(vma->vm_page_prot),
2324                                          NULL);
2325         case MLX5_IB_MMAP_CLOCK_INFO:
2326                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2327
2328         default:
2329                 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
2330         }
2331
2332         return 0;
2333 }
2334
2335 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2336 {
2337         struct mlx5_ib_pd *pd = to_mpd(ibpd);
2338         struct ib_device *ibdev = ibpd->device;
2339         struct mlx5_ib_alloc_pd_resp resp;
2340         int err;
2341         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2342         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2343         u16 uid = 0;
2344         struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2345                 udata, struct mlx5_ib_ucontext, ibucontext);
2346
2347         uid = context ? context->devx_uid : 0;
2348         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2349         MLX5_SET(alloc_pd_in, in, uid, uid);
2350         err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out);
2351         if (err)
2352                 return err;
2353
2354         pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2355         pd->uid = uid;
2356         if (udata) {
2357                 resp.pdn = pd->pdn;
2358                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2359                         mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2360                         return -EFAULT;
2361                 }
2362         }
2363
2364         return 0;
2365 }
2366
2367 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2368 {
2369         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2370         struct mlx5_ib_pd *mpd = to_mpd(pd);
2371
2372         return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2373 }
2374
2375 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2376 {
2377         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2378         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
2379         int err;
2380         u16 uid;
2381
2382         uid = ibqp->pd ?
2383                 to_mpd(ibqp->pd)->uid : 0;
2384
2385         if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) {
2386                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2387                 return -EOPNOTSUPP;
2388         }
2389
2390         err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2391         if (err)
2392                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2393                              ibqp->qp_num, gid->raw);
2394
2395         return err;
2396 }
2397
2398 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2399 {
2400         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2401         int err;
2402         u16 uid;
2403
2404         uid = ibqp->pd ?
2405                 to_mpd(ibqp->pd)->uid : 0;
2406         err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2407         if (err)
2408                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2409                              ibqp->qp_num, gid->raw);
2410
2411         return err;
2412 }
2413
2414 static int init_node_data(struct mlx5_ib_dev *dev)
2415 {
2416         int err;
2417
2418         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2419         if (err)
2420                 return err;
2421
2422         dev->mdev->rev_id = dev->mdev->pdev->revision;
2423
2424         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2425 }
2426
2427 static ssize_t fw_pages_show(struct device *device,
2428                              struct device_attribute *attr, char *buf)
2429 {
2430         struct mlx5_ib_dev *dev =
2431                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2432
2433         return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages);
2434 }
2435 static DEVICE_ATTR_RO(fw_pages);
2436
2437 static ssize_t reg_pages_show(struct device *device,
2438                               struct device_attribute *attr, char *buf)
2439 {
2440         struct mlx5_ib_dev *dev =
2441                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2442
2443         return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2444 }
2445 static DEVICE_ATTR_RO(reg_pages);
2446
2447 static ssize_t hca_type_show(struct device *device,
2448                              struct device_attribute *attr, char *buf)
2449 {
2450         struct mlx5_ib_dev *dev =
2451                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2452
2453         return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device);
2454 }
2455 static DEVICE_ATTR_RO(hca_type);
2456
2457 static ssize_t hw_rev_show(struct device *device,
2458                            struct device_attribute *attr, char *buf)
2459 {
2460         struct mlx5_ib_dev *dev =
2461                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2462
2463         return sysfs_emit(buf, "%x\n", dev->mdev->rev_id);
2464 }
2465 static DEVICE_ATTR_RO(hw_rev);
2466
2467 static ssize_t board_id_show(struct device *device,
2468                              struct device_attribute *attr, char *buf)
2469 {
2470         struct mlx5_ib_dev *dev =
2471                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2472
2473         return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2474                           dev->mdev->board_id);
2475 }
2476 static DEVICE_ATTR_RO(board_id);
2477
2478 static struct attribute *mlx5_class_attributes[] = {
2479         &dev_attr_hw_rev.attr,
2480         &dev_attr_hca_type.attr,
2481         &dev_attr_board_id.attr,
2482         &dev_attr_fw_pages.attr,
2483         &dev_attr_reg_pages.attr,
2484         NULL,
2485 };
2486
2487 static const struct attribute_group mlx5_attr_group = {
2488         .attrs = mlx5_class_attributes,
2489 };
2490
2491 static void pkey_change_handler(struct work_struct *work)
2492 {
2493         struct mlx5_ib_port_resources *ports =
2494                 container_of(work, struct mlx5_ib_port_resources,
2495                              pkey_change_work);
2496
2497         if (!ports->gsi)
2498                 /*
2499                  * We got this event before device was fully configured
2500                  * and MAD registration code wasn't called/finished yet.
2501                  */
2502                 return;
2503
2504         mlx5_ib_gsi_pkey_change(ports->gsi);
2505 }
2506
2507 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2508 {
2509         struct mlx5_ib_qp *mqp;
2510         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2511         struct mlx5_core_cq *mcq;
2512         struct list_head cq_armed_list;
2513         unsigned long flags_qp;
2514         unsigned long flags_cq;
2515         unsigned long flags;
2516
2517         INIT_LIST_HEAD(&cq_armed_list);
2518
2519         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2520         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2521         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2522                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2523                 if (mqp->sq.tail != mqp->sq.head) {
2524                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2525                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2526                         if (send_mcq->mcq.comp &&
2527                             mqp->ibqp.send_cq->comp_handler) {
2528                                 if (!send_mcq->mcq.reset_notify_added) {
2529                                         send_mcq->mcq.reset_notify_added = 1;
2530                                         list_add_tail(&send_mcq->mcq.reset_notify,
2531                                                       &cq_armed_list);
2532                                 }
2533                         }
2534                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2535                 }
2536                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2537                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2538                 /* no handling is needed for SRQ */
2539                 if (!mqp->ibqp.srq) {
2540                         if (mqp->rq.tail != mqp->rq.head) {
2541                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2542                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2543                                 if (recv_mcq->mcq.comp &&
2544                                     mqp->ibqp.recv_cq->comp_handler) {
2545                                         if (!recv_mcq->mcq.reset_notify_added) {
2546                                                 recv_mcq->mcq.reset_notify_added = 1;
2547                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2548                                                               &cq_armed_list);
2549                                         }
2550                                 }
2551                                 spin_unlock_irqrestore(&recv_mcq->lock,
2552                                                        flags_cq);
2553                         }
2554                 }
2555                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2556         }
2557         /*At that point all inflight post send were put to be executed as of we
2558          * lock/unlock above locks Now need to arm all involved CQs.
2559          */
2560         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2561                 mcq->comp(mcq, NULL);
2562         }
2563         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2564 }
2565
2566 static void delay_drop_handler(struct work_struct *work)
2567 {
2568         int err;
2569         struct mlx5_ib_delay_drop *delay_drop =
2570                 container_of(work, struct mlx5_ib_delay_drop,
2571                              delay_drop_work);
2572
2573         atomic_inc(&delay_drop->events_cnt);
2574
2575         mutex_lock(&delay_drop->lock);
2576         err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout);
2577         if (err) {
2578                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2579                              delay_drop->timeout);
2580                 delay_drop->activate = false;
2581         }
2582         mutex_unlock(&delay_drop->lock);
2583 }
2584
2585 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2586                                  struct ib_event *ibev)
2587 {
2588         u32 port = (eqe->data.port.port >> 4) & 0xf;
2589
2590         switch (eqe->sub_type) {
2591         case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
2592                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2593                                             IB_LINK_LAYER_ETHERNET)
2594                         schedule_work(&ibdev->delay_drop.delay_drop_work);
2595                 break;
2596         default: /* do nothing */
2597                 return;
2598         }
2599 }
2600
2601 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2602                               struct ib_event *ibev)
2603 {
2604         u32 port = (eqe->data.port.port >> 4) & 0xf;
2605
2606         ibev->element.port_num = port;
2607
2608         switch (eqe->sub_type) {
2609         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
2610         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
2611         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
2612                 /* In RoCE, port up/down events are handled in
2613                  * mlx5_netdev_event().
2614                  */
2615                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2616                                             IB_LINK_LAYER_ETHERNET)
2617                         return -EINVAL;
2618
2619                 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
2620                                 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2621                 break;
2622
2623         case MLX5_PORT_CHANGE_SUBTYPE_LID:
2624                 ibev->event = IB_EVENT_LID_CHANGE;
2625                 break;
2626
2627         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
2628                 ibev->event = IB_EVENT_PKEY_CHANGE;
2629                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2630                 break;
2631
2632         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
2633                 ibev->event = IB_EVENT_GID_CHANGE;
2634                 break;
2635
2636         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
2637                 ibev->event = IB_EVENT_CLIENT_REREGISTER;
2638                 break;
2639         default:
2640                 return -EINVAL;
2641         }
2642
2643         return 0;
2644 }
2645
2646 static void mlx5_ib_handle_event(struct work_struct *_work)
2647 {
2648         struct mlx5_ib_event_work *work =
2649                 container_of(_work, struct mlx5_ib_event_work, work);
2650         struct mlx5_ib_dev *ibdev;
2651         struct ib_event ibev;
2652         bool fatal = false;
2653
2654         if (work->is_slave) {
2655                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
2656                 if (!ibdev)
2657                         goto out;
2658         } else {
2659                 ibdev = work->dev;
2660         }
2661
2662         switch (work->event) {
2663         case MLX5_DEV_EVENT_SYS_ERROR:
2664                 ibev.event = IB_EVENT_DEVICE_FATAL;
2665                 mlx5_ib_handle_internal_error(ibdev);
2666                 ibev.element.port_num  = (u8)(unsigned long)work->param;
2667                 fatal = true;
2668                 break;
2669         case MLX5_EVENT_TYPE_PORT_CHANGE:
2670                 if (handle_port_change(ibdev, work->param, &ibev))
2671                         goto out;
2672                 break;
2673         case MLX5_EVENT_TYPE_GENERAL_EVENT:
2674                 handle_general_event(ibdev, work->param, &ibev);
2675                 fallthrough;
2676         default:
2677                 goto out;
2678         }
2679
2680         ibev.device = &ibdev->ib_dev;
2681
2682         if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
2683                 mlx5_ib_warn(ibdev, "warning: event on port %d\n",  ibev.element.port_num);
2684                 goto out;
2685         }
2686
2687         if (ibdev->ib_active)
2688                 ib_dispatch_event(&ibev);
2689
2690         if (fatal)
2691                 ibdev->ib_active = false;
2692 out:
2693         kfree(work);
2694 }
2695
2696 static int mlx5_ib_event(struct notifier_block *nb,
2697                          unsigned long event, void *param)
2698 {
2699         struct mlx5_ib_event_work *work;
2700
2701         work = kmalloc(sizeof(*work), GFP_ATOMIC);
2702         if (!work)
2703                 return NOTIFY_DONE;
2704
2705         INIT_WORK(&work->work, mlx5_ib_handle_event);
2706         work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
2707         work->is_slave = false;
2708         work->param = param;
2709         work->event = event;
2710
2711         queue_work(mlx5_ib_event_wq, &work->work);
2712
2713         return NOTIFY_OK;
2714 }
2715
2716 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
2717                                     unsigned long event, void *param)
2718 {
2719         struct mlx5_ib_event_work *work;
2720
2721         work = kmalloc(sizeof(*work), GFP_ATOMIC);
2722         if (!work)
2723                 return NOTIFY_DONE;
2724
2725         INIT_WORK(&work->work, mlx5_ib_handle_event);
2726         work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
2727         work->is_slave = true;
2728         work->param = param;
2729         work->event = event;
2730         queue_work(mlx5_ib_event_wq, &work->work);
2731
2732         return NOTIFY_OK;
2733 }
2734
2735 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2736 {
2737         struct mlx5_hca_vport_context vport_ctx;
2738         int err;
2739         int port;
2740
2741         for (port = 1; port <= ARRAY_SIZE(dev->port_caps); port++) {
2742                 dev->port_caps[port - 1].has_smi = false;
2743                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2744                     MLX5_CAP_PORT_TYPE_IB) {
2745                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2746                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2747                                                                    port, 0,
2748                                                                    &vport_ctx);
2749                                 if (err) {
2750                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2751                                                     port, err);
2752                                         return err;
2753                                 }
2754                                 dev->port_caps[port - 1].has_smi =
2755                                         vport_ctx.has_smi;
2756                         } else {
2757                                 dev->port_caps[port - 1].has_smi = true;
2758                         }
2759                 }
2760         }
2761         return 0;
2762 }
2763
2764 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2765 {
2766         unsigned int port;
2767
2768         rdma_for_each_port (&dev->ib_dev, port)
2769                 mlx5_query_ext_port_caps(dev, port);
2770 }
2771
2772 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2773 {
2774         switch (umr_fence_cap) {
2775         case MLX5_CAP_UMR_FENCE_NONE:
2776                 return MLX5_FENCE_MODE_NONE;
2777         case MLX5_CAP_UMR_FENCE_SMALL:
2778                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2779         default:
2780                 return MLX5_FENCE_MODE_STRONG_ORDERING;
2781         }
2782 }
2783
2784 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev)
2785 {
2786         struct mlx5_ib_resources *devr = &dev->devr;
2787         struct ib_srq_init_attr attr;
2788         struct ib_device *ibdev;
2789         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2790         int port;
2791         int ret = 0;
2792
2793         ibdev = &dev->ib_dev;
2794
2795         if (!MLX5_CAP_GEN(dev->mdev, xrc))
2796                 return -EOPNOTSUPP;
2797
2798         devr->p0 = ib_alloc_pd(ibdev, 0);
2799         if (IS_ERR(devr->p0))
2800                 return PTR_ERR(devr->p0);
2801
2802         devr->c0 = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr);
2803         if (IS_ERR(devr->c0)) {
2804                 ret = PTR_ERR(devr->c0);
2805                 goto error1;
2806         }
2807
2808         ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
2809         if (ret)
2810                 goto error2;
2811
2812         ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
2813         if (ret)
2814                 goto error3;
2815
2816         memset(&attr, 0, sizeof(attr));
2817         attr.attr.max_sge = 1;
2818         attr.attr.max_wr = 1;
2819         attr.srq_type = IB_SRQT_XRC;
2820         attr.ext.cq = devr->c0;
2821
2822         devr->s0 = ib_create_srq(devr->p0, &attr);
2823         if (IS_ERR(devr->s0)) {
2824                 ret = PTR_ERR(devr->s0);
2825                 goto err_create;
2826         }
2827
2828         memset(&attr, 0, sizeof(attr));
2829         attr.attr.max_sge = 1;
2830         attr.attr.max_wr = 1;
2831         attr.srq_type = IB_SRQT_BASIC;
2832
2833         devr->s1 = ib_create_srq(devr->p0, &attr);
2834         if (IS_ERR(devr->s1)) {
2835                 ret = PTR_ERR(devr->s1);
2836                 goto error6;
2837         }
2838
2839         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
2840                 INIT_WORK(&devr->ports[port].pkey_change_work,
2841                           pkey_change_handler);
2842
2843         return 0;
2844
2845 error6:
2846         ib_destroy_srq(devr->s0);
2847 err_create:
2848         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2849 error3:
2850         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2851 error2:
2852         ib_destroy_cq(devr->c0);
2853 error1:
2854         ib_dealloc_pd(devr->p0);
2855         return ret;
2856 }
2857
2858 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev)
2859 {
2860         struct mlx5_ib_resources *devr = &dev->devr;
2861         int port;
2862
2863         /*
2864          * Make sure no change P_Key work items are still executing.
2865          *
2866          * At this stage, the mlx5_ib_event should be unregistered
2867          * and it ensures that no new works are added.
2868          */
2869         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
2870                 cancel_work_sync(&devr->ports[port].pkey_change_work);
2871
2872         ib_destroy_srq(devr->s1);
2873         ib_destroy_srq(devr->s0);
2874         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2875         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2876         ib_destroy_cq(devr->c0);
2877         ib_dealloc_pd(devr->p0);
2878 }
2879
2880 static u32 get_core_cap_flags(struct ib_device *ibdev,
2881                               struct mlx5_hca_vport_context *rep)
2882 {
2883         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2884         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2885         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2886         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2887         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
2888         u32 ret = 0;
2889
2890         if (rep->grh_required)
2891                 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
2892
2893         if (ll == IB_LINK_LAYER_INFINIBAND)
2894                 return ret | RDMA_CORE_PORT_IBA_IB;
2895
2896         if (raw_support)
2897                 ret |= RDMA_CORE_PORT_RAW_PACKET;
2898
2899         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2900                 return ret;
2901
2902         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2903                 return ret;
2904
2905         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2906                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2907
2908         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2909                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2910
2911         return ret;
2912 }
2913
2914 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num,
2915                                struct ib_port_immutable *immutable)
2916 {
2917         struct ib_port_attr attr;
2918         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2919         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
2920         struct mlx5_hca_vport_context rep = {0};
2921         int err;
2922
2923         err = ib_query_port(ibdev, port_num, &attr);
2924         if (err)
2925                 return err;
2926
2927         if (ll == IB_LINK_LAYER_INFINIBAND) {
2928                 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
2929                                                    &rep);
2930                 if (err)
2931                         return err;
2932         }
2933
2934         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2935         immutable->gid_tbl_len = attr.gid_tbl_len;
2936         immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
2937         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2938
2939         return 0;
2940 }
2941
2942 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num,
2943                                    struct ib_port_immutable *immutable)
2944 {
2945         struct ib_port_attr attr;
2946         int err;
2947
2948         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
2949
2950         err = ib_query_port(ibdev, port_num, &attr);
2951         if (err)
2952                 return err;
2953
2954         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2955         immutable->gid_tbl_len = attr.gid_tbl_len;
2956         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
2957
2958         return 0;
2959 }
2960
2961 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
2962 {
2963         struct mlx5_ib_dev *dev =
2964                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2965         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
2966                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
2967                  fw_rev_sub(dev->mdev));
2968 }
2969
2970 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
2971 {
2972         struct mlx5_core_dev *mdev = dev->mdev;
2973         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
2974                                                                  MLX5_FLOW_NAMESPACE_LAG);
2975         struct mlx5_flow_table *ft;
2976         int err;
2977
2978         if (!ns || !mlx5_lag_is_active(mdev))
2979                 return 0;
2980
2981         err = mlx5_cmd_create_vport_lag(mdev);
2982         if (err)
2983                 return err;
2984
2985         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
2986         if (IS_ERR(ft)) {
2987                 err = PTR_ERR(ft);
2988                 goto err_destroy_vport_lag;
2989         }
2990
2991         dev->flow_db->lag_demux_ft = ft;
2992         dev->lag_ports = mlx5_lag_get_num_ports(mdev);
2993         dev->lag_active = true;
2994         return 0;
2995
2996 err_destroy_vport_lag:
2997         mlx5_cmd_destroy_vport_lag(mdev);
2998         return err;
2999 }
3000
3001 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3002 {
3003         struct mlx5_core_dev *mdev = dev->mdev;
3004
3005         if (dev->lag_active) {
3006                 dev->lag_active = false;
3007
3008                 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
3009                 dev->flow_db->lag_demux_ft = NULL;
3010
3011                 mlx5_cmd_destroy_vport_lag(mdev);
3012         }
3013 }
3014
3015 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num)
3016 {
3017         int err;
3018
3019         dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
3020         err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
3021         if (err) {
3022                 dev->port[port_num].roce.nb.notifier_call = NULL;
3023                 return err;
3024         }
3025
3026         return 0;
3027 }
3028
3029 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num)
3030 {
3031         if (dev->port[port_num].roce.nb.notifier_call) {
3032                 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
3033                 dev->port[port_num].roce.nb.notifier_call = NULL;
3034         }
3035 }
3036
3037 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3038 {
3039         int err;
3040
3041         if (!dev->is_rep && dev->profile != &raw_eth_profile) {
3042                 err = mlx5_nic_vport_enable_roce(dev->mdev);
3043                 if (err)
3044                         return err;
3045         }
3046
3047         err = mlx5_eth_lag_init(dev);
3048         if (err)
3049                 goto err_disable_roce;
3050
3051         return 0;
3052
3053 err_disable_roce:
3054         if (!dev->is_rep && dev->profile != &raw_eth_profile)
3055                 mlx5_nic_vport_disable_roce(dev->mdev);
3056
3057         return err;
3058 }
3059
3060 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3061 {
3062         mlx5_eth_lag_cleanup(dev);
3063         if (!dev->is_rep && dev->profile != &raw_eth_profile)
3064                 mlx5_nic_vport_disable_roce(dev->mdev);
3065 }
3066
3067 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num,
3068                                  enum rdma_netdev_t type,
3069                                  struct rdma_netdev_alloc_params *params)
3070 {
3071         if (type != RDMA_NETDEV_IPOIB)
3072                 return -EOPNOTSUPP;
3073
3074         return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
3075 }
3076
3077 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3078                                        size_t count, loff_t *pos)
3079 {
3080         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3081         char lbuf[20];
3082         int len;
3083
3084         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3085         return simple_read_from_buffer(buf, count, pos, lbuf, len);
3086 }
3087
3088 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3089                                         size_t count, loff_t *pos)
3090 {
3091         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3092         u32 timeout;
3093         u32 var;
3094
3095         if (kstrtouint_from_user(buf, count, 0, &var))
3096                 return -EFAULT;
3097
3098         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3099                         1000);
3100         if (timeout != var)
3101                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3102                             timeout);
3103
3104         delay_drop->timeout = timeout;
3105
3106         return count;
3107 }
3108
3109 static const struct file_operations fops_delay_drop_timeout = {
3110         .owner  = THIS_MODULE,
3111         .open   = simple_open,
3112         .write  = delay_drop_timeout_write,
3113         .read   = delay_drop_timeout_read,
3114 };
3115
3116 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
3117                                       struct mlx5_ib_multiport_info *mpi)
3118 {
3119         u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3120         struct mlx5_ib_port *port = &ibdev->port[port_num];
3121         int comps;
3122         int err;
3123         int i;
3124
3125         lockdep_assert_held(&mlx5_ib_multiport_mutex);
3126
3127         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
3128
3129         spin_lock(&port->mp.mpi_lock);
3130         if (!mpi->ibdev) {
3131                 spin_unlock(&port->mp.mpi_lock);
3132                 return;
3133         }
3134
3135         mpi->ibdev = NULL;
3136
3137         spin_unlock(&port->mp.mpi_lock);
3138         if (mpi->mdev_events.notifier_call)
3139                 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
3140         mpi->mdev_events.notifier_call = NULL;
3141         mlx5_remove_netdev_notifier(ibdev, port_num);
3142         spin_lock(&port->mp.mpi_lock);
3143
3144         comps = mpi->mdev_refcnt;
3145         if (comps) {
3146                 mpi->unaffiliate = true;
3147                 init_completion(&mpi->unref_comp);
3148                 spin_unlock(&port->mp.mpi_lock);
3149
3150                 for (i = 0; i < comps; i++)
3151                         wait_for_completion(&mpi->unref_comp);
3152
3153                 spin_lock(&port->mp.mpi_lock);
3154                 mpi->unaffiliate = false;
3155         }
3156
3157         port->mp.mpi = NULL;
3158
3159         spin_unlock(&port->mp.mpi_lock);
3160
3161         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
3162
3163         mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1);
3164         /* Log an error, still needed to cleanup the pointers and add
3165          * it back to the list.
3166          */
3167         if (err)
3168                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
3169                             port_num + 1);
3170
3171         ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
3172 }
3173
3174 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
3175                                     struct mlx5_ib_multiport_info *mpi)
3176 {
3177         u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3178         int err;
3179
3180         lockdep_assert_held(&mlx5_ib_multiport_mutex);
3181
3182         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
3183         if (ibdev->port[port_num].mp.mpi) {
3184                 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n",
3185                             port_num + 1);
3186                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3187                 return false;
3188         }
3189
3190         ibdev->port[port_num].mp.mpi = mpi;
3191         mpi->ibdev = ibdev;
3192         mpi->mdev_events.notifier_call = NULL;
3193         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3194
3195         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
3196         if (err)
3197                 goto unbind;
3198
3199         err = mlx5_add_netdev_notifier(ibdev, port_num);
3200         if (err) {
3201                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
3202                             port_num + 1);
3203                 goto unbind;
3204         }
3205
3206         mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
3207         mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
3208
3209         mlx5_ib_init_cong_debugfs(ibdev, port_num);
3210
3211         return true;
3212
3213 unbind:
3214         mlx5_ib_unbind_slave_port(ibdev, mpi);
3215         return false;
3216 }
3217
3218 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
3219 {
3220         u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3221         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3222                                                           port_num + 1);
3223         struct mlx5_ib_multiport_info *mpi;
3224         int err;
3225         u32 i;
3226
3227         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3228                 return 0;
3229
3230         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
3231                                                      &dev->sys_image_guid);
3232         if (err)
3233                 return err;
3234
3235         err = mlx5_nic_vport_enable_roce(dev->mdev);
3236         if (err)
3237                 return err;
3238
3239         mutex_lock(&mlx5_ib_multiport_mutex);
3240         for (i = 0; i < dev->num_ports; i++) {
3241                 bool bound = false;
3242
3243                 /* build a stub multiport info struct for the native port. */
3244                 if (i == port_num) {
3245                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
3246                         if (!mpi) {
3247                                 mutex_unlock(&mlx5_ib_multiport_mutex);
3248                                 mlx5_nic_vport_disable_roce(dev->mdev);
3249                                 return -ENOMEM;
3250                         }
3251
3252                         mpi->is_master = true;
3253                         mpi->mdev = dev->mdev;
3254                         mpi->sys_image_guid = dev->sys_image_guid;
3255                         dev->port[i].mp.mpi = mpi;
3256                         mpi->ibdev = dev;
3257                         mpi = NULL;
3258                         continue;
3259                 }
3260
3261                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
3262                                     list) {
3263                         if (dev->sys_image_guid == mpi->sys_image_guid &&
3264                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
3265                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
3266                         }
3267
3268                         if (bound) {
3269                                 dev_dbg(mpi->mdev->device,
3270                                         "removing port from unaffiliated list.\n");
3271                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
3272                                 list_del(&mpi->list);
3273                                 break;
3274                         }
3275                 }
3276                 if (!bound)
3277                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
3278                                     i + 1);
3279         }
3280
3281         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
3282         mutex_unlock(&mlx5_ib_multiport_mutex);
3283         return err;
3284 }
3285
3286 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
3287 {
3288         u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3289         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3290                                                           port_num + 1);
3291         u32 i;
3292
3293         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3294                 return;
3295
3296         mutex_lock(&mlx5_ib_multiport_mutex);
3297         for (i = 0; i < dev->num_ports; i++) {
3298                 if (dev->port[i].mp.mpi) {
3299                         /* Destroy the native port stub */
3300                         if (i == port_num) {
3301                                 kfree(dev->port[i].mp.mpi);
3302                                 dev->port[i].mp.mpi = NULL;
3303                         } else {
3304                                 mlx5_ib_dbg(dev, "unbinding port_num: %u\n",
3305                                             i + 1);
3306                                 list_add_tail(&dev->port[i].mp.mpi->list,
3307                                               &mlx5_ib_unaffiliated_port_list);
3308                                 mlx5_ib_unbind_slave_port(dev,
3309                                                           dev->port[i].mp.mpi);
3310                         }
3311                 }
3312         }
3313
3314         mlx5_ib_dbg(dev, "removing from devlist\n");
3315         list_del(&dev->ib_dev_list);
3316         mutex_unlock(&mlx5_ib_multiport_mutex);
3317
3318         mlx5_nic_vport_disable_roce(dev->mdev);
3319 }
3320
3321 static int mmap_obj_cleanup(struct ib_uobject *uobject,
3322                             enum rdma_remove_reason why,
3323                             struct uverbs_attr_bundle *attrs)
3324 {
3325         struct mlx5_user_mmap_entry *obj = uobject->object;
3326
3327         rdma_user_mmap_entry_remove(&obj->rdma_entry);
3328         return 0;
3329 }
3330
3331 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
3332                                             struct mlx5_user_mmap_entry *entry,
3333                                             size_t length)
3334 {
3335         return rdma_user_mmap_entry_insert_range(
3336                 &c->ibucontext, &entry->rdma_entry, length,
3337                 (MLX5_IB_MMAP_OFFSET_START << 16),
3338                 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
3339 }
3340
3341 static struct mlx5_user_mmap_entry *
3342 alloc_var_entry(struct mlx5_ib_ucontext *c)
3343 {
3344         struct mlx5_user_mmap_entry *entry;
3345         struct mlx5_var_table *var_table;
3346         u32 page_idx;
3347         int err;
3348
3349         var_table = &to_mdev(c->ibucontext.device)->var_table;
3350         entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3351         if (!entry)
3352                 return ERR_PTR(-ENOMEM);
3353
3354         mutex_lock(&var_table->bitmap_lock);
3355         page_idx = find_first_zero_bit(var_table->bitmap,
3356                                        var_table->num_var_hw_entries);
3357         if (page_idx >= var_table->num_var_hw_entries) {
3358                 err = -ENOSPC;
3359                 mutex_unlock(&var_table->bitmap_lock);
3360                 goto end;
3361         }
3362
3363         set_bit(page_idx, var_table->bitmap);
3364         mutex_unlock(&var_table->bitmap_lock);
3365
3366         entry->address = var_table->hw_start_addr +
3367                                 (page_idx * var_table->stride_size);
3368         entry->page_idx = page_idx;
3369         entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
3370
3371         err = mlx5_rdma_user_mmap_entry_insert(c, entry,
3372                                                var_table->stride_size);
3373         if (err)
3374                 goto err_insert;
3375
3376         return entry;
3377
3378 err_insert:
3379         mutex_lock(&var_table->bitmap_lock);
3380         clear_bit(page_idx, var_table->bitmap);
3381         mutex_unlock(&var_table->bitmap_lock);
3382 end:
3383         kfree(entry);
3384         return ERR_PTR(err);
3385 }
3386
3387 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
3388         struct uverbs_attr_bundle *attrs)
3389 {
3390         struct ib_uobject *uobj = uverbs_attr_get_uobject(
3391                 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3392         struct mlx5_ib_ucontext *c;
3393         struct mlx5_user_mmap_entry *entry;
3394         u64 mmap_offset;
3395         u32 length;
3396         int err;
3397
3398         c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3399         if (IS_ERR(c))
3400                 return PTR_ERR(c);
3401
3402         entry = alloc_var_entry(c);
3403         if (IS_ERR(entry))
3404                 return PTR_ERR(entry);
3405
3406         mmap_offset = mlx5_entry_to_mmap_offset(entry);
3407         length = entry->rdma_entry.npages * PAGE_SIZE;
3408         uobj->object = entry;
3409         uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3410
3411         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3412                              &mmap_offset, sizeof(mmap_offset));
3413         if (err)
3414                 return err;
3415
3416         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3417                              &entry->page_idx, sizeof(entry->page_idx));
3418         if (err)
3419                 return err;
3420
3421         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3422                              &length, sizeof(length));
3423         return err;
3424 }
3425
3426 DECLARE_UVERBS_NAMED_METHOD(
3427         MLX5_IB_METHOD_VAR_OBJ_ALLOC,
3428         UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
3429                         MLX5_IB_OBJECT_VAR,
3430                         UVERBS_ACCESS_NEW,
3431                         UA_MANDATORY),
3432         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3433                            UVERBS_ATTR_TYPE(u32),
3434                            UA_MANDATORY),
3435         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3436                            UVERBS_ATTR_TYPE(u32),
3437                            UA_MANDATORY),
3438         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3439                             UVERBS_ATTR_TYPE(u64),
3440                             UA_MANDATORY));
3441
3442 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3443         MLX5_IB_METHOD_VAR_OBJ_DESTROY,
3444         UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
3445                         MLX5_IB_OBJECT_VAR,
3446                         UVERBS_ACCESS_DESTROY,
3447                         UA_MANDATORY));
3448
3449 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
3450                             UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3451                             &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
3452                             &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
3453
3454 static bool var_is_supported(struct ib_device *device)
3455 {
3456         struct mlx5_ib_dev *dev = to_mdev(device);
3457
3458         return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3459                         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
3460 }
3461
3462 static struct mlx5_user_mmap_entry *
3463 alloc_uar_entry(struct mlx5_ib_ucontext *c,
3464                 enum mlx5_ib_uapi_uar_alloc_type alloc_type)
3465 {
3466         struct mlx5_user_mmap_entry *entry;
3467         struct mlx5_ib_dev *dev;
3468         u32 uar_index;
3469         int err;
3470
3471         entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3472         if (!entry)
3473                 return ERR_PTR(-ENOMEM);
3474
3475         dev = to_mdev(c->ibucontext.device);
3476         err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid);
3477         if (err)
3478                 goto end;
3479
3480         entry->page_idx = uar_index;
3481         entry->address = uar_index2paddress(dev, uar_index);
3482         if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3483                 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC;
3484         else
3485                 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC;
3486
3487         err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE);
3488         if (err)
3489                 goto err_insert;
3490
3491         return entry;
3492
3493 err_insert:
3494         mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid);
3495 end:
3496         kfree(entry);
3497         return ERR_PTR(err);
3498 }
3499
3500 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
3501         struct uverbs_attr_bundle *attrs)
3502 {
3503         struct ib_uobject *uobj = uverbs_attr_get_uobject(
3504                 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3505         enum mlx5_ib_uapi_uar_alloc_type alloc_type;
3506         struct mlx5_ib_ucontext *c;
3507         struct mlx5_user_mmap_entry *entry;
3508         u64 mmap_offset;
3509         u32 length;
3510         int err;
3511
3512         c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3513         if (IS_ERR(c))
3514                 return PTR_ERR(c);
3515
3516         err = uverbs_get_const(&alloc_type, attrs,
3517                                MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
3518         if (err)
3519                 return err;
3520
3521         if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
3522             alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
3523                 return -EOPNOTSUPP;
3524
3525         if (!to_mdev(c->ibucontext.device)->wc_support &&
3526             alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3527                 return -EOPNOTSUPP;
3528
3529         entry = alloc_uar_entry(c, alloc_type);
3530         if (IS_ERR(entry))
3531                 return PTR_ERR(entry);
3532
3533         mmap_offset = mlx5_entry_to_mmap_offset(entry);
3534         length = entry->rdma_entry.npages * PAGE_SIZE;
3535         uobj->object = entry;
3536         uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3537
3538         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3539                              &mmap_offset, sizeof(mmap_offset));
3540         if (err)
3541                 return err;
3542
3543         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3544                              &entry->page_idx, sizeof(entry->page_idx));
3545         if (err)
3546                 return err;
3547
3548         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3549                              &length, sizeof(length));
3550         return err;
3551 }
3552
3553 DECLARE_UVERBS_NAMED_METHOD(
3554         MLX5_IB_METHOD_UAR_OBJ_ALLOC,
3555         UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
3556                         MLX5_IB_OBJECT_UAR,
3557                         UVERBS_ACCESS_NEW,
3558                         UA_MANDATORY),
3559         UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
3560                              enum mlx5_ib_uapi_uar_alloc_type,
3561                              UA_MANDATORY),
3562         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3563                            UVERBS_ATTR_TYPE(u32),
3564                            UA_MANDATORY),
3565         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3566                            UVERBS_ATTR_TYPE(u32),
3567                            UA_MANDATORY),
3568         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3569                             UVERBS_ATTR_TYPE(u64),
3570                             UA_MANDATORY));
3571
3572 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3573         MLX5_IB_METHOD_UAR_OBJ_DESTROY,
3574         UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
3575                         MLX5_IB_OBJECT_UAR,
3576                         UVERBS_ACCESS_DESTROY,
3577                         UA_MANDATORY));
3578
3579 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
3580                             UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3581                             &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
3582                             &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
3583
3584 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3585         mlx5_ib_query_context,
3586         UVERBS_OBJECT_DEVICE,
3587         UVERBS_METHOD_QUERY_CONTEXT,
3588         UVERBS_ATTR_PTR_OUT(
3589                 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
3590                 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp,
3591                                    dump_fill_mkey),
3592                 UA_MANDATORY));
3593
3594 static const struct uapi_definition mlx5_ib_defs[] = {
3595         UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
3596         UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
3597         UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
3598         UAPI_DEF_CHAIN(mlx5_ib_std_types_defs),
3599         UAPI_DEF_CHAIN(mlx5_ib_dm_defs),
3600
3601         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context),
3602         UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
3603                                 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
3604         UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
3605         {}
3606 };
3607
3608 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
3609 {
3610         mlx5_ib_cleanup_multiport_master(dev);
3611         WARN_ON(!xa_empty(&dev->odp_mkeys));
3612         mutex_destroy(&dev->cap_mask_mutex);
3613         WARN_ON(!xa_empty(&dev->sig_mrs));
3614         WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
3615 }
3616
3617 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
3618 {
3619         struct mlx5_core_dev *mdev = dev->mdev;
3620         int err;
3621         int i;
3622
3623         dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3624         dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3625         dev->ib_dev.phys_port_cnt = dev->num_ports;
3626         dev->ib_dev.dev.parent = mdev->device;
3627         dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES;
3628
3629         for (i = 0; i < dev->num_ports; i++) {
3630                 spin_lock_init(&dev->port[i].mp.mpi_lock);
3631                 rwlock_init(&dev->port[i].roce.netdev_lock);
3632                 dev->port[i].roce.dev = dev;
3633                 dev->port[i].roce.native_port_num = i + 1;
3634                 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
3635         }
3636
3637         err = mlx5_ib_init_multiport_master(dev);
3638         if (err)
3639                 return err;
3640
3641         err = set_has_smi_cap(dev);
3642         if (err)
3643                 goto err_mp;
3644
3645         err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len);
3646         if (err)
3647                 goto err_mp;
3648
3649         if (mlx5_use_mad_ifc(dev))
3650                 get_ext_port_caps(dev);
3651
3652         dev->ib_dev.num_comp_vectors    = mlx5_comp_vectors_count(mdev);
3653
3654         mutex_init(&dev->cap_mask_mutex);
3655         INIT_LIST_HEAD(&dev->qp_list);
3656         spin_lock_init(&dev->reset_flow_resource_lock);
3657         xa_init(&dev->odp_mkeys);
3658         xa_init(&dev->sig_mrs);
3659         atomic_set(&dev->mkey_var, 0);
3660
3661         spin_lock_init(&dev->dm.lock);
3662         dev->dm.dev = mdev;
3663         return 0;
3664
3665 err_mp:
3666         mlx5_ib_cleanup_multiport_master(dev);
3667         return err;
3668 }
3669
3670 static int mlx5_ib_enable_driver(struct ib_device *dev)
3671 {
3672         struct mlx5_ib_dev *mdev = to_mdev(dev);
3673         int ret;
3674
3675         ret = mlx5_ib_test_wc(mdev);
3676         mlx5_ib_dbg(mdev, "Write-Combining %s",
3677                     mdev->wc_support ? "supported" : "not supported");
3678
3679         return ret;
3680 }
3681
3682 static const struct ib_device_ops mlx5_ib_dev_ops = {
3683         .owner = THIS_MODULE,
3684         .driver_id = RDMA_DRIVER_MLX5,
3685         .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
3686
3687         .add_gid = mlx5_ib_add_gid,
3688         .alloc_mr = mlx5_ib_alloc_mr,
3689         .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
3690         .alloc_pd = mlx5_ib_alloc_pd,
3691         .alloc_ucontext = mlx5_ib_alloc_ucontext,
3692         .attach_mcast = mlx5_ib_mcg_attach,
3693         .check_mr_status = mlx5_ib_check_mr_status,
3694         .create_ah = mlx5_ib_create_ah,
3695         .create_cq = mlx5_ib_create_cq,
3696         .create_qp = mlx5_ib_create_qp,
3697         .create_srq = mlx5_ib_create_srq,
3698         .create_user_ah = mlx5_ib_create_ah,
3699         .dealloc_pd = mlx5_ib_dealloc_pd,
3700         .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
3701         .del_gid = mlx5_ib_del_gid,
3702         .dereg_mr = mlx5_ib_dereg_mr,
3703         .destroy_ah = mlx5_ib_destroy_ah,
3704         .destroy_cq = mlx5_ib_destroy_cq,
3705         .destroy_qp = mlx5_ib_destroy_qp,
3706         .destroy_srq = mlx5_ib_destroy_srq,
3707         .detach_mcast = mlx5_ib_mcg_detach,
3708         .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
3709         .drain_rq = mlx5_ib_drain_rq,
3710         .drain_sq = mlx5_ib_drain_sq,
3711         .device_group = &mlx5_attr_group,
3712         .enable_driver = mlx5_ib_enable_driver,
3713         .get_dev_fw_str = get_dev_fw_str,
3714         .get_dma_mr = mlx5_ib_get_dma_mr,
3715         .get_link_layer = mlx5_ib_port_link_layer,
3716         .map_mr_sg = mlx5_ib_map_mr_sg,
3717         .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
3718         .mmap = mlx5_ib_mmap,
3719         .mmap_free = mlx5_ib_mmap_free,
3720         .modify_cq = mlx5_ib_modify_cq,
3721         .modify_device = mlx5_ib_modify_device,
3722         .modify_port = mlx5_ib_modify_port,
3723         .modify_qp = mlx5_ib_modify_qp,
3724         .modify_srq = mlx5_ib_modify_srq,
3725         .poll_cq = mlx5_ib_poll_cq,
3726         .post_recv = mlx5_ib_post_recv_nodrain,
3727         .post_send = mlx5_ib_post_send_nodrain,
3728         .post_srq_recv = mlx5_ib_post_srq_recv,
3729         .process_mad = mlx5_ib_process_mad,
3730         .query_ah = mlx5_ib_query_ah,
3731         .query_device = mlx5_ib_query_device,
3732         .query_gid = mlx5_ib_query_gid,
3733         .query_pkey = mlx5_ib_query_pkey,
3734         .query_qp = mlx5_ib_query_qp,
3735         .query_srq = mlx5_ib_query_srq,
3736         .query_ucontext = mlx5_ib_query_ucontext,
3737         .reg_user_mr = mlx5_ib_reg_user_mr,
3738         .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf,
3739         .req_notify_cq = mlx5_ib_arm_cq,
3740         .rereg_user_mr = mlx5_ib_rereg_user_mr,
3741         .resize_cq = mlx5_ib_resize_cq,
3742
3743         INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
3744         INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs),
3745         INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
3746         INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
3747         INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp),
3748         INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
3749         INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
3750 };
3751
3752 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
3753         .rdma_netdev_get_params = mlx5_ib_rn_get_params,
3754 };
3755
3756 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
3757         .get_vf_config = mlx5_ib_get_vf_config,
3758         .get_vf_guid = mlx5_ib_get_vf_guid,
3759         .get_vf_stats = mlx5_ib_get_vf_stats,
3760         .set_vf_guid = mlx5_ib_set_vf_guid,
3761         .set_vf_link_state = mlx5_ib_set_vf_link_state,
3762 };
3763
3764 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
3765         .alloc_mw = mlx5_ib_alloc_mw,
3766         .dealloc_mw = mlx5_ib_dealloc_mw,
3767
3768         INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw),
3769 };
3770
3771 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
3772         .alloc_xrcd = mlx5_ib_alloc_xrcd,
3773         .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
3774
3775         INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd),
3776 };
3777
3778 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
3779 {
3780         struct mlx5_core_dev *mdev = dev->mdev;
3781         struct mlx5_var_table *var_table = &dev->var_table;
3782         u8 log_doorbell_bar_size;
3783         u8 log_doorbell_stride;
3784         u64 bar_size;
3785
3786         log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3787                                         log_doorbell_bar_size);
3788         log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3789                                         log_doorbell_stride);
3790         var_table->hw_start_addr = dev->mdev->bar_addr +
3791                                 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
3792                                         doorbell_bar_offset);
3793         bar_size = (1ULL << log_doorbell_bar_size) * 4096;
3794         var_table->stride_size = 1ULL << log_doorbell_stride;
3795         var_table->num_var_hw_entries = div_u64(bar_size,
3796                                                 var_table->stride_size);
3797         mutex_init(&var_table->bitmap_lock);
3798         var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
3799                                           GFP_KERNEL);
3800         return (var_table->bitmap) ? 0 : -ENOMEM;
3801 }
3802
3803 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
3804 {
3805         bitmap_free(dev->var_table.bitmap);
3806 }
3807
3808 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
3809 {
3810         struct mlx5_core_dev *mdev = dev->mdev;
3811         int err;
3812
3813         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
3814             IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
3815                 ib_set_device_ops(&dev->ib_dev,
3816                                   &mlx5_ib_dev_ipoib_enhanced_ops);
3817
3818         if (mlx5_core_is_pf(mdev))
3819                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
3820
3821         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3822
3823         if (MLX5_CAP_GEN(mdev, imaicl))
3824                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
3825
3826         if (MLX5_CAP_GEN(mdev, xrc))
3827                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
3828
3829         if (MLX5_CAP_DEV_MEM(mdev, memic) ||
3830             MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3831             MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
3832                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
3833
3834         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
3835
3836         if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
3837                 dev->ib_dev.driver_def = mlx5_ib_defs;
3838
3839         err = init_node_data(dev);
3840         if (err)
3841                 return err;
3842
3843         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
3844             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
3845              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
3846                 mutex_init(&dev->lb.mutex);
3847
3848         if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3849                         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
3850                 err = mlx5_ib_init_var_table(dev);
3851                 if (err)
3852                         return err;
3853         }
3854
3855         dev->ib_dev.use_cq_dim = true;
3856
3857         return 0;
3858 }
3859
3860 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
3861         .get_port_immutable = mlx5_port_immutable,
3862         .query_port = mlx5_ib_query_port,
3863 };
3864
3865 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
3866 {
3867         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
3868         return 0;
3869 }
3870
3871 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
3872         .get_port_immutable = mlx5_port_rep_immutable,
3873         .query_port = mlx5_ib_rep_query_port,
3874         .query_pkey = mlx5_ib_rep_query_pkey,
3875 };
3876
3877 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
3878 {
3879         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
3880         return 0;
3881 }
3882
3883 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
3884         .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
3885         .create_wq = mlx5_ib_create_wq,
3886         .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
3887         .destroy_wq = mlx5_ib_destroy_wq,
3888         .get_netdev = mlx5_ib_get_netdev,
3889         .modify_wq = mlx5_ib_modify_wq,
3890
3891         INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table,
3892                            ib_rwq_ind_tbl),
3893 };
3894
3895 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev)
3896 {
3897         struct mlx5_core_dev *mdev = dev->mdev;
3898         enum rdma_link_layer ll;
3899         int port_type_cap;
3900         u32 port_num = 0;
3901         int err;
3902
3903         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3904         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3905
3906         if (ll == IB_LINK_LAYER_ETHERNET) {
3907                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
3908
3909                 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3910
3911                 /* Register only for native ports */
3912                 err = mlx5_add_netdev_notifier(dev, port_num);
3913                 if (err)
3914                         return err;
3915
3916                 err = mlx5_enable_eth(dev);
3917                 if (err)
3918                         goto cleanup;
3919         }
3920
3921         return 0;
3922 cleanup:
3923         mlx5_remove_netdev_notifier(dev, port_num);
3924         return err;
3925 }
3926
3927 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev)
3928 {
3929         struct mlx5_core_dev *mdev = dev->mdev;
3930         enum rdma_link_layer ll;
3931         int port_type_cap;
3932         u32 port_num;
3933
3934         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3935         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3936
3937         if (ll == IB_LINK_LAYER_ETHERNET) {
3938                 mlx5_disable_eth(dev);
3939
3940                 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3941                 mlx5_remove_netdev_notifier(dev, port_num);
3942         }
3943 }
3944
3945 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
3946 {
3947         mlx5_ib_init_cong_debugfs(dev,
3948                                   mlx5_core_native_port_num(dev->mdev) - 1);
3949         return 0;
3950 }
3951
3952 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
3953 {
3954         mlx5_ib_cleanup_cong_debugfs(dev,
3955                                      mlx5_core_native_port_num(dev->mdev) - 1);
3956 }
3957
3958 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
3959 {
3960         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
3961         return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
3962 }
3963
3964 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
3965 {
3966         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
3967 }
3968
3969 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
3970 {
3971         int err;
3972
3973         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
3974         if (err)
3975                 return err;
3976
3977         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
3978         if (err)
3979                 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3980
3981         return err;
3982 }
3983
3984 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
3985 {
3986         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3987         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3988 }
3989
3990 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
3991 {
3992         const char *name;
3993
3994         if (!mlx5_lag_is_active(dev->mdev))
3995                 name = "mlx5_%d";
3996         else
3997                 name = "mlx5_bond_%d";
3998         return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
3999 }
4000
4001 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
4002 {
4003         int err;
4004
4005         err = mlx5_mkey_cache_cleanup(dev);
4006         if (err)
4007                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4008
4009         mlx5r_umr_resource_cleanup(dev);
4010 }
4011
4012 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4013 {
4014         ib_unregister_device(&dev->ib_dev);
4015 }
4016
4017 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
4018 {
4019         int ret;
4020
4021         ret = mlx5r_umr_resource_init(dev);
4022         if (ret)
4023                 return ret;
4024
4025         ret = mlx5_mkey_cache_init(dev);
4026         if (ret) {
4027                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4028                 mlx5r_umr_resource_cleanup(dev);
4029         }
4030         return ret;
4031 }
4032
4033 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4034 {
4035         struct dentry *root;
4036
4037         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4038                 return 0;
4039
4040         mutex_init(&dev->delay_drop.lock);
4041         dev->delay_drop.dev = dev;
4042         dev->delay_drop.activate = false;
4043         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4044         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4045         atomic_set(&dev->delay_drop.rqs_cnt, 0);
4046         atomic_set(&dev->delay_drop.events_cnt, 0);
4047
4048         if (!mlx5_debugfs_root)
4049                 return 0;
4050
4051         root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev));
4052         dev->delay_drop.dir_debugfs = root;
4053
4054         debugfs_create_atomic_t("num_timeout_events", 0400, root,
4055                                 &dev->delay_drop.events_cnt);
4056         debugfs_create_atomic_t("num_rqs", 0400, root,
4057                                 &dev->delay_drop.rqs_cnt);
4058         debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
4059                             &fops_delay_drop_timeout);
4060         return 0;
4061 }
4062
4063 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4064 {
4065         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4066                 return;
4067
4068         cancel_work_sync(&dev->delay_drop.delay_drop_work);
4069         if (!dev->delay_drop.dir_debugfs)
4070                 return;
4071
4072         debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
4073         dev->delay_drop.dir_debugfs = NULL;
4074 }
4075
4076 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
4077 {
4078         dev->mdev_events.notifier_call = mlx5_ib_event;
4079         mlx5_notifier_register(dev->mdev, &dev->mdev_events);
4080         return 0;
4081 }
4082
4083 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
4084 {
4085         mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
4086 }
4087
4088 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4089                       const struct mlx5_ib_profile *profile,
4090                       int stage)
4091 {
4092         dev->ib_active = false;
4093
4094         /* Number of stages to cleanup */
4095         while (stage) {
4096                 stage--;
4097                 if (profile->stage[stage].cleanup)
4098                         profile->stage[stage].cleanup(dev);
4099         }
4100
4101         kfree(dev->port);
4102         ib_dealloc_device(&dev->ib_dev);
4103 }
4104
4105 int __mlx5_ib_add(struct mlx5_ib_dev *dev,
4106                   const struct mlx5_ib_profile *profile)
4107 {
4108         int err;
4109         int i;
4110
4111         dev->profile = profile;
4112
4113         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4114                 if (profile->stage[i].init) {
4115                         err = profile->stage[i].init(dev);
4116                         if (err)
4117                                 goto err_out;
4118                 }
4119         }
4120
4121         dev->ib_active = true;
4122         return 0;
4123
4124 err_out:
4125         /* Clean up stages which were initialized */
4126         while (i) {
4127                 i--;
4128                 if (profile->stage[i].cleanup)
4129                         profile->stage[i].cleanup(dev);
4130         }
4131         return -ENOMEM;
4132 }
4133
4134 static const struct mlx5_ib_profile pf_profile = {
4135         STAGE_CREATE(MLX5_IB_STAGE_INIT,
4136                      mlx5_ib_stage_init_init,
4137                      mlx5_ib_stage_init_cleanup),
4138         STAGE_CREATE(MLX5_IB_STAGE_FS,
4139                      mlx5_ib_fs_init,
4140                      mlx5_ib_fs_cleanup),
4141         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4142                      mlx5_ib_stage_caps_init,
4143                      mlx5_ib_stage_caps_cleanup),
4144         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4145                      mlx5_ib_stage_non_default_cb,
4146                      NULL),
4147         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4148                      mlx5_ib_roce_init,
4149                      mlx5_ib_roce_cleanup),
4150         STAGE_CREATE(MLX5_IB_STAGE_QP,
4151                      mlx5_init_qp_table,
4152                      mlx5_cleanup_qp_table),
4153         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4154                      mlx5_init_srq_table,
4155                      mlx5_cleanup_srq_table),
4156         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4157                      mlx5_ib_dev_res_init,
4158                      mlx5_ib_dev_res_cleanup),
4159         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4160                      mlx5_ib_stage_dev_notifier_init,
4161                      mlx5_ib_stage_dev_notifier_cleanup),
4162         STAGE_CREATE(MLX5_IB_STAGE_ODP,
4163                      mlx5_ib_odp_init_one,
4164                      mlx5_ib_odp_cleanup_one),
4165         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4166                      mlx5_ib_counters_init,
4167                      mlx5_ib_counters_cleanup),
4168         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4169                      mlx5_ib_stage_cong_debugfs_init,
4170                      mlx5_ib_stage_cong_debugfs_cleanup),
4171         STAGE_CREATE(MLX5_IB_STAGE_UAR,
4172                      mlx5_ib_stage_uar_init,
4173                      mlx5_ib_stage_uar_cleanup),
4174         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4175                      mlx5_ib_stage_bfrag_init,
4176                      mlx5_ib_stage_bfrag_cleanup),
4177         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4178                      NULL,
4179                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4180         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4181                      mlx5_ib_devx_init,
4182                      mlx5_ib_devx_cleanup),
4183         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4184                      mlx5_ib_stage_ib_reg_init,
4185                      mlx5_ib_stage_ib_reg_cleanup),
4186         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4187                      mlx5_ib_stage_post_ib_reg_umr_init,
4188                      NULL),
4189         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4190                      mlx5_ib_stage_delay_drop_init,
4191                      mlx5_ib_stage_delay_drop_cleanup),
4192         STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4193                      mlx5_ib_restrack_init,
4194                      NULL),
4195 };
4196
4197 const struct mlx5_ib_profile raw_eth_profile = {
4198         STAGE_CREATE(MLX5_IB_STAGE_INIT,
4199                      mlx5_ib_stage_init_init,
4200                      mlx5_ib_stage_init_cleanup),
4201         STAGE_CREATE(MLX5_IB_STAGE_FS,
4202                      mlx5_ib_fs_init,
4203                      mlx5_ib_fs_cleanup),
4204         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4205                      mlx5_ib_stage_caps_init,
4206                      mlx5_ib_stage_caps_cleanup),
4207         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4208                      mlx5_ib_stage_raw_eth_non_default_cb,
4209                      NULL),
4210         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4211                      mlx5_ib_roce_init,
4212                      mlx5_ib_roce_cleanup),
4213         STAGE_CREATE(MLX5_IB_STAGE_QP,
4214                      mlx5_init_qp_table,
4215                      mlx5_cleanup_qp_table),
4216         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4217                      mlx5_init_srq_table,
4218                      mlx5_cleanup_srq_table),
4219         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4220                      mlx5_ib_dev_res_init,
4221                      mlx5_ib_dev_res_cleanup),
4222         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4223                      mlx5_ib_stage_dev_notifier_init,
4224                      mlx5_ib_stage_dev_notifier_cleanup),
4225         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4226                      mlx5_ib_counters_init,
4227                      mlx5_ib_counters_cleanup),
4228         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4229                      mlx5_ib_stage_cong_debugfs_init,
4230                      mlx5_ib_stage_cong_debugfs_cleanup),
4231         STAGE_CREATE(MLX5_IB_STAGE_UAR,
4232                      mlx5_ib_stage_uar_init,
4233                      mlx5_ib_stage_uar_cleanup),
4234         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4235                      mlx5_ib_stage_bfrag_init,
4236                      mlx5_ib_stage_bfrag_cleanup),
4237         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4238                      NULL,
4239                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4240         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4241                      mlx5_ib_devx_init,
4242                      mlx5_ib_devx_cleanup),
4243         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4244                      mlx5_ib_stage_ib_reg_init,
4245                      mlx5_ib_stage_ib_reg_cleanup),
4246         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4247                      mlx5_ib_stage_post_ib_reg_umr_init,
4248                      NULL),
4249         STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4250                      mlx5_ib_restrack_init,
4251                      NULL),
4252 };
4253
4254 static int mlx5r_mp_probe(struct auxiliary_device *adev,
4255                           const struct auxiliary_device_id *id)
4256 {
4257         struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4258         struct mlx5_core_dev *mdev = idev->mdev;
4259         struct mlx5_ib_multiport_info *mpi;
4260         struct mlx5_ib_dev *dev;
4261         bool bound = false;
4262         int err;
4263
4264         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4265         if (!mpi)
4266                 return -ENOMEM;
4267
4268         mpi->mdev = mdev;
4269         err = mlx5_query_nic_vport_system_image_guid(mdev,
4270                                                      &mpi->sys_image_guid);
4271         if (err) {
4272                 kfree(mpi);
4273                 return err;
4274         }
4275
4276         mutex_lock(&mlx5_ib_multiport_mutex);
4277         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
4278                 if (dev->sys_image_guid == mpi->sys_image_guid)
4279                         bound = mlx5_ib_bind_slave_port(dev, mpi);
4280
4281                 if (bound) {
4282                         rdma_roce_rescan_device(&dev->ib_dev);
4283                         mpi->ibdev->ib_active = true;
4284                         break;
4285                 }
4286         }
4287
4288         if (!bound) {
4289                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4290                 dev_dbg(mdev->device,
4291                         "no suitable IB device found to bind to, added to unaffiliated list.\n");
4292         }
4293         mutex_unlock(&mlx5_ib_multiport_mutex);
4294
4295         auxiliary_set_drvdata(adev, mpi);
4296         return 0;
4297 }
4298
4299 static void mlx5r_mp_remove(struct auxiliary_device *adev)
4300 {
4301         struct mlx5_ib_multiport_info *mpi;
4302
4303         mpi = auxiliary_get_drvdata(adev);
4304         mutex_lock(&mlx5_ib_multiport_mutex);
4305         if (mpi->ibdev)
4306                 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
4307         else
4308                 list_del(&mpi->list);
4309         mutex_unlock(&mlx5_ib_multiport_mutex);
4310         kfree(mpi);
4311 }
4312
4313 static int mlx5r_probe(struct auxiliary_device *adev,
4314                        const struct auxiliary_device_id *id)
4315 {
4316         struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4317         struct mlx5_core_dev *mdev = idev->mdev;
4318         const struct mlx5_ib_profile *profile;
4319         int port_type_cap, num_ports, ret;
4320         enum rdma_link_layer ll;
4321         struct mlx5_ib_dev *dev;
4322
4323         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4324         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4325
4326         num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4327                         MLX5_CAP_GEN(mdev, num_vhca_ports));
4328         dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
4329         if (!dev)
4330                 return -ENOMEM;
4331         dev->port = kcalloc(num_ports, sizeof(*dev->port),
4332                              GFP_KERNEL);
4333         if (!dev->port) {
4334                 ib_dealloc_device(&dev->ib_dev);
4335                 return -ENOMEM;
4336         }
4337
4338         dev->mdev = mdev;
4339         dev->num_ports = num_ports;
4340
4341         if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_init_enabled(mdev))
4342                 profile = &raw_eth_profile;
4343         else
4344                 profile = &pf_profile;
4345
4346         ret = __mlx5_ib_add(dev, profile);
4347         if (ret) {
4348                 kfree(dev->port);
4349                 ib_dealloc_device(&dev->ib_dev);
4350                 return ret;
4351         }
4352
4353         auxiliary_set_drvdata(adev, dev);
4354         return 0;
4355 }
4356
4357 static void mlx5r_remove(struct auxiliary_device *adev)
4358 {
4359         struct mlx5_ib_dev *dev;
4360
4361         dev = auxiliary_get_drvdata(adev);
4362         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
4363 }
4364
4365 static const struct auxiliary_device_id mlx5r_mp_id_table[] = {
4366         { .name = MLX5_ADEV_NAME ".multiport", },
4367         {},
4368 };
4369
4370 static const struct auxiliary_device_id mlx5r_id_table[] = {
4371         { .name = MLX5_ADEV_NAME ".rdma", },
4372         {},
4373 };
4374
4375 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table);
4376 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table);
4377
4378 static struct auxiliary_driver mlx5r_mp_driver = {
4379         .name = "multiport",
4380         .probe = mlx5r_mp_probe,
4381         .remove = mlx5r_mp_remove,
4382         .id_table = mlx5r_mp_id_table,
4383 };
4384
4385 static struct auxiliary_driver mlx5r_driver = {
4386         .name = "rdma",
4387         .probe = mlx5r_probe,
4388         .remove = mlx5r_remove,
4389         .id_table = mlx5r_id_table,
4390 };
4391
4392 static int __init mlx5_ib_init(void)
4393 {
4394         int ret;
4395
4396         xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL);
4397         if (!xlt_emergency_page)
4398                 return -ENOMEM;
4399
4400         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
4401         if (!mlx5_ib_event_wq) {
4402                 free_page((unsigned long)xlt_emergency_page);
4403                 return -ENOMEM;
4404         }
4405
4406         mlx5_ib_odp_init();
4407         ret = mlx5r_rep_init();
4408         if (ret)
4409                 goto rep_err;
4410         ret = auxiliary_driver_register(&mlx5r_mp_driver);
4411         if (ret)
4412                 goto mp_err;
4413         ret = auxiliary_driver_register(&mlx5r_driver);
4414         if (ret)
4415                 goto drv_err;
4416         return 0;
4417
4418 drv_err:
4419         auxiliary_driver_unregister(&mlx5r_mp_driver);
4420 mp_err:
4421         mlx5r_rep_cleanup();
4422 rep_err:
4423         destroy_workqueue(mlx5_ib_event_wq);
4424         free_page((unsigned long)xlt_emergency_page);
4425         return ret;
4426 }
4427
4428 static void __exit mlx5_ib_cleanup(void)
4429 {
4430         auxiliary_driver_unregister(&mlx5r_driver);
4431         auxiliary_driver_unregister(&mlx5r_mp_driver);
4432         mlx5r_rep_cleanup();
4433
4434         destroy_workqueue(mlx5_ib_event_wq);
4435         free_page((unsigned long)xlt_emergency_page);
4436 }
4437
4438 module_init(mlx5_ib_init);
4439 module_exit(mlx5_ib_cleanup);