drivers/infiniband/hw/i40iw/i40iw_osdep.h

   1 /*******************************************************************************
   2 *
   3 * Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the
   9 * OpenFabrics.org BSD license below:
  10 *
  11 *   Redistribution and use in source and binary forms, with or
  12 *   without modification, are permitted provided that the following
  13 *   conditions are met:
  14 *
  15 *    - Redistributions of source code must retain the above
  16 *       copyright notice, this list of conditions and the following
  17 *       disclaimer.
  18 *
  19 *    - Redistributions in binary form must reproduce the above
  20 *       copyright notice, this list of conditions and the following
  21 *       disclaimer in the documentation and/or other materials
  22 *       provided with the distribution.
  23 *
  24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31 * SOFTWARE.
  32 *
  33 *******************************************************************************/
  34
  35 #ifndef I40IW_OSDEP_H
  36 #define I40IW_OSDEP_H
  37
  38 #include <linux/kernel.h>
  39 #include <linux/string.h>
  40 #include <linux/bitops.h>
  41 #include <net/tcp.h>
  42 #include <crypto/hash.h>
  43 /* get readq/writeq support for 32 bit kernels, use the low-first version */
  44 #include <linux/io-64-nonatomic-lo-hi.h>
  45
  46 #define STATS_TIMER_DELAY 1000
  47
  48 static inline void set_64bit_val(u64 *wqe_words, u32 byte_index, u64 value)
  49 {
  50         wqe_words[byte_index >> 3] = value;
  51 }
  52
  53 /**
  54  * get_64bit_val - read 64 bit value from wqe
  55  * @wqe_words: wqe addr
  56  * @byte_index: index to read from
  57  * @value: read value
  58  **/
  59 static inline void get_64bit_val(u64 *wqe_words, u32 byte_index, u64 *value)
  60 {
  61         *value = wqe_words[byte_index >> 3];
  62 }
  63
  64 struct i40iw_dma_mem {
  65         void *va;
  66         dma_addr_t pa;
  67         u32 size;
  68 } __packed;
  69
  70 struct i40iw_virt_mem {
  71         void *va;
  72         u32 size;
  73 } __packed;
  74
  75 #define i40iw_debug(h, m, s, ...)                               \
  76 do {                                                            \
  77         if (((m) & (h)->debug_mask))                            \
  78                 pr_info("i40iw " s, ##__VA_ARGS__);             \
  79 } while (0)
  80
  81 #define i40iw_flush(a)          readl((a)->hw_addr + I40E_GLGEN_STAT)
  82
  83 #define I40E_GLHMC_VFSDCMD(_i)  (0x000C8000 + ((_i) * 4)) \
  84                                 /* _i=0...31 */
  85 #define I40E_GLHMC_VFSDCMD_MAX_INDEX    31
  86 #define I40E_GLHMC_VFSDCMD_PMSDIDX_SHIFT  0
  87 #define I40E_GLHMC_VFSDCMD_PMSDIDX_MASK  (0xFFF \
  88                                           << I40E_GLHMC_VFSDCMD_PMSDIDX_SHIFT)
  89 #define I40E_GLHMC_VFSDCMD_PF_SHIFT       16
  90 #define I40E_GLHMC_VFSDCMD_PF_MASK        (0xF << I40E_GLHMC_VFSDCMD_PF_SHIFT)
  91 #define I40E_GLHMC_VFSDCMD_VF_SHIFT       20
  92 #define I40E_GLHMC_VFSDCMD_VF_MASK        (0x1FF << I40E_GLHMC_VFSDCMD_VF_SHIFT)
  93 #define I40E_GLHMC_VFSDCMD_PMF_TYPE_SHIFT 29
  94 #define I40E_GLHMC_VFSDCMD_PMF_TYPE_MASK  (0x3 \
  95                                            << I40E_GLHMC_VFSDCMD_PMF_TYPE_SHIFT)
  96 #define I40E_GLHMC_VFSDCMD_PMSDWR_SHIFT   31
  97 #define I40E_GLHMC_VFSDCMD_PMSDWR_MASK  (0x1 << I40E_GLHMC_VFSDCMD_PMSDWR_SHIFT)
  98
  99 #define I40E_GLHMC_VFSDDATAHIGH(_i)     (0x000C8200 + ((_i) * 4)) \
 100                                 /* _i=0...31 */
 101 #define I40E_GLHMC_VFSDDATAHIGH_MAX_INDEX       31
 102 #define I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_SHIFT 0
 103 #define I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_MASK  (0xFFFFFFFF \
 104                         << I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_SHIFT)
 105
 106 #define I40E_GLHMC_VFSDDATALOW(_i)      (0x000C8100 + ((_i) * 4)) \
 107                                 /* _i=0...31 */
 108 #define I40E_GLHMC_VFSDDATALOW_MAX_INDEX        31
 109 #define I40E_GLHMC_VFSDDATALOW_PMSDVALID_SHIFT   0
 110 #define I40E_GLHMC_VFSDDATALOW_PMSDVALID_MASK  (0x1 \
 111                         << I40E_GLHMC_VFSDDATALOW_PMSDVALID_SHIFT)
 112 #define I40E_GLHMC_VFSDDATALOW_PMSDTYPE_SHIFT    1
 113 #define I40E_GLHMC_VFSDDATALOW_PMSDTYPE_MASK  (0x1 \
 114                         << I40E_GLHMC_VFSDDATALOW_PMSDTYPE_SHIFT)
 115 #define I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_SHIFT 2
 116 #define I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_MASK  (0x3FF \
 117                         << I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_SHIFT)
 118 #define I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_SHIFT 12
 119 #define I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_MASK  (0xFFFFF \
 120                         << I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_SHIFT)
 121
 122 #define I40E_GLPE_FWLDSTATUS                     0x0000D200
 123 #define I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_SHIFT 0
 124 #define I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_MASK  (0x1 \
 125                         << I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_SHIFT)
 126 #define I40E_GLPE_FWLDSTATUS_DONE_SHIFT           1
 127 #define I40E_GLPE_FWLDSTATUS_DONE_MASK  (0x1 << I40E_GLPE_FWLDSTATUS_DONE_SHIFT)
 128 #define I40E_GLPE_FWLDSTATUS_CQP_FAIL_SHIFT       2
 129 #define I40E_GLPE_FWLDSTATUS_CQP_FAIL_MASK  (0x1 \
 130                          << I40E_GLPE_FWLDSTATUS_CQP_FAIL_SHIFT)
 131 #define I40E_GLPE_FWLDSTATUS_TEP_FAIL_SHIFT       3
 132 #define I40E_GLPE_FWLDSTATUS_TEP_FAIL_MASK  (0x1 \
 133                          << I40E_GLPE_FWLDSTATUS_TEP_FAIL_SHIFT)
 134 #define I40E_GLPE_FWLDSTATUS_OOP_FAIL_SHIFT       4
 135 #define I40E_GLPE_FWLDSTATUS_OOP_FAIL_MASK  (0x1 \
 136                          << I40E_GLPE_FWLDSTATUS_OOP_FAIL_SHIFT)
 137
 138 struct i40iw_sc_dev;
 139 struct i40iw_sc_qp;
 140 struct i40iw_puda_buf;
 141 struct i40iw_puda_completion_info;
 142 struct i40iw_update_sds_info;
 143 struct i40iw_hmc_fcn_info;
 144 struct i40iw_virtchnl_work_info;
 145 struct i40iw_manage_vf_pble_info;
 146 struct i40iw_device;
 147 struct i40iw_hmc_info;
 148 struct i40iw_hw;
 149
 150 u8 __iomem *i40iw_get_hw_addr(void *dev);
 151 void i40iw_ieq_mpa_crc_ae(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
 152 enum i40iw_status_code i40iw_vf_wait_vchnl_resp(struct i40iw_sc_dev *dev);
 153 bool i40iw_vf_clear_to_send(struct i40iw_sc_dev *dev);
 154 enum i40iw_status_code i40iw_ieq_check_mpacrc(struct shash_desc *desc, void *addr,
 155                                               u32 length, u32 value);
 156 struct i40iw_sc_qp *i40iw_ieq_get_qp(struct i40iw_sc_dev *dev, struct i40iw_puda_buf *buf);
 157 void i40iw_ieq_update_tcpip_info(struct i40iw_puda_buf *buf, u16 length, u32 seqnum);
 158 void i40iw_free_hash_desc(struct shash_desc *);
 159 enum i40iw_status_code i40iw_init_hash_desc(struct shash_desc **);
 160 enum i40iw_status_code i40iw_puda_get_tcpip_info(struct i40iw_puda_completion_info *info,
 161                                                  struct i40iw_puda_buf *buf);
 162 enum i40iw_status_code i40iw_cqp_sds_cmd(struct i40iw_sc_dev *dev,
 163                                          struct i40iw_update_sds_info *info);
 164 enum i40iw_status_code i40iw_cqp_manage_hmc_fcn_cmd(struct i40iw_sc_dev *dev,
 165                                                     struct i40iw_hmc_fcn_info *hmcfcninfo);
 166 enum i40iw_status_code i40iw_cqp_query_fpm_values_cmd(struct i40iw_sc_dev *dev,
 167                                                       struct i40iw_dma_mem *values_mem,
 168                                                       u8 hmc_fn_id);
 169 enum i40iw_status_code i40iw_cqp_commit_fpm_values_cmd(struct i40iw_sc_dev *dev,
 170                                                        struct i40iw_dma_mem *values_mem,
 171                                                        u8 hmc_fn_id);
 172 enum i40iw_status_code i40iw_alloc_query_fpm_buf(struct i40iw_sc_dev *dev,
 173                                                  struct i40iw_dma_mem *mem);
 174 enum i40iw_status_code i40iw_cqp_manage_vf_pble_bp(struct i40iw_sc_dev *dev,
 175                                                    struct i40iw_manage_vf_pble_info *info);
 176 void i40iw_cqp_spawn_worker(struct i40iw_sc_dev *dev,
 177                             struct i40iw_virtchnl_work_info *work_info, u32 iw_vf_idx);
 178 void *i40iw_remove_head(struct list_head *list);
 179 void i40iw_qp_suspend_resume(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp, bool suspend);
 180
 181 void i40iw_term_modify_qp(struct i40iw_sc_qp *qp, u8 next_state, u8 term, u8 term_len);
 182 void i40iw_terminate_done(struct i40iw_sc_qp *qp, int timeout_occurred);
 183 void i40iw_terminate_start_timer(struct i40iw_sc_qp *qp);
 184 void i40iw_terminate_del_timer(struct i40iw_sc_qp *qp);
 185
 186 enum i40iw_status_code i40iw_hw_manage_vf_pble_bp(struct i40iw_device *iwdev,
 187                                                   struct i40iw_manage_vf_pble_info *info,
 188                                                   bool wait);
 189 struct i40iw_sc_vsi;
 190 void i40iw_hw_stats_start_timer(struct i40iw_sc_vsi *vsi);
 191 void i40iw_hw_stats_stop_timer(struct i40iw_sc_vsi *vsi);
 192 #define i40iw_mmiowb() do { } while (0)
 193 void i40iw_wr32(struct i40iw_hw *hw, u32 reg, u32 value);
 194 u32  i40iw_rd32(struct i40iw_hw *hw, u32 reg);
 195 #endif                          /* _I40IW_OSDEP_H_ */