2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/acpi.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <rdma/ib_addr.h>
37 #include <rdma/ib_smi.h>
38 #include <rdma/ib_user_verbs.h>
39 #include <rdma/ib_cache.h>
40 #include "hns_roce_common.h"
41 #include "hns_roce_device.h"
42 #include "hns_roce_hem.h"
44 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port,
50 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
53 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
56 for (i = 0; i < ETH_ALEN; i++)
57 hr_dev->dev_addr[port][i] = addr[i];
59 phy_port = hr_dev->iboe.phy_port[port];
60 return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
63 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
65 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
66 u32 port = attr->port_num - 1;
69 if (port >= hr_dev->caps.num_ports)
72 ret = hr_dev->hw->set_gid(hr_dev, attr->index, &attr->gid, attr);
77 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
79 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
80 u32 port = attr->port_num - 1;
83 if (port >= hr_dev->caps.num_ports)
86 ret = hr_dev->hw->set_gid(hr_dev, attr->index, NULL, NULL);
91 static int handle_en_event(struct hns_roce_dev *hr_dev, u32 port,
94 struct device *dev = hr_dev->dev;
95 struct net_device *netdev;
98 netdev = hr_dev->iboe.netdevs[port];
100 dev_err(dev, "can't find netdev on port(%u)!\n", port);
107 case NETDEV_REGISTER:
108 case NETDEV_CHANGEADDR:
109 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
113 * In v1 engine, only support all ports closed together.
117 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
124 static int hns_roce_netdev_event(struct notifier_block *self,
125 unsigned long event, void *ptr)
127 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
128 struct hns_roce_ib_iboe *iboe = NULL;
129 struct hns_roce_dev *hr_dev = NULL;
133 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
134 iboe = &hr_dev->iboe;
136 for (port = 0; port < hr_dev->caps.num_ports; port++) {
137 if (dev == iboe->netdevs[port]) {
138 ret = handle_en_event(hr_dev, port, event);
148 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
153 for (i = 0; i < hr_dev->caps.num_ports; i++) {
154 ret = hns_roce_set_mac(hr_dev, i,
155 hr_dev->iboe.netdevs[i]->dev_addr);
163 static int hns_roce_query_device(struct ib_device *ib_dev,
164 struct ib_device_attr *props,
165 struct ib_udata *uhw)
167 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
169 memset(props, 0, sizeof(*props));
171 props->fw_ver = hr_dev->caps.fw_ver;
172 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
173 props->max_mr_size = (u64)(~(0ULL));
174 props->page_size_cap = hr_dev->caps.page_size_cap;
175 props->vendor_id = hr_dev->vendor_id;
176 props->vendor_part_id = hr_dev->vendor_part_id;
177 props->hw_ver = hr_dev->hw_rev;
178 props->max_qp = hr_dev->caps.num_qps;
179 props->max_qp_wr = hr_dev->caps.max_wqes;
180 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
181 IB_DEVICE_RC_RNR_NAK_GEN;
182 props->max_send_sge = hr_dev->caps.max_sq_sg;
183 props->max_recv_sge = hr_dev->caps.max_rq_sg;
184 props->max_sge_rd = 1;
185 props->max_cq = hr_dev->caps.num_cqs;
186 props->max_cqe = hr_dev->caps.max_cqes;
187 props->max_mr = hr_dev->caps.num_mtpts;
188 props->max_pd = hr_dev->caps.num_pds;
189 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
190 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
191 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
192 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
193 props->max_pkeys = 1;
194 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
195 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
196 props->max_srq = hr_dev->caps.num_srqs;
197 props->max_srq_wr = hr_dev->caps.max_srq_wrs;
198 props->max_srq_sge = hr_dev->caps.max_srq_sges;
201 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR &&
202 hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
203 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
204 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
207 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
208 props->device_cap_flags |= IB_DEVICE_XRC;
213 static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num,
214 struct ib_port_attr *props)
216 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
217 struct device *dev = hr_dev->dev;
218 struct net_device *net_dev;
226 /* props being zeroed by the caller, avoid zeroing it here */
228 props->max_mtu = hr_dev->caps.max_mtu;
229 props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
230 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
231 IB_PORT_VENDOR_CLASS_SUP |
232 IB_PORT_BOOT_MGMT_SUP;
233 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
234 props->pkey_tbl_len = 1;
235 ret = ib_get_eth_speed(ib_dev, port_num, &props->active_speed,
236 &props->active_width);
238 ibdev_warn(ib_dev, "failed to get speed, ret = %d.\n", ret);
240 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
242 net_dev = hr_dev->iboe.netdevs[port];
244 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
245 dev_err(dev, "find netdev %u failed!\n", port);
249 mtu = iboe_get_mtu(net_dev->mtu);
250 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
251 props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ?
254 props->phys_state = props->state == IB_PORT_ACTIVE ?
255 IB_PORT_PHYS_STATE_LINK_UP :
256 IB_PORT_PHYS_STATE_DISABLED;
258 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
263 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
266 return IB_LINK_LAYER_ETHERNET;
269 static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index,
280 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
281 struct ib_device_modify *props)
285 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
288 if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
289 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
290 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
291 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
297 struct hns_user_mmap_entry *
298 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
300 enum hns_roce_mmap_type mmap_type)
302 struct hns_user_mmap_entry *entry;
305 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
309 entry->address = address;
310 entry->mmap_type = mmap_type;
313 /* pgoff 0 must be used by DB for compatibility */
314 case HNS_ROCE_MMAP_TYPE_DB:
315 ret = rdma_user_mmap_entry_insert_exact(
316 ucontext, &entry->rdma_entry, length, 0);
318 case HNS_ROCE_MMAP_TYPE_DWQE:
319 ret = rdma_user_mmap_entry_insert_range(
320 ucontext, &entry->rdma_entry, length, 1,
336 static void hns_roce_dealloc_uar_entry(struct hns_roce_ucontext *context)
338 if (context->db_mmap_entry)
339 rdma_user_mmap_entry_remove(
340 &context->db_mmap_entry->rdma_entry);
343 static int hns_roce_alloc_uar_entry(struct ib_ucontext *uctx)
345 struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
348 address = context->uar.pfn << PAGE_SHIFT;
349 context->db_mmap_entry = hns_roce_user_mmap_entry_insert(
350 uctx, address, PAGE_SIZE, HNS_ROCE_MMAP_TYPE_DB);
351 if (!context->db_mmap_entry)
357 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
358 struct ib_udata *udata)
360 struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
361 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
362 struct hns_roce_ib_alloc_ucontext_resp resp = {};
363 struct hns_roce_ib_alloc_ucontext ucmd = {};
369 resp.qp_tab_size = hr_dev->caps.num_qps;
370 resp.srq_tab_size = hr_dev->caps.num_srqs;
372 ret = ib_copy_from_udata(&ucmd, udata,
373 min(udata->inlen, sizeof(ucmd)));
377 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
378 context->config = ucmd.config & HNS_ROCE_EXSGE_FLAGS;
380 if (context->config & HNS_ROCE_EXSGE_FLAGS) {
381 resp.config |= HNS_ROCE_RSP_EXSGE_FLAGS;
382 resp.max_inline_data = hr_dev->caps.max_sq_inline;
385 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
386 context->config |= ucmd.config & HNS_ROCE_RQ_INLINE_FLAGS;
387 if (context->config & HNS_ROCE_RQ_INLINE_FLAGS)
388 resp.config |= HNS_ROCE_RSP_RQ_INLINE_FLAGS;
391 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQE_INLINE) {
392 context->config |= ucmd.config & HNS_ROCE_CQE_INLINE_FLAGS;
393 if (context->config & HNS_ROCE_CQE_INLINE_FLAGS)
394 resp.config |= HNS_ROCE_RSP_CQE_INLINE_FLAGS;
397 ret = hns_roce_uar_alloc(hr_dev, &context->uar);
399 goto error_fail_uar_alloc;
401 ret = hns_roce_alloc_uar_entry(uctx);
403 goto error_fail_uar_entry;
405 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
406 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
407 INIT_LIST_HEAD(&context->page_list);
408 mutex_init(&context->page_mutex);
411 resp.cqe_size = hr_dev->caps.cqe_sz;
413 ret = ib_copy_to_udata(udata, &resp,
414 min(udata->outlen, sizeof(resp)));
416 goto error_fail_copy_to_udata;
420 error_fail_copy_to_udata:
421 hns_roce_dealloc_uar_entry(context);
423 error_fail_uar_entry:
424 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
426 error_fail_uar_alloc:
430 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
432 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
433 struct hns_roce_dev *hr_dev = to_hr_dev(ibcontext->device);
435 hns_roce_dealloc_uar_entry(context);
437 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
440 static int hns_roce_mmap(struct ib_ucontext *uctx, struct vm_area_struct *vma)
442 struct rdma_user_mmap_entry *rdma_entry;
443 struct hns_user_mmap_entry *entry;
448 rdma_entry = rdma_user_mmap_entry_get_pgoff(uctx, vma->vm_pgoff);
452 entry = to_hns_mmap(rdma_entry);
453 pfn = entry->address >> PAGE_SHIFT;
455 switch (entry->mmap_type) {
456 case HNS_ROCE_MMAP_TYPE_DB:
457 case HNS_ROCE_MMAP_TYPE_DWQE:
458 prot = pgprot_device(vma->vm_page_prot);
465 ret = rdma_user_mmap_io(uctx, vma, pfn, rdma_entry->npages * PAGE_SIZE,
469 rdma_user_mmap_entry_put(rdma_entry);
473 static void hns_roce_free_mmap(struct rdma_user_mmap_entry *rdma_entry)
475 struct hns_user_mmap_entry *entry = to_hns_mmap(rdma_entry);
480 static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num,
481 struct ib_port_immutable *immutable)
483 struct ib_port_attr attr;
486 ret = ib_query_port(ib_dev, port_num, &attr);
490 immutable->pkey_tbl_len = attr.pkey_tbl_len;
491 immutable->gid_tbl_len = attr.gid_tbl_len;
493 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
494 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
495 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
496 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
501 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
505 static void hns_roce_get_fw_ver(struct ib_device *device, char *str)
507 u64 fw_ver = to_hr_dev(device)->caps.fw_ver;
508 unsigned int major, minor, sub_minor;
510 major = upper_32_bits(fw_ver);
511 minor = high_16_bits(lower_32_bits(fw_ver));
512 sub_minor = low_16_bits(fw_ver);
514 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor,
518 #define HNS_ROCE_HW_CNT(ename, cname) \
519 [HNS_ROCE_HW_##ename##_CNT].name = cname
521 static const struct rdma_stat_desc hns_roce_port_stats_descs[] = {
522 HNS_ROCE_HW_CNT(RX_RC_PKT, "rx_rc_pkt"),
523 HNS_ROCE_HW_CNT(RX_UC_PKT, "rx_uc_pkt"),
524 HNS_ROCE_HW_CNT(RX_UD_PKT, "rx_ud_pkt"),
525 HNS_ROCE_HW_CNT(RX_XRC_PKT, "rx_xrc_pkt"),
526 HNS_ROCE_HW_CNT(RX_PKT, "rx_pkt"),
527 HNS_ROCE_HW_CNT(RX_ERR_PKT, "rx_err_pkt"),
528 HNS_ROCE_HW_CNT(RX_CNP_PKT, "rx_cnp_pkt"),
529 HNS_ROCE_HW_CNT(TX_RC_PKT, "tx_rc_pkt"),
530 HNS_ROCE_HW_CNT(TX_UC_PKT, "tx_uc_pkt"),
531 HNS_ROCE_HW_CNT(TX_UD_PKT, "tx_ud_pkt"),
532 HNS_ROCE_HW_CNT(TX_XRC_PKT, "tx_xrc_pkt"),
533 HNS_ROCE_HW_CNT(TX_PKT, "tx_pkt"),
534 HNS_ROCE_HW_CNT(TX_ERR_PKT, "tx_err_pkt"),
535 HNS_ROCE_HW_CNT(TX_CNP_PKT, "tx_cnp_pkt"),
536 HNS_ROCE_HW_CNT(TRP_GET_MPT_ERR_PKT, "trp_get_mpt_err_pkt"),
537 HNS_ROCE_HW_CNT(TRP_GET_IRRL_ERR_PKT, "trp_get_irrl_err_pkt"),
538 HNS_ROCE_HW_CNT(ECN_DB, "ecn_doorbell"),
539 HNS_ROCE_HW_CNT(RX_BUF, "rx_buffer"),
540 HNS_ROCE_HW_CNT(TRP_RX_SOF, "trp_rx_sof"),
541 HNS_ROCE_HW_CNT(CQ_CQE, "cq_cqe"),
542 HNS_ROCE_HW_CNT(CQ_POE, "cq_poe"),
543 HNS_ROCE_HW_CNT(CQ_NOTIFY, "cq_notify"),
546 static struct rdma_hw_stats *hns_roce_alloc_hw_port_stats(
547 struct ib_device *device, u32 port_num)
549 struct hns_roce_dev *hr_dev = to_hr_dev(device);
551 if (port_num > hr_dev->caps.num_ports) {
552 ibdev_err(device, "invalid port num.\n");
556 if (hr_dev->pci_dev->revision <= PCI_REVISION_ID_HIP08 ||
560 return rdma_alloc_hw_stats_struct(hns_roce_port_stats_descs,
561 ARRAY_SIZE(hns_roce_port_stats_descs),
562 RDMA_HW_STATS_DEFAULT_LIFESPAN);
565 static int hns_roce_get_hw_stats(struct ib_device *device,
566 struct rdma_hw_stats *stats,
569 struct hns_roce_dev *hr_dev = to_hr_dev(device);
570 int num_counters = HNS_ROCE_HW_CNT_TOTAL;
576 if (port > hr_dev->caps.num_ports)
579 if (hr_dev->pci_dev->revision <= PCI_REVISION_ID_HIP08 ||
583 ret = hr_dev->hw->query_hw_counter(hr_dev, stats->value, port,
586 ibdev_err(device, "failed to query hw counter, ret = %d\n",
594 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
596 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
598 hr_dev->active = false;
599 unregister_netdevice_notifier(&iboe->nb);
600 ib_unregister_device(&hr_dev->ib_dev);
603 static const struct ib_device_ops hns_roce_dev_ops = {
604 .owner = THIS_MODULE,
605 .driver_id = RDMA_DRIVER_HNS,
607 .uverbs_no_driver_id_binding = 1,
609 .get_dev_fw_str = hns_roce_get_fw_ver,
610 .add_gid = hns_roce_add_gid,
611 .alloc_pd = hns_roce_alloc_pd,
612 .alloc_ucontext = hns_roce_alloc_ucontext,
613 .create_ah = hns_roce_create_ah,
614 .create_user_ah = hns_roce_create_ah,
615 .create_cq = hns_roce_create_cq,
616 .create_qp = hns_roce_create_qp,
617 .dealloc_pd = hns_roce_dealloc_pd,
618 .dealloc_ucontext = hns_roce_dealloc_ucontext,
619 .del_gid = hns_roce_del_gid,
620 .dereg_mr = hns_roce_dereg_mr,
621 .destroy_ah = hns_roce_destroy_ah,
622 .destroy_cq = hns_roce_destroy_cq,
623 .disassociate_ucontext = hns_roce_disassociate_ucontext,
624 .get_dma_mr = hns_roce_get_dma_mr,
625 .get_link_layer = hns_roce_get_link_layer,
626 .get_port_immutable = hns_roce_port_immutable,
627 .mmap = hns_roce_mmap,
628 .mmap_free = hns_roce_free_mmap,
629 .modify_device = hns_roce_modify_device,
630 .modify_qp = hns_roce_modify_qp,
631 .query_ah = hns_roce_query_ah,
632 .query_device = hns_roce_query_device,
633 .query_pkey = hns_roce_query_pkey,
634 .query_port = hns_roce_query_port,
635 .reg_user_mr = hns_roce_reg_user_mr,
636 .alloc_hw_port_stats = hns_roce_alloc_hw_port_stats,
637 .get_hw_stats = hns_roce_get_hw_stats,
639 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
640 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq),
641 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
642 INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp),
643 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
646 static const struct ib_device_ops hns_roce_dev_mr_ops = {
647 .rereg_user_mr = hns_roce_rereg_user_mr,
650 static const struct ib_device_ops hns_roce_dev_mw_ops = {
651 .alloc_mw = hns_roce_alloc_mw,
652 .dealloc_mw = hns_roce_dealloc_mw,
654 INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw),
657 static const struct ib_device_ops hns_roce_dev_frmr_ops = {
658 .alloc_mr = hns_roce_alloc_mr,
659 .map_mr_sg = hns_roce_map_mr_sg,
662 static const struct ib_device_ops hns_roce_dev_srq_ops = {
663 .create_srq = hns_roce_create_srq,
664 .destroy_srq = hns_roce_destroy_srq,
666 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
669 static const struct ib_device_ops hns_roce_dev_xrcd_ops = {
670 .alloc_xrcd = hns_roce_alloc_xrcd,
671 .dealloc_xrcd = hns_roce_dealloc_xrcd,
673 INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd),
676 static const struct ib_device_ops hns_roce_dev_restrack_ops = {
677 .fill_res_cq_entry = hns_roce_fill_res_cq_entry,
678 .fill_res_cq_entry_raw = hns_roce_fill_res_cq_entry_raw,
679 .fill_res_qp_entry = hns_roce_fill_res_qp_entry,
680 .fill_res_qp_entry_raw = hns_roce_fill_res_qp_entry_raw,
681 .fill_res_mr_entry = hns_roce_fill_res_mr_entry,
682 .fill_res_mr_entry_raw = hns_roce_fill_res_mr_entry_raw,
685 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
688 struct hns_roce_ib_iboe *iboe = NULL;
689 struct ib_device *ib_dev = NULL;
690 struct device *dev = hr_dev->dev;
693 iboe = &hr_dev->iboe;
694 spin_lock_init(&iboe->lock);
696 ib_dev = &hr_dev->ib_dev;
698 ib_dev->node_type = RDMA_NODE_IB_CA;
699 ib_dev->dev.parent = dev;
701 ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
702 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
703 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
705 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR)
706 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
708 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW)
709 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops);
711 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
712 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
714 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
715 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
716 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
719 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
720 ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops);
722 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
723 ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
724 ib_set_device_ops(ib_dev, &hns_roce_dev_restrack_ops);
725 for (i = 0; i < hr_dev->caps.num_ports; i++) {
726 if (!hr_dev->iboe.netdevs[i])
729 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i],
734 dma_set_max_seg_size(dev, UINT_MAX);
735 ret = ib_register_device(ib_dev, "hns_%d", dev);
737 dev_err(dev, "ib_register_device failed!\n");
741 ret = hns_roce_setup_mtu_mac(hr_dev);
743 dev_err(dev, "setup_mtu_mac failed!\n");
744 goto error_failed_setup_mtu_mac;
747 iboe->nb.notifier_call = hns_roce_netdev_event;
748 ret = register_netdevice_notifier(&iboe->nb);
750 dev_err(dev, "register_netdevice_notifier failed!\n");
751 goto error_failed_setup_mtu_mac;
754 hr_dev->active = true;
757 error_failed_setup_mtu_mac:
758 ib_unregister_device(ib_dev);
763 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
765 struct device *dev = hr_dev->dev;
768 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
769 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
770 hr_dev->caps.num_mtpts);
772 dev_err(dev, "failed to init MTPT context memory, aborting.\n");
776 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
777 HEM_TYPE_QPC, hr_dev->caps.qpc_sz,
778 hr_dev->caps.num_qps);
780 dev_err(dev, "failed to init QP context memory, aborting.\n");
784 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
786 hr_dev->caps.irrl_entry_sz *
787 hr_dev->caps.max_qp_init_rdma,
788 hr_dev->caps.num_qps);
790 dev_err(dev, "failed to init irrl_table memory, aborting.\n");
794 if (hr_dev->caps.trrl_entry_sz) {
795 ret = hns_roce_init_hem_table(hr_dev,
796 &hr_dev->qp_table.trrl_table,
798 hr_dev->caps.trrl_entry_sz *
799 hr_dev->caps.max_qp_dest_rdma,
800 hr_dev->caps.num_qps);
803 "failed to init trrl_table memory, aborting.\n");
808 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
809 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
810 hr_dev->caps.num_cqs);
812 dev_err(dev, "failed to init CQ context memory, aborting.\n");
816 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
817 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
819 hr_dev->caps.srqc_entry_sz,
820 hr_dev->caps.num_srqs);
823 "failed to init SRQ context memory, aborting.\n");
828 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
829 ret = hns_roce_init_hem_table(hr_dev,
830 &hr_dev->qp_table.sccc_table,
832 hr_dev->caps.sccc_sz,
833 hr_dev->caps.num_qps);
836 "failed to init SCC context memory, aborting.\n");
841 if (hr_dev->caps.qpc_timer_entry_sz) {
842 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table,
844 hr_dev->caps.qpc_timer_entry_sz,
845 hr_dev->caps.qpc_timer_bt_num);
848 "failed to init QPC timer memory, aborting.\n");
853 if (hr_dev->caps.cqc_timer_entry_sz) {
854 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table,
856 hr_dev->caps.cqc_timer_entry_sz,
857 hr_dev->caps.cqc_timer_bt_num);
860 "failed to init CQC timer memory, aborting.\n");
861 goto err_unmap_qpc_timer;
865 if (hr_dev->caps.gmv_entry_sz) {
866 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table,
868 hr_dev->caps.gmv_entry_sz,
869 hr_dev->caps.gmv_entry_num);
872 "failed to init gmv table memory, ret = %d\n",
874 goto err_unmap_cqc_timer;
881 if (hr_dev->caps.cqc_timer_entry_sz)
882 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table);
885 if (hr_dev->caps.qpc_timer_entry_sz)
886 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table);
889 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
890 hns_roce_cleanup_hem_table(hr_dev,
891 &hr_dev->qp_table.sccc_table);
893 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
894 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
897 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
900 if (hr_dev->caps.trrl_entry_sz)
901 hns_roce_cleanup_hem_table(hr_dev,
902 &hr_dev->qp_table.trrl_table);
905 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
908 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
911 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
917 * hns_roce_setup_hca - setup host channel adapter
918 * @hr_dev: pointer to hns roce device
921 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
923 struct device *dev = hr_dev->dev;
926 spin_lock_init(&hr_dev->sm_lock);
928 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
929 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
930 INIT_LIST_HEAD(&hr_dev->pgdir_list);
931 mutex_init(&hr_dev->pgdir_mutex);
934 hns_roce_init_uar_table(hr_dev);
936 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
938 dev_err(dev, "failed to allocate priv_uar.\n");
939 goto err_uar_table_free;
942 ret = hns_roce_init_qp_table(hr_dev);
944 dev_err(dev, "failed to init qp_table.\n");
945 goto err_uar_table_free;
948 hns_roce_init_pd_table(hr_dev);
950 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
951 hns_roce_init_xrcd_table(hr_dev);
953 hns_roce_init_mr_table(hr_dev);
955 hns_roce_init_cq_table(hr_dev);
957 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
958 hns_roce_init_srq_table(hr_dev);
963 ida_destroy(&hr_dev->uar_ida.ida);
967 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq)
969 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
972 spin_lock_irqsave(&hr_cq->lock, flags);
973 if (cq->comp_handler) {
974 if (!hr_cq->is_armed) {
976 list_add_tail(&hr_cq->node, cq_list);
979 spin_unlock_irqrestore(&hr_cq->lock, flags);
982 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)
984 struct hns_roce_qp *hr_qp;
985 struct hns_roce_cq *hr_cq;
986 struct list_head cq_list;
987 unsigned long flags_qp;
990 INIT_LIST_HEAD(&cq_list);
992 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
993 list_for_each_entry(hr_qp, &hr_dev->qp_list, node) {
994 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp);
995 if (hr_qp->sq.tail != hr_qp->sq.head)
996 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq);
997 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp);
999 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp);
1000 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head))
1001 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq);
1002 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp);
1005 list_for_each_entry(hr_cq, &cq_list, node)
1006 hns_roce_cq_completion(hr_dev, hr_cq->cqn);
1008 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
1011 int hns_roce_init(struct hns_roce_dev *hr_dev)
1013 struct device *dev = hr_dev->dev;
1016 hr_dev->is_reset = false;
1018 if (hr_dev->hw->cmq_init) {
1019 ret = hr_dev->hw->cmq_init(hr_dev);
1021 dev_err(dev, "init RoCE Command Queue failed!\n");
1026 ret = hr_dev->hw->hw_profile(hr_dev);
1028 dev_err(dev, "get RoCE engine profile failed!\n");
1029 goto error_failed_cmd_init;
1032 ret = hns_roce_cmd_init(hr_dev);
1034 dev_err(dev, "cmd init failed!\n");
1035 goto error_failed_cmd_init;
1038 /* EQ depends on poll mode, event mode depends on EQ */
1039 ret = hr_dev->hw->init_eq(hr_dev);
1041 dev_err(dev, "eq init failed!\n");
1042 goto error_failed_eq_table;
1045 if (hr_dev->cmd_mod) {
1046 ret = hns_roce_cmd_use_events(hr_dev);
1049 "Cmd event mode failed, set back to poll!\n");
1052 ret = hns_roce_init_hem(hr_dev);
1054 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
1055 goto error_failed_init_hem;
1058 ret = hns_roce_setup_hca(hr_dev);
1060 dev_err(dev, "setup hca failed!\n");
1061 goto error_failed_setup_hca;
1064 if (hr_dev->hw->hw_init) {
1065 ret = hr_dev->hw->hw_init(hr_dev);
1067 dev_err(dev, "hw_init failed!\n");
1068 goto error_failed_engine_init;
1072 INIT_LIST_HEAD(&hr_dev->qp_list);
1073 spin_lock_init(&hr_dev->qp_list_lock);
1074 INIT_LIST_HEAD(&hr_dev->dip_list);
1075 spin_lock_init(&hr_dev->dip_list_lock);
1077 ret = hns_roce_register_device(hr_dev);
1079 goto error_failed_register_device;
1083 error_failed_register_device:
1084 if (hr_dev->hw->hw_exit)
1085 hr_dev->hw->hw_exit(hr_dev);
1087 error_failed_engine_init:
1088 hns_roce_cleanup_bitmap(hr_dev);
1090 error_failed_setup_hca:
1091 hns_roce_cleanup_hem(hr_dev);
1093 error_failed_init_hem:
1094 if (hr_dev->cmd_mod)
1095 hns_roce_cmd_use_polling(hr_dev);
1096 hr_dev->hw->cleanup_eq(hr_dev);
1098 error_failed_eq_table:
1099 hns_roce_cmd_cleanup(hr_dev);
1101 error_failed_cmd_init:
1102 if (hr_dev->hw->cmq_exit)
1103 hr_dev->hw->cmq_exit(hr_dev);
1108 void hns_roce_exit(struct hns_roce_dev *hr_dev)
1110 hns_roce_unregister_device(hr_dev);
1112 if (hr_dev->hw->hw_exit)
1113 hr_dev->hw->hw_exit(hr_dev);
1114 hns_roce_cleanup_bitmap(hr_dev);
1115 hns_roce_cleanup_hem(hr_dev);
1117 if (hr_dev->cmd_mod)
1118 hns_roce_cmd_use_polling(hr_dev);
1120 hr_dev->hw->cleanup_eq(hr_dev);
1121 hns_roce_cmd_cleanup(hr_dev);
1122 if (hr_dev->hw->cmq_exit)
1123 hr_dev->hw->cmq_exit(hr_dev);
1126 MODULE_LICENSE("Dual BSD/GPL");
1127 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
1128 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
1129 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
1130 MODULE_DESCRIPTION("HNS RoCE Driver");