drivers/infiniband/hw/hns/hns_roce_main.c

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33 #include <linux/acpi.h>
  34 #include <linux/of_platform.h>
  35 #include <linux/module.h>
  36 #include <linux/pci.h>
  37 #include <rdma/ib_addr.h>
  38 #include <rdma/ib_smi.h>
  39 #include <rdma/ib_user_verbs.h>
  40 #include <rdma/ib_cache.h>
  41 #include "hns_roce_common.h"
  42 #include "hns_roce_device.h"
  43 #include "hns_roce_hem.h"
  44
  45 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port, u8 *addr)
  46 {
  47         u8 phy_port;
  48         u32 i;
  49
  50         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
  51                 return 0;
  52
  53         if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
  54                 return 0;
  55
  56         for (i = 0; i < ETH_ALEN; i++)
  57                 hr_dev->dev_addr[port][i] = addr[i];
  58
  59         phy_port = hr_dev->iboe.phy_port[port];
  60         return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
  61 }
  62
  63 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
  64 {
  65         struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  66         u32 port = attr->port_num - 1;
  67         int ret;
  68
  69         if (port >= hr_dev->caps.num_ports)
  70                 return -EINVAL;
  71
  72         ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr);
  73
  74         return ret;
  75 }
  76
  77 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
  78 {
  79         struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  80         u32 port = attr->port_num - 1;
  81         int ret;
  82
  83         if (port >= hr_dev->caps.num_ports)
  84                 return -EINVAL;
  85
  86         ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, NULL, NULL);
  87
  88         return ret;
  89 }
  90
  91 static int handle_en_event(struct hns_roce_dev *hr_dev, u32 port,
  92                            unsigned long event)
  93 {
  94         struct device *dev = hr_dev->dev;
  95         struct net_device *netdev;
  96         int ret = 0;
  97
  98         netdev = hr_dev->iboe.netdevs[port];
  99         if (!netdev) {
 100                 dev_err(dev, "Can't find netdev on port(%u)!\n", port);
 101                 return -ENODEV;
 102         }
 103
 104         switch (event) {
 105         case NETDEV_UP:
 106         case NETDEV_CHANGE:
 107         case NETDEV_REGISTER:
 108         case NETDEV_CHANGEADDR:
 109                 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
 110                 break;
 111         case NETDEV_DOWN:
 112                 /*
 113                  * In v1 engine, only support all ports closed together.
 114                  */
 115                 break;
 116         default:
 117                 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
 118                 break;
 119         }
 120
 121         return ret;
 122 }
 123
 124 static int hns_roce_netdev_event(struct notifier_block *self,
 125                                  unsigned long event, void *ptr)
 126 {
 127         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
 128         struct hns_roce_ib_iboe *iboe = NULL;
 129         struct hns_roce_dev *hr_dev = NULL;
 130         int ret;
 131         u32 port;
 132
 133         hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
 134         iboe = &hr_dev->iboe;
 135
 136         for (port = 0; port < hr_dev->caps.num_ports; port++) {
 137                 if (dev == iboe->netdevs[port]) {
 138                         ret = handle_en_event(hr_dev, port, event);
 139                         if (ret)
 140                                 return NOTIFY_DONE;
 141                         break;
 142                 }
 143         }
 144
 145         return NOTIFY_DONE;
 146 }
 147
 148 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
 149 {
 150         int ret;
 151         u8 i;
 152
 153         for (i = 0; i < hr_dev->caps.num_ports; i++) {
 154                 if (hr_dev->hw->set_mtu)
 155                         hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
 156                                             hr_dev->caps.max_mtu);
 157                 ret = hns_roce_set_mac(hr_dev, i,
 158                                        hr_dev->iboe.netdevs[i]->dev_addr);
 159                 if (ret)
 160                         return ret;
 161         }
 162
 163         return 0;
 164 }
 165
 166 static int hns_roce_query_device(struct ib_device *ib_dev,
 167                                  struct ib_device_attr *props,
 168                                  struct ib_udata *uhw)
 169 {
 170         struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
 171
 172         memset(props, 0, sizeof(*props));
 173
 174         props->fw_ver = hr_dev->caps.fw_ver;
 175         props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
 176         props->max_mr_size = (u64)(~(0ULL));
 177         props->page_size_cap = hr_dev->caps.page_size_cap;
 178         props->vendor_id = hr_dev->vendor_id;
 179         props->vendor_part_id = hr_dev->vendor_part_id;
 180         props->hw_ver = hr_dev->hw_rev;
 181         props->max_qp = hr_dev->caps.num_qps;
 182         props->max_qp_wr = hr_dev->caps.max_wqes;
 183         props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
 184                                   IB_DEVICE_RC_RNR_NAK_GEN;
 185         props->max_send_sge = hr_dev->caps.max_sq_sg;
 186         props->max_recv_sge = hr_dev->caps.max_rq_sg;
 187         props->max_sge_rd = 1;
 188         props->max_cq = hr_dev->caps.num_cqs;
 189         props->max_cqe = hr_dev->caps.max_cqes;
 190         props->max_mr = hr_dev->caps.num_mtpts;
 191         props->max_pd = hr_dev->caps.num_pds;
 192         props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
 193         props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
 194         props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
 195                             IB_ATOMIC_HCA : IB_ATOMIC_NONE;
 196         props->max_pkeys = 1;
 197         props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
 198         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 199                 props->max_srq = hr_dev->caps.num_srqs;
 200                 props->max_srq_wr = hr_dev->caps.max_srq_wrs;
 201                 props->max_srq_sge = hr_dev->caps.max_srq_sges;
 202         }
 203
 204         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR &&
 205             hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
 206                 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 207                 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
 208         }
 209
 210         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
 211                 props->device_cap_flags |= IB_DEVICE_XRC;
 212
 213         return 0;
 214 }
 215
 216 static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num,
 217                                struct ib_port_attr *props)
 218 {
 219         struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
 220         struct device *dev = hr_dev->dev;
 221         struct net_device *net_dev;
 222         unsigned long flags;
 223         enum ib_mtu mtu;
 224         u32 port;
 225
 226         port = port_num - 1;
 227
 228         /* props being zeroed by the caller, avoid zeroing it here */
 229
 230         props->max_mtu = hr_dev->caps.max_mtu;
 231         props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
 232         props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
 233                                 IB_PORT_VENDOR_CLASS_SUP |
 234                                 IB_PORT_BOOT_MGMT_SUP;
 235         props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
 236         props->pkey_tbl_len = 1;
 237         props->active_width = IB_WIDTH_4X;
 238         props->active_speed = 1;
 239
 240         spin_lock_irqsave(&hr_dev->iboe.lock, flags);
 241
 242         net_dev = hr_dev->iboe.netdevs[port];
 243         if (!net_dev) {
 244                 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
 245                 dev_err(dev, "Find netdev %u failed!\n", port);
 246                 return -EINVAL;
 247         }
 248
 249         mtu = iboe_get_mtu(net_dev->mtu);
 250         props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
 251         props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ?
 252                                IB_PORT_ACTIVE :
 253                                IB_PORT_DOWN;
 254         props->phys_state = props->state == IB_PORT_ACTIVE ?
 255                                     IB_PORT_PHYS_STATE_LINK_UP :
 256                                     IB_PORT_PHYS_STATE_DISABLED;
 257
 258         spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
 259
 260         return 0;
 261 }
 262
 263 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
 264                                                     u32 port_num)
 265 {
 266         return IB_LINK_LAYER_ETHERNET;
 267 }
 268
 269 static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index,
 270                                u16 *pkey)
 271 {
 272         if (index > 0)
 273                 return -EINVAL;
 274
 275         *pkey = PKEY_ID;
 276
 277         return 0;
 278 }
 279
 280 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
 281                                   struct ib_device_modify *props)
 282 {
 283         unsigned long flags;
 284
 285         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 286                 return -EOPNOTSUPP;
 287
 288         if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
 289                 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
 290                 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
 291                 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
 292         }
 293
 294         return 0;
 295 }
 296
 297 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
 298                                    struct ib_udata *udata)
 299 {
 300         int ret;
 301         struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
 302         struct hns_roce_ib_alloc_ucontext_resp resp = {};
 303         struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
 304
 305         if (!hr_dev->active)
 306                 return -EAGAIN;
 307
 308         resp.qp_tab_size = hr_dev->caps.num_qps;
 309         resp.srq_tab_size = hr_dev->caps.num_srqs;
 310
 311         ret = hns_roce_uar_alloc(hr_dev, &context->uar);
 312         if (ret)
 313                 goto error_fail_uar_alloc;
 314
 315         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
 316             hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
 317                 INIT_LIST_HEAD(&context->page_list);
 318                 mutex_init(&context->page_mutex);
 319         }
 320
 321         resp.cqe_size = hr_dev->caps.cqe_sz;
 322
 323         ret = ib_copy_to_udata(udata, &resp,
 324                                min(udata->outlen, sizeof(resp)));
 325         if (ret)
 326                 goto error_fail_copy_to_udata;
 327
 328         return 0;
 329
 330 error_fail_copy_to_udata:
 331         ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
 332
 333 error_fail_uar_alloc:
 334         return ret;
 335 }
 336
 337 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
 338 {
 339         struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
 340         struct hns_roce_dev *hr_dev = to_hr_dev(ibcontext->device);
 341
 342         ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
 343 }
 344
 345 static int hns_roce_mmap(struct ib_ucontext *context,
 346                          struct vm_area_struct *vma)
 347 {
 348         struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
 349
 350         switch (vma->vm_pgoff) {
 351         case 0:
 352                 return rdma_user_mmap_io(context, vma,
 353                                          to_hr_ucontext(context)->uar.pfn,
 354                                          PAGE_SIZE,
 355                                          pgprot_device(vma->vm_page_prot),
 356                                          NULL);
 357
 358         /* vm_pgoff: 1 -- TPTR */
 359         case 1:
 360                 if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size)
 361                         return -EINVAL;
 362                 /*
 363                  * FIXME: using io_remap_pfn_range on the dma address returned
 364                  * by dma_alloc_coherent is totally wrong.
 365                  */
 366                 return rdma_user_mmap_io(context, vma,
 367                                          hr_dev->tptr_dma_addr >> PAGE_SHIFT,
 368                                          hr_dev->tptr_size,
 369                                          vma->vm_page_prot,
 370                                          NULL);
 371
 372         default:
 373                 return -EINVAL;
 374         }
 375 }
 376
 377 static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num,
 378                                    struct ib_port_immutable *immutable)
 379 {
 380         struct ib_port_attr attr;
 381         int ret;
 382
 383         ret = ib_query_port(ib_dev, port_num, &attr);
 384         if (ret)
 385                 return ret;
 386
 387         immutable->pkey_tbl_len = attr.pkey_tbl_len;
 388         immutable->gid_tbl_len = attr.gid_tbl_len;
 389
 390         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
 391         immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
 392         if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
 393                 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
 394
 395         return 0;
 396 }
 397
 398 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
 399 {
 400 }
 401
 402 static void hns_roce_get_fw_ver(struct ib_device *device, char *str)
 403 {
 404         u64 fw_ver = to_hr_dev(device)->caps.fw_ver;
 405         unsigned int major, minor, sub_minor;
 406
 407         major = upper_32_bits(fw_ver);
 408         minor = high_16_bits(lower_32_bits(fw_ver));
 409         sub_minor = low_16_bits(fw_ver);
 410
 411         snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor,
 412                  sub_minor);
 413 }
 414
 415 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
 416 {
 417         struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
 418
 419         hr_dev->active = false;
 420         unregister_netdevice_notifier(&iboe->nb);
 421         ib_unregister_device(&hr_dev->ib_dev);
 422 }
 423
 424 static const struct ib_device_ops hns_roce_dev_ops = {
 425         .owner = THIS_MODULE,
 426         .driver_id = RDMA_DRIVER_HNS,
 427         .uverbs_abi_ver = 1,
 428         .uverbs_no_driver_id_binding = 1,
 429
 430         .get_dev_fw_str = hns_roce_get_fw_ver,
 431         .add_gid = hns_roce_add_gid,
 432         .alloc_pd = hns_roce_alloc_pd,
 433         .alloc_ucontext = hns_roce_alloc_ucontext,
 434         .create_ah = hns_roce_create_ah,
 435         .create_user_ah = hns_roce_create_ah,
 436         .create_cq = hns_roce_create_cq,
 437         .create_qp = hns_roce_create_qp,
 438         .dealloc_pd = hns_roce_dealloc_pd,
 439         .dealloc_ucontext = hns_roce_dealloc_ucontext,
 440         .del_gid = hns_roce_del_gid,
 441         .dereg_mr = hns_roce_dereg_mr,
 442         .destroy_ah = hns_roce_destroy_ah,
 443         .destroy_cq = hns_roce_destroy_cq,
 444         .disassociate_ucontext = hns_roce_disassociate_ucontext,
 445         .fill_res_cq_entry = hns_roce_fill_res_cq_entry,
 446         .get_dma_mr = hns_roce_get_dma_mr,
 447         .get_link_layer = hns_roce_get_link_layer,
 448         .get_port_immutable = hns_roce_port_immutable,
 449         .mmap = hns_roce_mmap,
 450         .modify_device = hns_roce_modify_device,
 451         .modify_qp = hns_roce_modify_qp,
 452         .query_ah = hns_roce_query_ah,
 453         .query_device = hns_roce_query_device,
 454         .query_pkey = hns_roce_query_pkey,
 455         .query_port = hns_roce_query_port,
 456         .reg_user_mr = hns_roce_reg_user_mr,
 457
 458         INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
 459         INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq),
 460         INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
 461         INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp),
 462         INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
 463 };
 464
 465 static const struct ib_device_ops hns_roce_dev_mr_ops = {
 466         .rereg_user_mr = hns_roce_rereg_user_mr,
 467 };
 468
 469 static const struct ib_device_ops hns_roce_dev_mw_ops = {
 470         .alloc_mw = hns_roce_alloc_mw,
 471         .dealloc_mw = hns_roce_dealloc_mw,
 472
 473         INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw),
 474 };
 475
 476 static const struct ib_device_ops hns_roce_dev_frmr_ops = {
 477         .alloc_mr = hns_roce_alloc_mr,
 478         .map_mr_sg = hns_roce_map_mr_sg,
 479 };
 480
 481 static const struct ib_device_ops hns_roce_dev_srq_ops = {
 482         .create_srq = hns_roce_create_srq,
 483         .destroy_srq = hns_roce_destroy_srq,
 484
 485         INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
 486 };
 487
 488 static const struct ib_device_ops hns_roce_dev_xrcd_ops = {
 489         .alloc_xrcd = hns_roce_alloc_xrcd,
 490         .dealloc_xrcd = hns_roce_dealloc_xrcd,
 491
 492         INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd),
 493 };
 494
 495 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
 496 {
 497         int ret;
 498         struct hns_roce_ib_iboe *iboe = NULL;
 499         struct ib_device *ib_dev = NULL;
 500         struct device *dev = hr_dev->dev;
 501         unsigned int i;
 502
 503         iboe = &hr_dev->iboe;
 504         spin_lock_init(&iboe->lock);
 505
 506         ib_dev = &hr_dev->ib_dev;
 507
 508         ib_dev->node_type = RDMA_NODE_IB_CA;
 509         ib_dev->dev.parent = dev;
 510
 511         ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
 512         ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
 513         ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
 514
 515         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR)
 516                 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
 517
 518         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW)
 519                 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops);
 520
 521         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
 522                 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
 523
 524         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 525                 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
 526                 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
 527         }
 528
 529         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
 530                 ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops);
 531
 532         ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
 533         ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
 534         for (i = 0; i < hr_dev->caps.num_ports; i++) {
 535                 if (!hr_dev->iboe.netdevs[i])
 536                         continue;
 537
 538                 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i],
 539                                            i + 1);
 540                 if (ret)
 541                         return ret;
 542         }
 543         dma_set_max_seg_size(dev, UINT_MAX);
 544         ret = ib_register_device(ib_dev, "hns_%d", dev);
 545         if (ret) {
 546                 dev_err(dev, "ib_register_device failed!\n");
 547                 return ret;
 548         }
 549
 550         ret = hns_roce_setup_mtu_mac(hr_dev);
 551         if (ret) {
 552                 dev_err(dev, "setup_mtu_mac failed!\n");
 553                 goto error_failed_setup_mtu_mac;
 554         }
 555
 556         iboe->nb.notifier_call = hns_roce_netdev_event;
 557         ret = register_netdevice_notifier(&iboe->nb);
 558         if (ret) {
 559                 dev_err(dev, "register_netdevice_notifier failed!\n");
 560                 goto error_failed_setup_mtu_mac;
 561         }
 562
 563         hr_dev->active = true;
 564         return 0;
 565
 566 error_failed_setup_mtu_mac:
 567         ib_unregister_device(ib_dev);
 568
 569         return ret;
 570 }
 571
 572 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
 573 {
 574         struct device *dev = hr_dev->dev;
 575         int ret;
 576
 577         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
 578                                       HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
 579                                       hr_dev->caps.num_mtpts, 1);
 580         if (ret) {
 581                 dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
 582                 return ret;
 583         }
 584
 585         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
 586                                       HEM_TYPE_QPC, hr_dev->caps.qpc_sz,
 587                                       hr_dev->caps.num_qps, 1);
 588         if (ret) {
 589                 dev_err(dev, "Failed to init QP context memory, aborting.\n");
 590                 goto err_unmap_dmpt;
 591         }
 592
 593         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
 594                                       HEM_TYPE_IRRL,
 595                                       hr_dev->caps.irrl_entry_sz *
 596                                       hr_dev->caps.max_qp_init_rdma,
 597                                       hr_dev->caps.num_qps, 1);
 598         if (ret) {
 599                 dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
 600                 goto err_unmap_qp;
 601         }
 602
 603         if (hr_dev->caps.trrl_entry_sz) {
 604                 ret = hns_roce_init_hem_table(hr_dev,
 605                                               &hr_dev->qp_table.trrl_table,
 606                                               HEM_TYPE_TRRL,
 607                                               hr_dev->caps.trrl_entry_sz *
 608                                               hr_dev->caps.max_qp_dest_rdma,
 609                                               hr_dev->caps.num_qps, 1);
 610                 if (ret) {
 611                         dev_err(dev,
 612                                 "Failed to init trrl_table memory, aborting.\n");
 613                         goto err_unmap_irrl;
 614                 }
 615         }
 616
 617         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
 618                                       HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
 619                                       hr_dev->caps.num_cqs, 1);
 620         if (ret) {
 621                 dev_err(dev, "Failed to init CQ context memory, aborting.\n");
 622                 goto err_unmap_trrl;
 623         }
 624
 625         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 626                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
 627                                               HEM_TYPE_SRQC,
 628                                               hr_dev->caps.srqc_entry_sz,
 629                                               hr_dev->caps.num_srqs, 1);
 630                 if (ret) {
 631                         dev_err(dev,
 632                                 "Failed to init SRQ context memory, aborting.\n");
 633                         goto err_unmap_cq;
 634                 }
 635         }
 636
 637         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
 638                 ret = hns_roce_init_hem_table(hr_dev,
 639                                               &hr_dev->qp_table.sccc_table,
 640                                               HEM_TYPE_SCCC,
 641                                               hr_dev->caps.sccc_sz,
 642                                               hr_dev->caps.num_qps, 1);
 643                 if (ret) {
 644                         dev_err(dev,
 645                                 "Failed to init SCC context memory, aborting.\n");
 646                         goto err_unmap_srq;
 647                 }
 648         }
 649
 650         if (hr_dev->caps.qpc_timer_entry_sz) {
 651                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table,
 652                                               HEM_TYPE_QPC_TIMER,
 653                                               hr_dev->caps.qpc_timer_entry_sz,
 654                                               hr_dev->caps.num_qpc_timer, 1);
 655                 if (ret) {
 656                         dev_err(dev,
 657                                 "Failed to init QPC timer memory, aborting.\n");
 658                         goto err_unmap_ctx;
 659                 }
 660         }
 661
 662         if (hr_dev->caps.cqc_timer_entry_sz) {
 663                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table,
 664                                               HEM_TYPE_CQC_TIMER,
 665                                               hr_dev->caps.cqc_timer_entry_sz,
 666                                               hr_dev->caps.num_cqc_timer, 1);
 667                 if (ret) {
 668                         dev_err(dev,
 669                                 "Failed to init CQC timer memory, aborting.\n");
 670                         goto err_unmap_qpc_timer;
 671                 }
 672         }
 673
 674         if (hr_dev->caps.gmv_entry_sz) {
 675                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table,
 676                                               HEM_TYPE_GMV,
 677                                               hr_dev->caps.gmv_entry_sz,
 678                                               hr_dev->caps.gmv_entry_num, 1);
 679                 if (ret) {
 680                         dev_err(dev,
 681                                 "failed to init gmv table memory, ret = %d\n",
 682                                 ret);
 683                         goto err_unmap_cqc_timer;
 684                 }
 685         }
 686
 687         return 0;
 688
 689 err_unmap_cqc_timer:
 690         if (hr_dev->caps.cqc_timer_entry_sz)
 691                 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table);
 692
 693 err_unmap_qpc_timer:
 694         if (hr_dev->caps.qpc_timer_entry_sz)
 695                 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table);
 696
 697 err_unmap_ctx:
 698         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
 699                 hns_roce_cleanup_hem_table(hr_dev,
 700                                            &hr_dev->qp_table.sccc_table);
 701 err_unmap_srq:
 702         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
 703                 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
 704
 705 err_unmap_cq:
 706         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
 707
 708 err_unmap_trrl:
 709         if (hr_dev->caps.trrl_entry_sz)
 710                 hns_roce_cleanup_hem_table(hr_dev,
 711                                            &hr_dev->qp_table.trrl_table);
 712
 713 err_unmap_irrl:
 714         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
 715
 716 err_unmap_qp:
 717         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
 718
 719 err_unmap_dmpt:
 720         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
 721
 722         return ret;
 723 }
 724
 725 /**
 726  * hns_roce_setup_hca - setup host channel adapter
 727  * @hr_dev: pointer to hns roce device
 728  * Return : int
 729  */
 730 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
 731 {
 732         struct device *dev = hr_dev->dev;
 733         int ret;
 734
 735         spin_lock_init(&hr_dev->sm_lock);
 736         spin_lock_init(&hr_dev->bt_cmd_lock);
 737
 738         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
 739             hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
 740                 INIT_LIST_HEAD(&hr_dev->pgdir_list);
 741                 mutex_init(&hr_dev->pgdir_mutex);
 742         }
 743
 744         hns_roce_init_uar_table(hr_dev);
 745
 746         ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
 747         if (ret) {
 748                 dev_err(dev, "Failed to allocate priv_uar.\n");
 749                 goto err_uar_table_free;
 750         }
 751
 752         ret = hns_roce_init_qp_table(hr_dev);
 753         if (ret) {
 754                 dev_err(dev, "Failed to init qp_table.\n");
 755                 goto err_uar_table_free;
 756         }
 757
 758         hns_roce_init_pd_table(hr_dev);
 759
 760         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
 761                 hns_roce_init_xrcd_table(hr_dev);
 762
 763         hns_roce_init_mr_table(hr_dev);
 764
 765         hns_roce_init_cq_table(hr_dev);
 766
 767         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 768                 hns_roce_init_srq_table(hr_dev);
 769         }
 770
 771         return 0;
 772
 773 err_uar_table_free:
 774         ida_destroy(&hr_dev->uar_ida.ida);
 775         return ret;
 776 }
 777
 778 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq)
 779 {
 780         struct hns_roce_cq *hr_cq = to_hr_cq(cq);
 781         unsigned long flags;
 782
 783         spin_lock_irqsave(&hr_cq->lock, flags);
 784         if (cq->comp_handler) {
 785                 if (!hr_cq->is_armed) {
 786                         hr_cq->is_armed = 1;
 787                         list_add_tail(&hr_cq->node, cq_list);
 788                 }
 789         }
 790         spin_unlock_irqrestore(&hr_cq->lock, flags);
 791 }
 792
 793 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)
 794 {
 795         struct hns_roce_qp *hr_qp;
 796         struct hns_roce_cq *hr_cq;
 797         struct list_head cq_list;
 798         unsigned long flags_qp;
 799         unsigned long flags;
 800
 801         INIT_LIST_HEAD(&cq_list);
 802
 803         spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
 804         list_for_each_entry(hr_qp, &hr_dev->qp_list, node) {
 805                 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp);
 806                 if (hr_qp->sq.tail != hr_qp->sq.head)
 807                         check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq);
 808                 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp);
 809
 810                 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp);
 811                 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head))
 812                         check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq);
 813                 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp);
 814         }
 815
 816         list_for_each_entry(hr_cq, &cq_list, node)
 817                 hns_roce_cq_completion(hr_dev, hr_cq->cqn);
 818
 819         spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
 820 }
 821
 822 int hns_roce_init(struct hns_roce_dev *hr_dev)
 823 {
 824         struct device *dev = hr_dev->dev;
 825         int ret;
 826
 827         if (hr_dev->hw->reset) {
 828                 ret = hr_dev->hw->reset(hr_dev, true);
 829                 if (ret) {
 830                         dev_err(dev, "Reset RoCE engine failed!\n");
 831                         return ret;
 832                 }
 833         }
 834         hr_dev->is_reset = false;
 835
 836         if (hr_dev->hw->cmq_init) {
 837                 ret = hr_dev->hw->cmq_init(hr_dev);
 838                 if (ret) {
 839                         dev_err(dev, "Init RoCE Command Queue failed!\n");
 840                         goto error_failed_cmq_init;
 841                 }
 842         }
 843
 844         ret = hr_dev->hw->hw_profile(hr_dev);
 845         if (ret) {
 846                 dev_err(dev, "Get RoCE engine profile failed!\n");
 847                 goto error_failed_cmd_init;
 848         }
 849
 850         ret = hns_roce_cmd_init(hr_dev);
 851         if (ret) {
 852                 dev_err(dev, "cmd init failed!\n");
 853                 goto error_failed_cmd_init;
 854         }
 855
 856         /* EQ depends on poll mode, event mode depends on EQ */
 857         ret = hr_dev->hw->init_eq(hr_dev);
 858         if (ret) {
 859                 dev_err(dev, "eq init failed!\n");
 860                 goto error_failed_eq_table;
 861         }
 862
 863         if (hr_dev->cmd_mod) {
 864                 ret = hns_roce_cmd_use_events(hr_dev);
 865                 if (ret)
 866                         dev_warn(dev,
 867                                  "Cmd event  mode failed, set back to poll!\n");
 868         }
 869
 870         ret = hns_roce_init_hem(hr_dev);
 871         if (ret) {
 872                 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
 873                 goto error_failed_init_hem;
 874         }
 875
 876         ret = hns_roce_setup_hca(hr_dev);
 877         if (ret) {
 878                 dev_err(dev, "setup hca failed!\n");
 879                 goto error_failed_setup_hca;
 880         }
 881
 882         if (hr_dev->hw->hw_init) {
 883                 ret = hr_dev->hw->hw_init(hr_dev);
 884                 if (ret) {
 885                         dev_err(dev, "hw_init failed!\n");
 886                         goto error_failed_engine_init;
 887                 }
 888         }
 889
 890         INIT_LIST_HEAD(&hr_dev->qp_list);
 891         spin_lock_init(&hr_dev->qp_list_lock);
 892         INIT_LIST_HEAD(&hr_dev->dip_list);
 893         spin_lock_init(&hr_dev->dip_list_lock);
 894
 895         ret = hns_roce_register_device(hr_dev);
 896         if (ret)
 897                 goto error_failed_register_device;
 898
 899         return 0;
 900
 901 error_failed_register_device:
 902         if (hr_dev->hw->hw_exit)
 903                 hr_dev->hw->hw_exit(hr_dev);
 904
 905 error_failed_engine_init:
 906         hns_roce_cleanup_bitmap(hr_dev);
 907
 908 error_failed_setup_hca:
 909         hns_roce_cleanup_hem(hr_dev);
 910
 911 error_failed_init_hem:
 912         if (hr_dev->cmd_mod)
 913                 hns_roce_cmd_use_polling(hr_dev);
 914         hr_dev->hw->cleanup_eq(hr_dev);
 915
 916 error_failed_eq_table:
 917         hns_roce_cmd_cleanup(hr_dev);
 918
 919 error_failed_cmd_init:
 920         if (hr_dev->hw->cmq_exit)
 921                 hr_dev->hw->cmq_exit(hr_dev);
 922
 923 error_failed_cmq_init:
 924         if (hr_dev->hw->reset) {
 925                 if (hr_dev->hw->reset(hr_dev, false))
 926                         dev_err(dev, "Dereset RoCE engine failed!\n");
 927         }
 928
 929         return ret;
 930 }
 931
 932 void hns_roce_exit(struct hns_roce_dev *hr_dev)
 933 {
 934         hns_roce_unregister_device(hr_dev);
 935
 936         if (hr_dev->hw->hw_exit)
 937                 hr_dev->hw->hw_exit(hr_dev);
 938         hns_roce_cleanup_bitmap(hr_dev);
 939         hns_roce_cleanup_hem(hr_dev);
 940
 941         if (hr_dev->cmd_mod)
 942                 hns_roce_cmd_use_polling(hr_dev);
 943
 944         hr_dev->hw->cleanup_eq(hr_dev);
 945         hns_roce_cmd_cleanup(hr_dev);
 946         if (hr_dev->hw->cmq_exit)
 947                 hr_dev->hw->cmq_exit(hr_dev);
 948         if (hr_dev->hw->reset)
 949                 hr_dev->hw->reset(hr_dev, false);
 950 }
 951
 952 MODULE_LICENSE("Dual BSD/GPL");
 953 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
 954 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
 955 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
 956 MODULE_DESCRIPTION("HNS RoCE Driver");