2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef _HNS_ROCE_HW_V2_H
34 #define _HNS_ROCE_HW_V2_H
36 #include <linux/bitops.h>
38 #define HNS_ROCE_VF_QPC_BT_NUM 256
39 #define HNS_ROCE_VF_SCCC_BT_NUM 64
40 #define HNS_ROCE_VF_SRQC_BT_NUM 64
41 #define HNS_ROCE_VF_CQC_BT_NUM 64
42 #define HNS_ROCE_VF_MPT_BT_NUM 64
43 #define HNS_ROCE_VF_SMAC_NUM 32
44 #define HNS_ROCE_VF_SL_NUM 8
45 #define HNS_ROCE_VF_GMV_BT_NUM 256
47 #define HNS_ROCE_V2_MAX_QP_NUM 0x1000
48 #define HNS_ROCE_V2_MAX_QPC_TIMER_NUM 0x200
49 #define HNS_ROCE_V2_MAX_WQE_NUM 0x8000
50 #define HNS_ROCE_V2_MAX_SRQ 0x100000
51 #define HNS_ROCE_V2_MAX_SRQ_WR 0x8000
52 #define HNS_ROCE_V2_MAX_SRQ_SGE 64
53 #define HNS_ROCE_V2_MAX_CQ_NUM 0x100000
54 #define HNS_ROCE_V2_MAX_CQC_TIMER_BT_NUM 0x100
55 #define HNS_ROCE_V2_MAX_SRQ_NUM 0x100000
56 #define HNS_ROCE_V2_MAX_CQE_NUM 0x400000
57 #define HNS_ROCE_V2_MAX_SRQWQE_NUM 0x8000
58 #define HNS_ROCE_V2_MAX_RQ_SGE_NUM 64
59 #define HNS_ROCE_V2_MAX_SQ_SGE_NUM 64
60 #define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000
61 #define HNS_ROCE_V2_MAX_SQ_INLINE 0x20
62 #define HNS_ROCE_V3_MAX_SQ_INLINE 0x400
63 #define HNS_ROCE_V2_MAX_RC_INL_INN_SZ 32
64 #define HNS_ROCE_V2_UAR_NUM 256
65 #define HNS_ROCE_V2_PHY_UAR_NUM 1
66 #define HNS_ROCE_V2_MAX_IRQ_NUM 65
67 #define HNS_ROCE_V2_COMP_VEC_NUM 63
68 #define HNS_ROCE_V2_AEQE_VEC_NUM 1
69 #define HNS_ROCE_V2_ABNORMAL_VEC_NUM 1
70 #define HNS_ROCE_V2_MAX_MTPT_NUM 0x100000
71 #define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000
72 #define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000
73 #define HNS_ROCE_V2_MAX_SRQWQE_SEGS 0x1000000
74 #define HNS_ROCE_V2_MAX_IDX_SEGS 0x1000000
75 #define HNS_ROCE_V2_MAX_PD_NUM 0x1000000
76 #define HNS_ROCE_V2_MAX_XRCD_NUM 0x1000000
77 #define HNS_ROCE_V2_RSV_XRCD_NUM 0
78 #define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128
79 #define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128
80 #define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64
81 #define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16
82 #define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64
83 #define HNS_ROCE_V2_IRRL_ENTRY_SZ 64
84 #define HNS_ROCE_V2_TRRL_ENTRY_SZ 48
85 #define HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ 100
86 #define HNS_ROCE_V2_CQC_ENTRY_SZ 64
87 #define HNS_ROCE_V2_SRQC_ENTRY_SZ 64
88 #define HNS_ROCE_V2_MTPT_ENTRY_SZ 64
89 #define HNS_ROCE_V2_MTT_ENTRY_SZ 64
90 #define HNS_ROCE_V2_IDX_ENTRY_SZ 4
92 #define HNS_ROCE_V2_SCCC_SZ 32
93 #define HNS_ROCE_V3_SCCC_SZ 64
94 #define HNS_ROCE_V3_GMV_ENTRY_SZ 32
96 #define HNS_ROCE_V2_EXT_LLM_ENTRY_SZ 8
97 #define HNS_ROCE_V2_EXT_LLM_MAX_DEPTH 4096
99 #define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ PAGE_SIZE
100 #define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ PAGE_SIZE
101 #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFF000
102 #define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2
103 #define HNS_ROCE_INVALID_LKEY 0x0
104 #define HNS_ROCE_INVALID_SGE_LENGTH 0x80000000
105 #define HNS_ROCE_CMQ_TX_TIMEOUT 30000
106 #define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE 2
107 #define HNS_ROCE_V2_RSV_QPS 8
109 #define HNS_ROCE_V2_HW_RST_TIMEOUT 1000
110 #define HNS_ROCE_V2_HW_RST_UNINT_DELAY 100
112 #define HNS_ROCE_V2_HW_RST_COMPLETION_WAIT 20
114 #define HNS_ROCE_CONTEXT_HOP_NUM 1
115 #define HNS_ROCE_SCCC_HOP_NUM 1
116 #define HNS_ROCE_MTT_HOP_NUM 1
117 #define HNS_ROCE_CQE_HOP_NUM 1
118 #define HNS_ROCE_SRQWQE_HOP_NUM 1
119 #define HNS_ROCE_PBL_HOP_NUM 2
120 #define HNS_ROCE_EQE_HOP_NUM 2
121 #define HNS_ROCE_IDX_HOP_NUM 1
122 #define HNS_ROCE_SQWQE_HOP_NUM 2
123 #define HNS_ROCE_EXT_SGE_HOP_NUM 1
124 #define HNS_ROCE_RQWQE_HOP_NUM 2
126 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_256K 6
127 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_16K 2
128 #define HNS_ROCE_V2_GID_INDEX_NUM 16
130 #define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18)
133 HNS_ROCE_CMD_FLAG_IN = BIT(0),
134 HNS_ROCE_CMD_FLAG_OUT = BIT(1),
135 HNS_ROCE_CMD_FLAG_NEXT = BIT(2),
136 HNS_ROCE_CMD_FLAG_WR = BIT(3),
137 HNS_ROCE_CMD_FLAG_ERR_INTR = BIT(5),
140 #define HNS_ROCE_CMQ_DESC_NUM_S 3
142 #define HNS_ROCE_CMQ_SCC_CLR_DONE_CNT 5
144 #define HNS_ROCE_CONG_SIZE 64
146 #define check_whether_last_step(hop_num, step_idx) \
147 ((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \
148 (step_idx == 1 && hop_num == 1) || \
149 (step_idx == 2 && hop_num == 2))
150 #define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT 0
151 #define HNS_ICL_SWITCH_CMD_ROCEE_SEL BIT(HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT)
153 #define CMD_CSQ_DESC_NUM 1024
154 #define CMD_CRQ_DESC_NUM 1024
159 REG_NXT_SE_CEQE = 0x3
167 #define V2_CQ_DB_REQ_NOT_SOL 0
168 #define V2_CQ_DB_REQ_NOT 1
170 #define V2_CQ_STATE_VALID 1
171 #define V2_QKEY_VAL 0x80010000
173 #define GID_LEN_V2 16
176 HNS_ROCE_V2_WQE_OP_SEND = 0x0,
177 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1,
178 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2,
179 HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3,
180 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4,
181 HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5,
182 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6,
183 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7,
184 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8,
185 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9,
186 HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa,
187 HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb,
188 HNS_ROCE_V2_WQE_OP_BIND_MW = 0xc,
189 HNS_ROCE_V2_WQE_OP_MASK = 0x1f,
194 HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0,
195 HNS_ROCE_V2_OPCODE_SEND = 0x1,
196 HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2,
197 HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3,
205 HNS_ROCE_V2_CQ_DB_NOTIFY
209 HNS_ROCE_CQE_V2_SUCCESS = 0x00,
210 HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01,
211 HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02,
212 HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04,
213 HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05,
214 HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06,
215 HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10,
216 HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11,
217 HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12,
218 HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13,
219 HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14,
220 HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15,
221 HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16,
222 HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22,
223 HNS_ROCE_CQE_V2_GENERAL_ERR = 0x23,
225 HNS_ROCE_V2_CQE_STATUS_MASK = 0xff,
229 enum hns_roce_opcode_type {
230 HNS_QUERY_FW_VER = 0x0001,
231 HNS_ROCE_OPC_QUERY_HW_VER = 0x8000,
232 HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001,
233 HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004,
234 HNS_ROCE_OPC_QUERY_PF_RES = 0x8400,
235 HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401,
236 HNS_ROCE_OPC_CFG_EXT_LLM = 0x8403,
237 HNS_ROCE_OPC_QUERY_PF_TIMER_RES = 0x8406,
238 HNS_ROCE_OPC_QUERY_FUNC_INFO = 0x8407,
239 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM = 0x8408,
240 HNS_ROCE_OPC_CFG_ENTRY_SIZE = 0x8409,
241 HNS_ROCE_OPC_CFG_SGID_TB = 0x8500,
242 HNS_ROCE_OPC_CFG_SMAC_TB = 0x8501,
243 HNS_ROCE_OPC_POST_MB = 0x8504,
244 HNS_ROCE_OPC_QUERY_MB_ST = 0x8505,
245 HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506,
246 HNS_ROCE_OPC_FUNC_CLEAR = 0x8508,
247 HNS_ROCE_OPC_CLR_SCCC = 0x8509,
248 HNS_ROCE_OPC_QUERY_SCCC = 0x850a,
249 HNS_ROCE_OPC_RESET_SCCC = 0x850b,
250 HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO = 0x850d,
251 HNS_ROCE_OPC_QUERY_VF_RES = 0x850e,
252 HNS_ROCE_OPC_CFG_GMV_TBL = 0x850f,
253 HNS_ROCE_OPC_CFG_GMV_BT = 0x8510,
254 HNS_ROCE_OPC_EXT_CFG = 0x8512,
255 HNS_SWITCH_PARAMETER_CFG = 0x1033,
263 enum hns_roce_cmd_return_status {
280 enum hns_roce_sgid_type {
281 GID_TYPE_FLAG_ROCE_V1 = 0,
282 GID_TYPE_FLAG_ROCE_V2_IPV4,
283 GID_TYPE_FLAG_ROCE_V2_IPV6,
286 struct hns_roce_v2_cq_context {
287 __le32 byte_4_pg_ceqn;
289 __le32 cqe_cur_blk_addr;
290 __le32 byte_16_hop_addr;
291 __le32 cqe_nxt_blk_addr;
292 __le32 byte_24_pgsz_addr;
293 __le32 byte_28_cq_pi;
294 __le32 byte_32_cq_ci;
296 __le32 byte_40_cqe_ba;
297 __le32 byte_44_db_record;
298 __le32 db_record_addr;
299 __le32 byte_52_cqe_cnt;
300 __le32 byte_56_cqe_period_maxcnt;
301 __le32 cqe_report_timer;
302 __le32 byte_64_se_cqe_idx;
305 #define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0
306 #define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL 0x0
308 #define V2_CQC_BYTE_4_ARM_ST_S 6
309 #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6)
311 #define V2_CQC_BYTE_4_CEQN_S 15
312 #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)
314 #define V2_CQC_BYTE_8_CQN_S 0
315 #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
317 #define V2_CQC_BYTE_16_CQE_HOP_NUM_S 30
318 #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
320 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0
321 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0)
323 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0
324 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0)
326 #define V2_CQC_BYTE_52_CQE_CNT_S 0
327 #define V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0)
329 #define V2_CQC_BYTE_56_CQ_MAX_CNT_S 0
330 #define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0)
332 #define V2_CQC_BYTE_56_CQ_PERIOD_S 16
333 #define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16)
335 #define CQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_cq_context, h, l)
337 #define CQC_CQ_ST CQC_FIELD_LOC(1, 0)
338 #define CQC_POLL CQC_FIELD_LOC(2, 2)
339 #define CQC_SE CQC_FIELD_LOC(3, 3)
340 #define CQC_OVER_IGNORE CQC_FIELD_LOC(4, 4)
341 #define CQC_ARM_ST CQC_FIELD_LOC(7, 6)
342 #define CQC_SHIFT CQC_FIELD_LOC(12, 8)
343 #define CQC_CMD_SN CQC_FIELD_LOC(14, 13)
344 #define CQC_CEQN CQC_FIELD_LOC(23, 15)
345 #define CQC_CQN CQC_FIELD_LOC(55, 32)
346 #define CQC_POE_EN CQC_FIELD_LOC(56, 56)
347 #define CQC_POE_NUM CQC_FIELD_LOC(58, 57)
348 #define CQC_CQE_SIZE CQC_FIELD_LOC(60, 59)
349 #define CQC_CQ_CNT_MODE CQC_FIELD_LOC(61, 61)
350 #define CQC_STASH CQC_FIELD_LOC(63, 63)
351 #define CQC_CQE_CUR_BLK_ADDR_L CQC_FIELD_LOC(95, 64)
352 #define CQC_CQE_CUR_BLK_ADDR_H CQC_FIELD_LOC(115, 96)
353 #define CQC_POE_QID CQC_FIELD_LOC(125, 116)
354 #define CQC_CQE_HOP_NUM CQC_FIELD_LOC(127, 126)
355 #define CQC_CQE_NEX_BLK_ADDR_L CQC_FIELD_LOC(159, 128)
356 #define CQC_CQE_NEX_BLK_ADDR_H CQC_FIELD_LOC(179, 160)
357 #define CQC_CQE_BAR_PG_SZ CQC_FIELD_LOC(187, 184)
358 #define CQC_CQE_BUF_PG_SZ CQC_FIELD_LOC(191, 188)
359 #define CQC_CQ_PRODUCER_IDX CQC_FIELD_LOC(215, 192)
360 #define CQC_CQ_CONSUMER_IDX CQC_FIELD_LOC(247, 224)
361 #define CQC_CQE_BA_L CQC_FIELD_LOC(287, 256)
362 #define CQC_CQE_BA_H CQC_FIELD_LOC(316, 288)
363 #define CQC_POE_QID_H_0 CQC_FIELD_LOC(319, 317)
364 #define CQC_DB_RECORD_EN CQC_FIELD_LOC(320, 320)
365 #define CQC_CQE_DB_RECORD_ADDR_L CQC_FIELD_LOC(351, 321)
366 #define CQC_CQE_DB_RECORD_ADDR_H CQC_FIELD_LOC(383, 352)
367 #define CQC_CQE_CNT CQC_FIELD_LOC(407, 384)
368 #define CQC_CQ_MAX_CNT CQC_FIELD_LOC(431, 416)
369 #define CQC_CQ_PERIOD CQC_FIELD_LOC(447, 432)
370 #define CQC_CQE_REPORT_TIMER CQC_FIELD_LOC(471, 448)
371 #define CQC_WR_CQE_IDX CQC_FIELD_LOC(479, 472)
372 #define CQC_SE_CQE_IDX CQC_FIELD_LOC(503, 480)
373 #define CQC_POE_QID_H_1 CQC_FIELD_LOC(511, 511)
375 struct hns_roce_srq_context {
379 #define SRQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_srq_context, h, l)
381 #define SRQC_SRQ_ST SRQC_FIELD_LOC(1, 0)
382 #define SRQC_WQE_HOP_NUM SRQC_FIELD_LOC(3, 2)
383 #define SRQC_SHIFT SRQC_FIELD_LOC(7, 4)
384 #define SRQC_SRQN SRQC_FIELD_LOC(31, 8)
385 #define SRQC_LIMIT_WL SRQC_FIELD_LOC(47, 32)
386 #define SRQC_RSV0 SRQC_FIELD_LOC(63, 48)
387 #define SRQC_XRCD SRQC_FIELD_LOC(87, 64)
388 #define SRQC_RSV1 SRQC_FIELD_LOC(95, 88)
389 #define SRQC_PRODUCER_IDX SRQC_FIELD_LOC(111, 96)
390 #define SRQC_CONSUMER_IDX SRQC_FIELD_LOC(127, 112)
391 #define SRQC_WQE_BT_BA_L SRQC_FIELD_LOC(159, 128)
392 #define SRQC_WQE_BT_BA_H SRQC_FIELD_LOC(188, 160)
393 #define SRQC_RSV2 SRQC_FIELD_LOC(190, 189)
394 #define SRQC_SRQ_TYPE SRQC_FIELD_LOC(191, 191)
395 #define SRQC_PD SRQC_FIELD_LOC(215, 192)
396 #define SRQC_RQWS SRQC_FIELD_LOC(219, 216)
397 #define SRQC_RSV3 SRQC_FIELD_LOC(223, 220)
398 #define SRQC_IDX_BT_BA_L SRQC_FIELD_LOC(255, 224)
399 #define SRQC_IDX_BT_BA_H SRQC_FIELD_LOC(284, 256)
400 #define SRQC_RSV4 SRQC_FIELD_LOC(287, 285)
401 #define SRQC_IDX_CUR_BLK_ADDR_L SRQC_FIELD_LOC(319, 288)
402 #define SRQC_IDX_CUR_BLK_ADDR_H SRQC_FIELD_LOC(339, 320)
403 #define SRQC_RSV5 SRQC_FIELD_LOC(341, 340)
404 #define SRQC_IDX_HOP_NUM SRQC_FIELD_LOC(343, 342)
405 #define SRQC_IDX_BA_PG_SZ SRQC_FIELD_LOC(347, 344)
406 #define SRQC_IDX_BUF_PG_SZ SRQC_FIELD_LOC(351, 348)
407 #define SRQC_IDX_NXT_BLK_ADDR_L SRQC_FIELD_LOC(383, 352)
408 #define SRQC_IDX_NXT_BLK_ADDR_H SRQC_FIELD_LOC(403, 384)
409 #define SRQC_RSV6 SRQC_FIELD_LOC(415, 404)
410 #define SRQC_XRC_CQN SRQC_FIELD_LOC(439, 416)
411 #define SRQC_WQE_BA_PG_SZ SRQC_FIELD_LOC(443, 440)
412 #define SRQC_WQE_BUF_PG_SZ SRQC_FIELD_LOC(447, 444)
413 #define SRQC_DB_RECORD_EN SRQC_FIELD_LOC(448, 448)
414 #define SRQC_DB_RECORD_ADDR_L SRQC_FIELD_LOC(479, 449)
415 #define SRQC_DB_RECORD_ADDR_H SRQC_FIELD_LOC(511, 480)
418 V2_MPT_ST_VALID = 0x1,
419 V2_MPT_ST_FREE = 0x2,
422 enum hns_roce_v2_qp_state {
430 HNS_ROCE_QP_ST_SQ_DRAINING,
434 struct hns_roce_v2_qp_context_ex {
437 struct hns_roce_v2_qp_context {
438 __le32 byte_4_sqpn_tst;
440 __le32 byte_12_sq_hop;
441 __le32 byte_16_buf_ba_pg_sz;
442 __le32 byte_20_smac_sgid_idx;
443 __le32 byte_24_mtu_tc;
444 __le32 byte_28_at_fl;
447 __le32 byte_52_udpspn_dmac;
448 __le32 byte_56_dqpn_err;
449 __le32 byte_60_qpst_tempid;
451 __le32 byte_68_rq_db;
452 __le32 rq_db_record_addr;
453 __le32 byte_76_srqn_op_en;
454 __le32 byte_80_rnr_rx_cqn;
455 __le32 byte_84_rq_ci_pi;
456 __le32 rq_cur_blk_addr;
457 __le32 byte_92_srq_info;
458 __le32 byte_96_rx_reqmsn;
459 __le32 rq_nxt_blk_addr;
460 __le32 byte_104_rq_sge;
461 __le32 byte_108_rx_reqepsn;
464 __le32 rx_rkey_pkt_info;
466 __le32 byte_132_trrl;
473 __le32 byte_160_sq_ci_pi;
474 __le32 sq_cur_blk_addr;
475 __le32 byte_168_irrl_idx;
476 __le32 byte_172_sq_psn;
477 __le32 byte_176_msg_pktn;
478 __le32 sq_cur_sge_blk_addr;
479 __le32 byte_184_irrl_idx;
480 __le32 cur_sge_offset;
481 __le32 byte_192_ext_sge;
482 __le32 byte_196_sq_psn;
483 __le32 byte_200_sq_max;
485 __le32 byte_208_irrl;
488 __le32 byte_220_retry_psn_msn;
489 __le32 byte_224_retry_msg;
490 __le32 rx_sq_cur_blk_addr;
491 __le32 byte_232_irrl_sge;
492 __le32 irrl_cur_sge_offset;
493 __le32 byte_240_irrl_tail;
494 __le32 byte_244_rnr_rxack;
495 __le32 byte_248_ack_psn;
496 __le32 byte_252_err_txcqn;
497 __le32 byte_256_sqflush_rqcqe;
499 struct hns_roce_v2_qp_context_ex ext;
502 #define QPC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_qp_context, h, l)
504 #define QPC_TST QPC_FIELD_LOC(2, 0)
505 #define QPC_SGE_SHIFT QPC_FIELD_LOC(7, 3)
506 #define QPC_CNP_TIMER QPC_FIELD_LOC(31, 8)
507 #define QPC_WQE_SGE_BA_L QPC_FIELD_LOC(63, 32)
508 #define QPC_WQE_SGE_BA_H QPC_FIELD_LOC(92, 64)
509 #define QPC_SQ_HOP_NUM QPC_FIELD_LOC(94, 93)
510 #define QPC_CIRE_EN QPC_FIELD_LOC(95, 95)
511 #define QPC_WQE_SGE_BA_PG_SZ QPC_FIELD_LOC(99, 96)
512 #define QPC_WQE_SGE_BUF_PG_SZ QPC_FIELD_LOC(103, 100)
513 #define QPC_PD QPC_FIELD_LOC(127, 104)
514 #define QPC_RQ_HOP_NUM QPC_FIELD_LOC(129, 128)
515 #define QPC_SGE_HOP_NUM QPC_FIELD_LOC(131, 130)
516 #define QPC_RQWS QPC_FIELD_LOC(135, 132)
517 #define QPC_SQ_SHIFT QPC_FIELD_LOC(139, 136)
518 #define QPC_RQ_SHIFT QPC_FIELD_LOC(143, 140)
519 #define QPC_GMV_IDX QPC_FIELD_LOC(159, 144)
520 #define QPC_HOPLIMIT QPC_FIELD_LOC(167, 160)
521 #define QPC_TC QPC_FIELD_LOC(175, 168)
522 #define QPC_VLAN_ID QPC_FIELD_LOC(187, 176)
523 #define QPC_MTU QPC_FIELD_LOC(191, 188)
524 #define QPC_FL QPC_FIELD_LOC(211, 192)
525 #define QPC_SL QPC_FIELD_LOC(215, 212)
526 #define QPC_CNP_TX_FLAG QPC_FIELD_LOC(216, 216)
527 #define QPC_CE_FLAG QPC_FIELD_LOC(217, 217)
528 #define QPC_LBI QPC_FIELD_LOC(218, 218)
529 #define QPC_AT QPC_FIELD_LOC(223, 219)
530 #define QPC_DGID QPC_FIELD_LOC(351, 224)
531 #define QPC_DMAC_L QPC_FIELD_LOC(383, 352)
532 #define QPC_DMAC_H QPC_FIELD_LOC(399, 384)
533 #define QPC_UDPSPN QPC_FIELD_LOC(415, 400)
534 #define QPC_DQPN QPC_FIELD_LOC(439, 416)
535 #define QPC_SQ_TX_ERR QPC_FIELD_LOC(440, 440)
536 #define QPC_SQ_RX_ERR QPC_FIELD_LOC(441, 441)
537 #define QPC_RQ_TX_ERR QPC_FIELD_LOC(442, 442)
538 #define QPC_RQ_RX_ERR QPC_FIELD_LOC(443, 443)
539 #define QPC_LP_PKTN_INI QPC_FIELD_LOC(447, 444)
540 #define QPC_CONG_ALGO_TMPL_ID QPC_FIELD_LOC(455, 448)
541 #define QPC_SCC_TOKEN QPC_FIELD_LOC(474, 456)
542 #define QPC_SQ_DB_DOING QPC_FIELD_LOC(475, 475)
543 #define QPC_RQ_DB_DOING QPC_FIELD_LOC(476, 476)
544 #define QPC_QP_ST QPC_FIELD_LOC(479, 477)
545 #define QPC_QKEY_XRCD QPC_FIELD_LOC(511, 480)
546 #define QPC_RQ_RECORD_EN QPC_FIELD_LOC(512, 512)
547 #define QPC_RQ_DB_RECORD_ADDR_L QPC_FIELD_LOC(543, 513)
548 #define QPC_RQ_DB_RECORD_ADDR_H QPC_FIELD_LOC(575, 544)
549 #define QPC_SRQN QPC_FIELD_LOC(599, 576)
550 #define QPC_SRQ_EN QPC_FIELD_LOC(600, 600)
551 #define QPC_RRE QPC_FIELD_LOC(601, 601)
552 #define QPC_RWE QPC_FIELD_LOC(602, 602)
553 #define QPC_ATE QPC_FIELD_LOC(603, 603)
554 #define QPC_RQIE QPC_FIELD_LOC(604, 604)
555 #define QPC_EXT_ATE QPC_FIELD_LOC(605, 605)
556 #define QPC_RQ_VLAN_EN QPC_FIELD_LOC(606, 606)
557 #define QPC_RQ_RTY_TX_ERR QPC_FIELD_LOC(607, 607)
558 #define QPC_RX_CQN QPC_FIELD_LOC(631, 608)
559 #define QPC_XRC_QP_TYPE QPC_FIELD_LOC(632, 632)
560 #define QPC_RSV3 QPC_FIELD_LOC(634, 633)
561 #define QPC_MIN_RNR_TIME QPC_FIELD_LOC(639, 635)
562 #define QPC_RQ_PRODUCER_IDX QPC_FIELD_LOC(655, 640)
563 #define QPC_RQ_CONSUMER_IDX QPC_FIELD_LOC(671, 656)
564 #define QPC_RQ_CUR_BLK_ADDR_L QPC_FIELD_LOC(703, 672)
565 #define QPC_RQ_CUR_BLK_ADDR_H QPC_FIELD_LOC(723, 704)
566 #define QPC_SRQ_INFO QPC_FIELD_LOC(735, 724)
567 #define QPC_RX_REQ_MSN QPC_FIELD_LOC(759, 736)
568 #define QPC_REDUCE_CODE QPC_FIELD_LOC(766, 760)
569 #define QPC_RX_XRC_PKT_CQE_FLG QPC_FIELD_LOC(767, 767)
570 #define QPC_RQ_NXT_BLK_ADDR_L QPC_FIELD_LOC(799, 768)
571 #define QPC_RQ_NXT_BLK_ADDR_H QPC_FIELD_LOC(819, 800)
572 #define QPC_REDUCE_EN QPC_FIELD_LOC(820, 820)
573 #define QPC_FLUSH_EN QPC_FIELD_LOC(821, 821)
574 #define QPC_AW_EN QPC_FIELD_LOC(822, 822)
575 #define QPC_WN_EN QPC_FIELD_LOC(823, 823)
576 #define QPC_RQ_CUR_WQE_SGE_NUM QPC_FIELD_LOC(831, 824)
577 #define QPC_INV_CREDIT QPC_FIELD_LOC(832, 832)
578 #define QPC_LAST_WRITE_TYPE QPC_FIELD_LOC(834, 833)
579 #define QPC_RX_REQ_PSN_ERR QPC_FIELD_LOC(835, 835)
580 #define QPC_RX_REQ_LAST_OPTYPE QPC_FIELD_LOC(838, 836)
581 #define QPC_RX_REQ_RNR QPC_FIELD_LOC(839, 839)
582 #define QPC_RX_REQ_EPSN QPC_FIELD_LOC(863, 840)
583 #define QPC_RQ_RNR_TIMER QPC_FIELD_LOC(895, 864)
584 #define QPC_RX_MSG_LEN QPC_FIELD_LOC(927, 896)
585 #define QPC_RX_RKEY_PKT_INFO QPC_FIELD_LOC(959, 928)
586 #define QPC_RX_VA QPC_FIELD_LOC(1023, 960)
587 #define QPC_TRRL_HEAD_MAX QPC_FIELD_LOC(1031, 1024)
588 #define QPC_TRRL_TAIL_MAX QPC_FIELD_LOC(1039, 1032)
589 #define QPC_TRRL_BA_L QPC_FIELD_LOC(1055, 1040)
590 #define QPC_TRRL_BA_M QPC_FIELD_LOC(1087, 1056)
591 #define QPC_TRRL_BA_H QPC_FIELD_LOC(1099, 1088)
592 #define QPC_RR_MAX QPC_FIELD_LOC(1102, 1100)
593 #define QPC_RQ_RTY_WAIT_DO QPC_FIELD_LOC(1103, 1103)
594 #define QPC_RAQ_TRRL_HEAD QPC_FIELD_LOC(1111, 1104)
595 #define QPC_RAQ_TRRL_TAIL QPC_FIELD_LOC(1119, 1112)
596 #define QPC_RAQ_RTY_INI_PSN QPC_FIELD_LOC(1143, 1120)
597 #define QPC_CIRE_SLV_RQ_EN QPC_FIELD_LOC(1144, 1144)
598 #define QPC_RAQ_CREDIT QPC_FIELD_LOC(1149, 1145)
599 #define QPC_RQ_DB_IN_EXT QPC_FIELD_LOC(1150, 1150)
600 #define QPC_RESP_RTY_FLG QPC_FIELD_LOC(1151, 1151)
601 #define QPC_RAQ_MSN QPC_FIELD_LOC(1175, 1152)
602 #define QPC_RAQ_SYNDROME QPC_FIELD_LOC(1183, 1176)
603 #define QPC_RAQ_PSN QPC_FIELD_LOC(1207, 1184)
604 #define QPC_RAQ_TRRL_RTY_HEAD QPC_FIELD_LOC(1215, 1208)
605 #define QPC_RAQ_USE_PKTN QPC_FIELD_LOC(1239, 1216)
606 #define QPC_RQ_SCC_TOKEN QPC_FIELD_LOC(1245, 1240)
607 #define QPC_RVD10 QPC_FIELD_LOC(1247, 1246)
608 #define QPC_SQ_PRODUCER_IDX QPC_FIELD_LOC(1263, 1248)
609 #define QPC_SQ_CONSUMER_IDX QPC_FIELD_LOC(1279, 1264)
610 #define QPC_SQ_CUR_BLK_ADDR_L QPC_FIELD_LOC(1311, 1280)
611 #define QPC_SQ_CUR_BLK_ADDR_H QPC_FIELD_LOC(1331, 1312)
612 #define QPC_MSG_RTY_LP_FLG QPC_FIELD_LOC(1332, 1332)
613 #define QPC_SQ_INVLD_FLG QPC_FIELD_LOC(1333, 1333)
614 #define QPC_LP_SGEN_INI QPC_FIELD_LOC(1335, 1334)
615 #define QPC_SQ_VLAN_EN QPC_FIELD_LOC(1336, 1336)
616 #define QPC_POLL_DB_WAIT_DO QPC_FIELD_LOC(1337, 1337)
617 #define QPC_SCC_TOKEN_FORBID_SQ_DEQ QPC_FIELD_LOC(1338, 1338)
618 #define QPC_WAIT_ACK_TIMEOUT QPC_FIELD_LOC(1339, 1339)
619 #define QPC_IRRL_IDX_LSB QPC_FIELD_LOC(1343, 1340)
620 #define QPC_ACK_REQ_FREQ QPC_FIELD_LOC(1349, 1344)
621 #define QPC_MSG_RNR_FLG QPC_FIELD_LOC(1350, 1350)
622 #define QPC_FRE QPC_FIELD_LOC(1351, 1351)
623 #define QPC_SQ_CUR_PSN QPC_FIELD_LOC(1375, 1352)
624 #define QPC_MSG_USE_PKTN QPC_FIELD_LOC(1399, 1376)
625 #define QPC_IRRL_HEAD_PRE QPC_FIELD_LOC(1407, 1400)
626 #define QPC_SQ_CUR_SGE_BLK_ADDR_L QPC_FIELD_LOC(1439, 1408)
627 #define QPC_SQ_CUR_SGE_BLK_ADDR_H QPC_FIELD_LOC(1459, 1440)
628 #define QPC_IRRL_IDX_MSB QPC_FIELD_LOC(1471, 1460)
629 #define QPC_CUR_SGE_OFFSET QPC_FIELD_LOC(1503, 1472)
630 #define QPC_CUR_SGE_IDX QPC_FIELD_LOC(1527, 1504)
631 #define QPC_EXT_SGE_NUM_LEFT QPC_FIELD_LOC(1535, 1528)
632 #define QPC_OWNER_MODE QPC_FIELD_LOC(1536, 1536)
633 #define QPC_CIRE_SLV_SQ_EN QPC_FIELD_LOC(1537, 1537)
634 #define QPC_CIRE_DOING QPC_FIELD_LOC(1538, 1538)
635 #define QPC_CIRE_RESULT QPC_FIELD_LOC(1539, 1539)
636 #define QPC_OWNER_DB_WAIT_DO QPC_FIELD_LOC(1540, 1540)
637 #define QPC_SQ_WQE_INVLD QPC_FIELD_LOC(1541, 1541)
638 #define QPC_DCA_MODE QPC_FIELD_LOC(1542, 1542)
639 #define QPC_RTY_OWNER_NOCHK QPC_FIELD_LOC(1543, 1543)
640 #define QPC_V2_IRRL_HEAD QPC_FIELD_LOC(1543, 1536)
641 #define QPC_SQ_MAX_PSN QPC_FIELD_LOC(1567, 1544)
642 #define QPC_SQ_MAX_IDX QPC_FIELD_LOC(1583, 1568)
643 #define QPC_LCL_OPERATED_CNT QPC_FIELD_LOC(1599, 1584)
644 #define QPC_IRRL_BA_L QPC_FIELD_LOC(1631, 1600)
645 #define QPC_IRRL_BA_H QPC_FIELD_LOC(1657, 1632)
646 #define QPC_PKT_RNR_FLG QPC_FIELD_LOC(1658, 1658)
647 #define QPC_PKT_RTY_FLG QPC_FIELD_LOC(1659, 1659)
648 #define QPC_RMT_E2E QPC_FIELD_LOC(1660, 1660)
649 #define QPC_SR_MAX QPC_FIELD_LOC(1663, 1661)
650 #define QPC_LSN QPC_FIELD_LOC(1687, 1664)
651 #define QPC_RETRY_NUM_INIT QPC_FIELD_LOC(1690, 1688)
652 #define QPC_CHECK_FLG QPC_FIELD_LOC(1692, 1691)
653 #define QPC_RETRY_CNT QPC_FIELD_LOC(1695, 1693)
654 #define QPC_SQ_TIMER QPC_FIELD_LOC(1727, 1696)
655 #define QPC_RETRY_MSG_MSN QPC_FIELD_LOC(1743, 1728)
656 #define QPC_RETRY_MSG_PSN_L QPC_FIELD_LOC(1759, 1744)
657 #define QPC_RETRY_MSG_PSN_H QPC_FIELD_LOC(1767, 1760)
658 #define QPC_RETRY_MSG_FPKT_PSN QPC_FIELD_LOC(1791, 1768)
659 #define QPC_RX_SQ_CUR_BLK_ADDR_L QPC_FIELD_LOC(1823, 1792)
660 #define QPC_RX_SQ_CUR_BLK_ADDR_H QPC_FIELD_LOC(1843, 1824)
661 #define QPC_IRRL_SGE_IDX QPC_FIELD_LOC(1851, 1844)
662 #define QPC_LSAN_EN QPC_FIELD_LOC(1852, 1852)
663 #define QPC_SO_LP_VLD QPC_FIELD_LOC(1853, 1853)
664 #define QPC_FENCE_LP_VLD QPC_FIELD_LOC(1854, 1854)
665 #define QPC_IRRL_LP_VLD QPC_FIELD_LOC(1855, 1855)
666 #define QPC_IRRL_CUR_SGE_OFFSET QPC_FIELD_LOC(1887, 1856)
667 #define QPC_IRRL_TAIL_REAL QPC_FIELD_LOC(1895, 1888)
668 #define QPC_IRRL_TAIL_RD QPC_FIELD_LOC(1903, 1896)
669 #define QPC_RX_ACK_MSN QPC_FIELD_LOC(1919, 1904)
670 #define QPC_RX_ACK_EPSN QPC_FIELD_LOC(1943, 1920)
671 #define QPC_RNR_NUM_INIT QPC_FIELD_LOC(1946, 1944)
672 #define QPC_RNR_CNT QPC_FIELD_LOC(1949, 1947)
673 #define QPC_LCL_OP_FLG QPC_FIELD_LOC(1950, 1950)
674 #define QPC_IRRL_RD_FLG QPC_FIELD_LOC(1951, 1951)
675 #define QPC_IRRL_PSN QPC_FIELD_LOC(1975, 1952)
676 #define QPC_ACK_PSN_ERR QPC_FIELD_LOC(1976, 1976)
677 #define QPC_ACK_LAST_OPTYPE QPC_FIELD_LOC(1978, 1977)
678 #define QPC_IRRL_PSN_VLD QPC_FIELD_LOC(1979, 1979)
679 #define QPC_RNR_RETRY_FLAG QPC_FIELD_LOC(1980, 1980)
680 #define QPC_SQ_RTY_TX_ERR QPC_FIELD_LOC(1981, 1981)
681 #define QPC_LAST_IND QPC_FIELD_LOC(1982, 1982)
682 #define QPC_CQ_ERR_IND QPC_FIELD_LOC(1983, 1983)
683 #define QPC_TX_CQN QPC_FIELD_LOC(2007, 1984)
684 #define QPC_SIG_TYPE QPC_FIELD_LOC(2008, 2008)
685 #define QPC_ERR_TYPE QPC_FIELD_LOC(2015, 2009)
686 #define QPC_RQ_CQE_IDX QPC_FIELD_LOC(2031, 2016)
687 #define QPC_SQ_FLUSH_IDX QPC_FIELD_LOC(2047, 2032)
689 #define RETRY_MSG_PSN_SHIFT 16
691 #define QPCEX_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_qp_context_ex, h, l)
693 #define QPCEX_CONG_ALG_SEL QPCEX_FIELD_LOC(0, 0)
694 #define QPCEX_CONG_ALG_SUB_SEL QPCEX_FIELD_LOC(1, 1)
695 #define QPCEX_DIP_CTX_IDX_VLD QPCEX_FIELD_LOC(2, 2)
696 #define QPCEX_DIP_CTX_IDX QPCEX_FIELD_LOC(22, 3)
697 #define QPCEX_SQ_RQ_NOT_FORBID_EN QPCEX_FIELD_LOC(23, 23)
698 #define QPCEX_STASH QPCEX_FIELD_LOC(82, 82)
700 #define V2_QP_RWE_S 1 /* rdma write enable */
701 #define V2_QP_RRE_S 2 /* rdma read enable */
702 #define V2_QP_ATE_S 3 /* rdma atomic enable */
704 struct hns_roce_v2_cqe {
719 #define CQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_cqe, h, l)
721 #define CQE_OPCODE CQE_FIELD_LOC(4, 0)
722 #define CQE_RQ_INLINE CQE_FIELD_LOC(5, 5)
723 #define CQE_S_R CQE_FIELD_LOC(6, 6)
724 #define CQE_OWNER CQE_FIELD_LOC(7, 7)
725 #define CQE_STATUS CQE_FIELD_LOC(15, 8)
726 #define CQE_WQE_IDX CQE_FIELD_LOC(31, 16)
727 #define CQE_RKEY_IMMTDATA CQE_FIELD_LOC(63, 32)
728 #define CQE_XRC_SRQN CQE_FIELD_LOC(87, 64)
729 #define CQE_RSV0 CQE_FIELD_LOC(95, 88)
730 #define CQE_LCL_QPN CQE_FIELD_LOC(119, 96)
731 #define CQE_SUB_STATUS CQE_FIELD_LOC(127, 120)
732 #define CQE_BYTE_CNT CQE_FIELD_LOC(159, 128)
733 #define CQE_SMAC CQE_FIELD_LOC(207, 160)
734 #define CQE_PORT_TYPE CQE_FIELD_LOC(209, 208)
735 #define CQE_VID CQE_FIELD_LOC(221, 210)
736 #define CQE_VID_VLD CQE_FIELD_LOC(222, 222)
737 #define CQE_RSV2 CQE_FIELD_LOC(223, 223)
738 #define CQE_RMT_QPN CQE_FIELD_LOC(247, 224)
739 #define CQE_SL CQE_FIELD_LOC(250, 248)
740 #define CQE_PORTN CQE_FIELD_LOC(253, 251)
741 #define CQE_GRH CQE_FIELD_LOC(254, 254)
742 #define CQE_LPK CQE_FIELD_LOC(255, 255)
743 #define CQE_RSV3 CQE_FIELD_LOC(511, 256)
745 struct hns_roce_v2_mpt_entry {
746 __le32 byte_4_pd_hop_st;
747 __le32 byte_8_mw_cnt_en;
748 __le32 byte_12_mw_pa;
757 __le32 byte_48_mode_ba;
759 __le32 byte_56_pa0_h;
761 __le32 byte_64_buf_pa1;
764 #define MPT_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_mpt_entry, h, l)
766 #define MPT_ST MPT_FIELD_LOC(1, 0)
767 #define MPT_PBL_HOP_NUM MPT_FIELD_LOC(3, 2)
768 #define MPT_PBL_BA_PG_SZ MPT_FIELD_LOC(7, 4)
769 #define MPT_PD MPT_FIELD_LOC(31, 8)
770 #define MPT_RA_EN MPT_FIELD_LOC(32, 32)
771 #define MPT_R_INV_EN MPT_FIELD_LOC(33, 33)
772 #define MPT_L_INV_EN MPT_FIELD_LOC(34, 34)
773 #define MPT_BIND_EN MPT_FIELD_LOC(35, 35)
774 #define MPT_ATOMIC_EN MPT_FIELD_LOC(36, 36)
775 #define MPT_RR_EN MPT_FIELD_LOC(37, 37)
776 #define MPT_RW_EN MPT_FIELD_LOC(38, 38)
777 #define MPT_LW_EN MPT_FIELD_LOC(39, 39)
778 #define MPT_MW_CNT MPT_FIELD_LOC(63, 40)
779 #define MPT_FRE MPT_FIELD_LOC(64, 64)
780 #define MPT_PA MPT_FIELD_LOC(65, 65)
781 #define MPT_ZBVA MPT_FIELD_LOC(66, 66)
782 #define MPT_SHARE MPT_FIELD_LOC(67, 67)
783 #define MPT_MR_MW MPT_FIELD_LOC(68, 68)
784 #define MPT_BPD MPT_FIELD_LOC(69, 69)
785 #define MPT_BQP MPT_FIELD_LOC(70, 70)
786 #define MPT_INNER_PA_VLD MPT_FIELD_LOC(71, 71)
787 #define MPT_MW_BIND_QPN MPT_FIELD_LOC(95, 72)
788 #define MPT_BOUND_LKEY MPT_FIELD_LOC(127, 96)
789 #define MPT_LEN MPT_FIELD_LOC(191, 128)
790 #define MPT_LKEY MPT_FIELD_LOC(223, 192)
791 #define MPT_VA MPT_FIELD_LOC(287, 224)
792 #define MPT_PBL_SIZE MPT_FIELD_LOC(319, 288)
793 #define MPT_PBL_BA MPT_FIELD_LOC(380, 320)
794 #define MPT_BLK_MODE MPT_FIELD_LOC(381, 381)
795 #define MPT_RSV0 MPT_FIELD_LOC(383, 382)
796 #define MPT_PA0 MPT_FIELD_LOC(441, 384)
797 #define MPT_BOUND_VA MPT_FIELD_LOC(447, 442)
798 #define MPT_PA1 MPT_FIELD_LOC(505, 448)
799 #define MPT_PERSIST_EN MPT_FIELD_LOC(506, 506)
800 #define MPT_RSV2 MPT_FIELD_LOC(507, 507)
801 #define MPT_PBL_BUF_PG_SZ MPT_FIELD_LOC(511, 508)
803 #define V2_MPT_BYTE_4_MPT_ST_S 0
804 #define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0)
806 #define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2
807 #define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2)
809 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4
810 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4)
812 #define V2_MPT_BYTE_4_PD_S 8
813 #define V2_MPT_BYTE_4_PD_M GENMASK(31, 8)
815 #define V2_MPT_BYTE_8_RA_EN_S 0
817 #define V2_MPT_BYTE_8_R_INV_EN_S 1
819 #define V2_MPT_BYTE_8_L_INV_EN_S 2
821 #define V2_MPT_BYTE_8_BIND_EN_S 3
823 #define V2_MPT_BYTE_8_ATOMIC_EN_S 4
825 #define V2_MPT_BYTE_8_RR_EN_S 5
827 #define V2_MPT_BYTE_8_RW_EN_S 6
829 #define V2_MPT_BYTE_8_LW_EN_S 7
831 #define V2_MPT_BYTE_8_MW_CNT_S 8
832 #define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8)
834 #define V2_MPT_BYTE_12_FRE_S 0
836 #define V2_MPT_BYTE_12_PA_S 1
838 #define V2_MPT_BYTE_12_MR_MW_S 4
840 #define V2_MPT_BYTE_12_BPD_S 5
842 #define V2_MPT_BYTE_12_BQP_S 6
844 #define V2_MPT_BYTE_12_INNER_PA_VLD_S 7
846 #define V2_MPT_BYTE_12_MW_BIND_QPN_S 8
847 #define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8)
849 #define V2_MPT_BYTE_48_PBL_BA_H_S 0
850 #define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0)
852 #define V2_MPT_BYTE_48_BLK_MODE_S 29
854 #define V2_MPT_BYTE_56_PA0_H_S 0
855 #define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0)
857 #define V2_MPT_BYTE_64_PA1_H_S 0
858 #define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0)
860 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28
861 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28)
863 struct hns_roce_v2_db {
867 #define DB_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_db, h, l)
869 #define DB_TAG DB_FIELD_LOC(23, 0)
870 #define DB_CMD DB_FIELD_LOC(27, 24)
871 #define DB_FLAG DB_FIELD_LOC(31, 31)
872 #define DB_PI DB_FIELD_LOC(47, 32)
873 #define DB_SL DB_FIELD_LOC(50, 48)
874 #define DB_CQ_CI DB_FIELD_LOC(55, 32)
875 #define DB_CQ_NOTIFY DB_FIELD_LOC(56, 56)
876 #define DB_CQ_CMD_SN DB_FIELD_LOC(58, 57)
877 #define EQ_DB_TAG DB_FIELD_LOC(7, 0)
878 #define EQ_DB_CMD DB_FIELD_LOC(17, 16)
879 #define EQ_DB_CI DB_FIELD_LOC(55, 32)
881 #define V2_DB_PRODUCER_IDX_S 0
882 #define V2_DB_PRODUCER_IDX_M GENMASK(15, 0)
884 #define V2_CQ_DB_CONS_IDX_S 0
885 #define V2_CQ_DB_CONS_IDX_M GENMASK(23, 0)
887 struct hns_roce_v2_ud_send_wqe {
904 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0
905 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
907 #define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7
909 #define V2_UD_SEND_WQE_BYTE_4_CQE_S 8
911 #define V2_UD_SEND_WQE_BYTE_4_SE_S 11
913 #define V2_UD_SEND_WQE_BYTE_16_PD_S 0
914 #define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0)
916 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24
917 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
919 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
920 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
922 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16
923 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16)
925 #define V2_UD_SEND_WQE_BYTE_32_DQPN_S 0
926 #define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0)
928 #define V2_UD_SEND_WQE_BYTE_36_VLAN_S 0
929 #define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0)
931 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16
932 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16)
934 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24
935 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24)
937 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0
938 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0)
940 #define V2_UD_SEND_WQE_BYTE_40_SL_S 20
941 #define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20)
943 #define V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S 30
945 #define V2_UD_SEND_WQE_BYTE_40_LBI_S 31
947 struct hns_roce_v2_rc_send_wqe {
960 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0
961 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
963 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S 5
964 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M GENMASK(6, 5)
966 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S 13
967 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M GENMASK(14, 13)
969 #define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S 15
970 #define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M GENMASK(30, 15)
972 #define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7
974 #define V2_RC_SEND_WQE_BYTE_4_CQE_S 8
976 #define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9
978 #define V2_RC_SEND_WQE_BYTE_4_SO_S 10
980 #define V2_RC_SEND_WQE_BYTE_4_SE_S 11
982 #define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12
984 #define V2_RC_SEND_WQE_BYTE_4_FLAG_S 31
986 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0
987 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0)
989 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24
990 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
992 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
993 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
995 #define V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S 31
997 struct hns_roce_wqe_frmr_seg {
1002 #define FRMR_WQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_wqe_frmr_seg, h, l)
1004 #define FRMR_PBL_SIZE FRMR_WQE_FIELD_LOC(31, 0)
1005 #define FRMR_BLOCK_SIZE FRMR_WQE_FIELD_LOC(35, 32)
1006 #define FRMR_PBL_BUF_PG_SZ FRMR_WQE_FIELD_LOC(39, 36)
1007 #define FRMR_BLK_MODE FRMR_WQE_FIELD_LOC(40, 40)
1008 #define FRMR_ZBVA FRMR_WQE_FIELD_LOC(41, 41)
1009 #define FRMR_BIND_EN FRMR_WQE_FIELD_LOC(42, 42)
1010 #define FRMR_ATOMIC FRMR_WQE_FIELD_LOC(43, 43)
1011 #define FRMR_RR FRMR_WQE_FIELD_LOC(44, 44)
1012 #define FRMR_RW FRMR_WQE_FIELD_LOC(45, 45)
1013 #define FRMR_LW FRMR_WQE_FIELD_LOC(46, 46)
1015 struct hns_roce_v2_wqe_data_seg {
1021 struct hns_roce_query_version {
1022 __le16 rocee_vendor_id;
1023 __le16 rocee_hw_version;
1027 struct hns_roce_query_fw_info {
1032 struct hns_roce_func_clear {
1033 __le32 rst_funcid_en;
1038 #define FUNC_CLEAR_RST_FUN_DONE_S 0
1039 /* Each physical function manages up to 248 virtual functions, it takes up to
1040 * 100ms for each function to execute clear. If an abnormal reset occurs, it is
1041 * executed twice at most, so it takes up to 249 * 2 * 100ms.
1043 #define HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS (249 * 2 * 100)
1044 #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL 40
1045 #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT 20
1047 /* Fields of HNS_ROCE_OPC_EXT_CFG */
1048 #define EXT_CFG_VF_ID CMQ_REQ_FIELD_LOC(31, 0)
1049 #define EXT_CFG_QP_PI_IDX CMQ_REQ_FIELD_LOC(45, 32)
1050 #define EXT_CFG_QP_PI_NUM CMQ_REQ_FIELD_LOC(63, 48)
1051 #define EXT_CFG_QP_NUM CMQ_REQ_FIELD_LOC(87, 64)
1052 #define EXT_CFG_QP_IDX CMQ_REQ_FIELD_LOC(119, 96)
1053 #define EXT_CFG_LLM_IDX CMQ_REQ_FIELD_LOC(139, 128)
1054 #define EXT_CFG_LLM_NUM CMQ_REQ_FIELD_LOC(156, 144)
1056 #define CFG_LLM_A_BA_L CMQ_REQ_FIELD_LOC(31, 0)
1057 #define CFG_LLM_A_BA_H CMQ_REQ_FIELD_LOC(63, 32)
1058 #define CFG_LLM_A_DEPTH CMQ_REQ_FIELD_LOC(76, 64)
1059 #define CFG_LLM_A_PGSZ CMQ_REQ_FIELD_LOC(83, 80)
1060 #define CFG_LLM_A_INIT_EN CMQ_REQ_FIELD_LOC(84, 84)
1061 #define CFG_LLM_A_HEAD_BA_L CMQ_REQ_FIELD_LOC(127, 96)
1062 #define CFG_LLM_A_HEAD_BA_H CMQ_REQ_FIELD_LOC(147, 128)
1063 #define CFG_LLM_A_HEAD_NXTPTR CMQ_REQ_FIELD_LOC(159, 148)
1064 #define CFG_LLM_A_HEAD_PTR CMQ_REQ_FIELD_LOC(171, 160)
1065 #define CFG_LLM_B_TAIL_BA_L CMQ_REQ_FIELD_LOC(31, 0)
1066 #define CFG_LLM_B_TAIL_BA_H CMQ_REQ_FIELD_LOC(63, 32)
1067 #define CFG_LLM_B_TAIL_PTR CMQ_REQ_FIELD_LOC(75, 64)
1069 /* Fields of HNS_ROCE_OPC_CFG_GLOBAL_PARAM */
1070 #define CFG_GLOBAL_PARAM_1US_CYCLES CMQ_REQ_FIELD_LOC(9, 0)
1071 #define CFG_GLOBAL_PARAM_UDP_PORT CMQ_REQ_FIELD_LOC(31, 16)
1074 * Fields of HNS_ROCE_OPC_QUERY_PF_RES, HNS_ROCE_OPC_QUERY_VF_RES
1075 * and HNS_ROCE_OPC_ALLOC_VF_RES
1077 #define FUNC_RES_A_VF_ID CMQ_REQ_FIELD_LOC(7, 0)
1078 #define FUNC_RES_A_QPC_BT_IDX CMQ_REQ_FIELD_LOC(42, 32)
1079 #define FUNC_RES_A_QPC_BT_NUM CMQ_REQ_FIELD_LOC(59, 48)
1080 #define FUNC_RES_A_SRQC_BT_IDX CMQ_REQ_FIELD_LOC(72, 64)
1081 #define FUNC_RES_A_SRQC_BT_NUM CMQ_REQ_FIELD_LOC(89, 80)
1082 #define FUNC_RES_A_CQC_BT_IDX CMQ_REQ_FIELD_LOC(104, 96)
1083 #define FUNC_RES_A_CQC_BT_NUM CMQ_REQ_FIELD_LOC(121, 112)
1084 #define FUNC_RES_A_MPT_BT_IDX CMQ_REQ_FIELD_LOC(136, 128)
1085 #define FUNC_RES_A_MPT_BT_NUM CMQ_REQ_FIELD_LOC(153, 144)
1086 #define FUNC_RES_A_EQC_BT_IDX CMQ_REQ_FIELD_LOC(168, 160)
1087 #define FUNC_RES_A_EQC_BT_NUM CMQ_REQ_FIELD_LOC(185, 176)
1088 #define FUNC_RES_B_SMAC_IDX CMQ_REQ_FIELD_LOC(39, 32)
1089 #define FUNC_RES_B_SMAC_NUM CMQ_REQ_FIELD_LOC(48, 40)
1090 #define FUNC_RES_B_SGID_IDX CMQ_REQ_FIELD_LOC(71, 64)
1091 #define FUNC_RES_B_SGID_NUM CMQ_REQ_FIELD_LOC(80, 72)
1092 #define FUNC_RES_B_QID_IDX CMQ_REQ_FIELD_LOC(105, 96)
1093 #define FUNC_RES_B_QID_NUM CMQ_REQ_FIELD_LOC(122, 112)
1094 #define FUNC_RES_V_QID_NUM CMQ_REQ_FIELD_LOC(115, 112)
1096 #define FUNC_RES_B_SCCC_BT_IDX CMQ_REQ_FIELD_LOC(136, 128)
1097 #define FUNC_RES_B_SCCC_BT_NUM CMQ_REQ_FIELD_LOC(145, 137)
1098 #define FUNC_RES_B_GMV_BT_IDX CMQ_REQ_FIELD_LOC(167, 160)
1099 #define FUNC_RES_B_GMV_BT_NUM CMQ_REQ_FIELD_LOC(176, 168)
1100 #define FUNC_RES_V_GMV_BT_NUM CMQ_REQ_FIELD_LOC(184, 176)
1102 /* Fields of HNS_ROCE_OPC_QUERY_PF_TIMER_RES */
1103 #define PF_TIMER_RES_QPC_ITEM_IDX CMQ_REQ_FIELD_LOC(43, 32)
1104 #define PF_TIMER_RES_QPC_ITEM_NUM CMQ_REQ_FIELD_LOC(60, 48)
1105 #define PF_TIMER_RES_CQC_ITEM_IDX CMQ_REQ_FIELD_LOC(74, 64)
1106 #define PF_TIMER_RES_CQC_ITEM_NUM CMQ_REQ_FIELD_LOC(91, 80)
1108 struct hns_roce_vf_switch {
1117 #define VF_SWITCH_DATA_FUN_ID_VF_ID_S 3
1118 #define VF_SWITCH_DATA_FUN_ID_VF_ID_M GENMASK(10, 3)
1120 #define VF_SWITCH_DATA_CFG_ALW_LPBK_S 1
1121 #define VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S 2
1122 #define VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S 3
1124 struct hns_roce_post_mbox {
1130 __le32 token_event_en;
1133 struct hns_roce_mbox_status {
1134 __le32 mb_status_hw_run;
1138 #define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000
1140 #define MB_ST_HW_RUN_M BIT(31)
1141 #define MB_ST_COMPLETE_M GENMASK(7, 0)
1143 #define MB_ST_COMPLETE_SUCC 1
1145 /* Fields of HNS_ROCE_OPC_CFG_BT_ATTR */
1146 #define CFG_BT_ATTR_QPC_BA_PGSZ CMQ_REQ_FIELD_LOC(3, 0)
1147 #define CFG_BT_ATTR_QPC_BUF_PGSZ CMQ_REQ_FIELD_LOC(7, 4)
1148 #define CFG_BT_ATTR_QPC_HOPNUM CMQ_REQ_FIELD_LOC(9, 8)
1149 #define CFG_BT_ATTR_SRQC_BA_PGSZ CMQ_REQ_FIELD_LOC(35, 32)
1150 #define CFG_BT_ATTR_SRQC_BUF_PGSZ CMQ_REQ_FIELD_LOC(39, 36)
1151 #define CFG_BT_ATTR_SRQC_HOPNUM CMQ_REQ_FIELD_LOC(41, 40)
1152 #define CFG_BT_ATTR_CQC_BA_PGSZ CMQ_REQ_FIELD_LOC(67, 64)
1153 #define CFG_BT_ATTR_CQC_BUF_PGSZ CMQ_REQ_FIELD_LOC(71, 68)
1154 #define CFG_BT_ATTR_CQC_HOPNUM CMQ_REQ_FIELD_LOC(73, 72)
1155 #define CFG_BT_ATTR_MPT_BA_PGSZ CMQ_REQ_FIELD_LOC(99, 96)
1156 #define CFG_BT_ATTR_MPT_BUF_PGSZ CMQ_REQ_FIELD_LOC(103, 100)
1157 #define CFG_BT_ATTR_MPT_HOPNUM CMQ_REQ_FIELD_LOC(105, 104)
1158 #define CFG_BT_ATTR_SCCC_BA_PGSZ CMQ_REQ_FIELD_LOC(131, 128)
1159 #define CFG_BT_ATTR_SCCC_BUF_PGSZ CMQ_REQ_FIELD_LOC(135, 132)
1160 #define CFG_BT_ATTR_SCCC_HOPNUM CMQ_REQ_FIELD_LOC(137, 136)
1162 /* Fields of HNS_ROCE_OPC_CFG_ENTRY_SIZE */
1163 #define CFG_HEM_ENTRY_SIZE_TYPE CMQ_REQ_FIELD_LOC(31, 0)
1165 HNS_ROCE_CFG_QPC_SIZE = BIT(0),
1166 HNS_ROCE_CFG_SCCC_SIZE = BIT(1),
1169 #define CFG_HEM_ENTRY_SIZE_VALUE CMQ_REQ_FIELD_LOC(191, 160)
1171 /* Fields of HNS_ROCE_OPC_CFG_GMV_BT */
1172 #define CFG_GMV_BT_BA_L CMQ_REQ_FIELD_LOC(31, 0)
1173 #define CFG_GMV_BT_BA_H CMQ_REQ_FIELD_LOC(51, 32)
1174 #define CFG_GMV_BT_IDX CMQ_REQ_FIELD_LOC(95, 64)
1176 struct hns_roce_cfg_sgid_tb {
1177 __le32 table_idx_rsv;
1182 __le32 vf_sgid_type_rsv;
1185 #define CFG_SGID_TB_TABLE_IDX_S 0
1186 #define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0)
1188 #define CFG_SGID_TB_VF_SGID_TYPE_S 0
1189 #define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0)
1191 struct hns_roce_cfg_smac_tb {
1194 __le32 vf_smac_h_rsv;
1197 #define CFG_SMAC_TB_IDX_S 0
1198 #define CFG_SMAC_TB_IDX_M GENMASK(7, 0)
1200 #define CFG_SMAC_TB_VF_SMAC_H_S 0
1201 #define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0)
1203 struct hns_roce_cfg_gmv_tb_a {
1208 __le32 vf_sgid_type_vlan;
1212 #define CFG_GMV_TB_SGID_IDX_S 0
1213 #define CFG_GMV_TB_SGID_IDX_M GENMASK(7, 0)
1215 #define CFG_GMV_TB_VF_SGID_TYPE_S 0
1216 #define CFG_GMV_TB_VF_SGID_TYPE_M GENMASK(1, 0)
1218 #define CFG_GMV_TB_VF_VLAN_EN_S 2
1220 #define CFG_GMV_TB_VF_VLAN_ID_S 16
1221 #define CFG_GMV_TB_VF_VLAN_ID_M GENMASK(27, 16)
1223 struct hns_roce_cfg_gmv_tb_b {
1226 __le32 table_idx_rsv;
1230 #define CFG_GMV_TB_SMAC_H_S 0
1231 #define CFG_GMV_TB_SMAC_H_M GENMASK(15, 0)
1233 #define HNS_ROCE_QUERY_PF_CAPS_CMD_NUM 5
1234 struct hns_roce_query_pf_caps_a {
1236 u8 local_ca_ack_delay;
1238 __le16 max_sq_inline;
1240 __le32 max_extend_sg;
1241 __le16 num_qpc_timer;
1242 __le16 num_cqc_timer;
1243 __le16 max_srq_sges;
1245 u8 num_other_vectors;
1252 struct hns_roce_query_pf_caps_b {
1262 __le16 qpc_timer_entry_sz;
1263 __le16 cqc_timer_entry_sz;
1266 __le32 page_size_cap;
1273 struct hns_roce_query_pf_caps_c {
1274 __le32 cap_flags_num_pds;
1275 __le32 max_gid_num_cqs;
1283 #define V2_QUERY_PF_CAPS_C_NUM_PDS_S 0
1284 #define V2_QUERY_PF_CAPS_C_NUM_PDS_M GENMASK(19, 0)
1286 #define V2_QUERY_PF_CAPS_C_CAP_FLAGS_S 20
1287 #define V2_QUERY_PF_CAPS_C_CAP_FLAGS_M GENMASK(31, 20)
1289 #define V2_QUERY_PF_CAPS_C_NUM_CQS_S 0
1290 #define V2_QUERY_PF_CAPS_C_NUM_CQS_M GENMASK(19, 0)
1292 #define V2_QUERY_PF_CAPS_C_MAX_GID_S 20
1293 #define V2_QUERY_PF_CAPS_C_MAX_GID_M GENMASK(28, 20)
1295 #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_S 0
1296 #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_M GENMASK(22, 0)
1298 #define V2_QUERY_PF_CAPS_C_NUM_MRWS_S 0
1299 #define V2_QUERY_PF_CAPS_C_NUM_MRWS_M GENMASK(19, 0)
1301 #define V2_QUERY_PF_CAPS_C_NUM_QPS_S 0
1302 #define V2_QUERY_PF_CAPS_C_NUM_QPS_M GENMASK(19, 0)
1304 #define V2_QUERY_PF_CAPS_C_MAX_ORD_S 20
1305 #define V2_QUERY_PF_CAPS_C_MAX_ORD_M GENMASK(27, 20)
1307 struct hns_roce_query_pf_caps_d {
1308 __le32 wq_hop_num_max_srqs;
1310 __le16 cap_flags_ex;
1311 __le32 num_ceqs_ceq_depth;
1312 __le32 arm_st_aeq_depth;
1313 __le32 num_uars_rsv_pds;
1314 __le32 rsv_uars_rsv_qps;
1316 #define V2_QUERY_PF_CAPS_D_NUM_SRQS_S 0
1317 #define V2_QUERY_PF_CAPS_D_NUM_SRQS_M GENMASK(19, 0)
1319 #define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S 20
1320 #define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M GENMASK(21, 20)
1322 #define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S 22
1323 #define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M GENMASK(23, 22)
1325 #define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S 24
1326 #define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M GENMASK(25, 24)
1328 #define V2_QUERY_PF_CAPS_D_CONG_TYPE_S 26
1329 #define V2_QUERY_PF_CAPS_D_CONG_TYPE_M GENMASK(29, 26)
1331 struct hns_roce_congestion_algorithm {
1338 #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S 0
1339 #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M GENMASK(21, 0)
1341 #define V2_QUERY_PF_CAPS_D_NUM_CEQS_S 22
1342 #define V2_QUERY_PF_CAPS_D_NUM_CEQS_M GENMASK(31, 22)
1344 #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S 0
1345 #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M GENMASK(21, 0)
1347 #define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S 22
1348 #define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M GENMASK(23, 22)
1350 #define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S 24
1351 #define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M GENMASK(25, 24)
1353 #define V2_QUERY_PF_CAPS_D_RSV_PDS_S 0
1354 #define V2_QUERY_PF_CAPS_D_RSV_PDS_M GENMASK(19, 0)
1356 #define V2_QUERY_PF_CAPS_D_NUM_UARS_S 20
1357 #define V2_QUERY_PF_CAPS_D_NUM_UARS_M GENMASK(27, 20)
1359 #define V2_QUERY_PF_CAPS_D_RSV_QPS_S 0
1360 #define V2_QUERY_PF_CAPS_D_RSV_QPS_M GENMASK(19, 0)
1362 #define V2_QUERY_PF_CAPS_D_RSV_UARS_S 20
1363 #define V2_QUERY_PF_CAPS_D_RSV_UARS_M GENMASK(27, 20)
1365 struct hns_roce_query_pf_caps_e {
1366 __le32 chunk_size_shift_rsv_mrws;
1376 #define V2_QUERY_PF_CAPS_E_RSV_MRWS_S 0
1377 #define V2_QUERY_PF_CAPS_E_RSV_MRWS_M GENMASK(19, 0)
1379 #define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S 20
1380 #define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M GENMASK(31, 20)
1382 #define V2_QUERY_PF_CAPS_E_RSV_CQS_S 0
1383 #define V2_QUERY_PF_CAPS_E_RSV_CQS_M GENMASK(19, 0)
1385 #define V2_QUERY_PF_CAPS_E_RSV_SRQS_S 0
1386 #define V2_QUERY_PF_CAPS_E_RSV_SRQS_M GENMASK(19, 0)
1388 #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_S 0
1389 #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_M GENMASK(19, 0)
1391 struct hns_roce_cmq_req {
1395 #define CMQ_REQ_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_cmq_req, h, l)
1397 struct hns_roce_cmq_desc {
1405 __le32 own_func_num;
1412 struct hns_roce_v2_cmq_ring {
1413 dma_addr_t desc_dma_addr;
1414 struct hns_roce_cmq_desc *desc;
1419 spinlock_t lock; /* command queue lock */
1422 struct hns_roce_v2_cmq {
1423 struct hns_roce_v2_cmq_ring csq;
1427 struct hns_roce_link_table {
1428 struct hns_roce_buf_list table;
1429 struct hns_roce_buf *buf;
1432 #define HNS_ROCE_EXT_LLM_ENTRY(addr, id) (((id) << (64 - 12)) | ((addr) >> 12))
1433 #define HNS_ROCE_EXT_LLM_MIN_PAGES(que_num) ((que_num) * 4 + 2)
1435 struct hns_roce_v2_priv {
1436 struct hnae3_handle *handle;
1437 struct hns_roce_v2_cmq cmq;
1438 struct hns_roce_link_table ext_llm;
1441 struct hns_roce_dip {
1442 u8 dgid[GID_LEN_V2];
1444 struct list_head node; /* all dips are on a list */
1447 /* only for RNR timeout issue of HIP08 */
1448 #define HNS_ROCE_CLOCK_ADJUST 1000
1449 #define HNS_ROCE_MAX_CQ_PERIOD 65
1450 #define HNS_ROCE_MAX_EQ_PERIOD 65
1451 #define HNS_ROCE_RNR_TIMER_10NS 1
1452 #define HNS_ROCE_1US_CFG 999
1453 #define HNS_ROCE_1NS_CFG 0
1455 #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0
1456 #define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0
1457 #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x0
1458 #define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x0
1460 #define HNS_ROCE_V2_EQ_STATE_INVALID 0
1461 #define HNS_ROCE_V2_EQ_STATE_VALID 1
1462 #define HNS_ROCE_V2_EQ_STATE_OVERFLOW 2
1463 #define HNS_ROCE_V2_EQ_STATE_FAILURE 3
1465 #define HNS_ROCE_V2_EQ_OVER_IGNORE_0 0
1466 #define HNS_ROCE_V2_EQ_OVER_IGNORE_1 1
1468 #define HNS_ROCE_V2_EQ_COALESCE_0 0
1469 #define HNS_ROCE_V2_EQ_COALESCE_1 1
1471 #define HNS_ROCE_V2_EQ_FIRED 0
1472 #define HNS_ROCE_V2_EQ_ARMED 1
1473 #define HNS_ROCE_V2_EQ_ALWAYS_ARMED 3
1475 #define HNS_ROCE_EQ_INIT_EQE_CNT 0
1476 #define HNS_ROCE_EQ_INIT_PROD_IDX 0
1477 #define HNS_ROCE_EQ_INIT_REPORT_TIMER 0
1478 #define HNS_ROCE_EQ_INIT_MSI_IDX 0
1479 #define HNS_ROCE_EQ_INIT_CONS_IDX 0
1480 #define HNS_ROCE_EQ_INIT_NXT_EQE_BA 0
1482 #define HNS_ROCE_V2_CEQ_CEQE_OWNER_S 31
1483 #define HNS_ROCE_V2_AEQ_AEQE_OWNER_S 31
1485 #define HNS_ROCE_V2_COMP_EQE_NUM 0x1000
1486 #define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000
1488 #define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0
1489 #define HNS_ROCE_V2_VF_INT_ST_RAS_INT_S 1
1491 #define HNS_ROCE_EQ_DB_CMD_AEQ 0x0
1492 #define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1
1493 #define HNS_ROCE_EQ_DB_CMD_CEQ 0x2
1494 #define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED 0x3
1497 #define EQ_DISABLE 0
1499 #define EQ_REG_OFFSET 0x4
1501 #define HNS_ROCE_INT_NAME_LEN 32
1502 #define HNS_ROCE_V2_EQN_M GENMASK(23, 0)
1504 #define HNS_ROCE_V2_VF_ABN_INT_EN_S 0
1505 #define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0)
1506 #define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0)
1507 #define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)
1508 #define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)
1510 struct hns_roce_eq_context {
1514 #define EQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_eq_context, h, l)
1516 #define EQC_EQ_ST EQC_FIELD_LOC(1, 0)
1517 #define EQC_EQE_HOP_NUM EQC_FIELD_LOC(3, 2)
1518 #define EQC_OVER_IGNORE EQC_FIELD_LOC(4, 4)
1519 #define EQC_COALESCE EQC_FIELD_LOC(5, 5)
1520 #define EQC_ARM_ST EQC_FIELD_LOC(7, 6)
1521 #define EQC_EQN EQC_FIELD_LOC(15, 8)
1522 #define EQC_EQE_CNT EQC_FIELD_LOC(31, 16)
1523 #define EQC_EQE_BA_PG_SZ EQC_FIELD_LOC(35, 32)
1524 #define EQC_EQE_BUF_PG_SZ EQC_FIELD_LOC(39, 36)
1525 #define EQC_EQ_PROD_INDX EQC_FIELD_LOC(63, 40)
1526 #define EQC_EQ_MAX_CNT EQC_FIELD_LOC(79, 64)
1527 #define EQC_EQ_PERIOD EQC_FIELD_LOC(95, 80)
1528 #define EQC_EQE_REPORT_TIMER EQC_FIELD_LOC(127, 96)
1529 #define EQC_EQE_BA_L EQC_FIELD_LOC(159, 128)
1530 #define EQC_EQE_BA_H EQC_FIELD_LOC(188, 160)
1531 #define EQC_SHIFT EQC_FIELD_LOC(199, 192)
1532 #define EQC_MSI_INDX EQC_FIELD_LOC(207, 200)
1533 #define EQC_CUR_EQE_BA_L EQC_FIELD_LOC(223, 208)
1534 #define EQC_CUR_EQE_BA_M EQC_FIELD_LOC(255, 224)
1535 #define EQC_CUR_EQE_BA_H EQC_FIELD_LOC(259, 256)
1536 #define EQC_EQ_CONS_INDX EQC_FIELD_LOC(287, 264)
1537 #define EQC_NEX_EQE_BA_L EQC_FIELD_LOC(319, 288)
1538 #define EQC_NEX_EQE_BA_H EQC_FIELD_LOC(339, 320)
1539 #define EQC_EQE_SIZE EQC_FIELD_LOC(341, 340)
1541 #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
1542 #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
1544 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0
1545 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0)
1547 #define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8
1548 #define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8)
1550 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0
1551 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0)
1553 #define MAX_SERVICE_LEVEL 0x7
1555 struct hns_roce_wqe_atomic_seg {
1556 __le64 fetchadd_swap_data;
1560 struct hns_roce_sccc_clr {
1565 struct hns_roce_sccc_clr_done {
1570 int hns_roce_v2_query_cqc_info(struct hns_roce_dev *hr_dev, u32 cqn,
1573 static inline void hns_roce_write64(struct hns_roce_dev *hr_dev, __le32 val[2],
1576 struct hns_roce_v2_priv *priv = hr_dev->priv;
1577 struct hnae3_handle *handle = priv->handle;
1578 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1580 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
1581 hns_roce_write64_k(val, dest);