2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/acpi.h>
34 #include <linux/etherdevice.h>
35 #include <linux/interrupt.h>
36 #include <linux/iopoll.h>
37 #include <linux/kernel.h>
38 #include <linux/types.h>
39 #include <net/addrconf.h>
40 #include <rdma/ib_addr.h>
41 #include <rdma/ib_cache.h>
42 #include <rdma/ib_umem.h>
43 #include <rdma/uverbs_ioctl.h>
46 #include "hns_roce_common.h"
47 #include "hns_roce_device.h"
48 #include "hns_roce_cmd.h"
49 #include "hns_roce_hem.h"
50 #include "hns_roce_hw_v2.h"
58 enum ecc_resource_type {
64 ECC_RESOURCE_QPC_TIMER,
65 ECC_RESOURCE_CQC_TIMER,
76 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 },
78 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 },
80 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 },
81 { "ECC_RESOURCE_SRQC",
82 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 },
83 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */
86 { "ECC_RESOURCE_QPC_TIMER",
87 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 },
88 { "ECC_RESOURCE_CQC_TIMER",
89 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 },
90 { "ECC_RESOURCE_SCCC",
91 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 },
94 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
97 dseg->lkey = cpu_to_le32(sg->lkey);
98 dseg->addr = cpu_to_le64(sg->addr);
99 dseg->len = cpu_to_le32(sg->length);
103 * mapped-value = 1 + real-value
104 * The hns wr opcode real value is start from 0, In order to distinguish between
105 * initialized and uninitialized map values, we plus 1 to the actual value when
106 * defining the mapping, so that the validity can be identified by checking the
107 * mapped value is greater than 0.
109 #define HR_OPC_MAP(ib_key, hr_key) \
110 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key
112 static const u32 hns_roce_op_code[] = {
113 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE),
114 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM),
115 HR_OPC_MAP(SEND, SEND),
116 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM),
117 HR_OPC_MAP(RDMA_READ, RDMA_READ),
118 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP),
119 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD),
120 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV),
121 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP),
122 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD),
123 HR_OPC_MAP(REG_MR, FAST_REG_PMR),
126 static u32 to_hr_opcode(u32 ib_opcode)
128 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code))
129 return HNS_ROCE_V2_WQE_OP_MASK;
131 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 :
132 HNS_ROCE_V2_WQE_OP_MASK;
135 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
136 const struct ib_reg_wr *wr)
138 struct hns_roce_wqe_frmr_seg *fseg =
139 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
140 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
143 /* use ib_access_flags */
144 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND);
145 hr_reg_write_bool(fseg, FRMR_ATOMIC,
146 wr->access & IB_ACCESS_REMOTE_ATOMIC);
147 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ);
148 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE);
149 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE);
151 /* Data structure reuse may lead to confusion */
152 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba;
153 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba));
154 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba));
156 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
157 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
158 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
159 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
161 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages);
162 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ,
163 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
164 hr_reg_clear(fseg, FRMR_BLK_MODE);
167 static void set_atomic_seg(const struct ib_send_wr *wr,
168 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
169 unsigned int valid_num_sge)
171 struct hns_roce_v2_wqe_data_seg *dseg =
172 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
173 struct hns_roce_wqe_atomic_seg *aseg =
174 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg);
176 set_data_seg_v2(dseg, wr->sg_list);
178 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
179 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap);
180 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add);
182 aseg->fetchadd_swap_data =
183 cpu_to_le64(atomic_wr(wr)->compare_add);
187 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
190 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp,
191 const struct ib_send_wr *wr,
192 unsigned int *sge_idx, u32 msg_len)
194 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev;
195 unsigned int ext_sge_sz = qp->sq.max_gs * HNS_ROCE_SGE_SIZE;
196 unsigned int left_len_in_pg;
197 unsigned int idx = *sge_idx;
203 if (msg_len > ext_sge_sz) {
205 "no enough extended sge space for inline data.\n");
209 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
210 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg;
211 len = wr->sg_list[0].length;
212 addr = (void *)(unsigned long)(wr->sg_list[0].addr);
214 /* When copying data to extended sge space, the left length in page may
215 * not long enough for current user's sge. So the data should be
216 * splited into several parts, one in the first page, and the others in
217 * the subsequent pages.
220 if (len <= left_len_in_pg) {
221 memcpy(dseg, addr, len);
223 idx += len / HNS_ROCE_SGE_SIZE;
226 if (i >= wr->num_sge)
229 left_len_in_pg -= len;
230 len = wr->sg_list[i].length;
231 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
234 memcpy(dseg, addr, left_len_in_pg);
236 len -= left_len_in_pg;
237 addr += left_len_in_pg;
238 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE;
239 dseg = hns_roce_get_extend_sge(qp,
240 idx & (qp->sge.sge_cnt - 1));
241 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT;
250 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge,
251 unsigned int *sge_ind, unsigned int cnt)
253 struct hns_roce_v2_wqe_data_seg *dseg;
254 unsigned int idx = *sge_ind;
257 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
258 if (likely(sge->length)) {
259 set_data_seg_v2(dseg, sge);
269 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len)
271 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
272 int mtu = ib_mtu_enum_to_int(qp->path_mtu);
274 if (len > qp->max_inline_data || len > mtu) {
275 ibdev_err(&hr_dev->ib_dev,
276 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n",
277 len, qp->max_inline_data, mtu);
284 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
285 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
286 unsigned int *sge_idx)
288 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
289 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len);
290 struct ib_device *ibdev = &hr_dev->ib_dev;
291 unsigned int curr_idx = *sge_idx;
292 void *dseg = rc_sq_wqe;
296 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) {
297 ibdev_err(ibdev, "invalid inline parameters!\n");
301 if (!check_inl_data_len(qp, msg_len))
304 dseg += sizeof(struct hns_roce_v2_rc_send_wqe);
306 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) {
307 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
309 for (i = 0; i < wr->num_sge; i++) {
310 memcpy(dseg, ((void *)wr->sg_list[i].addr),
311 wr->sg_list[i].length);
312 dseg += wr->sg_list[i].length;
315 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
317 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len);
321 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx);
329 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
330 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
331 unsigned int *sge_ind,
332 unsigned int valid_num_sge)
334 struct hns_roce_v2_wqe_data_seg *dseg =
335 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
336 struct hns_roce_qp *qp = to_hr_qp(ibqp);
340 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX,
341 (*sge_ind) & (qp->sge.sge_cnt - 1));
343 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE,
344 !!(wr->send_flags & IB_SEND_INLINE));
345 if (wr->send_flags & IB_SEND_INLINE)
346 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind);
348 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) {
349 for (i = 0; i < wr->num_sge; i++) {
350 if (likely(wr->sg_list[i].length)) {
351 set_data_seg_v2(dseg, wr->sg_list + i);
356 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) {
357 if (likely(wr->sg_list[i].length)) {
358 set_data_seg_v2(dseg, wr->sg_list + i);
364 set_extend_sge(qp, wr->sg_list + i, sge_ind,
365 valid_num_sge - HNS_ROCE_SGE_IN_WQE);
368 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
373 static int check_send_valid(struct hns_roce_dev *hr_dev,
374 struct hns_roce_qp *hr_qp)
376 struct ib_device *ibdev = &hr_dev->ib_dev;
377 struct ib_qp *ibqp = &hr_qp->ibqp;
379 if (unlikely(ibqp->qp_type != IB_QPT_RC &&
380 ibqp->qp_type != IB_QPT_GSI &&
381 ibqp->qp_type != IB_QPT_UD)) {
382 ibdev_err(ibdev, "not supported QP(0x%x)type!\n",
385 } else if (unlikely(hr_qp->state == IB_QPS_RESET ||
386 hr_qp->state == IB_QPS_INIT ||
387 hr_qp->state == IB_QPS_RTR)) {
388 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n",
391 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) {
392 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n",
400 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr,
401 unsigned int *sge_len)
403 unsigned int valid_num = 0;
404 unsigned int len = 0;
407 for (i = 0; i < wr->num_sge; i++) {
408 if (likely(wr->sg_list[i].length)) {
409 len += wr->sg_list[i].length;
418 static __le32 get_immtdata(const struct ib_send_wr *wr)
420 switch (wr->opcode) {
421 case IB_WR_SEND_WITH_IMM:
422 case IB_WR_RDMA_WRITE_WITH_IMM:
423 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
429 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
430 const struct ib_send_wr *wr)
432 u32 ib_op = wr->opcode;
434 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM)
437 ud_sq_wqe->immtdata = get_immtdata(wr);
439 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
444 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
445 struct hns_roce_ah *ah)
447 struct ib_device *ib_dev = ah->ibah.device;
448 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
450 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport);
451 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit);
452 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass);
453 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel);
455 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL))
458 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl);
460 ud_sq_wqe->sgid_index = ah->av.gid_index;
462 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN);
463 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2);
465 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
468 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en);
469 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id);
474 static inline int set_ud_wqe(struct hns_roce_qp *qp,
475 const struct ib_send_wr *wr,
476 void *wqe, unsigned int *sge_idx,
477 unsigned int owner_bit)
479 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
480 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe;
481 unsigned int curr_idx = *sge_idx;
482 unsigned int valid_num_sge;
486 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
488 ret = set_ud_opcode(ud_sq_wqe, wr);
492 ud_sq_wqe->msg_len = cpu_to_le32(msg_len);
494 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE,
495 !!(wr->send_flags & IB_SEND_SIGNALED));
496 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE,
497 !!(wr->send_flags & IB_SEND_SOLICITED));
499 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn);
500 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge);
501 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX,
502 curr_idx & (qp->sge.sge_cnt - 1));
504 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
505 qp->qkey : ud_wr(wr)->remote_qkey);
506 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn);
508 ret = fill_ud_av(ud_sq_wqe, ah);
512 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl;
514 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge);
517 * The pipeline can sequentially post all valid WQEs into WQ buffer,
518 * including new WQEs waiting for the doorbell to update the PI again.
519 * Therefore, the owner bit of WQE MUST be updated after all fields
520 * and extSGEs have been written into DDR instead of cache.
522 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
526 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit);
531 static int set_rc_opcode(struct hns_roce_dev *hr_dev,
532 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
533 const struct ib_send_wr *wr)
535 u32 ib_op = wr->opcode;
538 rc_sq_wqe->immtdata = get_immtdata(wr);
541 case IB_WR_RDMA_READ:
542 case IB_WR_RDMA_WRITE:
543 case IB_WR_RDMA_WRITE_WITH_IMM:
544 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
545 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
548 case IB_WR_SEND_WITH_IMM:
550 case IB_WR_ATOMIC_CMP_AND_SWP:
551 case IB_WR_ATOMIC_FETCH_AND_ADD:
552 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey);
553 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr);
556 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
557 set_frmr_seg(rc_sq_wqe, reg_wr(wr));
561 case IB_WR_SEND_WITH_INV:
562 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
571 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
576 static inline int set_rc_wqe(struct hns_roce_qp *qp,
577 const struct ib_send_wr *wr,
578 void *wqe, unsigned int *sge_idx,
579 unsigned int owner_bit)
581 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
582 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
583 unsigned int curr_idx = *sge_idx;
584 unsigned int valid_num_sge;
588 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
590 rc_sq_wqe->msg_len = cpu_to_le32(msg_len);
592 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr);
596 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_FENCE,
597 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
599 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE,
600 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
602 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE,
603 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
605 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
606 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
607 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge);
608 else if (wr->opcode != IB_WR_REG_MR)
609 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
610 &curr_idx, valid_num_sge);
613 * The pipeline can sequentially post all valid WQEs into WQ buffer,
614 * including new WQEs waiting for the doorbell to update the PI again.
615 * Therefore, the owner bit of WQE MUST be updated after all fields
616 * and extSGEs have been written into DDR instead of cache.
618 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
622 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit);
627 static inline void update_sq_db(struct hns_roce_dev *hr_dev,
628 struct hns_roce_qp *qp)
630 if (unlikely(qp->state == IB_QPS_ERR)) {
631 flush_cqe(hr_dev, qp);
633 struct hns_roce_v2_db sq_db = {};
635 hr_reg_write(&sq_db, DB_TAG, qp->qpn);
636 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB);
637 hr_reg_write(&sq_db, DB_PI, qp->sq.head);
638 hr_reg_write(&sq_db, DB_SL, qp->sl);
640 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg);
644 static inline void update_rq_db(struct hns_roce_dev *hr_dev,
645 struct hns_roce_qp *qp)
647 if (unlikely(qp->state == IB_QPS_ERR)) {
648 flush_cqe(hr_dev, qp);
650 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) {
652 qp->rq.head & V2_DB_PRODUCER_IDX_M;
654 struct hns_roce_v2_db rq_db = {};
656 hr_reg_write(&rq_db, DB_TAG, qp->qpn);
657 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB);
658 hr_reg_write(&rq_db, DB_PI, qp->rq.head);
660 hns_roce_write64(hr_dev, (__le32 *)&rq_db,
666 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val,
669 #define HNS_ROCE_WRITE_TIMES 8
670 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
671 struct hnae3_handle *handle = priv->handle;
672 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
675 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
676 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++)
677 writeq_relaxed(*(val + i), dest + i);
680 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
683 #define HNS_ROCE_SL_SHIFT 2
684 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
686 /* All kinds of DirectWQE have the same header field layout */
687 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG);
688 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl);
689 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H,
690 qp->sl >> HNS_ROCE_SL_SHIFT);
691 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head);
693 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg);
696 static int hns_roce_v2_post_send(struct ib_qp *ibqp,
697 const struct ib_send_wr *wr,
698 const struct ib_send_wr **bad_wr)
700 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
701 struct ib_device *ibdev = &hr_dev->ib_dev;
702 struct hns_roce_qp *qp = to_hr_qp(ibqp);
703 unsigned long flags = 0;
704 unsigned int owner_bit;
705 unsigned int sge_idx;
706 unsigned int wqe_idx;
711 spin_lock_irqsave(&qp->sq.lock, flags);
713 ret = check_send_valid(hr_dev, qp);
720 sge_idx = qp->next_sge;
722 for (nreq = 0; wr; ++nreq, wr = wr->next) {
723 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
729 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
731 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
732 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n",
733 wr->num_sge, qp->sq.max_gs);
739 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
740 qp->sq.wrid[wqe_idx] = wr->wr_id;
742 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
744 /* Corresponding to the QP type, wqe process separately */
745 if (ibqp->qp_type == IB_QPT_RC)
746 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit);
748 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit);
759 qp->next_sge = sge_idx;
761 if (nreq == 1 && (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE))
762 write_dwqe(hr_dev, qp, wqe);
764 update_sq_db(hr_dev, qp);
767 spin_unlock_irqrestore(&qp->sq.lock, flags);
772 static int check_recv_valid(struct hns_roce_dev *hr_dev,
773 struct hns_roce_qp *hr_qp)
775 struct ib_device *ibdev = &hr_dev->ib_dev;
776 struct ib_qp *ibqp = &hr_qp->ibqp;
778 if (unlikely(ibqp->qp_type != IB_QPT_RC &&
779 ibqp->qp_type != IB_QPT_GSI &&
780 ibqp->qp_type != IB_QPT_UD)) {
781 ibdev_err(ibdev, "unsupported qp type, qp_type = %d.\n",
786 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
789 if (hr_qp->state == IB_QPS_RESET)
795 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe,
796 u32 max_sge, bool rsv)
798 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
801 for (i = 0, cnt = 0; i < wr->num_sge; i++) {
802 /* Skip zero-length sge */
803 if (!wr->sg_list[i].length)
805 set_data_seg_v2(dseg + cnt, wr->sg_list + i);
809 /* Fill a reserved sge to make hw stop reading remaining segments */
811 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
813 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH);
815 /* Clear remaining segments to make ROCEE ignore sges */
817 memset(dseg + cnt, 0,
818 (max_sge - cnt) * HNS_ROCE_SGE_SIZE);
822 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr,
823 u32 wqe_idx, u32 max_sge)
825 struct hns_roce_rinl_sge *sge_list;
829 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
830 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge);
832 /* rq support inline data */
833 if (hr_qp->rq_inl_buf.wqe_cnt) {
834 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list;
835 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt = (u32)wr->num_sge;
836 for (i = 0; i < wr->num_sge; i++) {
837 sge_list[i].addr = (void *)(u64)wr->sg_list[i].addr;
838 sge_list[i].len = wr->sg_list[i].length;
843 static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
844 const struct ib_recv_wr *wr,
845 const struct ib_recv_wr **bad_wr)
847 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
848 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
849 struct ib_device *ibdev = &hr_dev->ib_dev;
850 u32 wqe_idx, nreq, max_sge;
854 spin_lock_irqsave(&hr_qp->rq.lock, flags);
856 ret = check_recv_valid(hr_dev, hr_qp);
863 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
864 for (nreq = 0; wr; ++nreq, wr = wr->next) {
865 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq,
866 hr_qp->ibqp.recv_cq))) {
872 if (unlikely(wr->num_sge > max_sge)) {
873 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n",
874 wr->num_sge, max_sge);
880 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
881 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge);
882 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
887 hr_qp->rq.head += nreq;
889 update_rq_db(hr_dev, hr_qp);
891 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
896 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n)
898 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
901 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n)
903 return hns_roce_buf_offset(idx_que->mtr.kmem,
904 n << idx_que->entry_shift);
907 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index)
909 /* always called with interrupts disabled. */
910 spin_lock(&srq->lock);
912 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1);
915 spin_unlock(&srq->lock);
918 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq)
920 struct hns_roce_idx_que *idx_que = &srq->idx_que;
922 return idx_que->head - idx_que->tail >= srq->wqe_cnt;
925 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge,
926 const struct ib_recv_wr *wr)
928 struct ib_device *ib_dev = srq->ibsrq.device;
930 if (unlikely(wr->num_sge > max_sge)) {
932 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n",
933 wr->num_sge, max_sge);
937 if (unlikely(hns_roce_srqwq_overflow(srq))) {
939 "failed to check srqwq status, srqwq is full.\n");
946 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx)
948 struct hns_roce_idx_que *idx_que = &srq->idx_que;
951 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt);
952 if (unlikely(pos == srq->wqe_cnt))
955 bitmap_set(idx_que->bitmap, pos, 1);
960 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx)
962 struct hns_roce_idx_que *idx_que = &srq->idx_que;
966 head = idx_que->head & (srq->wqe_cnt - 1);
968 buf = get_idx_buf(idx_que, head);
969 *buf = cpu_to_le32(wqe_idx);
974 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq)
976 hr_reg_write(db, DB_TAG, srq->srqn);
977 hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB);
978 hr_reg_write(db, DB_PI, srq->idx_que.head);
981 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
982 const struct ib_recv_wr *wr,
983 const struct ib_recv_wr **bad_wr)
985 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
986 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
987 struct hns_roce_v2_db srq_db;
995 spin_lock_irqsave(&srq->lock, flags);
997 max_sge = srq->max_gs - srq->rsv_sge;
998 for (nreq = 0; wr; ++nreq, wr = wr->next) {
999 ret = check_post_srq_valid(srq, max_sge, wr);
1005 ret = get_srq_wqe_idx(srq, &wqe_idx);
1006 if (unlikely(ret)) {
1011 wqe = get_srq_wqe_buf(srq, wqe_idx);
1012 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge);
1013 fill_wqe_idx(srq, wqe_idx);
1014 srq->wrid[wqe_idx] = wr->wr_id;
1018 update_srq_db(&srq_db, srq);
1020 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg);
1023 spin_unlock_irqrestore(&srq->lock, flags);
1028 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
1029 unsigned long instance_stage,
1030 unsigned long reset_stage)
1032 /* When hardware reset has been completed once or more, we should stop
1033 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
1034 * function, we should exit with error. If now at HNAE3_INIT_CLIENT
1035 * stage of soft reset process, we should exit with error, and then
1036 * HNAE3_INIT_CLIENT related process can rollback the operation like
1037 * notifing hardware to free resources, HNAE3_INIT_CLIENT related
1038 * process will exit with error to notify NIC driver to reschedule soft
1039 * reset process once again.
1041 hr_dev->is_reset = true;
1042 hr_dev->dis_db = true;
1044 if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
1045 instance_stage == HNS_ROCE_STATE_INIT)
1046 return CMD_RST_PRC_EBUSY;
1048 return CMD_RST_PRC_SUCCESS;
1051 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
1052 unsigned long instance_stage,
1053 unsigned long reset_stage)
1055 #define HW_RESET_TIMEOUT_US 1000000
1056 #define HW_RESET_SLEEP_US 1000
1058 struct hns_roce_v2_priv *priv = hr_dev->priv;
1059 struct hnae3_handle *handle = priv->handle;
1060 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1064 /* When hardware reset is detected, we should stop sending mailbox&cmq&
1065 * doorbell to hardware. If now in .init_instance() function, we should
1066 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
1067 * process, we should exit with error, and then HNAE3_INIT_CLIENT
1068 * related process can rollback the operation like notifing hardware to
1069 * free resources, HNAE3_INIT_CLIENT related process will exit with
1070 * error to notify NIC driver to reschedule soft reset process once
1073 hr_dev->dis_db = true;
1075 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val,
1076 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US,
1077 HW_RESET_TIMEOUT_US, false, handle);
1079 hr_dev->is_reset = true;
1081 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
1082 instance_stage == HNS_ROCE_STATE_INIT)
1083 return CMD_RST_PRC_EBUSY;
1085 return CMD_RST_PRC_SUCCESS;
1088 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
1090 struct hns_roce_v2_priv *priv = hr_dev->priv;
1091 struct hnae3_handle *handle = priv->handle;
1092 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1094 /* When software reset is detected at .init_instance() function, we
1095 * should stop sending mailbox&cmq&doorbell to hardware, and exit
1098 hr_dev->dis_db = true;
1099 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
1100 hr_dev->is_reset = true;
1102 return CMD_RST_PRC_EBUSY;
1105 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev,
1106 struct hnae3_handle *handle)
1108 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1109 unsigned long instance_stage; /* the current instance stage */
1110 unsigned long reset_stage; /* the current reset stage */
1111 unsigned long reset_cnt;
1115 /* Get information about reset from NIC driver or RoCE driver itself,
1116 * the meaning of the following variables from NIC driver are described
1118 * reset_cnt -- The count value of completed hardware reset.
1119 * hw_resetting -- Whether hardware device is resetting now.
1120 * sw_resetting -- Whether NIC's software reset process is running now.
1122 instance_stage = handle->rinfo.instance_state;
1123 reset_stage = handle->rinfo.reset_state;
1124 reset_cnt = ops->ae_dev_reset_cnt(handle);
1125 if (reset_cnt != hr_dev->reset_cnt)
1126 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
1129 hw_resetting = ops->get_cmdq_stat(handle);
1131 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
1134 sw_resetting = ops->ae_dev_resetting(handle);
1135 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
1136 return hns_roce_v2_cmd_sw_resetting(hr_dev);
1138 return CMD_RST_PRC_OTHERS;
1141 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev)
1143 struct hns_roce_v2_priv *priv = hr_dev->priv;
1144 struct hnae3_handle *handle = priv->handle;
1145 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1147 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle))
1150 if (ops->get_hw_reset_stat(handle))
1153 if (ops->ae_dev_resetting(handle))
1159 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy)
1161 struct hns_roce_v2_priv *priv = hr_dev->priv;
1164 if (hr_dev->is_reset)
1165 status = CMD_RST_PRC_SUCCESS;
1167 status = check_aedev_reset_status(hr_dev, priv->handle);
1169 *busy = (status == CMD_RST_PRC_EBUSY);
1171 return status == CMD_RST_PRC_OTHERS;
1174 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
1175 struct hns_roce_v2_cmq_ring *ring)
1177 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
1179 ring->desc = dma_alloc_coherent(hr_dev->dev, size,
1180 &ring->desc_dma_addr, GFP_KERNEL);
1187 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
1188 struct hns_roce_v2_cmq_ring *ring)
1190 dma_free_coherent(hr_dev->dev,
1191 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
1192 ring->desc, ring->desc_dma_addr);
1194 ring->desc_dma_addr = 0;
1197 static int init_csq(struct hns_roce_dev *hr_dev,
1198 struct hns_roce_v2_cmq_ring *csq)
1203 csq->desc_num = CMD_CSQ_DESC_NUM;
1204 spin_lock_init(&csq->lock);
1205 csq->flag = TYPE_CSQ;
1208 ret = hns_roce_alloc_cmq_desc(hr_dev, csq);
1212 dma = csq->desc_dma_addr;
1213 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma));
1214 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma));
1215 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
1216 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1218 /* Make sure to write CI first and then PI */
1219 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0);
1220 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0);
1225 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
1227 struct hns_roce_v2_priv *priv = hr_dev->priv;
1230 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
1232 ret = init_csq(hr_dev, &priv->cmq.csq);
1234 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret);
1239 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
1241 struct hns_roce_v2_priv *priv = hr_dev->priv;
1243 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1246 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
1247 enum hns_roce_opcode_type opcode,
1250 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
1251 desc->opcode = cpu_to_le16(opcode);
1252 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1254 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
1256 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1259 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
1261 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1262 struct hns_roce_v2_priv *priv = hr_dev->priv;
1264 return tail == priv->cmq.csq.head;
1267 static void update_cmdq_status(struct hns_roce_dev *hr_dev)
1269 struct hns_roce_v2_priv *priv = hr_dev->priv;
1270 struct hnae3_handle *handle = priv->handle;
1272 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
1273 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT)
1274 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR;
1277 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1278 struct hns_roce_cmq_desc *desc, int num)
1280 struct hns_roce_v2_priv *priv = hr_dev->priv;
1281 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1288 spin_lock_bh(&csq->lock);
1292 for (i = 0; i < num; i++) {
1293 csq->desc[csq->head++] = desc[i];
1294 if (csq->head == csq->desc_num)
1298 /* Write to hardware */
1299 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head);
1302 if (hns_roce_cmq_csq_done(hr_dev))
1305 } while (++timeout < priv->cmq.tx_timeout);
1307 if (hns_roce_cmq_csq_done(hr_dev)) {
1309 for (i = 0; i < num; i++) {
1310 /* check the result of hardware write back */
1311 desc[i] = csq->desc[tail++];
1312 if (tail == csq->desc_num)
1315 desc_ret = le16_to_cpu(desc[i].retval);
1316 if (likely(desc_ret == CMD_EXEC_SUCCESS))
1319 dev_err_ratelimited(hr_dev->dev,
1320 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n",
1321 desc->opcode, desc_ret);
1325 /* FW/HW reset or incorrect number of desc */
1326 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1327 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n",
1331 update_cmdq_status(hr_dev);
1336 spin_unlock_bh(&csq->lock);
1341 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1342 struct hns_roce_cmq_desc *desc, int num)
1347 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1350 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1351 return busy ? -EBUSY : 0;
1353 ret = __hns_roce_cmq_send(hr_dev, desc, num);
1355 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1356 return busy ? -EBUSY : 0;
1362 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev,
1363 dma_addr_t base_addr, u8 cmd, unsigned long tag)
1365 struct hns_roce_cmd_mailbox *mbox;
1368 mbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1370 return PTR_ERR(mbox);
1372 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag);
1373 hns_roce_free_cmd_mailbox(hr_dev, mbox);
1377 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
1379 struct hns_roce_query_version *resp;
1380 struct hns_roce_cmq_desc desc;
1383 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1384 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1388 resp = (struct hns_roce_query_version *)desc.data;
1389 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version);
1390 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1395 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev,
1396 struct hnae3_handle *handle)
1398 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1401 hr_dev->dis_db = true;
1403 dev_warn(hr_dev->dev,
1404 "func clear is pending, device in resetting state.\n");
1405 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1407 if (!ops->get_hw_reset_stat(handle)) {
1408 hr_dev->is_reset = true;
1409 dev_info(hr_dev->dev,
1410 "func clear success after reset.\n");
1413 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1414 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1417 dev_warn(hr_dev->dev, "func clear failed.\n");
1420 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev,
1421 struct hnae3_handle *handle)
1423 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1426 hr_dev->dis_db = true;
1428 dev_warn(hr_dev->dev,
1429 "func clear is pending, device in resetting state.\n");
1430 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1432 if (ops->ae_dev_reset_cnt(handle) !=
1433 hr_dev->reset_cnt) {
1434 hr_dev->is_reset = true;
1435 dev_info(hr_dev->dev,
1436 "func clear success after sw reset\n");
1439 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1440 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1443 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n");
1446 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval,
1449 struct hns_roce_v2_priv *priv = hr_dev->priv;
1450 struct hnae3_handle *handle = priv->handle;
1451 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1453 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) {
1454 hr_dev->dis_db = true;
1455 hr_dev->is_reset = true;
1456 dev_info(hr_dev->dev, "func clear success after reset.\n");
1460 if (ops->get_hw_reset_stat(handle)) {
1461 func_clr_hw_resetting_state(hr_dev, handle);
1465 if (ops->ae_dev_resetting(handle) &&
1466 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) {
1467 func_clr_sw_resetting_state(hr_dev, handle);
1471 if (retval && !flag)
1472 dev_warn(hr_dev->dev,
1473 "func clear read failed, ret = %d.\n", retval);
1475 dev_warn(hr_dev->dev, "func clear failed.\n");
1478 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id)
1480 bool fclr_write_fail_flag = false;
1481 struct hns_roce_func_clear *resp;
1482 struct hns_roce_cmq_desc desc;
1486 if (check_device_is_in_reset(hr_dev))
1489 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
1490 resp = (struct hns_roce_func_clear *)desc.data;
1491 resp->rst_funcid_en = cpu_to_le32(vf_id);
1493 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1495 fclr_write_fail_flag = true;
1496 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n",
1501 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
1502 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
1504 if (check_device_is_in_reset(hr_dev))
1506 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
1507 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
1509 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR,
1512 resp->rst_funcid_en = cpu_to_le32(vf_id);
1513 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1517 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) {
1519 hr_dev->is_reset = true;
1525 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag);
1528 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id)
1530 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1531 struct hns_roce_cmq_desc desc[2];
1532 struct hns_roce_cmq_req *req_a;
1534 req_a = (struct hns_roce_cmq_req *)desc[0].data;
1535 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1536 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1537 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1538 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id);
1540 return hns_roce_cmq_send(hr_dev, desc, 2);
1543 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
1548 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1551 for (i = hr_dev->func_num - 1; i >= 0; i--) {
1552 __hns_roce_function_clear(hr_dev, i);
1557 ret = hns_roce_free_vf_resource(hr_dev, i);
1559 ibdev_err(&hr_dev->ib_dev,
1560 "failed to free vf resource, vf_id = %d, ret = %d.\n",
1565 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev)
1567 struct hns_roce_cmq_desc desc;
1570 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO,
1572 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1574 ibdev_err(&hr_dev->ib_dev,
1575 "failed to clear extended doorbell info, ret = %d.\n",
1581 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1583 struct hns_roce_query_fw_info *resp;
1584 struct hns_roce_cmq_desc desc;
1587 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1588 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1592 resp = (struct hns_roce_query_fw_info *)desc.data;
1593 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
1598 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev)
1600 struct hns_roce_cmq_desc desc;
1603 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
1604 hr_dev->func_num = 1;
1608 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO,
1610 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1612 hr_dev->func_num = 1;
1616 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num);
1617 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id);
1622 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1624 struct hns_roce_cmq_desc desc;
1625 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1626 u32 clock_cycles_of_1us;
1628 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1631 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
1632 clock_cycles_of_1us = HNS_ROCE_1NS_CFG;
1634 clock_cycles_of_1us = HNS_ROCE_1US_CFG;
1636 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us);
1637 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT);
1639 return hns_roce_cmq_send(hr_dev, &desc, 1);
1642 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1644 struct hns_roce_cmq_desc desc[2];
1645 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1646 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1647 struct hns_roce_caps *caps = &hr_dev->caps;
1648 enum hns_roce_opcode_type opcode;
1653 opcode = HNS_ROCE_OPC_QUERY_VF_RES;
1656 opcode = HNS_ROCE_OPC_QUERY_PF_RES;
1657 func_num = hr_dev->func_num;
1660 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true);
1661 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1662 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true);
1664 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1668 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num;
1669 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num;
1670 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num;
1671 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num;
1672 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num;
1673 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num;
1674 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num;
1675 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num;
1678 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num;
1679 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) /
1682 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num;
1683 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) /
1690 static int load_ext_cfg_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1692 struct hns_roce_cmq_desc desc;
1693 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1694 struct hns_roce_caps *caps = &hr_dev->caps;
1695 u32 func_num, qp_num;
1698 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, true);
1699 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1703 func_num = is_vf ? 1 : max_t(u32, 1, hr_dev->func_num);
1704 qp_num = hr_reg_read(req, EXT_CFG_QP_PI_NUM) / func_num;
1705 caps->num_pi_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM);
1707 qp_num = hr_reg_read(req, EXT_CFG_QP_NUM) / func_num;
1708 caps->num_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM);
1713 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev)
1715 struct hns_roce_cmq_desc desc;
1716 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1717 struct hns_roce_caps *caps = &hr_dev->caps;
1720 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1723 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1727 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM);
1728 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM);
1733 static int query_func_resource_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1735 struct device *dev = hr_dev->dev;
1738 ret = load_func_res_caps(hr_dev, is_vf);
1740 dev_err(dev, "failed to load res caps, ret = %d (%s).\n", ret,
1741 is_vf ? "vf" : "pf");
1745 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1746 ret = load_ext_cfg_caps(hr_dev, is_vf);
1748 dev_err(dev, "failed to load ext cfg, ret = %d (%s).\n",
1749 ret, is_vf ? "vf" : "pf");
1755 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1757 struct device *dev = hr_dev->dev;
1760 ret = query_func_resource_caps(hr_dev, false);
1764 ret = load_pf_timer_res_caps(hr_dev);
1766 dev_err(dev, "failed to load pf timer resource, ret = %d.\n",
1772 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev)
1774 return query_func_resource_caps(hr_dev, true);
1777 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev,
1780 struct hns_roce_vf_switch *swt;
1781 struct hns_roce_cmq_desc desc;
1784 swt = (struct hns_roce_vf_switch *)desc.data;
1785 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
1786 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
1787 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id);
1788 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1792 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1793 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1794 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK);
1795 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK);
1796 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD);
1798 return hns_roce_cmq_send(hr_dev, &desc, 1);
1801 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev)
1806 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) {
1807 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id);
1814 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id)
1816 struct hns_roce_cmq_desc desc[2];
1817 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1818 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1819 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1820 struct hns_roce_caps *caps = &hr_dev->caps;
1822 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1823 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1824 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1826 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id);
1828 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num);
1829 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num);
1830 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num);
1831 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num);
1832 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num);
1833 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num);
1834 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num);
1835 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num);
1836 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num);
1837 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num);
1838 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num);
1839 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num);
1840 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num);
1841 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num);
1843 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1844 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num);
1845 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX,
1846 vf_id * caps->gmv_bt_num);
1848 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num);
1849 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX,
1850 vf_id * caps->sgid_bt_num);
1851 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num);
1852 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX,
1853 vf_id * caps->smac_bt_num);
1856 return hns_roce_cmq_send(hr_dev, desc, 2);
1859 static int config_vf_ext_resource(struct hns_roce_dev *hr_dev, u32 vf_id)
1861 struct hns_roce_cmq_desc desc;
1862 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1863 struct hns_roce_caps *caps = &hr_dev->caps;
1865 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, false);
1867 hr_reg_write(req, EXT_CFG_VF_ID, vf_id);
1869 hr_reg_write(req, EXT_CFG_QP_PI_NUM, caps->num_pi_qps);
1870 hr_reg_write(req, EXT_CFG_QP_PI_IDX, vf_id * caps->num_pi_qps);
1871 hr_reg_write(req, EXT_CFG_QP_NUM, caps->num_qps);
1872 hr_reg_write(req, EXT_CFG_QP_IDX, vf_id * caps->num_qps);
1874 return hns_roce_cmq_send(hr_dev, &desc, 1);
1877 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1879 u32 func_num = max_t(u32, 1, hr_dev->func_num);
1883 for (vf_id = 0; vf_id < func_num; vf_id++) {
1884 ret = config_vf_hem_resource(hr_dev, vf_id);
1886 dev_err(hr_dev->dev,
1887 "failed to config vf-%u hem res, ret = %d.\n",
1892 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1893 ret = config_vf_ext_resource(hr_dev, vf_id);
1895 dev_err(hr_dev->dev,
1896 "failed to config vf-%u ext res, ret = %d.\n",
1906 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1908 struct hns_roce_cmq_desc desc;
1909 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1910 struct hns_roce_caps *caps = &hr_dev->caps;
1912 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1914 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ,
1915 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET);
1916 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ,
1917 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET);
1918 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM,
1919 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps));
1921 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ,
1922 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET);
1923 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ,
1924 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET);
1925 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM,
1926 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs));
1928 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ,
1929 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET);
1930 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ,
1931 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET);
1932 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM,
1933 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs));
1935 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ,
1936 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET);
1937 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ,
1938 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET);
1939 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM,
1940 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts));
1942 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ,
1943 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1944 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ,
1945 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1946 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM,
1947 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps));
1949 return hns_roce_cmq_send(hr_dev, &desc, 1);
1952 /* Use default caps when hns_roce_query_pf_caps() failed or init VF profile */
1953 static void set_default_caps(struct hns_roce_dev *hr_dev)
1955 struct hns_roce_caps *caps = &hr_dev->caps;
1957 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
1958 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
1959 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
1960 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM;
1961 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM;
1962 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
1963 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
1964 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1966 caps->num_uars = HNS_ROCE_V2_UAR_NUM;
1967 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
1968 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM;
1969 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
1970 caps->num_comp_vectors = 0;
1972 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
1973 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
1974 caps->qpc_timer_bt_num = HNS_ROCE_V2_MAX_QPC_TIMER_BT_NUM;
1975 caps->cqc_timer_bt_num = HNS_ROCE_V2_MAX_CQC_TIMER_BT_NUM;
1977 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1978 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1979 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1980 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1981 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
1982 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ;
1983 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
1984 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ;
1985 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1986 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ;
1987 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1988 caps->reserved_lkey = 0;
1989 caps->reserved_pds = 0;
1990 caps->reserved_mrws = 1;
1991 caps->reserved_uars = 0;
1992 caps->reserved_cqs = 0;
1993 caps->reserved_srqs = 0;
1994 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS;
1996 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1997 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1998 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1999 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
2000 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM;
2002 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM;
2003 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM;
2004 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM;
2005 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM;
2006 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM;
2007 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM;
2008 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM;
2009 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
2011 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR |
2012 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
2013 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB |
2014 HNS_ROCE_CAP_FLAG_QP_RECORD_DB;
2016 caps->pkey_table_len[0] = 1;
2017 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
2018 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
2019 caps->local_ca_ack_delay = 0;
2020 caps->max_mtu = IB_MTU_4096;
2022 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR;
2023 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE;
2025 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW |
2026 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR |
2027 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL | HNS_ROCE_CAP_FLAG_XRC;
2029 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
2031 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2032 caps->flags |= HNS_ROCE_CAP_FLAG_STASH |
2033 HNS_ROCE_CAP_FLAG_DIRECT_WQE;
2034 caps->max_sq_inline = HNS_ROCE_V3_MAX_SQ_INLINE;
2036 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
2038 /* The following configuration are only valid for HIP08 */
2039 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ;
2040 caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ;
2041 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE;
2045 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num,
2046 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type)
2049 u64 bt_chunk_size = PAGE_SIZE;
2050 u64 buf_chunk_size = PAGE_SIZE;
2051 u64 obj_per_chunk_default = buf_chunk_size / obj_size;
2058 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2059 (bt_chunk_size / BA_BYTE_LEN) *
2060 (bt_chunk_size / BA_BYTE_LEN) *
2061 obj_per_chunk_default;
2064 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2065 (bt_chunk_size / BA_BYTE_LEN) *
2066 obj_per_chunk_default;
2069 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2070 obj_per_chunk_default;
2072 case HNS_ROCE_HOP_NUM_0:
2073 obj_per_chunk = ctx_bt_num * obj_per_chunk_default;
2076 pr_err("table %u not support hop_num = %u!\n", hem_type,
2081 if (hem_type >= HEM_TYPE_MTT)
2082 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
2084 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
2087 static void set_hem_page_size(struct hns_roce_dev *hr_dev)
2089 struct hns_roce_caps *caps = &hr_dev->caps;
2092 caps->eqe_ba_pg_sz = 0;
2093 caps->eqe_buf_pg_sz = 0;
2096 caps->llm_buf_pg_sz = 0;
2099 caps->mpt_ba_pg_sz = 0;
2100 caps->mpt_buf_pg_sz = 0;
2101 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K;
2102 caps->pbl_buf_pg_sz = 0;
2103 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
2104 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
2108 caps->qpc_ba_pg_sz = 0;
2109 caps->qpc_buf_pg_sz = 0;
2110 caps->qpc_timer_ba_pg_sz = 0;
2111 caps->qpc_timer_buf_pg_sz = 0;
2112 caps->sccc_ba_pg_sz = 0;
2113 caps->sccc_buf_pg_sz = 0;
2114 caps->mtt_ba_pg_sz = 0;
2115 caps->mtt_buf_pg_sz = 0;
2116 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num,
2117 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
2120 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
2121 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num,
2122 caps->sccc_bt_num, &caps->sccc_buf_pg_sz,
2123 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC);
2126 caps->cqc_ba_pg_sz = 0;
2127 caps->cqc_buf_pg_sz = 0;
2128 caps->cqc_timer_ba_pg_sz = 0;
2129 caps->cqc_timer_buf_pg_sz = 0;
2130 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
2131 caps->cqe_buf_pg_sz = 0;
2132 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
2133 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
2135 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num,
2136 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
2139 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) {
2140 caps->srqc_ba_pg_sz = 0;
2141 caps->srqc_buf_pg_sz = 0;
2142 caps->srqwqe_ba_pg_sz = 0;
2143 caps->srqwqe_buf_pg_sz = 0;
2144 caps->idx_ba_pg_sz = 0;
2145 caps->idx_buf_pg_sz = 0;
2146 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz,
2147 caps->srqc_hop_num, caps->srqc_bt_num,
2148 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz,
2150 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
2151 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
2152 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
2153 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz,
2154 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz,
2155 &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
2159 caps->gmv_ba_pg_sz = 0;
2160 caps->gmv_buf_pg_sz = 0;
2163 /* Apply all loaded caps before setting to hardware */
2164 static void apply_func_caps(struct hns_roce_dev *hr_dev)
2166 struct hns_roce_caps *caps = &hr_dev->caps;
2167 struct hns_roce_v2_priv *priv = hr_dev->priv;
2169 /* The following configurations don't need to be got from firmware. */
2170 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
2171 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
2172 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
2174 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
2175 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2176 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2178 caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM;
2179 caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM;
2181 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
2182 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
2184 if (!caps->num_comp_vectors)
2185 caps->num_comp_vectors =
2186 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM,
2187 (u32)priv->handle->rinfo.num_vectors -
2188 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM));
2190 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2191 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM;
2192 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
2193 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
2195 /* The following configurations will be overwritten */
2196 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
2197 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE;
2198 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ;
2200 /* The following configurations are not got from firmware */
2201 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ;
2203 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0;
2204 caps->gid_table_len[0] = caps->gmv_bt_num *
2205 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz);
2207 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE /
2208 caps->gmv_entry_sz);
2210 u32 func_num = max_t(u32, 1, hr_dev->func_num);
2212 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM;
2213 caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
2214 caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
2215 caps->gid_table_len[0] /= func_num;
2218 if (hr_dev->is_vf) {
2219 caps->default_aeq_arm_st = 0x3;
2220 caps->default_ceq_arm_st = 0x3;
2221 caps->default_ceq_max_cnt = 0x1;
2222 caps->default_ceq_period = 0x10;
2223 caps->default_aeq_max_cnt = 0x1;
2224 caps->default_aeq_period = 0x10;
2227 set_hem_page_size(hr_dev);
2230 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
2232 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM];
2233 struct hns_roce_caps *caps = &hr_dev->caps;
2234 struct hns_roce_query_pf_caps_a *resp_a;
2235 struct hns_roce_query_pf_caps_b *resp_b;
2236 struct hns_roce_query_pf_caps_c *resp_c;
2237 struct hns_roce_query_pf_caps_d *resp_d;
2238 struct hns_roce_query_pf_caps_e *resp_e;
2244 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) {
2245 hns_roce_cmq_setup_basic_desc(&desc[i],
2246 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM,
2248 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1))
2249 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2251 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2254 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM);
2258 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data;
2259 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data;
2260 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data;
2261 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data;
2262 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data;
2264 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay;
2265 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg);
2266 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline);
2267 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg);
2268 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg);
2269 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges);
2270 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges);
2271 caps->num_aeq_vectors = resp_a->num_aeq_vectors;
2272 caps->num_other_vectors = resp_a->num_other_vectors;
2273 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz;
2274 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz;
2275 caps->cqe_sz = resp_a->cqe_sz;
2277 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz;
2278 caps->irrl_entry_sz = resp_b->irrl_entry_sz;
2279 caps->trrl_entry_sz = resp_b->trrl_entry_sz;
2280 caps->cqc_entry_sz = resp_b->cqc_entry_sz;
2281 caps->srqc_entry_sz = resp_b->srqc_entry_sz;
2282 caps->idx_entry_sz = resp_b->idx_entry_sz;
2283 caps->sccc_sz = resp_b->sccc_sz;
2284 caps->max_mtu = resp_b->max_mtu;
2285 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz);
2286 caps->min_cqes = resp_b->min_cqes;
2287 caps->min_wqes = resp_b->min_wqes;
2288 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap);
2289 caps->pkey_table_len[0] = resp_b->pkey_table_len;
2290 caps->phy_num_uars = resp_b->phy_num_uars;
2291 ctx_hop_num = resp_b->ctx_hop_num;
2292 pbl_hop_num = resp_b->pbl_hop_num;
2294 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS);
2296 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS);
2297 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) <<
2298 HNS_ROCE_CAP_FLAGS_EX_SHIFT;
2300 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS);
2301 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID);
2302 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH);
2303 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS);
2304 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS);
2305 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD);
2306 caps->max_qp_dest_rdma = caps->max_qp_init_rdma;
2307 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);
2309 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS);
2310 caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE);
2311 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);
2312 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH);
2313 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS);
2314 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH);
2315 caps->default_aeq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST);
2316 caps->default_ceq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST);
2317 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS);
2318 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS);
2319 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS);
2320 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS);
2322 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS);
2323 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT);
2324 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS);
2325 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS);
2326 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS);
2327 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);
2328 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);
2329 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
2330 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);
2332 caps->qpc_hop_num = ctx_hop_num;
2333 caps->sccc_hop_num = ctx_hop_num;
2334 caps->srqc_hop_num = ctx_hop_num;
2335 caps->cqc_hop_num = ctx_hop_num;
2336 caps->mpt_hop_num = ctx_hop_num;
2337 caps->mtt_hop_num = pbl_hop_num;
2338 caps->cqe_hop_num = pbl_hop_num;
2339 caps->srqwqe_hop_num = pbl_hop_num;
2340 caps->idx_hop_num = pbl_hop_num;
2341 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM);
2342 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM);
2343 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM);
2348 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val)
2350 struct hns_roce_cmq_desc desc;
2351 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
2353 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE,
2356 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type);
2357 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val);
2359 return hns_roce_cmq_send(hr_dev, &desc, 1);
2362 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev)
2364 struct hns_roce_caps *caps = &hr_dev->caps;
2367 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
2370 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE,
2373 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret);
2377 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE,
2380 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret);
2385 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev)
2387 struct device *dev = hr_dev->dev;
2390 hr_dev->func_num = 1;
2392 set_default_caps(hr_dev);
2394 ret = hns_roce_query_vf_resource(hr_dev);
2396 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret);
2400 apply_func_caps(hr_dev);
2402 ret = hns_roce_v2_set_bt(hr_dev);
2404 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret);
2409 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev)
2411 struct device *dev = hr_dev->dev;
2414 ret = hns_roce_query_func_info(hr_dev);
2416 dev_err(dev, "failed to query func info, ret = %d.\n", ret);
2420 ret = hns_roce_config_global_param(hr_dev);
2422 dev_err(dev, "failed to config global param, ret = %d.\n", ret);
2426 ret = hns_roce_set_vf_switch_param(hr_dev);
2428 dev_err(dev, "failed to set switch param, ret = %d.\n", ret);
2432 ret = hns_roce_query_pf_caps(hr_dev);
2434 set_default_caps(hr_dev);
2436 ret = hns_roce_query_pf_resource(hr_dev);
2438 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret);
2442 apply_func_caps(hr_dev);
2444 ret = hns_roce_alloc_vf_resource(hr_dev);
2446 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret);
2450 ret = hns_roce_v2_set_bt(hr_dev);
2452 dev_err(dev, "failed to config BA table, ret = %d.\n", ret);
2456 /* Configure the size of QPC, SCCC, etc. */
2457 return hns_roce_config_entry_size(hr_dev);
2460 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
2462 struct device *dev = hr_dev->dev;
2465 ret = hns_roce_cmq_query_hw_info(hr_dev);
2467 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret);
2471 ret = hns_roce_query_fw_ver(hr_dev);
2473 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret);
2477 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
2478 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
2481 return hns_roce_v2_vf_profile(hr_dev);
2483 return hns_roce_v2_pf_profile(hr_dev);
2486 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf)
2488 u32 i, next_ptr, page_num;
2489 __le64 *entry = cfg_buf;
2493 page_num = data_buf->npages;
2494 for (i = 0; i < page_num; i++) {
2495 addr = hns_roce_buf_page(data_buf, i);
2496 if (i == (page_num - 1))
2501 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr);
2502 entry[i] = cpu_to_le64(val);
2506 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev,
2507 struct hns_roce_link_table *table)
2509 struct hns_roce_cmq_desc desc[2];
2510 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
2511 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
2512 struct hns_roce_buf *buf = table->buf;
2513 enum hns_roce_opcode_type opcode;
2516 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
2517 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
2518 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2519 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
2521 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map));
2522 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map));
2523 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages);
2524 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift));
2525 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN);
2527 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0));
2528 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr));
2529 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr));
2530 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1);
2531 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0);
2533 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1));
2534 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr));
2535 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr));
2536 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1);
2538 return hns_roce_cmq_send(hr_dev, desc, 2);
2541 static struct hns_roce_link_table *
2542 alloc_link_table_buf(struct hns_roce_dev *hr_dev)
2544 struct hns_roce_v2_priv *priv = hr_dev->priv;
2545 struct hns_roce_link_table *link_tbl;
2546 u32 pg_shift, size, min_size;
2548 link_tbl = &priv->ext_llm;
2549 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT;
2550 size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ;
2551 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift;
2553 /* Alloc data table */
2554 size = max(size, min_size);
2555 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0);
2556 if (IS_ERR(link_tbl->buf))
2557 return ERR_PTR(-ENOMEM);
2559 /* Alloc config table */
2560 size = link_tbl->buf->npages * sizeof(u64);
2561 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size,
2562 &link_tbl->table.map,
2564 if (!link_tbl->table.buf) {
2565 hns_roce_buf_free(hr_dev, link_tbl->buf);
2566 return ERR_PTR(-ENOMEM);
2572 static void free_link_table_buf(struct hns_roce_dev *hr_dev,
2573 struct hns_roce_link_table *tbl)
2576 u32 size = tbl->buf->npages * sizeof(u64);
2578 dma_free_coherent(hr_dev->dev, size, tbl->table.buf,
2582 hns_roce_buf_free(hr_dev, tbl->buf);
2585 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev)
2587 struct hns_roce_link_table *link_tbl;
2590 link_tbl = alloc_link_table_buf(hr_dev);
2591 if (IS_ERR(link_tbl))
2594 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) {
2599 config_llm_table(link_tbl->buf, link_tbl->table.buf);
2600 ret = set_llm_cfg_to_hw(hr_dev, link_tbl);
2607 free_link_table_buf(hr_dev, link_tbl);
2611 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev)
2613 struct hns_roce_v2_priv *priv = hr_dev->priv;
2615 free_link_table_buf(hr_dev, &priv->ext_llm);
2618 static void free_dip_list(struct hns_roce_dev *hr_dev)
2620 struct hns_roce_dip *hr_dip;
2621 struct hns_roce_dip *tmp;
2622 unsigned long flags;
2624 spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
2626 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) {
2627 list_del(&hr_dip->node);
2631 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
2634 static void free_mr_exit(struct hns_roce_dev *hr_dev)
2636 struct hns_roce_v2_priv *priv = hr_dev->priv;
2637 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2641 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2642 if (free_mr->rsv_qp[i]) {
2643 ret = ib_destroy_qp(free_mr->rsv_qp[i]);
2645 ibdev_err(&hr_dev->ib_dev,
2646 "failed to destroy qp in free mr.\n");
2648 free_mr->rsv_qp[i] = NULL;
2652 if (free_mr->rsv_cq) {
2653 ib_destroy_cq(free_mr->rsv_cq);
2654 free_mr->rsv_cq = NULL;
2657 if (free_mr->rsv_pd) {
2658 ib_dealloc_pd(free_mr->rsv_pd);
2659 free_mr->rsv_pd = NULL;
2663 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev)
2665 struct hns_roce_v2_priv *priv = hr_dev->priv;
2666 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2667 struct ib_device *ibdev = &hr_dev->ib_dev;
2668 struct ib_cq_init_attr cq_init_attr = {};
2669 struct ib_qp_init_attr qp_init_attr = {};
2676 pd = ib_alloc_pd(ibdev, 0);
2678 ibdev_err(ibdev, "failed to create pd for free mr.\n");
2681 free_mr->rsv_pd = pd;
2683 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM;
2684 cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_init_attr);
2686 ibdev_err(ibdev, "failed to create cq for free mr.\n");
2690 free_mr->rsv_cq = cq;
2692 qp_init_attr.qp_type = IB_QPT_RC;
2693 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
2694 qp_init_attr.send_cq = free_mr->rsv_cq;
2695 qp_init_attr.recv_cq = free_mr->rsv_cq;
2696 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2697 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM;
2698 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM;
2699 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM;
2700 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM;
2702 qp = ib_create_qp(free_mr->rsv_pd, &qp_init_attr);
2704 ibdev_err(ibdev, "failed to create qp for free mr.\n");
2709 free_mr->rsv_qp[i] = qp;
2715 free_mr_exit(hr_dev);
2720 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev,
2721 struct ib_qp_attr *attr, int sl_num)
2723 struct hns_roce_v2_priv *priv = hr_dev->priv;
2724 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2725 struct ib_device *ibdev = &hr_dev->ib_dev;
2726 struct hns_roce_qp *hr_qp;
2731 hr_qp = to_hr_qp(free_mr->rsv_qp[sl_num]);
2732 hr_qp->free_mr_en = 1;
2734 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS;
2735 attr->qp_state = IB_QPS_INIT;
2737 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE;
2738 ret = ib_modify_qp(&hr_qp->ibqp, attr, mask);
2740 ibdev_err(ibdev, "failed to modify qp to init, ret = %d.\n",
2745 loopback = hr_dev->loop_idc;
2746 /* Set qpc lbi = 1 incidate loopback IO */
2747 hr_dev->loop_idc = 1;
2749 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN |
2750 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER;
2751 attr->qp_state = IB_QPS_RTR;
2752 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2753 attr->path_mtu = IB_MTU_256;
2754 attr->dest_qp_num = hr_qp->qpn;
2755 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2757 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num);
2759 ret = ib_modify_qp(&hr_qp->ibqp, attr, mask);
2760 hr_dev->loop_idc = loopback;
2762 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n",
2767 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT |
2768 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC;
2769 attr->qp_state = IB_QPS_RTS;
2770 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2771 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT;
2772 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT;
2773 ret = ib_modify_qp(&hr_qp->ibqp, attr, mask);
2775 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n",
2781 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev)
2783 struct hns_roce_v2_priv *priv = hr_dev->priv;
2784 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2785 struct ib_qp_attr attr = {};
2789 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
2790 rdma_ah_set_static_rate(&attr.ah_attr, 3);
2791 rdma_ah_set_port_num(&attr.ah_attr, 1);
2793 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2794 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i);
2802 static int free_mr_init(struct hns_roce_dev *hr_dev)
2804 struct hns_roce_v2_priv *priv = hr_dev->priv;
2805 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2808 mutex_init(&free_mr->mutex);
2810 ret = free_mr_alloc_res(hr_dev);
2814 ret = free_mr_modify_qp(hr_dev);
2821 free_mr_exit(hr_dev);
2826 static int get_hem_table(struct hns_roce_dev *hr_dev)
2828 unsigned int qpc_count;
2829 unsigned int cqc_count;
2830 unsigned int gmv_count;
2834 /* Alloc memory for source address table buffer space chunk */
2835 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num;
2837 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count);
2839 goto err_gmv_failed;
2845 /* Alloc memory for QPC Timer buffer space chunk */
2846 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
2848 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
2851 dev_err(hr_dev->dev, "QPC Timer get failed\n");
2852 goto err_qpc_timer_failed;
2856 /* Alloc memory for CQC Timer buffer space chunk */
2857 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
2859 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
2862 dev_err(hr_dev->dev, "CQC Timer get failed\n");
2863 goto err_cqc_timer_failed;
2869 err_cqc_timer_failed:
2870 for (i = 0; i < cqc_count; i++)
2871 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2873 err_qpc_timer_failed:
2874 for (i = 0; i < qpc_count; i++)
2875 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2878 for (i = 0; i < gmv_count; i++)
2879 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2884 static void put_hem_table(struct hns_roce_dev *hr_dev)
2888 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++)
2889 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2894 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++)
2895 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2897 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++)
2898 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2901 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
2905 /* The hns ROCEE requires the extdb info to be cleared before using */
2906 ret = hns_roce_clear_extdb_list_info(hr_dev);
2910 ret = get_hem_table(hr_dev);
2917 ret = hns_roce_init_link_table(hr_dev);
2919 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret);
2920 goto err_llm_init_failed;
2925 err_llm_init_failed:
2926 put_hem_table(hr_dev);
2931 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
2933 hns_roce_function_clear(hr_dev);
2936 hns_roce_free_link_table(hr_dev);
2938 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09)
2939 free_dip_list(hr_dev);
2942 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev,
2943 struct hns_roce_mbox_msg *mbox_msg)
2945 struct hns_roce_cmq_desc desc;
2946 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
2948 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
2950 mb->in_param_l = cpu_to_le32(mbox_msg->in_param);
2951 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32);
2952 mb->out_param_l = cpu_to_le32(mbox_msg->out_param);
2953 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32);
2954 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd);
2955 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 |
2958 return hns_roce_cmq_send(hr_dev, &desc, 1);
2961 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout,
2962 u8 *complete_status)
2964 struct hns_roce_mbox_status *mb_st;
2965 struct hns_roce_cmq_desc desc;
2971 mb_st = (struct hns_roce_mbox_status *)desc.data;
2972 end = msecs_to_jiffies(timeout) + jiffies;
2973 while (v2_chk_mbox_is_avail(hr_dev, &busy)) {
2974 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
2978 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST,
2980 ret = __hns_roce_cmq_send(hr_dev, &desc, 1);
2982 status = le32_to_cpu(mb_st->mb_status_hw_run);
2983 /* No pending message exists in ROCEE mbox. */
2984 if (!(status & MB_ST_HW_RUN_M))
2986 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
2990 if (time_after(jiffies, end)) {
2991 dev_err_ratelimited(hr_dev->dev,
2992 "failed to wait mbox status 0x%x\n",
3002 *complete_status = (u8)(status & MB_ST_COMPLETE_M);
3003 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
3004 /* Ignore all errors if the mbox is unavailable. */
3006 *complete_status = MB_ST_COMPLETE_M;
3012 static int v2_post_mbox(struct hns_roce_dev *hr_dev,
3013 struct hns_roce_mbox_msg *mbox_msg)
3018 /* Waiting for the mbox to be idle */
3019 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS,
3021 if (unlikely(ret)) {
3022 dev_err_ratelimited(hr_dev->dev,
3023 "failed to check post mbox status = 0x%x, ret = %d.\n",
3028 /* Post new message to mbox */
3029 ret = hns_roce_mbox_post(hr_dev, mbox_msg);
3031 dev_err_ratelimited(hr_dev->dev,
3032 "failed to post mailbox, ret = %d.\n", ret);
3037 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev)
3042 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS,
3045 if (status != MB_ST_COMPLETE_SUCC)
3048 dev_err_ratelimited(hr_dev->dev,
3049 "failed to check mbox status = 0x%x, ret = %d.\n",
3056 static void copy_gid(void *dest, const union ib_gid *gid)
3059 const union ib_gid *src = gid;
3060 __le32 (*p)[GID_SIZE] = dest;
3066 for (i = 0; i < GID_SIZE; i++)
3067 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]);
3070 static int config_sgid_table(struct hns_roce_dev *hr_dev,
3071 int gid_index, const union ib_gid *gid,
3072 enum hns_roce_sgid_type sgid_type)
3074 struct hns_roce_cmq_desc desc;
3075 struct hns_roce_cfg_sgid_tb *sgid_tb =
3076 (struct hns_roce_cfg_sgid_tb *)desc.data;
3078 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
3080 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index);
3081 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type);
3083 copy_gid(&sgid_tb->vf_sgid_l, gid);
3085 return hns_roce_cmq_send(hr_dev, &desc, 1);
3088 static int config_gmv_table(struct hns_roce_dev *hr_dev,
3089 int gid_index, const union ib_gid *gid,
3090 enum hns_roce_sgid_type sgid_type,
3091 const struct ib_gid_attr *attr)
3093 struct hns_roce_cmq_desc desc[2];
3094 struct hns_roce_cfg_gmv_tb_a *tb_a =
3095 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data;
3096 struct hns_roce_cfg_gmv_tb_b *tb_b =
3097 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data;
3099 u16 vlan_id = VLAN_CFI_MASK;
3100 u8 mac[ETH_ALEN] = {};
3104 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac);
3109 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3110 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
3112 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3114 copy_gid(&tb_a->vf_sgid_l, gid);
3116 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type);
3117 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK);
3118 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id);
3120 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac);
3122 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]);
3123 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index);
3125 return hns_roce_cmq_send(hr_dev, desc, 2);
3128 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index,
3129 const union ib_gid *gid,
3130 const struct ib_gid_attr *attr)
3132 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
3136 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
3137 if (ipv6_addr_v4mapped((void *)gid))
3138 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
3140 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
3141 } else if (attr->gid_type == IB_GID_TYPE_ROCE) {
3142 sgid_type = GID_TYPE_FLAG_ROCE_V1;
3146 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
3147 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr);
3149 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type);
3152 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n",
3158 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
3161 struct hns_roce_cmq_desc desc;
3162 struct hns_roce_cfg_smac_tb *smac_tb =
3163 (struct hns_roce_cfg_smac_tb *)desc.data;
3167 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
3169 reg_smac_l = *(u32 *)(&addr[0]);
3170 reg_smac_h = *(u16 *)(&addr[4]);
3172 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port);
3173 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h);
3174 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l);
3176 return hns_roce_cmq_send(hr_dev, &desc, 1);
3179 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev,
3180 struct hns_roce_v2_mpt_entry *mpt_entry,
3181 struct hns_roce_mr *mr)
3183 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 };
3184 struct ib_device *ibdev = &hr_dev->ib_dev;
3188 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
3189 ARRAY_SIZE(pages), &pbl_ba);
3191 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n",
3196 /* Aligned to the hardware address access unit */
3197 for (i = 0; i < count; i++)
3200 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3201 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3);
3202 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));
3204 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
3205 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0]));
3207 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
3208 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1]));
3209 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3210 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3215 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev,
3216 void *mb_buf, struct hns_roce_mr *mr)
3218 struct hns_roce_v2_mpt_entry *mpt_entry;
3221 memset(mpt_entry, 0, sizeof(*mpt_entry));
3223 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3224 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3226 hr_reg_write_bool(mpt_entry, MPT_BIND_EN,
3227 mr->access & IB_ACCESS_MW_BIND);
3228 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN,
3229 mr->access & IB_ACCESS_REMOTE_ATOMIC);
3230 hr_reg_write_bool(mpt_entry, MPT_RR_EN,
3231 mr->access & IB_ACCESS_REMOTE_READ);
3232 hr_reg_write_bool(mpt_entry, MPT_RW_EN,
3233 mr->access & IB_ACCESS_REMOTE_WRITE);
3234 hr_reg_write_bool(mpt_entry, MPT_LW_EN,
3235 mr->access & IB_ACCESS_LOCAL_WRITE);
3237 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3238 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3239 mpt_entry->lkey = cpu_to_le32(mr->key);
3240 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3241 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3243 if (mr->type != MR_TYPE_MR)
3244 hr_reg_enable(mpt_entry, MPT_PA);
3246 if (mr->type == MR_TYPE_DMA)
3249 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0)
3250 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num);
3252 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3253 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3254 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD);
3256 return set_mtpt_pbl(hr_dev, mpt_entry, mr);
3259 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
3260 struct hns_roce_mr *mr, int flags,
3263 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
3264 u32 mr_access_flags = mr->access;
3267 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3268 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3270 if (flags & IB_MR_REREG_ACCESS) {
3271 hr_reg_write(mpt_entry, MPT_BIND_EN,
3272 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
3273 hr_reg_write(mpt_entry, MPT_ATOMIC_EN,
3274 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3275 hr_reg_write(mpt_entry, MPT_RR_EN,
3276 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
3277 hr_reg_write(mpt_entry, MPT_RW_EN,
3278 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
3279 hr_reg_write(mpt_entry, MPT_LW_EN,
3280 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
3283 if (flags & IB_MR_REREG_TRANS) {
3284 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3285 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3286 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3287 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3289 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
3295 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev,
3296 void *mb_buf, struct hns_roce_mr *mr)
3298 struct ib_device *ibdev = &hr_dev->ib_dev;
3299 struct hns_roce_v2_mpt_entry *mpt_entry;
3300 dma_addr_t pbl_ba = 0;
3303 memset(mpt_entry, 0, sizeof(*mpt_entry));
3305 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) {
3306 ibdev_err(ibdev, "failed to find frmr mtr.\n");
3310 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3311 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3313 hr_reg_enable(mpt_entry, MPT_RA_EN);
3314 hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3316 hr_reg_enable(mpt_entry, MPT_FRE);
3317 hr_reg_clear(mpt_entry, MPT_MR_MW);
3318 hr_reg_enable(mpt_entry, MPT_BPD);
3319 hr_reg_clear(mpt_entry, MPT_PA);
3321 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1);
3322 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3323 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3324 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3325 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3327 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3329 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3));
3330 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));
3335 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
3337 struct hns_roce_v2_mpt_entry *mpt_entry;
3340 memset(mpt_entry, 0, sizeof(*mpt_entry));
3342 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3343 hr_reg_write(mpt_entry, MPT_PD, mw->pdn);
3345 hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3346 hr_reg_enable(mpt_entry, MPT_LW_EN);
3348 hr_reg_enable(mpt_entry, MPT_MR_MW);
3349 hr_reg_enable(mpt_entry, MPT_BPD);
3350 hr_reg_clear(mpt_entry, MPT_PA);
3351 hr_reg_write(mpt_entry, MPT_BQP,
3352 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
3354 mpt_entry->lkey = cpu_to_le32(mw->rkey);
3356 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM,
3357 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
3359 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3360 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3361 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3362 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
3367 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp)
3369 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
3370 struct ib_device *ibdev = &hr_dev->ib_dev;
3371 const struct ib_send_wr *bad_wr;
3372 struct ib_rdma_wr rdma_wr = {};
3373 struct ib_send_wr *send_wr;
3376 send_wr = &rdma_wr.wr;
3377 send_wr->opcode = IB_WR_RDMA_WRITE;
3379 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr);
3381 ibdev_err(ibdev, "failed to post wqe for free mr, ret = %d.\n",
3389 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3392 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev)
3394 struct hns_roce_v2_priv *priv = hr_dev->priv;
3395 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
3396 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)];
3397 struct ib_device *ibdev = &hr_dev->ib_dev;
3398 struct hns_roce_qp *hr_qp;
3406 * If the device initialization is not complete or in the uninstall
3407 * process, then there is no need to execute free mr.
3409 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
3410 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT ||
3411 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT)
3414 mutex_lock(&free_mr->mutex);
3416 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
3417 hr_qp = to_hr_qp(free_mr->rsv_qp[i]);
3419 ret = free_mr_post_send_lp_wqe(hr_qp);
3422 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n",
3430 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies;
3432 npolled = hns_roce_v2_poll_cq(free_mr->rsv_cq, cqe_cnt, wc);
3435 "failed to poll cqe for free mr, remain %d cqe.\n",
3440 if (time_after(jiffies, end)) {
3442 "failed to poll cqe for free mr and timeout, remain %d cqe.\n",
3450 mutex_unlock(&free_mr->mutex);
3453 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev)
3455 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
3456 free_mr_send_cmd_to_hw(hr_dev);
3459 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
3461 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);
3464 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n)
3466 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
3468 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
3469 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe :
3473 static inline void update_cq_db(struct hns_roce_dev *hr_dev,
3474 struct hns_roce_cq *hr_cq)
3476 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) {
3477 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M;
3479 struct hns_roce_v2_db cq_db = {};
3481 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3482 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB);
3483 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3484 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1);
3486 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3490 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3491 struct hns_roce_srq *srq)
3493 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3494 struct hns_roce_v2_cqe *cqe, *dest;
3500 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
3502 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe)
3507 * Now backwards through the CQ, removing CQ entries
3508 * that match our QP by overwriting them with next entries.
3510 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
3511 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
3512 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) {
3513 if (srq && hr_reg_read(cqe, CQE_S_R)) {
3514 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX);
3515 hns_roce_free_srq_wqe(srq, wqe_index);
3518 } else if (nfreed) {
3519 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
3521 owner_bit = hr_reg_read(dest, CQE_OWNER);
3522 memcpy(dest, cqe, hr_cq->cqe_size);
3523 hr_reg_write(dest, CQE_OWNER, owner_bit);
3528 hr_cq->cons_index += nfreed;
3529 update_cq_db(hr_dev, hr_cq);
3533 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3534 struct hns_roce_srq *srq)
3536 spin_lock_irq(&hr_cq->lock);
3537 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
3538 spin_unlock_irq(&hr_cq->lock);
3541 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
3542 struct hns_roce_cq *hr_cq, void *mb_buf,
3543 u64 *mtts, dma_addr_t dma_handle)
3545 struct hns_roce_v2_cq_context *cq_context;
3547 cq_context = mb_buf;
3548 memset(cq_context, 0, sizeof(*cq_context));
3550 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID);
3551 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED);
3552 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth));
3553 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector);
3554 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn);
3556 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE)
3557 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B);
3559 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
3560 hr_reg_enable(cq_context, CQC_STASH);
3562 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L,
3563 to_hr_hw_page_addr(mtts[0]));
3564 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H,
3565 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
3566 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num ==
3567 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
3568 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L,
3569 to_hr_hw_page_addr(mtts[1]));
3570 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H,
3571 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
3572 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ,
3573 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift));
3574 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ,
3575 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift));
3576 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3);
3577 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3)));
3578 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN,
3579 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB);
3580 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L,
3581 ((u32)hr_cq->db.dma) >> 1);
3582 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H,
3583 hr_cq->db.dma >> 32);
3584 hr_reg_write(cq_context, CQC_CQ_MAX_CNT,
3585 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
3586 hr_reg_write(cq_context, CQC_CQ_PERIOD,
3587 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
3590 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
3591 enum ib_cq_notify_flags flags)
3593 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3594 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3595 struct hns_roce_v2_db cq_db = {};
3599 * flags = 0, then notify_flag : next
3600 * flags = 1, then notify flag : solocited
3602 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
3603 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
3605 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3606 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY);
3607 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3608 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn);
3609 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag);
3611 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3616 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
3617 struct hns_roce_qp *qp,
3620 struct hns_roce_rinl_sge *sge_list;
3621 u32 wr_num, wr_cnt, sge_num;
3622 u32 sge_cnt, data_len, size;
3625 wr_num = hr_reg_read(cqe, CQE_WQE_IDX);
3626 wr_cnt = wr_num & (qp->rq.wqe_cnt - 1);
3628 sge_list = qp->rq_inl_buf.wqe_list[wr_cnt].sg_list;
3629 sge_num = qp->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
3630 wqe_buf = hns_roce_get_recv_wqe(qp, wr_cnt);
3631 data_len = wc->byte_len;
3633 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
3634 size = min(sge_list[sge_cnt].len, data_len);
3635 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
3641 if (unlikely(data_len)) {
3642 wc->status = IB_WC_LOC_LEN_ERR;
3649 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq,
3650 int num_entries, struct ib_wc *wc)
3655 left = wq->head - wq->tail;
3659 left = min_t(unsigned int, (unsigned int)num_entries, left);
3660 while (npolled < left) {
3661 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3662 wc->status = IB_WC_WR_FLUSH_ERR;
3664 wc->qp = &hr_qp->ibqp;
3674 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
3677 struct hns_roce_qp *hr_qp;
3680 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) {
3681 npolled += sw_comp(hr_qp, &hr_qp->sq,
3682 num_entries - npolled, wc + npolled);
3683 if (npolled >= num_entries)
3687 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) {
3688 npolled += sw_comp(hr_qp, &hr_qp->rq,
3689 num_entries - npolled, wc + npolled);
3690 if (npolled >= num_entries)
3698 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
3699 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe,
3702 static const struct {
3704 enum ib_wc_status wc_status;
3706 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS },
3707 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR },
3708 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR },
3709 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR },
3710 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR },
3711 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR },
3712 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR },
3713 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR },
3714 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR },
3715 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR },
3716 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR },
3717 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR,
3718 IB_WC_RETRY_EXC_ERR },
3719 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR },
3720 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR },
3721 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR}
3724 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS);
3727 wc->status = IB_WC_GENERAL_ERR;
3728 for (i = 0; i < ARRAY_SIZE(map); i++)
3729 if (cqe_status == map[i].cqe_status) {
3730 wc->status = map[i].wc_status;
3734 if (likely(wc->status == IB_WC_SUCCESS ||
3735 wc->status == IB_WC_WR_FLUSH_ERR))
3738 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status);
3739 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe,
3740 cq->cqe_size, false);
3741 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS);
3744 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in
3745 * the standard protocol, the driver must ignore it and needn't to set
3746 * the QP to an error state.
3748 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR)
3751 flush_cqe(hr_dev, qp);
3754 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe,
3755 struct hns_roce_qp **cur_qp)
3757 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3758 struct hns_roce_qp *hr_qp = *cur_qp;
3761 qpn = hr_reg_read(cqe, CQE_LCL_QPN);
3763 if (!hr_qp || qpn != hr_qp->qpn) {
3764 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
3765 if (unlikely(!hr_qp)) {
3766 ibdev_err(&hr_dev->ib_dev,
3767 "CQ %06lx with entry for unknown QPN %06x\n",
3778 * mapped-value = 1 + real-value
3779 * The ib wc opcode's real value is start from 0, In order to distinguish
3780 * between initialized and uninitialized map values, we plus 1 to the actual
3781 * value when defining the mapping, so that the validity can be identified by
3782 * checking whether the mapped value is greater than 0.
3784 #define HR_WC_OP_MAP(hr_key, ib_key) \
3785 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key
3787 static const u32 wc_send_op_map[] = {
3788 HR_WC_OP_MAP(SEND, SEND),
3789 HR_WC_OP_MAP(SEND_WITH_INV, SEND),
3790 HR_WC_OP_MAP(SEND_WITH_IMM, SEND),
3791 HR_WC_OP_MAP(RDMA_READ, RDMA_READ),
3792 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE),
3793 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE),
3794 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP),
3795 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD),
3796 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP),
3797 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD),
3798 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR),
3799 HR_WC_OP_MAP(BIND_MW, REG_MR),
3802 static int to_ib_wc_send_op(u32 hr_opcode)
3804 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map))
3807 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 :
3811 static const u32 wc_recv_op_map[] = {
3812 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM),
3813 HR_WC_OP_MAP(SEND, RECV),
3814 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM),
3815 HR_WC_OP_MAP(SEND_WITH_INV, RECV),
3818 static int to_ib_wc_recv_op(u32 hr_opcode)
3820 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map))
3823 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 :
3827 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3834 hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3835 switch (hr_opcode) {
3836 case HNS_ROCE_V2_WQE_OP_RDMA_READ:
3837 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3839 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM:
3840 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM:
3841 wc->wc_flags |= IB_WC_WITH_IMM;
3843 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP:
3844 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD:
3845 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP:
3846 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD:
3853 ib_opcode = to_ib_wc_send_op(hr_opcode);
3855 wc->status = IB_WC_GENERAL_ERR;
3857 wc->opcode = ib_opcode;
3860 static inline bool is_rq_inl_enabled(struct ib_wc *wc, u32 hr_opcode,
3861 struct hns_roce_v2_cqe *cqe)
3863 return wc->qp->qp_type != IB_QPT_UD && wc->qp->qp_type != IB_QPT_GSI &&
3864 (hr_opcode == HNS_ROCE_V2_OPCODE_SEND ||
3865 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
3866 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
3867 hr_reg_read(cqe, CQE_RQ_INLINE);
3870 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3872 struct hns_roce_qp *qp = to_hr_qp(wc->qp);
3877 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3879 hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3880 switch (hr_opcode) {
3881 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
3882 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
3883 wc->wc_flags = IB_WC_WITH_IMM;
3884 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata));
3886 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
3887 wc->wc_flags = IB_WC_WITH_INVALIDATE;
3888 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
3894 ib_opcode = to_ib_wc_recv_op(hr_opcode);
3896 wc->status = IB_WC_GENERAL_ERR;
3898 wc->opcode = ib_opcode;
3900 if (is_rq_inl_enabled(wc, hr_opcode, cqe)) {
3901 ret = hns_roce_handle_recv_inl_wqe(cqe, qp, wc);
3906 wc->sl = hr_reg_read(cqe, CQE_SL);
3907 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN);
3909 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0;
3910 wc->port_num = hr_reg_read(cqe, CQE_PORTN);
3913 if (hr_reg_read(cqe, CQE_VID_VLD)) {
3914 wc->vlan_id = hr_reg_read(cqe, CQE_VID);
3915 wc->wc_flags |= IB_WC_WITH_VLAN;
3917 wc->vlan_id = 0xffff;
3920 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE);
3925 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
3926 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
3928 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3929 struct hns_roce_qp *qp = *cur_qp;
3930 struct hns_roce_srq *srq = NULL;
3931 struct hns_roce_v2_cqe *cqe;
3932 struct hns_roce_wq *wq;
3937 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
3941 ++hr_cq->cons_index;
3942 /* Memory barrier */
3945 ret = get_cur_qp(hr_cq, cqe, &qp);
3952 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX);
3954 is_send = !hr_reg_read(cqe, CQE_S_R);
3958 /* If sg_signal_bit is set, tail pointer will be updated to
3959 * the WQE corresponding to the current CQE.
3961 if (qp->sq_signal_bits)
3962 wq->tail += (wqe_idx - (u16)wq->tail) &
3965 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3968 fill_send_wc(wc, cqe);
3971 srq = to_hr_srq(qp->ibqp.srq);
3972 wc->wr_id = srq->wrid[wqe_idx];
3973 hns_roce_free_srq_wqe(srq, wqe_idx);
3976 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3980 ret = fill_recv_wc(wc, cqe);
3983 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc);
3984 if (unlikely(wc->status != IB_WC_SUCCESS))
3990 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3993 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3994 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3995 struct hns_roce_qp *cur_qp = NULL;
3996 unsigned long flags;
3999 spin_lock_irqsave(&hr_cq->lock, flags);
4002 * When the device starts to reset, the state is RST_DOWN. At this time,
4003 * there may still be some valid CQEs in the hardware that are not
4004 * polled. Therefore, it is not allowed to switch to the software mode
4005 * immediately. When the state changes to UNINIT, CQE no longer exists
4006 * in the hardware, and then switch to software mode.
4008 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
4009 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc);
4013 for (npolled = 0; npolled < num_entries; ++npolled) {
4014 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
4019 update_cq_db(hr_dev, hr_cq);
4022 spin_unlock_irqrestore(&hr_cq->lock, flags);
4027 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
4028 u32 step_idx, u8 *mbox_cmd)
4034 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0;
4037 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0;
4040 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0;
4043 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0;
4046 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0;
4048 case HEM_TYPE_QPC_TIMER:
4049 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
4051 case HEM_TYPE_CQC_TIMER:
4052 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
4055 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type);
4059 *mbox_cmd = cmd + step_idx;
4064 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj,
4065 dma_addr_t base_addr)
4067 struct hns_roce_cmq_desc desc;
4068 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
4069 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz);
4070 u64 addr = to_hr_hw_page_addr(base_addr);
4072 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
4074 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr));
4075 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr));
4076 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
4078 return hns_roce_cmq_send(hr_dev, &desc, 1);
4081 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj,
4082 dma_addr_t base_addr, u32 hem_type, u32 step_idx)
4087 if (unlikely(hem_type == HEM_TYPE_GMV))
4088 return config_gmv_ba_to_hw(hr_dev, obj, base_addr);
4090 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx))
4093 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd);
4097 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj);
4100 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
4101 struct hns_roce_hem_table *table, int obj,
4104 struct hns_roce_hem_iter iter;
4105 struct hns_roce_hem_mhop mhop;
4106 struct hns_roce_hem *hem;
4107 unsigned long mhop_obj = obj;
4116 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4119 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
4123 hop_num = mhop.hop_num;
4124 chunk_ba_num = mhop.bt_chunk_size / 8;
4127 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
4129 l1_idx = i * chunk_ba_num + j;
4130 } else if (hop_num == 1) {
4131 hem_idx = i * chunk_ba_num + j;
4132 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
4136 if (table->type == HEM_TYPE_SCCC)
4139 if (check_whether_last_step(hop_num, step_idx)) {
4140 hem = table->hem[hem_idx];
4141 for (hns_roce_hem_first(hem, &iter);
4142 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
4143 bt_ba = hns_roce_hem_addr(&iter);
4144 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type,
4149 bt_ba = table->bt_l0_dma_addr[i];
4150 else if (step_idx == 1 && hop_num == 2)
4151 bt_ba = table->bt_l1_dma_addr[l1_idx];
4153 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx);
4159 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
4160 struct hns_roce_hem_table *table,
4161 int tag, u32 step_idx)
4163 struct hns_roce_cmd_mailbox *mailbox;
4164 struct device *dev = hr_dev->dev;
4168 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4171 switch (table->type) {
4173 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0;
4176 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0;
4179 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0;
4182 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
4185 case HEM_TYPE_QPC_TIMER:
4186 case HEM_TYPE_CQC_TIMER:
4190 dev_warn(dev, "table %u not to be destroyed by mailbox!\n",
4197 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4198 if (IS_ERR(mailbox))
4199 return PTR_ERR(mailbox);
4201 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag);
4203 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4207 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
4208 struct hns_roce_v2_qp_context *context,
4209 struct hns_roce_v2_qp_context *qpc_mask,
4210 struct hns_roce_qp *hr_qp)
4212 struct hns_roce_cmd_mailbox *mailbox;
4216 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4217 if (IS_ERR(mailbox))
4218 return PTR_ERR(mailbox);
4220 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */
4221 qpc_size = hr_dev->caps.qpc_sz;
4222 memcpy(mailbox->buf, context, qpc_size);
4223 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size);
4225 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
4226 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn);
4228 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4233 static void set_access_flags(struct hns_roce_qp *hr_qp,
4234 struct hns_roce_v2_qp_context *context,
4235 struct hns_roce_v2_qp_context *qpc_mask,
4236 const struct ib_qp_attr *attr, int attr_mask)
4241 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
4242 attr->max_dest_rd_atomic : hr_qp->resp_depth;
4244 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
4245 attr->qp_access_flags : hr_qp->atomic_rd_en;
4247 if (!dest_rd_atomic)
4248 access_flags &= IB_ACCESS_REMOTE_WRITE;
4250 hr_reg_write_bool(context, QPC_RRE,
4251 access_flags & IB_ACCESS_REMOTE_READ);
4252 hr_reg_clear(qpc_mask, QPC_RRE);
4254 hr_reg_write_bool(context, QPC_RWE,
4255 access_flags & IB_ACCESS_REMOTE_WRITE);
4256 hr_reg_clear(qpc_mask, QPC_RWE);
4258 hr_reg_write_bool(context, QPC_ATE,
4259 access_flags & IB_ACCESS_REMOTE_ATOMIC);
4260 hr_reg_clear(qpc_mask, QPC_ATE);
4261 hr_reg_write_bool(context, QPC_EXT_ATE,
4262 access_flags & IB_ACCESS_REMOTE_ATOMIC);
4263 hr_reg_clear(qpc_mask, QPC_EXT_ATE);
4266 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp,
4267 struct hns_roce_v2_qp_context *context,
4268 struct hns_roce_v2_qp_context *qpc_mask)
4270 hr_reg_write(context, QPC_SGE_SHIFT,
4271 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt,
4272 hr_qp->sge.sge_shift));
4274 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt));
4276 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt));
4279 static inline int get_cqn(struct ib_cq *ib_cq)
4281 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0;
4284 static inline int get_pdn(struct ib_pd *ib_pd)
4286 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0;
4289 static void modify_qp_reset_to_init(struct ib_qp *ibqp,
4290 const struct ib_qp_attr *attr,
4291 struct hns_roce_v2_qp_context *context,
4292 struct hns_roce_v2_qp_context *qpc_mask)
4294 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4295 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4298 * In v2 engine, software pass context and context mask to hardware
4299 * when modifying qp. If software need modify some fields in context,
4300 * we should set all bits of the relevant fields in context mask to
4301 * 0 at the same time, else set them to 0x1.
4303 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4305 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4307 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs));
4309 set_qpc_wqe_cnt(hr_qp, context, qpc_mask);
4311 /* No VLAN need to set 0xFFF */
4312 hr_reg_write(context, QPC_VLAN_ID, 0xfff);
4314 if (ibqp->qp_type == IB_QPT_XRC_TGT) {
4315 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn);
4317 hr_reg_enable(context, QPC_XRC_QP_TYPE);
4320 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
4321 hr_reg_enable(context, QPC_RQ_RECORD_EN);
4323 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
4324 hr_reg_enable(context, QPC_OWNER_MODE);
4326 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L,
4327 lower_32_bits(hr_qp->rdb.dma) >> 1);
4328 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H,
4329 upper_32_bits(hr_qp->rdb.dma));
4331 if (ibqp->qp_type != IB_QPT_UD && ibqp->qp_type != IB_QPT_GSI)
4332 hr_reg_write_bool(context, QPC_RQIE,
4333 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE);
4335 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4338 hr_reg_enable(context, QPC_SRQ_EN);
4339 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4342 hr_reg_enable(context, QPC_FRE);
4344 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4346 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ)
4349 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
4350 hr_reg_enable(&context->ext, QPCEX_STASH);
4353 static void modify_qp_init_to_init(struct ib_qp *ibqp,
4354 const struct ib_qp_attr *attr,
4355 struct hns_roce_v2_qp_context *context,
4356 struct hns_roce_v2_qp_context *qpc_mask)
4359 * In v2 engine, software pass context and context mask to hardware
4360 * when modifying qp. If software need modify some fields in context,
4361 * we should set all bits of the relevant fields in context mask to
4362 * 0 at the same time, else set them to 0x1.
4364 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4365 hr_reg_clear(qpc_mask, QPC_TST);
4367 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4368 hr_reg_clear(qpc_mask, QPC_PD);
4370 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4371 hr_reg_clear(qpc_mask, QPC_RX_CQN);
4373 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4374 hr_reg_clear(qpc_mask, QPC_TX_CQN);
4377 hr_reg_enable(context, QPC_SRQ_EN);
4378 hr_reg_clear(qpc_mask, QPC_SRQ_EN);
4379 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4380 hr_reg_clear(qpc_mask, QPC_SRQN);
4384 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev,
4385 struct hns_roce_qp *hr_qp,
4386 struct hns_roce_v2_qp_context *context,
4387 struct hns_roce_v2_qp_context *qpc_mask)
4389 u64 mtts[MTT_MIN_COUNT] = { 0 };
4393 /* Search qp buf's mtts */
4394 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts,
4395 MTT_MIN_COUNT, &wqe_sge_ba);
4396 if (hr_qp->rq.wqe_cnt && count < 1) {
4397 ibdev_err(&hr_dev->ib_dev,
4398 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn);
4402 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3);
4403 qpc_mask->wqe_sge_ba = 0;
4406 * In v2 engine, software pass context and context mask to hardware
4407 * when modifying qp. If software need modify some fields in context,
4408 * we should set all bits of the relevant fields in context mask to
4409 * 0 at the same time, else set them to 0x1.
4411 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3));
4412 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H);
4414 hr_reg_write(context, QPC_SQ_HOP_NUM,
4415 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num,
4416 hr_qp->sq.wqe_cnt));
4417 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM);
4419 hr_reg_write(context, QPC_SGE_HOP_NUM,
4420 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num,
4421 hr_qp->sge.sge_cnt));
4422 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM);
4424 hr_reg_write(context, QPC_RQ_HOP_NUM,
4425 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num,
4426 hr_qp->rq.wqe_cnt));
4428 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM);
4430 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ,
4431 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift));
4432 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ);
4434 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ,
4435 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift));
4436 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ);
4438 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
4439 qpc_mask->rq_cur_blk_addr = 0;
4441 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H,
4442 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
4443 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H);
4445 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
4446 qpc_mask->rq_nxt_blk_addr = 0;
4448 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H,
4449 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
4450 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H);
4455 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev,
4456 struct hns_roce_qp *hr_qp,
4457 struct hns_roce_v2_qp_context *context,
4458 struct hns_roce_v2_qp_context *qpc_mask)
4460 struct ib_device *ibdev = &hr_dev->ib_dev;
4461 u64 sge_cur_blk = 0;
4465 /* search qp buf's mtts */
4466 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL);
4468 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n",
4472 if (hr_qp->sge.sge_cnt > 0) {
4473 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
4475 &sge_cur_blk, 1, NULL);
4477 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n",
4484 * In v2 engine, software pass context and context mask to hardware
4485 * when modifying qp. If software need modify some fields in context,
4486 * we should set all bits of the relevant fields in context mask to
4487 * 0 at the same time, else set them to 0x1.
4489 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L,
4490 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4491 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H,
4492 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4493 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L);
4494 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H);
4496 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L,
4497 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4498 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H,
4499 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4500 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L);
4501 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H);
4503 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L,
4504 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4505 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H,
4506 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4507 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L);
4508 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H);
4513 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp,
4514 const struct ib_qp_attr *attr)
4516 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
4519 return attr->path_mtu;
4522 static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
4523 const struct ib_qp_attr *attr, int attr_mask,
4524 struct hns_roce_v2_qp_context *context,
4525 struct hns_roce_v2_qp_context *qpc_mask)
4527 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4528 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4529 struct ib_device *ibdev = &hr_dev->ib_dev;
4541 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask);
4543 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret);
4547 /* Search IRRL's mtts */
4548 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
4549 hr_qp->qpn, &irrl_ba);
4551 ibdev_err(ibdev, "failed to find qp irrl_table.\n");
4555 /* Search TRRL's mtts */
4556 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
4557 hr_qp->qpn, &trrl_ba);
4559 ibdev_err(ibdev, "failed to find qp trrl_table.\n");
4563 if (attr_mask & IB_QP_ALT_PATH) {
4564 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n",
4569 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4);
4570 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L);
4571 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4));
4572 qpc_mask->trrl_ba = 0;
4573 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4));
4574 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H);
4576 context->irrl_ba = cpu_to_le32(irrl_ba >> 6);
4577 qpc_mask->irrl_ba = 0;
4578 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6));
4579 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H);
4581 hr_reg_enable(context, QPC_RMT_E2E);
4582 hr_reg_clear(qpc_mask, QPC_RMT_E2E);
4584 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits);
4585 hr_reg_clear(qpc_mask, QPC_SIG_TYPE);
4587 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
4589 smac = (const u8 *)hr_dev->dev_addr[port];
4590 dmac = (u8 *)attr->ah_attr.roce.dmac;
4591 /* when dmac equals smac or loop_idc is 1, it should loopback */
4592 if (ether_addr_equal_unaligned(dmac, smac) ||
4593 hr_dev->loop_idc == 0x1) {
4594 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc);
4595 hr_reg_clear(qpc_mask, QPC_LBI);
4598 if (attr_mask & IB_QP_DEST_QPN) {
4599 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num);
4600 hr_reg_clear(qpc_mask, QPC_DQPN);
4603 memcpy(&context->dmac, dmac, sizeof(u32));
4604 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4])));
4606 hr_reg_clear(qpc_mask, QPC_DMAC_H);
4608 ib_mtu = get_mtu(ibqp, attr);
4609 hr_qp->path_mtu = ib_mtu;
4611 mtu = ib_mtu_enum_to_int(ib_mtu);
4612 if (WARN_ON(mtu <= 0))
4614 #define MAX_LP_MSG_LEN 16384
4615 /* MTU * (2 ^ LP_PKTN_INI) shouldn't be bigger than 16KB */
4616 lp_pktn_ini = ilog2(MAX_LP_MSG_LEN / mtu);
4617 if (WARN_ON(lp_pktn_ini >= 0xF))
4620 if (attr_mask & IB_QP_PATH_MTU) {
4621 hr_reg_write(context, QPC_MTU, ib_mtu);
4622 hr_reg_clear(qpc_mask, QPC_MTU);
4625 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini);
4626 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI);
4628 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */
4629 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini);
4630 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ);
4632 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR);
4633 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN);
4634 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE);
4636 context->rq_rnr_timer = 0;
4637 qpc_mask->rq_rnr_timer = 0;
4639 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX);
4640 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX);
4642 /* rocee send 2^lp_sgen_ini segs every time */
4643 hr_reg_write(context, QPC_LP_SGEN_INI, 3);
4644 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI);
4649 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
4650 const struct ib_qp_attr *attr, int attr_mask,
4651 struct hns_roce_v2_qp_context *context,
4652 struct hns_roce_v2_qp_context *qpc_mask)
4654 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4655 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4656 struct ib_device *ibdev = &hr_dev->ib_dev;
4659 /* Not support alternate path and path migration */
4660 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) {
4661 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
4665 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask);
4667 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret);
4672 * Set some fields in context to zero, Because the default values
4673 * of all fields in context are zero, we need not set them to 0 again.
4674 * but we should set the relevant fields of context mask to 0.
4676 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX);
4678 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN);
4680 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE);
4681 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD);
4682 hr_reg_clear(qpc_mask, QPC_IRRL_PSN);
4684 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL);
4686 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN);
4688 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG);
4690 hr_reg_clear(qpc_mask, QPC_CHECK_FLG);
4692 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD);
4697 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4700 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4701 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4702 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx;
4703 u32 *head = &hr_dev->qp_table.idx_table.head;
4704 u32 *tail = &hr_dev->qp_table.idx_table.tail;
4705 struct hns_roce_dip *hr_dip;
4706 unsigned long flags;
4709 spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
4711 spare_idx[*tail] = ibqp->qp_num;
4712 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1);
4714 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) {
4715 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) {
4716 *dip_idx = hr_dip->dip_idx;
4721 /* If no dgid is found, a new dip and a mapping between dgid and
4722 * dip_idx will be created.
4724 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC);
4730 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4731 hr_dip->dip_idx = *dip_idx = spare_idx[*head];
4732 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1);
4733 list_add_tail(&hr_dip->node, &hr_dev->dip_list);
4736 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
4746 UNSUPPORT_CONG_LEVEL,
4765 static int check_cong_type(struct ib_qp *ibqp,
4766 struct hns_roce_congestion_algorithm *cong_alg)
4768 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4770 /* different congestion types match different configurations */
4771 switch (hr_dev->caps.cong_type) {
4772 case CONG_TYPE_DCQCN:
4773 cong_alg->alg_sel = CONG_DCQCN;
4774 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4775 cong_alg->dip_vld = DIP_INVALID;
4776 cong_alg->wnd_mode_sel = WND_LIMIT;
4778 case CONG_TYPE_LDCP:
4779 cong_alg->alg_sel = CONG_WINDOW;
4780 cong_alg->alg_sub_sel = CONG_LDCP;
4781 cong_alg->dip_vld = DIP_INVALID;
4782 cong_alg->wnd_mode_sel = WND_UNLIMIT;
4785 cong_alg->alg_sel = CONG_WINDOW;
4786 cong_alg->alg_sub_sel = CONG_HC3;
4787 cong_alg->dip_vld = DIP_INVALID;
4788 cong_alg->wnd_mode_sel = WND_LIMIT;
4791 cong_alg->alg_sel = CONG_DCQCN;
4792 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4793 cong_alg->dip_vld = DIP_VALID;
4794 cong_alg->wnd_mode_sel = WND_LIMIT;
4797 ibdev_err(&hr_dev->ib_dev,
4798 "error type(%u) for congestion selection.\n",
4799 hr_dev->caps.cong_type);
4806 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4807 struct hns_roce_v2_qp_context *context,
4808 struct hns_roce_v2_qp_context *qpc_mask)
4810 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4811 struct hns_roce_congestion_algorithm cong_field;
4812 struct ib_device *ibdev = ibqp->device;
4813 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
4817 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ||
4818 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE)
4821 ret = check_cong_type(ibqp, &cong_field);
4825 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id +
4826 hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE);
4827 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID);
4828 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel);
4829 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL);
4830 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL,
4831 cong_field.alg_sub_sel);
4832 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL);
4833 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld);
4834 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD);
4835 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN,
4836 cong_field.wnd_mode_sel);
4837 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN);
4839 /* if dip is disabled, there is no need to set dip idx */
4840 if (cong_field.dip_vld == 0)
4843 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx);
4845 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret);
4849 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx);
4850 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0);
4855 static int hns_roce_v2_set_path(struct ib_qp *ibqp,
4856 const struct ib_qp_attr *attr,
4858 struct hns_roce_v2_qp_context *context,
4859 struct hns_roce_v2_qp_context *qpc_mask)
4861 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4862 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4863 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4864 struct ib_device *ibdev = &hr_dev->ib_dev;
4865 const struct ib_gid_attr *gid_attr = NULL;
4866 int is_roce_protocol;
4867 u16 vlan_id = 0xffff;
4868 bool is_udp = false;
4874 * If free_mr_en of qp is set, it means that this qp comes from
4875 * free mr. This qp will perform the loopback operation.
4876 * In the loopback scenario, only sl needs to be set.
4878 if (hr_qp->free_mr_en) {
4879 hr_reg_write(context, QPC_SL, rdma_ah_get_sl(&attr->ah_attr));
4880 hr_reg_clear(qpc_mask, QPC_SL);
4881 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
4885 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
4886 hr_port = ib_port - 1;
4887 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
4888 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
4890 if (is_roce_protocol) {
4891 gid_attr = attr->ah_attr.grh.sgid_attr;
4892 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL);
4896 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP);
4899 /* Only HIP08 needs to set the vlan_en bits in QPC */
4900 if (vlan_id < VLAN_N_VID &&
4901 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
4902 hr_reg_enable(context, QPC_RQ_VLAN_EN);
4903 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN);
4904 hr_reg_enable(context, QPC_SQ_VLAN_EN);
4905 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN);
4908 hr_reg_write(context, QPC_VLAN_ID, vlan_id);
4909 hr_reg_clear(qpc_mask, QPC_VLAN_ID);
4911 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
4912 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n",
4913 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]);
4917 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
4918 ibdev_err(ibdev, "ah attr is not RDMA roce type\n");
4922 hr_reg_write(context, QPC_UDPSPN,
4923 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num,
4924 attr->dest_qp_num) :
4927 hr_reg_clear(qpc_mask, QPC_UDPSPN);
4929 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index);
4931 hr_reg_clear(qpc_mask, QPC_GMV_IDX);
4933 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit);
4934 hr_reg_clear(qpc_mask, QPC_HOPLIMIT);
4936 ret = fill_cong_field(ibqp, attr, context, qpc_mask);
4940 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh));
4941 hr_reg_clear(qpc_mask, QPC_TC);
4943 hr_reg_write(context, QPC_FL, grh->flow_label);
4944 hr_reg_clear(qpc_mask, QPC_FL);
4945 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4946 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
4948 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
4949 if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) {
4951 "failed to fill QPC, sl (%u) shouldn't be larger than %d.\n",
4952 hr_qp->sl, MAX_SERVICE_LEVEL);
4956 hr_reg_write(context, QPC_SL, hr_qp->sl);
4957 hr_reg_clear(qpc_mask, QPC_SL);
4962 static bool check_qp_state(enum ib_qp_state cur_state,
4963 enum ib_qp_state new_state)
4965 static const bool sm[][IB_QPS_ERR + 1] = {
4966 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
4967 [IB_QPS_INIT] = true },
4968 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
4969 [IB_QPS_INIT] = true,
4970 [IB_QPS_RTR] = true,
4971 [IB_QPS_ERR] = true },
4972 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
4973 [IB_QPS_RTS] = true,
4974 [IB_QPS_ERR] = true },
4975 [IB_QPS_RTS] = { [IB_QPS_RESET] = true,
4976 [IB_QPS_RTS] = true,
4977 [IB_QPS_ERR] = true },
4980 [IB_QPS_ERR] = { [IB_QPS_RESET] = true,
4981 [IB_QPS_ERR] = true }
4984 return sm[cur_state][new_state];
4987 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
4988 const struct ib_qp_attr *attr,
4990 enum ib_qp_state cur_state,
4991 enum ib_qp_state new_state,
4992 struct hns_roce_v2_qp_context *context,
4993 struct hns_roce_v2_qp_context *qpc_mask)
4995 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4998 if (!check_qp_state(cur_state, new_state)) {
4999 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n");
5003 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
5004 memset(qpc_mask, 0, hr_dev->caps.qpc_sz);
5005 modify_qp_reset_to_init(ibqp, attr, context, qpc_mask);
5006 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
5007 modify_qp_init_to_init(ibqp, attr, context, qpc_mask);
5008 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
5009 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
5011 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
5012 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
5019 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout)
5021 #define QP_ACK_TIMEOUT_MAX_HIP08 20
5022 #define QP_ACK_TIMEOUT_OFFSET 10
5023 #define QP_ACK_TIMEOUT_MAX 31
5025 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5026 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) {
5027 ibdev_warn(&hr_dev->ib_dev,
5028 "local ACK timeout shall be 0 to 20.\n");
5031 *timeout += QP_ACK_TIMEOUT_OFFSET;
5032 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) {
5033 if (*timeout > QP_ACK_TIMEOUT_MAX) {
5034 ibdev_warn(&hr_dev->ib_dev,
5035 "local ACK timeout shall be 0 to 31.\n");
5043 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp,
5044 const struct ib_qp_attr *attr,
5046 struct hns_roce_v2_qp_context *context,
5047 struct hns_roce_v2_qp_context *qpc_mask)
5049 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5050 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5054 if (attr_mask & IB_QP_AV) {
5055 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context,
5061 if (attr_mask & IB_QP_TIMEOUT) {
5062 timeout = attr->timeout;
5063 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) {
5064 hr_reg_write(context, QPC_AT, timeout);
5065 hr_reg_clear(qpc_mask, QPC_AT);
5069 if (attr_mask & IB_QP_RETRY_CNT) {
5070 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt);
5071 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT);
5073 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt);
5074 hr_reg_clear(qpc_mask, QPC_RETRY_CNT);
5077 if (attr_mask & IB_QP_RNR_RETRY) {
5078 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry);
5079 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT);
5081 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry);
5082 hr_reg_clear(qpc_mask, QPC_RNR_CNT);
5085 if (attr_mask & IB_QP_SQ_PSN) {
5086 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn);
5087 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN);
5089 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn);
5090 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN);
5092 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn);
5093 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L);
5095 hr_reg_write(context, QPC_RETRY_MSG_PSN_H,
5096 attr->sq_psn >> RETRY_MSG_PSN_SHIFT);
5097 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H);
5099 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn);
5100 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN);
5102 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn);
5103 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN);
5106 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
5107 attr->max_dest_rd_atomic) {
5108 hr_reg_write(context, QPC_RR_MAX,
5109 fls(attr->max_dest_rd_atomic - 1));
5110 hr_reg_clear(qpc_mask, QPC_RR_MAX);
5113 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
5114 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1));
5115 hr_reg_clear(qpc_mask, QPC_SR_MAX);
5118 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
5119 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
5121 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
5122 hr_reg_write(context, QPC_MIN_RNR_TIME,
5123 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ?
5124 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer);
5125 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME);
5128 if (attr_mask & IB_QP_RQ_PSN) {
5129 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn);
5130 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN);
5132 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1);
5133 hr_reg_clear(qpc_mask, QPC_RAQ_PSN);
5136 if (attr_mask & IB_QP_QKEY) {
5137 context->qkey_xrcd = cpu_to_le32(attr->qkey);
5138 qpc_mask->qkey_xrcd = 0;
5139 hr_qp->qkey = attr->qkey;
5145 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp,
5146 const struct ib_qp_attr *attr,
5149 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5150 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5152 if (attr_mask & IB_QP_ACCESS_FLAGS)
5153 hr_qp->atomic_rd_en = attr->qp_access_flags;
5155 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
5156 hr_qp->resp_depth = attr->max_dest_rd_atomic;
5157 if (attr_mask & IB_QP_PORT) {
5158 hr_qp->port = attr->port_num - 1;
5159 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
5163 static void clear_qp(struct hns_roce_qp *hr_qp)
5165 struct ib_qp *ibqp = &hr_qp->ibqp;
5168 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
5171 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq)
5172 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq),
5173 hr_qp->qpn, ibqp->srq ?
5174 to_hr_srq(ibqp->srq) : NULL);
5176 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
5177 *hr_qp->rdb.db_record = 0;
5183 hr_qp->next_sge = 0;
5186 static void v2_set_flushed_fields(struct ib_qp *ibqp,
5187 struct hns_roce_v2_qp_context *context,
5188 struct hns_roce_v2_qp_context *qpc_mask)
5190 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5191 unsigned long sq_flag = 0;
5192 unsigned long rq_flag = 0;
5194 if (ibqp->qp_type == IB_QPT_XRC_TGT)
5197 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag);
5198 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head);
5199 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX);
5200 hr_qp->state = IB_QPS_ERR;
5201 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag);
5203 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */
5206 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag);
5207 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head);
5208 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX);
5209 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag);
5212 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
5213 const struct ib_qp_attr *attr,
5214 int attr_mask, enum ib_qp_state cur_state,
5215 enum ib_qp_state new_state)
5217 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5218 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5219 struct hns_roce_v2_qp_context ctx[2];
5220 struct hns_roce_v2_qp_context *context = ctx;
5221 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1;
5222 struct ib_device *ibdev = &hr_dev->ib_dev;
5225 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
5229 * In v2 engine, software pass context and context mask to hardware
5230 * when modifying qp. If software need modify some fields in context,
5231 * we should set all bits of the relevant fields in context mask to
5232 * 0 at the same time, else set them to 0x1.
5234 memset(context, 0, hr_dev->caps.qpc_sz);
5235 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz);
5237 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
5238 new_state, context, qpc_mask);
5242 /* When QP state is err, SQ and RQ WQE should be flushed */
5243 if (new_state == IB_QPS_ERR)
5244 v2_set_flushed_fields(ibqp, context, qpc_mask);
5246 /* Configure the optional fields */
5247 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context,
5252 hr_reg_write_bool(context, QPC_INV_CREDIT,
5253 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC ||
5255 hr_reg_clear(qpc_mask, QPC_INV_CREDIT);
5257 /* Every status migrate must change state */
5258 hr_reg_write(context, QPC_QP_ST, new_state);
5259 hr_reg_clear(qpc_mask, QPC_QP_ST);
5261 /* SW pass context to HW */
5262 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp);
5264 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret);
5268 hr_qp->state = new_state;
5270 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask);
5272 if (new_state == IB_QPS_RESET && !ibqp->uobject)
5279 static int to_ib_qp_st(enum hns_roce_v2_qp_state state)
5281 static const enum ib_qp_state map[] = {
5282 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET,
5283 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT,
5284 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR,
5285 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS,
5286 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD,
5287 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE,
5288 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR,
5289 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD
5292 return (state < ARRAY_SIZE(map)) ? map[state] : -1;
5295 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn,
5298 struct hns_roce_cmd_mailbox *mailbox;
5301 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5302 if (IS_ERR(mailbox))
5303 return PTR_ERR(mailbox);
5305 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC,
5310 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz);
5313 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5317 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5319 struct ib_qp_init_attr *qp_init_attr)
5321 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5322 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5323 struct hns_roce_v2_qp_context context = {};
5324 struct ib_device *ibdev = &hr_dev->ib_dev;
5329 memset(qp_attr, 0, sizeof(*qp_attr));
5330 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5332 mutex_lock(&hr_qp->mutex);
5334 if (hr_qp->state == IB_QPS_RESET) {
5335 qp_attr->qp_state = IB_QPS_RESET;
5340 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context);
5342 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret);
5347 state = hr_reg_read(&context, QPC_QP_ST);
5348 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
5349 if (tmp_qp_state == -1) {
5350 ibdev_err(ibdev, "Illegal ib_qp_state\n");
5354 hr_qp->state = (u8)tmp_qp_state;
5355 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
5356 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU);
5357 qp_attr->path_mig_state = IB_MIG_ARMED;
5358 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
5359 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
5360 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd);
5362 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN);
5363 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN);
5364 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN);
5365 qp_attr->qp_access_flags =
5366 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) |
5367 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) |
5368 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S);
5370 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
5371 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5372 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) {
5373 struct ib_global_route *grh =
5374 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
5376 rdma_ah_set_sl(&qp_attr->ah_attr,
5377 hr_reg_read(&context, QPC_SL));
5378 grh->flow_label = hr_reg_read(&context, QPC_FL);
5379 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX);
5380 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT);
5381 grh->traffic_class = hr_reg_read(&context, QPC_TC);
5383 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw));
5386 qp_attr->port_num = hr_qp->port + 1;
5387 qp_attr->sq_draining = 0;
5388 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX);
5389 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX);
5391 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME);
5392 qp_attr->timeout = (u8)hr_reg_read(&context, QPC_AT);
5393 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT);
5394 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT);
5397 qp_attr->cur_qp_state = qp_attr->qp_state;
5398 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
5399 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
5400 qp_attr->cap.max_inline_data = hr_qp->max_inline_data;
5402 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
5403 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
5405 qp_init_attr->qp_context = ibqp->qp_context;
5406 qp_init_attr->qp_type = ibqp->qp_type;
5407 qp_init_attr->recv_cq = ibqp->recv_cq;
5408 qp_init_attr->send_cq = ibqp->send_cq;
5409 qp_init_attr->srq = ibqp->srq;
5410 qp_init_attr->cap = qp_attr->cap;
5411 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits;
5414 mutex_unlock(&hr_qp->mutex);
5418 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp)
5420 return ((hr_qp->ibqp.qp_type == IB_QPT_RC ||
5421 hr_qp->ibqp.qp_type == IB_QPT_UD ||
5422 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5423 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
5424 hr_qp->state != IB_QPS_RESET);
5427 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
5428 struct hns_roce_qp *hr_qp,
5429 struct ib_udata *udata)
5431 struct ib_device *ibdev = &hr_dev->ib_dev;
5432 struct hns_roce_cq *send_cq, *recv_cq;
5433 unsigned long flags;
5436 if (modify_qp_is_ok(hr_qp)) {
5437 /* Modify qp to reset before destroying qp */
5438 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
5439 hr_qp->state, IB_QPS_RESET);
5442 "failed to modify QP to RST, ret = %d.\n",
5446 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
5447 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
5449 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
5450 hns_roce_lock_cqs(send_cq, recv_cq);
5454 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn,
5456 to_hr_srq(hr_qp->ibqp.srq) :
5459 if (send_cq && send_cq != recv_cq)
5460 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
5463 hns_roce_qp_remove(hr_dev, hr_qp);
5465 hns_roce_unlock_cqs(send_cq, recv_cq);
5466 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
5471 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
5473 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5474 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5477 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
5479 ibdev_err(&hr_dev->ib_dev,
5480 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n",
5483 hns_roce_qp_destroy(hr_dev, hr_qp, udata);
5488 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
5489 struct hns_roce_qp *hr_qp)
5491 struct ib_device *ibdev = &hr_dev->ib_dev;
5492 struct hns_roce_sccc_clr_done *resp;
5493 struct hns_roce_sccc_clr *clr;
5494 struct hns_roce_cmq_desc desc;
5497 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
5500 mutex_lock(&hr_dev->qp_table.scc_mutex);
5502 /* set scc ctx clear done flag */
5503 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
5504 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5506 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret);
5510 /* clear scc context */
5511 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
5512 clr = (struct hns_roce_sccc_clr *)desc.data;
5513 clr->qpn = cpu_to_le32(hr_qp->qpn);
5514 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5516 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret);
5520 /* query scc context clear is done or not */
5521 resp = (struct hns_roce_sccc_clr_done *)desc.data;
5522 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
5523 hns_roce_cmq_setup_basic_desc(&desc,
5524 HNS_ROCE_OPC_QUERY_SCCC, true);
5525 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5527 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
5538 ibdev_err(ibdev, "query SCC clr done flag overtime.\n");
5542 mutex_unlock(&hr_dev->qp_table.scc_mutex);
5546 #define DMA_IDX_SHIFT 3
5547 #define DMA_WQE_SHIFT 3
5549 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq,
5550 struct hns_roce_srq_context *ctx)
5552 struct hns_roce_idx_que *idx_que = &srq->idx_que;
5553 struct ib_device *ibdev = srq->ibsrq.device;
5554 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5555 u64 mtts_idx[MTT_MIN_COUNT] = {};
5556 dma_addr_t dma_handle_idx = 0;
5559 /* Get physical address of idx que buf */
5560 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx,
5561 ARRAY_SIZE(mtts_idx), &dma_handle_idx);
5563 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n",
5568 hr_reg_write(ctx, SRQC_IDX_HOP_NUM,
5569 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt));
5571 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT);
5572 hr_reg_write(ctx, SRQC_IDX_BT_BA_H,
5573 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT));
5575 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ,
5576 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift));
5577 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ,
5578 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift));
5580 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L,
5581 to_hr_hw_page_addr(mtts_idx[0]));
5582 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H,
5583 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0])));
5585 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L,
5586 to_hr_hw_page_addr(mtts_idx[1]));
5587 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H,
5588 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
5593 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf)
5595 struct ib_device *ibdev = srq->ibsrq.device;
5596 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5597 struct hns_roce_srq_context *ctx = mb_buf;
5598 u64 mtts_wqe[MTT_MIN_COUNT] = {};
5599 dma_addr_t dma_handle_wqe = 0;
5602 memset(ctx, 0, sizeof(*ctx));
5604 /* Get the physical address of srq buf */
5605 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe,
5606 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe);
5608 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n",
5613 hr_reg_write(ctx, SRQC_SRQ_ST, 1);
5614 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE,
5615 srq->ibsrq.srq_type == IB_SRQT_XRC);
5616 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn);
5617 hr_reg_write(ctx, SRQC_SRQN, srq->srqn);
5618 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn);
5619 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn);
5620 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt));
5621 hr_reg_write(ctx, SRQC_RQWS,
5622 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1));
5624 hr_reg_write(ctx, SRQC_WQE_HOP_NUM,
5625 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num,
5628 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT);
5629 hr_reg_write(ctx, SRQC_WQE_BT_BA_H,
5630 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT));
5632 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ,
5633 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift));
5634 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ,
5635 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift));
5637 return hns_roce_v2_write_srqc_index_queue(srq, ctx);
5640 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5641 struct ib_srq_attr *srq_attr,
5642 enum ib_srq_attr_mask srq_attr_mask,
5643 struct ib_udata *udata)
5645 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5646 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5647 struct hns_roce_srq_context *srq_context;
5648 struct hns_roce_srq_context *srqc_mask;
5649 struct hns_roce_cmd_mailbox *mailbox;
5652 /* Resizing SRQs is not supported yet */
5653 if (srq_attr_mask & IB_SRQ_MAX_WR)
5656 if (srq_attr_mask & IB_SRQ_LIMIT) {
5657 if (srq_attr->srq_limit > srq->wqe_cnt)
5660 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5661 if (IS_ERR(mailbox))
5662 return PTR_ERR(mailbox);
5664 srq_context = mailbox->buf;
5665 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5667 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5669 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit);
5670 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL);
5672 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5673 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn);
5674 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5676 ibdev_err(&hr_dev->ib_dev,
5677 "failed to handle cmd of modifying SRQ, ret = %d.\n",
5686 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
5688 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5689 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5690 struct hns_roce_srq_context *srq_context;
5691 struct hns_roce_cmd_mailbox *mailbox;
5694 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5695 if (IS_ERR(mailbox))
5696 return PTR_ERR(mailbox);
5698 srq_context = mailbox->buf;
5699 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5700 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn);
5702 ibdev_err(&hr_dev->ib_dev,
5703 "failed to process cmd of querying SRQ, ret = %d.\n",
5708 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL);
5709 attr->max_wr = srq->wqe_cnt;
5710 attr->max_sge = srq->max_gs - srq->rsv_sge;
5713 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5717 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
5719 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
5720 struct hns_roce_v2_cq_context *cq_context;
5721 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
5722 struct hns_roce_v2_cq_context *cqc_mask;
5723 struct hns_roce_cmd_mailbox *mailbox;
5726 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5727 if (IS_ERR(mailbox))
5728 return PTR_ERR(mailbox);
5730 cq_context = mailbox->buf;
5731 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
5733 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
5735 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count);
5736 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT);
5738 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5739 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
5740 dev_info(hr_dev->dev,
5741 "cq_period(%u) reached the upper limit, adjusted to 65.\n",
5743 cq_period = HNS_ROCE_MAX_CQ_PERIOD;
5745 cq_period *= HNS_ROCE_CLOCK_ADJUST;
5747 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period);
5748 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD);
5750 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5751 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn);
5752 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5754 ibdev_err(&hr_dev->ib_dev,
5755 "failed to process cmd when modifying CQ, ret = %d.\n",
5761 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn,
5764 struct hns_roce_v2_cq_context *context;
5765 struct hns_roce_cmd_mailbox *mailbox;
5768 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5769 if (IS_ERR(mailbox))
5770 return PTR_ERR(mailbox);
5772 context = mailbox->buf;
5773 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5774 HNS_ROCE_CMD_QUERY_CQC, cqn);
5776 ibdev_err(&hr_dev->ib_dev,
5777 "failed to process cmd when querying CQ, ret = %d.\n",
5782 memcpy(buffer, context, sizeof(*context));
5785 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5790 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key,
5793 struct hns_roce_v2_mpt_entry *context;
5794 struct hns_roce_cmd_mailbox *mailbox;
5797 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5798 if (IS_ERR(mailbox))
5799 return PTR_ERR(mailbox);
5801 context = mailbox->buf;
5802 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT,
5803 key_to_hw_index(key));
5805 ibdev_err(&hr_dev->ib_dev,
5806 "failed to process cmd when querying MPT, ret = %d.\n",
5811 memcpy(buffer, context, sizeof(*context));
5814 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5819 static void hns_roce_irq_work_handle(struct work_struct *work)
5821 struct hns_roce_work *irq_work =
5822 container_of(work, struct hns_roce_work, work);
5823 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev;
5825 switch (irq_work->event_type) {
5826 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5827 ibdev_info(ibdev, "path migrated succeeded.\n");
5829 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5830 ibdev_warn(ibdev, "path migration failed.\n");
5832 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5834 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5835 ibdev_warn(ibdev, "send queue drained.\n");
5837 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5838 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n",
5839 irq_work->queue_num, irq_work->sub_type);
5841 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5842 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n",
5843 irq_work->queue_num);
5845 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5846 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n",
5847 irq_work->queue_num, irq_work->sub_type);
5849 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5850 ibdev_warn(ibdev, "SRQ limit reach.\n");
5852 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5853 ibdev_warn(ibdev, "SRQ last wqe reach.\n");
5855 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5856 ibdev_err(ibdev, "SRQ catas error.\n");
5858 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5859 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num);
5861 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5862 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num);
5864 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5865 ibdev_warn(ibdev, "DB overflow.\n");
5867 case HNS_ROCE_EVENT_TYPE_FLR:
5868 ibdev_warn(ibdev, "function level reset.\n");
5870 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5871 ibdev_err(ibdev, "xrc domain violation error.\n");
5873 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5874 ibdev_err(ibdev, "invalid xrceth error.\n");
5883 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
5884 struct hns_roce_eq *eq, u32 queue_num)
5886 struct hns_roce_work *irq_work;
5888 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
5892 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle);
5893 irq_work->hr_dev = hr_dev;
5894 irq_work->event_type = eq->event_type;
5895 irq_work->sub_type = eq->sub_type;
5896 irq_work->queue_num = queue_num;
5897 queue_work(hr_dev->irq_workq, &irq_work->work);
5900 static void update_eq_db(struct hns_roce_eq *eq)
5902 struct hns_roce_dev *hr_dev = eq->hr_dev;
5903 struct hns_roce_v2_db eq_db = {};
5905 if (eq->type_flag == HNS_ROCE_AEQ) {
5906 hr_reg_write(&eq_db, EQ_DB_CMD,
5907 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5908 HNS_ROCE_EQ_DB_CMD_AEQ :
5909 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
5911 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn);
5913 hr_reg_write(&eq_db, EQ_DB_CMD,
5914 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5915 HNS_ROCE_EQ_DB_CMD_CEQ :
5916 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
5919 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index);
5921 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg);
5924 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
5926 struct hns_roce_aeqe *aeqe;
5928 aeqe = hns_roce_buf_offset(eq->mtr.kmem,
5929 (eq->cons_index & (eq->entries - 1)) *
5932 return (hr_reg_read(aeqe, AEQE_OWNER) ^
5933 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
5936 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
5937 struct hns_roce_eq *eq)
5939 struct device *dev = hr_dev->dev;
5940 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);
5941 irqreturn_t aeqe_found = IRQ_NONE;
5947 /* Make sure we read AEQ entry after we have checked the
5952 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE);
5953 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE);
5954 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM);
5956 switch (event_type) {
5957 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5958 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5959 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5960 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5961 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5962 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5963 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5964 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5965 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5966 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5967 hns_roce_qp_event(hr_dev, queue_num, event_type);
5969 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5970 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5971 hns_roce_srq_event(hr_dev, queue_num, event_type);
5973 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5974 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5975 hns_roce_cq_event(hr_dev, queue_num, event_type);
5977 case HNS_ROCE_EVENT_TYPE_MB:
5978 hns_roce_cmd_event(hr_dev,
5979 le16_to_cpu(aeqe->event.cmd.token),
5980 aeqe->event.cmd.status,
5981 le64_to_cpu(aeqe->event.cmd.out_param));
5983 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5984 case HNS_ROCE_EVENT_TYPE_FLR:
5987 dev_err(dev, "unhandled event %d on EQ %d at idx %u.\n",
5988 event_type, eq->eqn, eq->cons_index);
5992 eq->event_type = event_type;
5993 eq->sub_type = sub_type;
5995 aeqe_found = IRQ_HANDLED;
5997 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num);
5999 aeqe = next_aeqe_sw_v2(eq);
6004 return IRQ_RETVAL(aeqe_found);
6007 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
6009 struct hns_roce_ceqe *ceqe;
6011 ceqe = hns_roce_buf_offset(eq->mtr.kmem,
6012 (eq->cons_index & (eq->entries - 1)) *
6015 return (hr_reg_read(ceqe, CEQE_OWNER) ^
6016 !!(eq->cons_index & eq->entries)) ? ceqe : NULL;
6019 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
6020 struct hns_roce_eq *eq)
6022 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
6023 irqreturn_t ceqe_found = IRQ_NONE;
6027 /* Make sure we read CEQ entry after we have checked the
6032 cqn = hr_reg_read(ceqe, CEQE_CQN);
6034 hns_roce_cq_completion(hr_dev, cqn);
6037 ceqe_found = IRQ_HANDLED;
6039 ceqe = next_ceqe_sw_v2(eq);
6044 return IRQ_RETVAL(ceqe_found);
6047 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
6049 struct hns_roce_eq *eq = eq_ptr;
6050 struct hns_roce_dev *hr_dev = eq->hr_dev;
6051 irqreturn_t int_work;
6053 if (eq->type_flag == HNS_ROCE_CEQ)
6054 /* Completion event interrupt */
6055 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
6057 /* Asynchronous event interrupt */
6058 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
6060 return IRQ_RETVAL(int_work);
6063 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev,
6066 struct pci_dev *pdev = hr_dev->pci_dev;
6067 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
6068 const struct hnae3_ae_ops *ops = ae_dev->ops;
6069 irqreturn_t int_work = IRQ_NONE;
6072 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
6074 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
6075 dev_err(hr_dev->dev, "AEQ overflow!\n");
6077 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG,
6078 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S);
6080 /* Set reset level for reset_event() */
6081 if (ops->set_default_reset_request)
6082 ops->set_default_reset_request(ae_dev,
6084 if (ops->reset_event)
6085 ops->reset_event(pdev, NULL);
6087 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
6088 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
6090 int_work = IRQ_HANDLED;
6092 dev_err(hr_dev->dev, "there is no basic abn irq found.\n");
6095 return IRQ_RETVAL(int_work);
6098 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev,
6099 struct fmea_ram_ecc *ecc_info)
6101 struct hns_roce_cmq_desc desc;
6102 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6105 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true);
6106 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6110 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR);
6111 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE);
6112 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG);
6117 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx)
6119 struct hns_roce_cmq_desc desc;
6120 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6125 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true);
6126 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6128 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6130 dev_err(hr_dev->dev,
6131 "failed to execute cmd to read gmv, ret = %d.\n", ret);
6135 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L);
6136 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H);
6138 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
6139 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low);
6140 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper);
6141 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6143 return hns_roce_cmq_send(hr_dev, &desc, 1);
6146 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data)
6148 if (res_type == ECC_RESOURCE_QPC_TIMER ||
6149 res_type == ECC_RESOURCE_CQC_TIMER ||
6150 res_type == ECC_RESOURCE_SCCC)
6151 return le64_to_cpu(*data);
6153 return le64_to_cpu(*data) << PAGE_SHIFT;
6156 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type,
6159 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op;
6160 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op;
6161 struct hns_roce_cmd_mailbox *mailbox;
6165 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6166 if (IS_ERR(mailbox))
6167 return PTR_ERR(mailbox);
6169 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index);
6171 dev_err(hr_dev->dev,
6172 "failed to execute cmd to read fmea ram, ret = %d.\n",
6177 addr = fmea_get_ram_res_addr(res_type, mailbox->buf);
6179 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index);
6181 dev_err(hr_dev->dev,
6182 "failed to execute cmd to write fmea ram, ret = %d.\n",
6186 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6190 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev,
6191 struct fmea_ram_ecc *ecc_info)
6193 u32 res_type = ecc_info->res_type;
6194 u32 index = ecc_info->index;
6197 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT);
6199 if (res_type >= ECC_RESOURCE_COUNT) {
6200 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n",
6205 if (res_type == ECC_RESOURCE_GMV)
6206 ret = fmea_recover_gmv(hr_dev, index);
6208 ret = fmea_recover_others(hr_dev, res_type, index);
6210 dev_err(hr_dev->dev,
6211 "failed to recover %s, index = %u, ret = %d.\n",
6212 fmea_ram_res[res_type].name, index, ret);
6215 static void fmea_ram_ecc_work(struct work_struct *ecc_work)
6217 struct hns_roce_dev *hr_dev =
6218 container_of(ecc_work, struct hns_roce_dev, ecc_work);
6219 struct fmea_ram_ecc ecc_info = {};
6221 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) {
6222 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n");
6226 if (!ecc_info.is_ecc_err) {
6227 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n");
6231 fmea_ram_ecc_recover(hr_dev, &ecc_info);
6234 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
6236 struct hns_roce_dev *hr_dev = dev_id;
6237 irqreturn_t int_work = IRQ_NONE;
6240 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
6243 int_work = abnormal_interrupt_basic(hr_dev, int_st);
6244 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
6245 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work);
6246 int_work = IRQ_HANDLED;
6248 dev_err(hr_dev->dev, "there is no abnormal irq found.\n");
6251 return IRQ_RETVAL(int_work);
6254 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
6255 int eq_num, u32 enable_flag)
6259 for (i = 0; i < eq_num; i++)
6260 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
6261 i * EQ_REG_OFFSET, enable_flag);
6263 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag);
6264 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag);
6267 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn)
6269 struct device *dev = hr_dev->dev;
6273 if (eqn < hr_dev->caps.num_comp_vectors)
6274 cmd = HNS_ROCE_CMD_DESTROY_CEQC;
6276 cmd = HNS_ROCE_CMD_DESTROY_AEQC;
6278 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M);
6280 dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn);
6283 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6285 hns_roce_mtr_destroy(hr_dev, &eq->mtr);
6288 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6290 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
6292 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
6293 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
6294 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
6295 eq->shift = ilog2((unsigned int)eq->entries);
6298 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
6301 u64 eqe_ba[MTT_MIN_COUNT] = { 0 };
6302 struct hns_roce_eq_context *eqc;
6307 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
6309 init_eq_config(hr_dev, eq);
6311 /* if not multi-hop, eqe buffer only use one trunk */
6312 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT,
6315 dev_err(hr_dev->dev, "failed to find EQE mtr\n");
6319 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID);
6320 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num);
6321 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore);
6322 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce);
6323 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st);
6324 hr_reg_write(eqc, EQC_EQN, eq->eqn);
6325 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT);
6326 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ,
6327 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
6328 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ,
6329 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
6330 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX);
6331 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt);
6333 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6334 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
6335 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n",
6337 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD;
6339 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST;
6342 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period);
6343 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER);
6344 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3);
6345 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35);
6346 hr_reg_write(eqc, EQC_SHIFT, eq->shift);
6347 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX);
6348 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12);
6349 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28);
6350 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60);
6351 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX);
6352 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12);
6353 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44);
6354 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE);
6359 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6361 struct hns_roce_buf_attr buf_attr = {};
6364 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0)
6367 eq->hop_num = hr_dev->caps.eqe_hop_num;
6369 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT;
6370 buf_attr.region[0].size = eq->entries * eq->eqe_size;
6371 buf_attr.region[0].hopnum = eq->hop_num;
6372 buf_attr.region_count = 1;
6374 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr,
6375 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL,
6378 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err);
6383 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
6384 struct hns_roce_eq *eq, u8 eq_cmd)
6386 struct hns_roce_cmd_mailbox *mailbox;
6389 /* Allocate mailbox memory */
6390 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6391 if (IS_ERR(mailbox))
6392 return PTR_ERR(mailbox);
6394 ret = alloc_eq_buf(hr_dev, eq);
6398 ret = config_eqc(hr_dev, eq, mailbox->buf);
6402 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn);
6404 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
6408 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6413 free_eq_buf(hr_dev, eq);
6416 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6421 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
6422 int comp_num, int aeq_num, int other_num)
6424 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6428 for (i = 0; i < irq_num; i++) {
6429 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
6431 if (!hr_dev->irq_names[i]) {
6433 goto err_kzalloc_failed;
6437 /* irq contains: abnormal + AEQ + CEQ */
6438 for (j = 0; j < other_num; j++)
6439 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6442 for (j = other_num; j < (other_num + aeq_num); j++)
6443 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6444 "hns-aeq-%d", j - other_num);
6446 for (j = (other_num + aeq_num); j < irq_num; j++)
6447 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6448 "hns-ceq-%d", j - other_num - aeq_num);
6450 for (j = 0; j < irq_num; j++) {
6452 ret = request_irq(hr_dev->irq[j],
6453 hns_roce_v2_msix_interrupt_abn,
6454 0, hr_dev->irq_names[j], hr_dev);
6456 else if (j < (other_num + comp_num))
6457 ret = request_irq(eq_table->eq[j - other_num].irq,
6458 hns_roce_v2_msix_interrupt_eq,
6459 0, hr_dev->irq_names[j + aeq_num],
6460 &eq_table->eq[j - other_num]);
6462 ret = request_irq(eq_table->eq[j - other_num].irq,
6463 hns_roce_v2_msix_interrupt_eq,
6464 0, hr_dev->irq_names[j - comp_num],
6465 &eq_table->eq[j - other_num]);
6467 dev_err(hr_dev->dev, "request irq error!\n");
6468 goto err_request_failed;
6475 for (j -= 1; j >= 0; j--)
6477 free_irq(hr_dev->irq[j], hr_dev);
6479 free_irq(eq_table->eq[j - other_num].irq,
6480 &eq_table->eq[j - other_num]);
6483 for (i -= 1; i >= 0; i--)
6484 kfree(hr_dev->irq_names[i]);
6489 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev)
6495 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6496 irq_num = eq_num + hr_dev->caps.num_other_vectors;
6498 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
6499 free_irq(hr_dev->irq[i], hr_dev);
6501 for (i = 0; i < eq_num; i++)
6502 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
6504 for (i = 0; i < irq_num; i++)
6505 kfree(hr_dev->irq_names[i]);
6508 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
6510 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6511 struct device *dev = hr_dev->dev;
6512 struct hns_roce_eq *eq;
6522 other_num = hr_dev->caps.num_other_vectors;
6523 comp_num = hr_dev->caps.num_comp_vectors;
6524 aeq_num = hr_dev->caps.num_aeq_vectors;
6526 eq_num = comp_num + aeq_num;
6527 irq_num = eq_num + other_num;
6529 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
6534 for (i = 0; i < eq_num; i++) {
6535 eq = &eq_table->eq[i];
6536 eq->hr_dev = hr_dev;
6540 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
6541 eq->type_flag = HNS_ROCE_CEQ;
6542 eq->entries = hr_dev->caps.ceqe_depth;
6543 eq->eqe_size = hr_dev->caps.ceqe_size;
6544 eq->irq = hr_dev->irq[i + other_num + aeq_num];
6545 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
6546 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
6549 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
6550 eq->type_flag = HNS_ROCE_AEQ;
6551 eq->entries = hr_dev->caps.aeqe_depth;
6552 eq->eqe_size = hr_dev->caps.aeqe_size;
6553 eq->irq = hr_dev->irq[i - comp_num + other_num];
6554 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
6555 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
6558 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
6560 dev_err(dev, "failed to create eq.\n");
6561 goto err_create_eq_fail;
6565 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work);
6567 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0);
6568 if (!hr_dev->irq_workq) {
6569 dev_err(dev, "failed to create irq workqueue.\n");
6571 goto err_create_eq_fail;
6574 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num,
6577 dev_err(dev, "failed to request irq.\n");
6578 goto err_request_irq_fail;
6582 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
6586 err_request_irq_fail:
6587 destroy_workqueue(hr_dev->irq_workq);
6590 for (i -= 1; i >= 0; i--)
6591 free_eq_buf(hr_dev, &eq_table->eq[i]);
6592 kfree(eq_table->eq);
6597 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
6599 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6603 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6606 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
6608 __hns_roce_free_irq(hr_dev);
6609 destroy_workqueue(hr_dev->irq_workq);
6611 for (i = 0; i < eq_num; i++) {
6612 hns_roce_v2_destroy_eqc(hr_dev, i);
6614 free_eq_buf(hr_dev, &eq_table->eq[i]);
6617 kfree(eq_table->eq);
6620 static const struct ib_device_ops hns_roce_v2_dev_ops = {
6621 .destroy_qp = hns_roce_v2_destroy_qp,
6622 .modify_cq = hns_roce_v2_modify_cq,
6623 .poll_cq = hns_roce_v2_poll_cq,
6624 .post_recv = hns_roce_v2_post_recv,
6625 .post_send = hns_roce_v2_post_send,
6626 .query_qp = hns_roce_v2_query_qp,
6627 .req_notify_cq = hns_roce_v2_req_notify_cq,
6630 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
6631 .modify_srq = hns_roce_v2_modify_srq,
6632 .post_srq_recv = hns_roce_v2_post_srq_recv,
6633 .query_srq = hns_roce_v2_query_srq,
6636 static const struct hns_roce_hw hns_roce_hw_v2 = {
6637 .cmq_init = hns_roce_v2_cmq_init,
6638 .cmq_exit = hns_roce_v2_cmq_exit,
6639 .hw_profile = hns_roce_v2_profile,
6640 .hw_init = hns_roce_v2_init,
6641 .hw_exit = hns_roce_v2_exit,
6642 .post_mbox = v2_post_mbox,
6643 .poll_mbox_done = v2_poll_mbox_done,
6644 .chk_mbox_avail = v2_chk_mbox_is_avail,
6645 .set_gid = hns_roce_v2_set_gid,
6646 .set_mac = hns_roce_v2_set_mac,
6647 .write_mtpt = hns_roce_v2_write_mtpt,
6648 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
6649 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
6650 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
6651 .write_cqc = hns_roce_v2_write_cqc,
6652 .set_hem = hns_roce_v2_set_hem,
6653 .clear_hem = hns_roce_v2_clear_hem,
6654 .modify_qp = hns_roce_v2_modify_qp,
6655 .dereg_mr = hns_roce_v2_dereg_mr,
6656 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
6657 .init_eq = hns_roce_v2_init_eq_table,
6658 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
6659 .write_srqc = hns_roce_v2_write_srqc,
6660 .query_cqc = hns_roce_v2_query_cqc,
6661 .query_qpc = hns_roce_v2_query_qpc,
6662 .query_mpt = hns_roce_v2_query_mpt,
6663 .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
6664 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
6667 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
6668 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
6669 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
6670 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
6671 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
6672 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
6673 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
6674 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
6675 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
6676 /* required last entry */
6680 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
6682 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
6683 struct hnae3_handle *handle)
6685 struct hns_roce_v2_priv *priv = hr_dev->priv;
6686 const struct pci_device_id *id;
6689 hr_dev->pci_dev = handle->pdev;
6690 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
6691 hr_dev->is_vf = id->driver_data;
6692 hr_dev->dev = &handle->pdev->dev;
6693 hr_dev->hw = &hns_roce_hw_v2;
6694 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
6695 hr_dev->odb_offset = hr_dev->sdb_offset;
6697 /* Get info from NIC driver. */
6698 hr_dev->reg_base = handle->rinfo.roce_io_base;
6699 hr_dev->mem_base = handle->rinfo.roce_mem_base;
6700 hr_dev->caps.num_ports = 1;
6701 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
6702 hr_dev->iboe.phy_port[0] = 0;
6704 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
6705 hr_dev->iboe.netdevs[0]->dev_addr);
6707 for (i = 0; i < handle->rinfo.num_vectors; i++)
6708 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
6709 i + handle->rinfo.base_vector);
6711 /* cmd issue mode: 0 is poll, 1 is event */
6712 hr_dev->cmd_mod = 1;
6713 hr_dev->loop_idc = 0;
6715 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
6716 priv->handle = handle;
6719 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6721 struct hns_roce_dev *hr_dev;
6724 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
6728 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
6729 if (!hr_dev->priv) {
6731 goto error_failed_kzalloc;
6734 hns_roce_hw_v2_get_cfg(hr_dev, handle);
6736 ret = hns_roce_init(hr_dev);
6738 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6739 goto error_failed_cfg;
6742 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6743 ret = free_mr_init(hr_dev);
6745 dev_err(hr_dev->dev, "failed to init free mr!\n");
6746 goto error_failed_roce_init;
6750 handle->priv = hr_dev;
6754 error_failed_roce_init:
6755 hns_roce_exit(hr_dev);
6758 kfree(hr_dev->priv);
6760 error_failed_kzalloc:
6761 ib_dealloc_device(&hr_dev->ib_dev);
6766 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6769 struct hns_roce_dev *hr_dev = handle->priv;
6774 handle->priv = NULL;
6776 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
6777 hns_roce_handle_device_err(hr_dev);
6779 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
6780 free_mr_exit(hr_dev);
6782 hns_roce_exit(hr_dev);
6783 kfree(hr_dev->priv);
6784 ib_dealloc_device(&hr_dev->ib_dev);
6787 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6789 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
6790 const struct pci_device_id *id;
6791 struct device *dev = &handle->pdev->dev;
6794 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
6796 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
6797 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6801 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
6805 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08)
6808 ret = __hns_roce_hw_v2_init_instance(handle);
6810 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6811 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
6812 if (ops->ae_dev_resetting(handle) ||
6813 ops->get_hw_reset_stat(handle))
6819 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
6824 dev_err(dev, "Device is busy in resetting state.\n"
6825 "please retry later.\n");
6830 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6833 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
6836 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
6838 __hns_roce_hw_v2_uninit_instance(handle, reset);
6840 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6842 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
6844 struct hns_roce_dev *hr_dev;
6846 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
6847 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6851 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
6852 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6854 hr_dev = handle->priv;
6858 hr_dev->active = false;
6859 hr_dev->dis_db = true;
6860 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN;
6865 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
6867 struct device *dev = &handle->pdev->dev;
6870 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
6871 &handle->rinfo.state)) {
6872 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6876 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
6878 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
6879 ret = __hns_roce_hw_v2_init_instance(handle);
6881 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
6882 * callback function, RoCE Engine reinitialize. If RoCE reinit
6883 * failed, we should inform NIC driver.
6885 handle->priv = NULL;
6886 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
6888 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6889 dev_info(dev, "reset done, RoCE client reinit finished.\n");
6895 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
6897 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
6900 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
6901 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
6902 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
6903 __hns_roce_hw_v2_uninit_instance(handle, false);
6908 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
6909 enum hnae3_reset_notify_type type)
6914 case HNAE3_DOWN_CLIENT:
6915 ret = hns_roce_hw_v2_reset_notify_down(handle);
6917 case HNAE3_INIT_CLIENT:
6918 ret = hns_roce_hw_v2_reset_notify_init(handle);
6920 case HNAE3_UNINIT_CLIENT:
6921 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
6930 static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
6931 .init_instance = hns_roce_hw_v2_init_instance,
6932 .uninit_instance = hns_roce_hw_v2_uninit_instance,
6933 .reset_notify = hns_roce_hw_v2_reset_notify,
6936 static struct hnae3_client hns_roce_hw_v2_client = {
6937 .name = "hns_roce_hw_v2",
6938 .type = HNAE3_CLIENT_ROCE,
6939 .ops = &hns_roce_hw_v2_ops,
6942 static int __init hns_roce_hw_v2_init(void)
6944 return hnae3_register_client(&hns_roce_hw_v2_client);
6947 static void __exit hns_roce_hw_v2_exit(void)
6949 hnae3_unregister_client(&hns_roce_hw_v2_client);
6952 module_init(hns_roce_hw_v2_init);
6953 module_exit(hns_roce_hw_v2_exit);
6955 MODULE_LICENSE("Dual BSD/GPL");
6956 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
6957 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
6958 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
6959 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");