drivers/infiniband/hw/hns/hns_roce_hw_v2.c

   1 /*
   2  * Copyright (c) 2016-2017 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/acpi.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/iopoll.h>
  37 #include <linux/kernel.h>
  38 #include <linux/types.h>
  39 #include <net/addrconf.h>
  40 #include <rdma/ib_addr.h>
  41 #include <rdma/ib_cache.h>
  42 #include <rdma/ib_umem.h>
  43 #include <rdma/uverbs_ioctl.h>
  44
  45 #include "hnae3.h"
  46 #include "hns_roce_common.h"
  47 #include "hns_roce_device.h"
  48 #include "hns_roce_cmd.h"
  49 #include "hns_roce_hem.h"
  50 #include "hns_roce_hw_v2.h"
  51
  52 enum {
  53         CMD_RST_PRC_OTHERS,
  54         CMD_RST_PRC_SUCCESS,
  55         CMD_RST_PRC_EBUSY,
  56 };
  57
  58 enum ecc_resource_type {
  59         ECC_RESOURCE_QPC,
  60         ECC_RESOURCE_CQC,
  61         ECC_RESOURCE_MPT,
  62         ECC_RESOURCE_SRQC,
  63         ECC_RESOURCE_GMV,
  64         ECC_RESOURCE_QPC_TIMER,
  65         ECC_RESOURCE_CQC_TIMER,
  66         ECC_RESOURCE_SCCC,
  67         ECC_RESOURCE_COUNT,
  68 };
  69
  70 static const struct {
  71         const char *name;
  72         u8 read_bt0_op;
  73         u8 write_bt0_op;
  74 } fmea_ram_res[] = {
  75         { "ECC_RESOURCE_QPC",
  76           HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 },
  77         { "ECC_RESOURCE_CQC",
  78           HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 },
  79         { "ECC_RESOURCE_MPT",
  80           HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 },
  81         { "ECC_RESOURCE_SRQC",
  82           HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 },
  83         /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */
  84         { "ECC_RESOURCE_GMV",
  85           0, 0 },
  86         { "ECC_RESOURCE_QPC_TIMER",
  87           HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 },
  88         { "ECC_RESOURCE_CQC_TIMER",
  89           HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 },
  90         { "ECC_RESOURCE_SCCC",
  91           HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 },
  92 };
  93
  94 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
  95                                    struct ib_sge *sg)
  96 {
  97         dseg->lkey = cpu_to_le32(sg->lkey);
  98         dseg->addr = cpu_to_le64(sg->addr);
  99         dseg->len  = cpu_to_le32(sg->length);
 100 }
 101
 102 /*
 103  * mapped-value = 1 + real-value
 104  * The hns wr opcode real value is start from 0, In order to distinguish between
 105  * initialized and uninitialized map values, we plus 1 to the actual value when
 106  * defining the mapping, so that the validity can be identified by checking the
 107  * mapped value is greater than 0.
 108  */
 109 #define HR_OPC_MAP(ib_key, hr_key) \
 110                 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key
 111
 112 static const u32 hns_roce_op_code[] = {
 113         HR_OPC_MAP(RDMA_WRITE,                  RDMA_WRITE),
 114         HR_OPC_MAP(RDMA_WRITE_WITH_IMM,         RDMA_WRITE_WITH_IMM),
 115         HR_OPC_MAP(SEND,                        SEND),
 116         HR_OPC_MAP(SEND_WITH_IMM,               SEND_WITH_IMM),
 117         HR_OPC_MAP(RDMA_READ,                   RDMA_READ),
 118         HR_OPC_MAP(ATOMIC_CMP_AND_SWP,          ATOM_CMP_AND_SWAP),
 119         HR_OPC_MAP(ATOMIC_FETCH_AND_ADD,        ATOM_FETCH_AND_ADD),
 120         HR_OPC_MAP(SEND_WITH_INV,               SEND_WITH_INV),
 121         HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP,   ATOM_MSK_CMP_AND_SWAP),
 122         HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD),
 123         HR_OPC_MAP(REG_MR,                      FAST_REG_PMR),
 124 };
 125
 126 static u32 to_hr_opcode(u32 ib_opcode)
 127 {
 128         if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code))
 129                 return HNS_ROCE_V2_WQE_OP_MASK;
 130
 131         return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 :
 132                                              HNS_ROCE_V2_WQE_OP_MASK;
 133 }
 134
 135 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
 136                          const struct ib_reg_wr *wr)
 137 {
 138         struct hns_roce_wqe_frmr_seg *fseg =
 139                 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
 140         struct hns_roce_mr *mr = to_hr_mr(wr->mr);
 141         u64 pbl_ba;
 142
 143         /* use ib_access_flags */
 144         hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND);
 145         hr_reg_write_bool(fseg, FRMR_ATOMIC,
 146                           wr->access & IB_ACCESS_REMOTE_ATOMIC);
 147         hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ);
 148         hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE);
 149         hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE);
 150
 151         /* Data structure reuse may lead to confusion */
 152         pbl_ba = mr->pbl_mtr.hem_cfg.root_ba;
 153         rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba));
 154         rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba));
 155
 156         rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
 157         rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
 158         rc_sq_wqe->rkey = cpu_to_le32(wr->key);
 159         rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
 160
 161         hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages);
 162         hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ,
 163                      to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
 164         hr_reg_clear(fseg, FRMR_BLK_MODE);
 165 }
 166
 167 static void set_atomic_seg(const struct ib_send_wr *wr,
 168                            struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
 169                            unsigned int valid_num_sge)
 170 {
 171         struct hns_roce_v2_wqe_data_seg *dseg =
 172                 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
 173         struct hns_roce_wqe_atomic_seg *aseg =
 174                 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg);
 175
 176         set_data_seg_v2(dseg, wr->sg_list);
 177
 178         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
 179                 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap);
 180                 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add);
 181         } else {
 182                 aseg->fetchadd_swap_data =
 183                         cpu_to_le64(atomic_wr(wr)->compare_add);
 184                 aseg->cmp_data = 0;
 185         }
 186
 187         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
 188 }
 189
 190 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp,
 191                                  const struct ib_send_wr *wr,
 192                                  unsigned int *sge_idx, u32 msg_len)
 193 {
 194         struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev;
 195         unsigned int left_len_in_pg;
 196         unsigned int idx = *sge_idx;
 197         unsigned int i = 0;
 198         unsigned int len;
 199         void *addr;
 200         void *dseg;
 201
 202         if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) {
 203                 ibdev_err(ibdev,
 204                           "no enough extended sge space for inline data.\n");
 205                 return -EINVAL;
 206         }
 207
 208         dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
 209         left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg;
 210         len = wr->sg_list[0].length;
 211         addr = (void *)(unsigned long)(wr->sg_list[0].addr);
 212
 213         /* When copying data to extended sge space, the left length in page may
 214          * not long enough for current user's sge. So the data should be
 215          * splited into several parts, one in the first page, and the others in
 216          * the subsequent pages.
 217          */
 218         while (1) {
 219                 if (len <= left_len_in_pg) {
 220                         memcpy(dseg, addr, len);
 221
 222                         idx += len / HNS_ROCE_SGE_SIZE;
 223
 224                         i++;
 225                         if (i >= wr->num_sge)
 226                                 break;
 227
 228                         left_len_in_pg -= len;
 229                         len = wr->sg_list[i].length;
 230                         addr = (void *)(unsigned long)(wr->sg_list[i].addr);
 231                         dseg += len;
 232                 } else {
 233                         memcpy(dseg, addr, left_len_in_pg);
 234
 235                         len -= left_len_in_pg;
 236                         addr += left_len_in_pg;
 237                         idx += left_len_in_pg / HNS_ROCE_SGE_SIZE;
 238                         dseg = hns_roce_get_extend_sge(qp,
 239                                                 idx & (qp->sge.sge_cnt - 1));
 240                         left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT;
 241                 }
 242         }
 243
 244         *sge_idx = idx;
 245
 246         return 0;
 247 }
 248
 249 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge,
 250                            unsigned int *sge_ind, unsigned int cnt)
 251 {
 252         struct hns_roce_v2_wqe_data_seg *dseg;
 253         unsigned int idx = *sge_ind;
 254
 255         while (cnt > 0) {
 256                 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
 257                 if (likely(sge->length)) {
 258                         set_data_seg_v2(dseg, sge);
 259                         idx++;
 260                         cnt--;
 261                 }
 262                 sge++;
 263         }
 264
 265         *sge_ind = idx;
 266 }
 267
 268 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len)
 269 {
 270         struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
 271         int mtu = ib_mtu_enum_to_int(qp->path_mtu);
 272
 273         if (len > qp->max_inline_data || len > mtu) {
 274                 ibdev_err(&hr_dev->ib_dev,
 275                           "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n",
 276                           len, qp->max_inline_data, mtu);
 277                 return false;
 278         }
 279
 280         return true;
 281 }
 282
 283 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
 284                       struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
 285                       unsigned int *sge_idx)
 286 {
 287         struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
 288         u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len);
 289         struct ib_device *ibdev = &hr_dev->ib_dev;
 290         unsigned int curr_idx = *sge_idx;
 291         void *dseg = rc_sq_wqe;
 292         unsigned int i;
 293         int ret;
 294
 295         if (unlikely(wr->opcode == IB_WR_RDMA_READ)) {
 296                 ibdev_err(ibdev, "invalid inline parameters!\n");
 297                 return -EINVAL;
 298         }
 299
 300         if (!check_inl_data_len(qp, msg_len))
 301                 return -EINVAL;
 302
 303         dseg += sizeof(struct hns_roce_v2_rc_send_wqe);
 304
 305         if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) {
 306                 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
 307
 308                 for (i = 0; i < wr->num_sge; i++) {
 309                         memcpy(dseg, ((void *)wr->sg_list[i].addr),
 310                                wr->sg_list[i].length);
 311                         dseg += wr->sg_list[i].length;
 312                 }
 313         } else {
 314                 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
 315
 316                 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len);
 317                 if (ret)
 318                         return ret;
 319
 320                 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx);
 321         }
 322
 323         *sge_idx = curr_idx;
 324
 325         return 0;
 326 }
 327
 328 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
 329                              struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
 330                              unsigned int *sge_ind,
 331                              unsigned int valid_num_sge)
 332 {
 333         struct hns_roce_v2_wqe_data_seg *dseg =
 334                 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
 335         struct hns_roce_qp *qp = to_hr_qp(ibqp);
 336         int j = 0;
 337         int i;
 338
 339         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX,
 340                      (*sge_ind) & (qp->sge.sge_cnt - 1));
 341
 342         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE,
 343                      !!(wr->send_flags & IB_SEND_INLINE));
 344         if (wr->send_flags & IB_SEND_INLINE)
 345                 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind);
 346
 347         if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) {
 348                 for (i = 0; i < wr->num_sge; i++) {
 349                         if (likely(wr->sg_list[i].length)) {
 350                                 set_data_seg_v2(dseg, wr->sg_list + i);
 351                                 dseg++;
 352                         }
 353                 }
 354         } else {
 355                 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) {
 356                         if (likely(wr->sg_list[i].length)) {
 357                                 set_data_seg_v2(dseg, wr->sg_list + i);
 358                                 dseg++;
 359                                 j++;
 360                         }
 361                 }
 362
 363                 set_extend_sge(qp, wr->sg_list + i, sge_ind,
 364                                valid_num_sge - HNS_ROCE_SGE_IN_WQE);
 365         }
 366
 367         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
 368
 369         return 0;
 370 }
 371
 372 static int check_send_valid(struct hns_roce_dev *hr_dev,
 373                             struct hns_roce_qp *hr_qp)
 374 {
 375         struct ib_device *ibdev = &hr_dev->ib_dev;
 376         struct ib_qp *ibqp = &hr_qp->ibqp;
 377
 378         if (unlikely(ibqp->qp_type != IB_QPT_RC &&
 379                      ibqp->qp_type != IB_QPT_GSI &&
 380                      ibqp->qp_type != IB_QPT_UD)) {
 381                 ibdev_err(ibdev, "not supported QP(0x%x)type!\n",
 382                           ibqp->qp_type);
 383                 return -EOPNOTSUPP;
 384         } else if (unlikely(hr_qp->state == IB_QPS_RESET ||
 385                    hr_qp->state == IB_QPS_INIT ||
 386                    hr_qp->state == IB_QPS_RTR)) {
 387                 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n",
 388                           hr_qp->state);
 389                 return -EINVAL;
 390         } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) {
 391                 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n",
 392                           hr_dev->state);
 393                 return -EIO;
 394         }
 395
 396         return 0;
 397 }
 398
 399 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr,
 400                                     unsigned int *sge_len)
 401 {
 402         unsigned int valid_num = 0;
 403         unsigned int len = 0;
 404         int i;
 405
 406         for (i = 0; i < wr->num_sge; i++) {
 407                 if (likely(wr->sg_list[i].length)) {
 408                         len += wr->sg_list[i].length;
 409                         valid_num++;
 410                 }
 411         }
 412
 413         *sge_len = len;
 414         return valid_num;
 415 }
 416
 417 static __le32 get_immtdata(const struct ib_send_wr *wr)
 418 {
 419         switch (wr->opcode) {
 420         case IB_WR_SEND_WITH_IMM:
 421         case IB_WR_RDMA_WRITE_WITH_IMM:
 422                 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
 423         default:
 424                 return 0;
 425         }
 426 }
 427
 428 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
 429                          const struct ib_send_wr *wr)
 430 {
 431         u32 ib_op = wr->opcode;
 432
 433         if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM)
 434                 return -EINVAL;
 435
 436         ud_sq_wqe->immtdata = get_immtdata(wr);
 437
 438         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
 439
 440         return 0;
 441 }
 442
 443 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
 444                       struct hns_roce_ah *ah)
 445 {
 446         struct ib_device *ib_dev = ah->ibah.device;
 447         struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
 448
 449         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport);
 450         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit);
 451         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass);
 452         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel);
 453
 454         if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL))
 455                 return -EINVAL;
 456
 457         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl);
 458
 459         ud_sq_wqe->sgid_index = ah->av.gid_index;
 460
 461         memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN);
 462         memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2);
 463
 464         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
 465                 return 0;
 466
 467         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en);
 468         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id);
 469
 470         return 0;
 471 }
 472
 473 static inline int set_ud_wqe(struct hns_roce_qp *qp,
 474                              const struct ib_send_wr *wr,
 475                              void *wqe, unsigned int *sge_idx,
 476                              unsigned int owner_bit)
 477 {
 478         struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
 479         struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe;
 480         unsigned int curr_idx = *sge_idx;
 481         unsigned int valid_num_sge;
 482         u32 msg_len = 0;
 483         int ret;
 484
 485         valid_num_sge = calc_wr_sge_num(wr, &msg_len);
 486
 487         ret = set_ud_opcode(ud_sq_wqe, wr);
 488         if (WARN_ON(ret))
 489                 return ret;
 490
 491         ud_sq_wqe->msg_len = cpu_to_le32(msg_len);
 492
 493         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE,
 494                      !!(wr->send_flags & IB_SEND_SIGNALED));
 495         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE,
 496                      !!(wr->send_flags & IB_SEND_SOLICITED));
 497
 498         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn);
 499         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge);
 500         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX,
 501                      curr_idx & (qp->sge.sge_cnt - 1));
 502
 503         ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
 504                           qp->qkey : ud_wr(wr)->remote_qkey);
 505         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn);
 506
 507         ret = fill_ud_av(ud_sq_wqe, ah);
 508         if (ret)
 509                 return ret;
 510
 511         qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl;
 512
 513         set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge);
 514
 515         /*
 516          * The pipeline can sequentially post all valid WQEs into WQ buffer,
 517          * including new WQEs waiting for the doorbell to update the PI again.
 518          * Therefore, the owner bit of WQE MUST be updated after all fields
 519          * and extSGEs have been written into DDR instead of cache.
 520          */
 521         if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
 522                 dma_wmb();
 523
 524         *sge_idx = curr_idx;
 525         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit);
 526
 527         return 0;
 528 }
 529
 530 static int set_rc_opcode(struct hns_roce_dev *hr_dev,
 531                          struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
 532                          const struct ib_send_wr *wr)
 533 {
 534         u32 ib_op = wr->opcode;
 535         int ret = 0;
 536
 537         rc_sq_wqe->immtdata = get_immtdata(wr);
 538
 539         switch (ib_op) {
 540         case IB_WR_RDMA_READ:
 541         case IB_WR_RDMA_WRITE:
 542         case IB_WR_RDMA_WRITE_WITH_IMM:
 543                 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
 544                 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
 545                 break;
 546         case IB_WR_SEND:
 547         case IB_WR_SEND_WITH_IMM:
 548                 break;
 549         case IB_WR_ATOMIC_CMP_AND_SWP:
 550         case IB_WR_ATOMIC_FETCH_AND_ADD:
 551                 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey);
 552                 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr);
 553                 break;
 554         case IB_WR_REG_MR:
 555                 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
 556                         set_frmr_seg(rc_sq_wqe, reg_wr(wr));
 557                 else
 558                         ret = -EOPNOTSUPP;
 559                 break;
 560         case IB_WR_SEND_WITH_INV:
 561                 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
 562                 break;
 563         default:
 564                 ret = -EINVAL;
 565         }
 566
 567         if (unlikely(ret))
 568                 return ret;
 569
 570         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
 571
 572         return ret;
 573 }
 574
 575 static inline int set_rc_wqe(struct hns_roce_qp *qp,
 576                              const struct ib_send_wr *wr,
 577                              void *wqe, unsigned int *sge_idx,
 578                              unsigned int owner_bit)
 579 {
 580         struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
 581         struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
 582         unsigned int curr_idx = *sge_idx;
 583         unsigned int valid_num_sge;
 584         u32 msg_len = 0;
 585         int ret;
 586
 587         valid_num_sge = calc_wr_sge_num(wr, &msg_len);
 588
 589         rc_sq_wqe->msg_len = cpu_to_le32(msg_len);
 590
 591         ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr);
 592         if (WARN_ON(ret))
 593                 return ret;
 594
 595         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_FENCE,
 596                      (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
 597
 598         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE,
 599                      (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
 600
 601         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE,
 602                      (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
 603
 604         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
 605             wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
 606                 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge);
 607         else if (wr->opcode != IB_WR_REG_MR)
 608                 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
 609                                         &curr_idx, valid_num_sge);
 610
 611         /*
 612          * The pipeline can sequentially post all valid WQEs into WQ buffer,
 613          * including new WQEs waiting for the doorbell to update the PI again.
 614          * Therefore, the owner bit of WQE MUST be updated after all fields
 615          * and extSGEs have been written into DDR instead of cache.
 616          */
 617         if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
 618                 dma_wmb();
 619
 620         *sge_idx = curr_idx;
 621         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit);
 622
 623         return ret;
 624 }
 625
 626 static inline void update_sq_db(struct hns_roce_dev *hr_dev,
 627                                 struct hns_roce_qp *qp)
 628 {
 629         if (unlikely(qp->state == IB_QPS_ERR)) {
 630                 flush_cqe(hr_dev, qp);
 631         } else {
 632                 struct hns_roce_v2_db sq_db = {};
 633
 634                 hr_reg_write(&sq_db, DB_TAG, qp->qpn);
 635                 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB);
 636                 hr_reg_write(&sq_db, DB_PI, qp->sq.head);
 637                 hr_reg_write(&sq_db, DB_SL, qp->sl);
 638
 639                 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg);
 640         }
 641 }
 642
 643 static inline void update_rq_db(struct hns_roce_dev *hr_dev,
 644                                 struct hns_roce_qp *qp)
 645 {
 646         if (unlikely(qp->state == IB_QPS_ERR)) {
 647                 flush_cqe(hr_dev, qp);
 648         } else {
 649                 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) {
 650                         *qp->rdb.db_record =
 651                                         qp->rq.head & V2_DB_PRODUCER_IDX_M;
 652                 } else {
 653                         struct hns_roce_v2_db rq_db = {};
 654
 655                         hr_reg_write(&rq_db, DB_TAG, qp->qpn);
 656                         hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB);
 657                         hr_reg_write(&rq_db, DB_PI, qp->rq.head);
 658
 659                         hns_roce_write64(hr_dev, (__le32 *)&rq_db,
 660                                          qp->rq.db_reg);
 661                 }
 662         }
 663 }
 664
 665 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val,
 666                               u64 __iomem *dest)
 667 {
 668 #define HNS_ROCE_WRITE_TIMES 8
 669         struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
 670         struct hnae3_handle *handle = priv->handle;
 671         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
 672         int i;
 673
 674         if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
 675                 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++)
 676                         writeq_relaxed(*(val + i), dest + i);
 677 }
 678
 679 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
 680                        void *wqe)
 681 {
 682 #define HNS_ROCE_SL_SHIFT 2
 683         struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
 684
 685         /* All kinds of DirectWQE have the same header field layout */
 686         hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG);
 687         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl);
 688         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H,
 689                      qp->sl >> HNS_ROCE_SL_SHIFT);
 690         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head);
 691
 692         hns_roce_write512(hr_dev, wqe, qp->sq.db_reg);
 693 }
 694
 695 static int hns_roce_v2_post_send(struct ib_qp *ibqp,
 696                                  const struct ib_send_wr *wr,
 697                                  const struct ib_send_wr **bad_wr)
 698 {
 699         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
 700         struct ib_device *ibdev = &hr_dev->ib_dev;
 701         struct hns_roce_qp *qp = to_hr_qp(ibqp);
 702         unsigned long flags = 0;
 703         unsigned int owner_bit;
 704         unsigned int sge_idx;
 705         unsigned int wqe_idx;
 706         void *wqe = NULL;
 707         u32 nreq;
 708         int ret;
 709
 710         spin_lock_irqsave(&qp->sq.lock, flags);
 711
 712         ret = check_send_valid(hr_dev, qp);
 713         if (unlikely(ret)) {
 714                 *bad_wr = wr;
 715                 nreq = 0;
 716                 goto out;
 717         }
 718
 719         sge_idx = qp->next_sge;
 720
 721         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 722                 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
 723                         ret = -ENOMEM;
 724                         *bad_wr = wr;
 725                         goto out;
 726                 }
 727
 728                 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
 729
 730                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
 731                         ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n",
 732                                   wr->num_sge, qp->sq.max_gs);
 733                         ret = -EINVAL;
 734                         *bad_wr = wr;
 735                         goto out;
 736                 }
 737
 738                 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
 739                 qp->sq.wrid[wqe_idx] = wr->wr_id;
 740                 owner_bit =
 741                        ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
 742
 743                 /* Corresponding to the QP type, wqe process separately */
 744                 if (ibqp->qp_type == IB_QPT_RC)
 745                         ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit);
 746                 else
 747                         ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit);
 748
 749                 if (unlikely(ret)) {
 750                         *bad_wr = wr;
 751                         goto out;
 752                 }
 753         }
 754
 755 out:
 756         if (likely(nreq)) {
 757                 qp->sq.head += nreq;
 758                 qp->next_sge = sge_idx;
 759
 760                 if (nreq == 1 && (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE))
 761                         write_dwqe(hr_dev, qp, wqe);
 762                 else
 763                         update_sq_db(hr_dev, qp);
 764         }
 765
 766         spin_unlock_irqrestore(&qp->sq.lock, flags);
 767
 768         return ret;
 769 }
 770
 771 static int check_recv_valid(struct hns_roce_dev *hr_dev,
 772                             struct hns_roce_qp *hr_qp)
 773 {
 774         struct ib_device *ibdev = &hr_dev->ib_dev;
 775         struct ib_qp *ibqp = &hr_qp->ibqp;
 776
 777         if (unlikely(ibqp->qp_type != IB_QPT_RC &&
 778                      ibqp->qp_type != IB_QPT_GSI &&
 779                      ibqp->qp_type != IB_QPT_UD)) {
 780                 ibdev_err(ibdev, "unsupported qp type, qp_type = %d.\n",
 781                           ibqp->qp_type);
 782                 return -EOPNOTSUPP;
 783         }
 784
 785         if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
 786                 return -EIO;
 787
 788         if (hr_qp->state == IB_QPS_RESET)
 789                 return -EINVAL;
 790
 791         return 0;
 792 }
 793
 794 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe,
 795                                  u32 max_sge, bool rsv)
 796 {
 797         struct hns_roce_v2_wqe_data_seg *dseg = wqe;
 798         u32 i, cnt;
 799
 800         for (i = 0, cnt = 0; i < wr->num_sge; i++) {
 801                 /* Skip zero-length sge */
 802                 if (!wr->sg_list[i].length)
 803                         continue;
 804                 set_data_seg_v2(dseg + cnt, wr->sg_list + i);
 805                 cnt++;
 806         }
 807
 808         /* Fill a reserved sge to make hw stop reading remaining segments */
 809         if (rsv) {
 810                 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
 811                 dseg[cnt].addr = 0;
 812                 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH);
 813         } else {
 814                 /* Clear remaining segments to make ROCEE ignore sges */
 815                 if (cnt < max_sge)
 816                         memset(dseg + cnt, 0,
 817                                (max_sge - cnt) * HNS_ROCE_SGE_SIZE);
 818         }
 819 }
 820
 821 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr,
 822                         u32 wqe_idx, u32 max_sge)
 823 {
 824         struct hns_roce_rinl_sge *sge_list;
 825         void *wqe = NULL;
 826         u32 i;
 827
 828         wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
 829         fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge);
 830
 831         /* rq support inline data */
 832         if (hr_qp->rq_inl_buf.wqe_cnt) {
 833                 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list;
 834                 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt = (u32)wr->num_sge;
 835                 for (i = 0; i < wr->num_sge; i++) {
 836                         sge_list[i].addr = (void *)(u64)wr->sg_list[i].addr;
 837                         sge_list[i].len = wr->sg_list[i].length;
 838                 }
 839         }
 840 }
 841
 842 static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
 843                                  const struct ib_recv_wr *wr,
 844                                  const struct ib_recv_wr **bad_wr)
 845 {
 846         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
 847         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
 848         struct ib_device *ibdev = &hr_dev->ib_dev;
 849         u32 wqe_idx, nreq, max_sge;
 850         unsigned long flags;
 851         int ret;
 852
 853         spin_lock_irqsave(&hr_qp->rq.lock, flags);
 854
 855         ret = check_recv_valid(hr_dev, hr_qp);
 856         if (unlikely(ret)) {
 857                 *bad_wr = wr;
 858                 nreq = 0;
 859                 goto out;
 860         }
 861
 862         max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
 863         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 864                 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq,
 865                                                   hr_qp->ibqp.recv_cq))) {
 866                         ret = -ENOMEM;
 867                         *bad_wr = wr;
 868                         goto out;
 869                 }
 870
 871                 if (unlikely(wr->num_sge > max_sge)) {
 872                         ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n",
 873                                   wr->num_sge, max_sge);
 874                         ret = -EINVAL;
 875                         *bad_wr = wr;
 876                         goto out;
 877                 }
 878
 879                 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
 880                 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge);
 881                 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
 882         }
 883
 884 out:
 885         if (likely(nreq)) {
 886                 hr_qp->rq.head += nreq;
 887
 888                 update_rq_db(hr_dev, hr_qp);
 889         }
 890         spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
 891
 892         return ret;
 893 }
 894
 895 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n)
 896 {
 897         return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
 898 }
 899
 900 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n)
 901 {
 902         return hns_roce_buf_offset(idx_que->mtr.kmem,
 903                                    n << idx_que->entry_shift);
 904 }
 905
 906 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index)
 907 {
 908         /* always called with interrupts disabled. */
 909         spin_lock(&srq->lock);
 910
 911         bitmap_clear(srq->idx_que.bitmap, wqe_index, 1);
 912         srq->idx_que.tail++;
 913
 914         spin_unlock(&srq->lock);
 915 }
 916
 917 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq)
 918 {
 919         struct hns_roce_idx_que *idx_que = &srq->idx_que;
 920
 921         return idx_que->head - idx_que->tail >= srq->wqe_cnt;
 922 }
 923
 924 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge,
 925                                 const struct ib_recv_wr *wr)
 926 {
 927         struct ib_device *ib_dev = srq->ibsrq.device;
 928
 929         if (unlikely(wr->num_sge > max_sge)) {
 930                 ibdev_err(ib_dev,
 931                           "failed to check sge, wr->num_sge = %d, max_sge = %u.\n",
 932                           wr->num_sge, max_sge);
 933                 return -EINVAL;
 934         }
 935
 936         if (unlikely(hns_roce_srqwq_overflow(srq))) {
 937                 ibdev_err(ib_dev,
 938                           "failed to check srqwq status, srqwq is full.\n");
 939                 return -ENOMEM;
 940         }
 941
 942         return 0;
 943 }
 944
 945 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx)
 946 {
 947         struct hns_roce_idx_que *idx_que = &srq->idx_que;
 948         u32 pos;
 949
 950         pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt);
 951         if (unlikely(pos == srq->wqe_cnt))
 952                 return -ENOSPC;
 953
 954         bitmap_set(idx_que->bitmap, pos, 1);
 955         *wqe_idx = pos;
 956         return 0;
 957 }
 958
 959 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx)
 960 {
 961         struct hns_roce_idx_que *idx_que = &srq->idx_que;
 962         unsigned int head;
 963         __le32 *buf;
 964
 965         head = idx_que->head & (srq->wqe_cnt - 1);
 966
 967         buf = get_idx_buf(idx_que, head);
 968         *buf = cpu_to_le32(wqe_idx);
 969
 970         idx_que->head++;
 971 }
 972
 973 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq)
 974 {
 975         hr_reg_write(db, DB_TAG, srq->srqn);
 976         hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB);
 977         hr_reg_write(db, DB_PI, srq->idx_que.head);
 978 }
 979
 980 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
 981                                      const struct ib_recv_wr *wr,
 982                                      const struct ib_recv_wr **bad_wr)
 983 {
 984         struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
 985         struct hns_roce_srq *srq = to_hr_srq(ibsrq);
 986         struct hns_roce_v2_db srq_db;
 987         unsigned long flags;
 988         int ret = 0;
 989         u32 max_sge;
 990         u32 wqe_idx;
 991         void *wqe;
 992         u32 nreq;
 993
 994         spin_lock_irqsave(&srq->lock, flags);
 995
 996         max_sge = srq->max_gs - srq->rsv_sge;
 997         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 998                 ret = check_post_srq_valid(srq, max_sge, wr);
 999                 if (ret) {
1000                         *bad_wr = wr;
1001                         break;
1002                 }
1003
1004                 ret = get_srq_wqe_idx(srq, &wqe_idx);
1005                 if (unlikely(ret)) {
1006                         *bad_wr = wr;
1007                         break;
1008                 }
1009
1010                 wqe = get_srq_wqe_buf(srq, wqe_idx);
1011                 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge);
1012                 fill_wqe_idx(srq, wqe_idx);
1013                 srq->wrid[wqe_idx] = wr->wr_id;
1014         }
1015
1016         if (likely(nreq)) {
1017                 update_srq_db(&srq_db, srq);
1018
1019                 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg);
1020         }
1021
1022         spin_unlock_irqrestore(&srq->lock, flags);
1023
1024         return ret;
1025 }
1026
1027 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
1028                                       unsigned long instance_stage,
1029                                       unsigned long reset_stage)
1030 {
1031         /* When hardware reset has been completed once or more, we should stop
1032          * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
1033          * function, we should exit with error. If now at HNAE3_INIT_CLIENT
1034          * stage of soft reset process, we should exit with error, and then
1035          * HNAE3_INIT_CLIENT related process can rollback the operation like
1036          * notifing hardware to free resources, HNAE3_INIT_CLIENT related
1037          * process will exit with error to notify NIC driver to reschedule soft
1038          * reset process once again.
1039          */
1040         hr_dev->is_reset = true;
1041         hr_dev->dis_db = true;
1042
1043         if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
1044             instance_stage == HNS_ROCE_STATE_INIT)
1045                 return CMD_RST_PRC_EBUSY;
1046
1047         return CMD_RST_PRC_SUCCESS;
1048 }
1049
1050 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
1051                                         unsigned long instance_stage,
1052                                         unsigned long reset_stage)
1053 {
1054 #define HW_RESET_TIMEOUT_US 1000000
1055 #define HW_RESET_SLEEP_US 1000
1056
1057         struct hns_roce_v2_priv *priv = hr_dev->priv;
1058         struct hnae3_handle *handle = priv->handle;
1059         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1060         unsigned long val;
1061         int ret;
1062
1063         /* When hardware reset is detected, we should stop sending mailbox&cmq&
1064          * doorbell to hardware. If now in .init_instance() function, we should
1065          * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
1066          * process, we should exit with error, and then HNAE3_INIT_CLIENT
1067          * related process can rollback the operation like notifing hardware to
1068          * free resources, HNAE3_INIT_CLIENT related process will exit with
1069          * error to notify NIC driver to reschedule soft reset process once
1070          * again.
1071          */
1072         hr_dev->dis_db = true;
1073
1074         ret = read_poll_timeout(ops->ae_dev_reset_cnt, val,
1075                                 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US,
1076                                 HW_RESET_TIMEOUT_US, false, handle);
1077         if (!ret)
1078                 hr_dev->is_reset = true;
1079
1080         if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
1081             instance_stage == HNS_ROCE_STATE_INIT)
1082                 return CMD_RST_PRC_EBUSY;
1083
1084         return CMD_RST_PRC_SUCCESS;
1085 }
1086
1087 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
1088 {
1089         struct hns_roce_v2_priv *priv = hr_dev->priv;
1090         struct hnae3_handle *handle = priv->handle;
1091         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1092
1093         /* When software reset is detected at .init_instance() function, we
1094          * should stop sending mailbox&cmq&doorbell to hardware, and exit
1095          * with error.
1096          */
1097         hr_dev->dis_db = true;
1098         if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
1099                 hr_dev->is_reset = true;
1100
1101         return CMD_RST_PRC_EBUSY;
1102 }
1103
1104 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev,
1105                                     struct hnae3_handle *handle)
1106 {
1107         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1108         unsigned long instance_stage; /* the current instance stage */
1109         unsigned long reset_stage; /* the current reset stage */
1110         unsigned long reset_cnt;
1111         bool sw_resetting;
1112         bool hw_resetting;
1113
1114         /* Get information about reset from NIC driver or RoCE driver itself,
1115          * the meaning of the following variables from NIC driver are described
1116          * as below:
1117          * reset_cnt -- The count value of completed hardware reset.
1118          * hw_resetting -- Whether hardware device is resetting now.
1119          * sw_resetting -- Whether NIC's software reset process is running now.
1120          */
1121         instance_stage = handle->rinfo.instance_state;
1122         reset_stage = handle->rinfo.reset_state;
1123         reset_cnt = ops->ae_dev_reset_cnt(handle);
1124         if (reset_cnt != hr_dev->reset_cnt)
1125                 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
1126                                                   reset_stage);
1127
1128         hw_resetting = ops->get_cmdq_stat(handle);
1129         if (hw_resetting)
1130                 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
1131                                                     reset_stage);
1132
1133         sw_resetting = ops->ae_dev_resetting(handle);
1134         if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
1135                 return hns_roce_v2_cmd_sw_resetting(hr_dev);
1136
1137         return CMD_RST_PRC_OTHERS;
1138 }
1139
1140 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev)
1141 {
1142         struct hns_roce_v2_priv *priv = hr_dev->priv;
1143         struct hnae3_handle *handle = priv->handle;
1144         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1145
1146         if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle))
1147                 return true;
1148
1149         if (ops->get_hw_reset_stat(handle))
1150                 return true;
1151
1152         if (ops->ae_dev_resetting(handle))
1153                 return true;
1154
1155         return false;
1156 }
1157
1158 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy)
1159 {
1160         struct hns_roce_v2_priv *priv = hr_dev->priv;
1161         u32 status;
1162
1163         if (hr_dev->is_reset)
1164                 status = CMD_RST_PRC_SUCCESS;
1165         else
1166                 status = check_aedev_reset_status(hr_dev, priv->handle);
1167
1168         *busy = (status == CMD_RST_PRC_EBUSY);
1169
1170         return status == CMD_RST_PRC_OTHERS;
1171 }
1172
1173 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
1174                                    struct hns_roce_v2_cmq_ring *ring)
1175 {
1176         int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
1177
1178         ring->desc = dma_alloc_coherent(hr_dev->dev, size,
1179                                         &ring->desc_dma_addr, GFP_KERNEL);
1180         if (!ring->desc)
1181                 return -ENOMEM;
1182
1183         return 0;
1184 }
1185
1186 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
1187                                    struct hns_roce_v2_cmq_ring *ring)
1188 {
1189         dma_free_coherent(hr_dev->dev,
1190                           ring->desc_num * sizeof(struct hns_roce_cmq_desc),
1191                           ring->desc, ring->desc_dma_addr);
1192
1193         ring->desc_dma_addr = 0;
1194 }
1195
1196 static int init_csq(struct hns_roce_dev *hr_dev,
1197                     struct hns_roce_v2_cmq_ring *csq)
1198 {
1199         dma_addr_t dma;
1200         int ret;
1201
1202         csq->desc_num = CMD_CSQ_DESC_NUM;
1203         spin_lock_init(&csq->lock);
1204         csq->flag = TYPE_CSQ;
1205         csq->head = 0;
1206
1207         ret = hns_roce_alloc_cmq_desc(hr_dev, csq);
1208         if (ret)
1209                 return ret;
1210
1211         dma = csq->desc_dma_addr;
1212         roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma));
1213         roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma));
1214         roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
1215                    (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1216
1217         /* Make sure to write CI first and then PI */
1218         roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0);
1219         roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0);
1220
1221         return 0;
1222 }
1223
1224 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
1225 {
1226         struct hns_roce_v2_priv *priv = hr_dev->priv;
1227         int ret;
1228
1229         priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
1230
1231         ret = init_csq(hr_dev, &priv->cmq.csq);
1232         if (ret)
1233                 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret);
1234
1235         return ret;
1236 }
1237
1238 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
1239 {
1240         struct hns_roce_v2_priv *priv = hr_dev->priv;
1241
1242         hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1243 }
1244
1245 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
1246                                           enum hns_roce_opcode_type opcode,
1247                                           bool is_read)
1248 {
1249         memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
1250         desc->opcode = cpu_to_le16(opcode);
1251         desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1252         if (is_read)
1253                 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
1254         else
1255                 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1256 }
1257
1258 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
1259 {
1260         u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1261         struct hns_roce_v2_priv *priv = hr_dev->priv;
1262
1263         return tail == priv->cmq.csq.head;
1264 }
1265
1266 static void update_cmdq_status(struct hns_roce_dev *hr_dev)
1267 {
1268         struct hns_roce_v2_priv *priv = hr_dev->priv;
1269         struct hnae3_handle *handle = priv->handle;
1270
1271         if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
1272             handle->rinfo.instance_state == HNS_ROCE_STATE_INIT)
1273                 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR;
1274 }
1275
1276 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1277                                struct hns_roce_cmq_desc *desc, int num)
1278 {
1279         struct hns_roce_v2_priv *priv = hr_dev->priv;
1280         struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1281         u32 timeout = 0;
1282         u16 desc_ret;
1283         u32 tail;
1284         int ret;
1285         int i;
1286
1287         spin_lock_bh(&csq->lock);
1288
1289         tail = csq->head;
1290
1291         for (i = 0; i < num; i++) {
1292                 csq->desc[csq->head++] = desc[i];
1293                 if (csq->head == csq->desc_num)
1294                         csq->head = 0;
1295         }
1296
1297         /* Write to hardware */
1298         roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head);
1299
1300         do {
1301                 if (hns_roce_cmq_csq_done(hr_dev))
1302                         break;
1303                 udelay(1);
1304         } while (++timeout < priv->cmq.tx_timeout);
1305
1306         if (hns_roce_cmq_csq_done(hr_dev)) {
1307                 ret = 0;
1308                 for (i = 0; i < num; i++) {
1309                         /* check the result of hardware write back */
1310                         desc[i] = csq->desc[tail++];
1311                         if (tail == csq->desc_num)
1312                                 tail = 0;
1313
1314                         desc_ret = le16_to_cpu(desc[i].retval);
1315                         if (likely(desc_ret == CMD_EXEC_SUCCESS))
1316                                 continue;
1317
1318                         dev_err_ratelimited(hr_dev->dev,
1319                                             "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n",
1320                                             desc->opcode, desc_ret);
1321                         ret = -EIO;
1322                 }
1323         } else {
1324                 /* FW/HW reset or incorrect number of desc */
1325                 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1326                 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n",
1327                          csq->head, tail);
1328                 csq->head = tail;
1329
1330                 update_cmdq_status(hr_dev);
1331
1332                 ret = -EAGAIN;
1333         }
1334
1335         spin_unlock_bh(&csq->lock);
1336
1337         return ret;
1338 }
1339
1340 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1341                              struct hns_roce_cmq_desc *desc, int num)
1342 {
1343         bool busy;
1344         int ret;
1345
1346         if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1347                 return -EIO;
1348
1349         if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1350                 return busy ? -EBUSY : 0;
1351
1352         ret = __hns_roce_cmq_send(hr_dev, desc, num);
1353         if (ret) {
1354                 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1355                         return busy ? -EBUSY : 0;
1356         }
1357
1358         return ret;
1359 }
1360
1361 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev,
1362                                dma_addr_t base_addr, u8 cmd, unsigned long tag)
1363 {
1364         struct hns_roce_cmd_mailbox *mbox;
1365         int ret;
1366
1367         mbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1368         if (IS_ERR(mbox))
1369                 return PTR_ERR(mbox);
1370
1371         ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag);
1372         hns_roce_free_cmd_mailbox(hr_dev, mbox);
1373         return ret;
1374 }
1375
1376 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
1377 {
1378         struct hns_roce_query_version *resp;
1379         struct hns_roce_cmq_desc desc;
1380         int ret;
1381
1382         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1383         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1384         if (ret)
1385                 return ret;
1386
1387         resp = (struct hns_roce_query_version *)desc.data;
1388         hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version);
1389         hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1390
1391         return 0;
1392 }
1393
1394 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev,
1395                                         struct hnae3_handle *handle)
1396 {
1397         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1398         unsigned long end;
1399
1400         hr_dev->dis_db = true;
1401
1402         dev_warn(hr_dev->dev,
1403                  "func clear is pending, device in resetting state.\n");
1404         end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1405         while (end) {
1406                 if (!ops->get_hw_reset_stat(handle)) {
1407                         hr_dev->is_reset = true;
1408                         dev_info(hr_dev->dev,
1409                                  "func clear success after reset.\n");
1410                         return;
1411                 }
1412                 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1413                 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1414         }
1415
1416         dev_warn(hr_dev->dev, "func clear failed.\n");
1417 }
1418
1419 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev,
1420                                         struct hnae3_handle *handle)
1421 {
1422         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1423         unsigned long end;
1424
1425         hr_dev->dis_db = true;
1426
1427         dev_warn(hr_dev->dev,
1428                  "func clear is pending, device in resetting state.\n");
1429         end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1430         while (end) {
1431                 if (ops->ae_dev_reset_cnt(handle) !=
1432                     hr_dev->reset_cnt) {
1433                         hr_dev->is_reset = true;
1434                         dev_info(hr_dev->dev,
1435                                  "func clear success after sw reset\n");
1436                         return;
1437                 }
1438                 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1439                 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1440         }
1441
1442         dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n");
1443 }
1444
1445 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval,
1446                                        int flag)
1447 {
1448         struct hns_roce_v2_priv *priv = hr_dev->priv;
1449         struct hnae3_handle *handle = priv->handle;
1450         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1451
1452         if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) {
1453                 hr_dev->dis_db = true;
1454                 hr_dev->is_reset = true;
1455                 dev_info(hr_dev->dev, "func clear success after reset.\n");
1456                 return;
1457         }
1458
1459         if (ops->get_hw_reset_stat(handle)) {
1460                 func_clr_hw_resetting_state(hr_dev, handle);
1461                 return;
1462         }
1463
1464         if (ops->ae_dev_resetting(handle) &&
1465             handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) {
1466                 func_clr_sw_resetting_state(hr_dev, handle);
1467                 return;
1468         }
1469
1470         if (retval && !flag)
1471                 dev_warn(hr_dev->dev,
1472                          "func clear read failed, ret = %d.\n", retval);
1473
1474         dev_warn(hr_dev->dev, "func clear failed.\n");
1475 }
1476
1477 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id)
1478 {
1479         bool fclr_write_fail_flag = false;
1480         struct hns_roce_func_clear *resp;
1481         struct hns_roce_cmq_desc desc;
1482         unsigned long end;
1483         int ret = 0;
1484
1485         if (check_device_is_in_reset(hr_dev))
1486                 goto out;
1487
1488         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
1489         resp = (struct hns_roce_func_clear *)desc.data;
1490         resp->rst_funcid_en = cpu_to_le32(vf_id);
1491
1492         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1493         if (ret) {
1494                 fclr_write_fail_flag = true;
1495                 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n",
1496                          ret);
1497                 goto out;
1498         }
1499
1500         msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
1501         end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
1502         while (end) {
1503                 if (check_device_is_in_reset(hr_dev))
1504                         goto out;
1505                 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
1506                 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
1507
1508                 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR,
1509                                               true);
1510
1511                 resp->rst_funcid_en = cpu_to_le32(vf_id);
1512                 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1513                 if (ret)
1514                         continue;
1515
1516                 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) {
1517                         if (vf_id == 0)
1518                                 hr_dev->is_reset = true;
1519                         return;
1520                 }
1521         }
1522
1523 out:
1524         hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag);
1525 }
1526
1527 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id)
1528 {
1529         enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1530         struct hns_roce_cmq_desc desc[2];
1531         struct hns_roce_cmq_req *req_a;
1532
1533         req_a = (struct hns_roce_cmq_req *)desc[0].data;
1534         hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1535         desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1536         hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1537         hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id);
1538
1539         return hns_roce_cmq_send(hr_dev, desc, 2);
1540 }
1541
1542 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
1543 {
1544         int ret;
1545         int i;
1546
1547         if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1548                 return;
1549
1550         for (i = hr_dev->func_num - 1; i >= 0; i--) {
1551                 __hns_roce_function_clear(hr_dev, i);
1552
1553                 if (i == 0)
1554                         continue;
1555
1556                 ret = hns_roce_free_vf_resource(hr_dev, i);
1557                 if (ret)
1558                         ibdev_err(&hr_dev->ib_dev,
1559                                   "failed to free vf resource, vf_id = %d, ret = %d.\n",
1560                                   i, ret);
1561         }
1562 }
1563
1564 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev)
1565 {
1566         struct hns_roce_cmq_desc desc;
1567         int ret;
1568
1569         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO,
1570                                       false);
1571         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1572         if (ret)
1573                 ibdev_err(&hr_dev->ib_dev,
1574                           "failed to clear extended doorbell info, ret = %d.\n",
1575                           ret);
1576
1577         return ret;
1578 }
1579
1580 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1581 {
1582         struct hns_roce_query_fw_info *resp;
1583         struct hns_roce_cmq_desc desc;
1584         int ret;
1585
1586         hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1587         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1588         if (ret)
1589                 return ret;
1590
1591         resp = (struct hns_roce_query_fw_info *)desc.data;
1592         hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
1593
1594         return 0;
1595 }
1596
1597 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev)
1598 {
1599         struct hns_roce_cmq_desc desc;
1600         int ret;
1601
1602         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
1603                 hr_dev->func_num = 1;
1604                 return 0;
1605         }
1606
1607         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO,
1608                                       true);
1609         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1610         if (ret) {
1611                 hr_dev->func_num = 1;
1612                 return ret;
1613         }
1614
1615         hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num);
1616         hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id);
1617
1618         return 0;
1619 }
1620
1621 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1622 {
1623         struct hns_roce_cmq_desc desc;
1624         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1625         u32 clock_cycles_of_1us;
1626
1627         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1628                                       false);
1629
1630         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
1631                 clock_cycles_of_1us = HNS_ROCE_1NS_CFG;
1632         else
1633                 clock_cycles_of_1us = HNS_ROCE_1US_CFG;
1634
1635         hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us);
1636         hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT);
1637
1638         return hns_roce_cmq_send(hr_dev, &desc, 1);
1639 }
1640
1641 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1642 {
1643         struct hns_roce_cmq_desc desc[2];
1644         struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1645         struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1646         struct hns_roce_caps *caps = &hr_dev->caps;
1647         enum hns_roce_opcode_type opcode;
1648         u32 func_num;
1649         int ret;
1650
1651         if (is_vf) {
1652                 opcode = HNS_ROCE_OPC_QUERY_VF_RES;
1653                 func_num = 1;
1654         } else {
1655                 opcode = HNS_ROCE_OPC_QUERY_PF_RES;
1656                 func_num = hr_dev->func_num;
1657         }
1658
1659         hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true);
1660         desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1661         hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true);
1662
1663         ret = hns_roce_cmq_send(hr_dev, desc, 2);
1664         if (ret)
1665                 return ret;
1666
1667         caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num;
1668         caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num;
1669         caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num;
1670         caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num;
1671         caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num;
1672         caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num;
1673         caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num;
1674         caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num;
1675
1676         if (is_vf) {
1677                 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num;
1678                 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) /
1679                                                func_num;
1680         } else {
1681                 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num;
1682                 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) /
1683                                                func_num;
1684         }
1685
1686         return 0;
1687 }
1688
1689 static int load_ext_cfg_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1690 {
1691         struct hns_roce_cmq_desc desc;
1692         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1693         struct hns_roce_caps *caps = &hr_dev->caps;
1694         u32 func_num, qp_num;
1695         int ret;
1696
1697         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, true);
1698         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1699         if (ret)
1700                 return ret;
1701
1702         func_num = is_vf ? 1 : max_t(u32, 1, hr_dev->func_num);
1703         qp_num = hr_reg_read(req, EXT_CFG_QP_PI_NUM) / func_num;
1704         caps->num_pi_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM);
1705
1706         qp_num = hr_reg_read(req, EXT_CFG_QP_NUM) / func_num;
1707         caps->num_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM);
1708
1709         return 0;
1710 }
1711
1712 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev)
1713 {
1714         struct hns_roce_cmq_desc desc;
1715         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1716         struct hns_roce_caps *caps = &hr_dev->caps;
1717         int ret;
1718
1719         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1720                                       true);
1721
1722         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1723         if (ret)
1724                 return ret;
1725
1726         caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM);
1727         caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM);
1728
1729         return 0;
1730 }
1731
1732 static int query_func_resource_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1733 {
1734         struct device *dev = hr_dev->dev;
1735         int ret;
1736
1737         ret = load_func_res_caps(hr_dev, is_vf);
1738         if (ret) {
1739                 dev_err(dev, "failed to load res caps, ret = %d (%s).\n", ret,
1740                         is_vf ? "vf" : "pf");
1741                 return ret;
1742         }
1743
1744         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1745                 ret = load_ext_cfg_caps(hr_dev, is_vf);
1746                 if (ret)
1747                         dev_err(dev, "failed to load ext cfg, ret = %d (%s).\n",
1748                                 ret, is_vf ? "vf" : "pf");
1749         }
1750
1751         return ret;
1752 }
1753
1754 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1755 {
1756         struct device *dev = hr_dev->dev;
1757         int ret;
1758
1759         ret = query_func_resource_caps(hr_dev, false);
1760         if (ret)
1761                 return ret;
1762
1763         ret = load_pf_timer_res_caps(hr_dev);
1764         if (ret)
1765                 dev_err(dev, "failed to load pf timer resource, ret = %d.\n",
1766                         ret);
1767
1768         return ret;
1769 }
1770
1771 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev)
1772 {
1773         return query_func_resource_caps(hr_dev, true);
1774 }
1775
1776 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev,
1777                                           u32 vf_id)
1778 {
1779         struct hns_roce_vf_switch *swt;
1780         struct hns_roce_cmq_desc desc;
1781         int ret;
1782
1783         swt = (struct hns_roce_vf_switch *)desc.data;
1784         hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
1785         swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
1786         hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id);
1787         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1788         if (ret)
1789                 return ret;
1790
1791         desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1792         desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1793         hr_reg_enable(swt, VF_SWITCH_ALW_LPBK);
1794         hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK);
1795         hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD);
1796
1797         return hns_roce_cmq_send(hr_dev, &desc, 1);
1798 }
1799
1800 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev)
1801 {
1802         u32 vf_id;
1803         int ret;
1804
1805         for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) {
1806                 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id);
1807                 if (ret)
1808                         return ret;
1809         }
1810         return 0;
1811 }
1812
1813 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id)
1814 {
1815         struct hns_roce_cmq_desc desc[2];
1816         struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1817         struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1818         enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1819         struct hns_roce_caps *caps = &hr_dev->caps;
1820
1821         hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1822         desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1823         hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1824
1825         hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id);
1826
1827         hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num);
1828         hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num);
1829         hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num);
1830         hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num);
1831         hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num);
1832         hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num);
1833         hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num);
1834         hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num);
1835         hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num);
1836         hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num);
1837         hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num);
1838         hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num);
1839         hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num);
1840         hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num);
1841
1842         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1843                 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num);
1844                 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX,
1845                              vf_id * caps->gmv_bt_num);
1846         } else {
1847                 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num);
1848                 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX,
1849                              vf_id * caps->sgid_bt_num);
1850                 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num);
1851                 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX,
1852                              vf_id * caps->smac_bt_num);
1853         }
1854
1855         return hns_roce_cmq_send(hr_dev, desc, 2);
1856 }
1857
1858 static int config_vf_ext_resource(struct hns_roce_dev *hr_dev, u32 vf_id)
1859 {
1860         struct hns_roce_cmq_desc desc;
1861         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1862         struct hns_roce_caps *caps = &hr_dev->caps;
1863
1864         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, false);
1865
1866         hr_reg_write(req, EXT_CFG_VF_ID, vf_id);
1867
1868         hr_reg_write(req, EXT_CFG_QP_PI_NUM, caps->num_pi_qps);
1869         hr_reg_write(req, EXT_CFG_QP_PI_IDX, vf_id * caps->num_pi_qps);
1870         hr_reg_write(req, EXT_CFG_QP_NUM, caps->num_qps);
1871         hr_reg_write(req, EXT_CFG_QP_IDX, vf_id * caps->num_qps);
1872
1873         return hns_roce_cmq_send(hr_dev, &desc, 1);
1874 }
1875
1876 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1877 {
1878         u32 func_num = max_t(u32, 1, hr_dev->func_num);
1879         u32 vf_id;
1880         int ret;
1881
1882         for (vf_id = 0; vf_id < func_num; vf_id++) {
1883                 ret = config_vf_hem_resource(hr_dev, vf_id);
1884                 if (ret) {
1885                         dev_err(hr_dev->dev,
1886                                 "failed to config vf-%u hem res, ret = %d.\n",
1887                                 vf_id, ret);
1888                         return ret;
1889                 }
1890
1891                 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1892                         ret = config_vf_ext_resource(hr_dev, vf_id);
1893                         if (ret) {
1894                                 dev_err(hr_dev->dev,
1895                                         "failed to config vf-%u ext res, ret = %d.\n",
1896                                         vf_id, ret);
1897                                 return ret;
1898                         }
1899                 }
1900         }
1901
1902         return 0;
1903 }
1904
1905 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1906 {
1907         struct hns_roce_cmq_desc desc;
1908         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1909         struct hns_roce_caps *caps = &hr_dev->caps;
1910
1911         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1912
1913         hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ,
1914                      caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET);
1915         hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ,
1916                      caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET);
1917         hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM,
1918                      to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps));
1919
1920         hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ,
1921                      caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET);
1922         hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ,
1923                      caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET);
1924         hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM,
1925                      to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs));
1926
1927         hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ,
1928                      caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET);
1929         hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ,
1930                      caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET);
1931         hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM,
1932                      to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs));
1933
1934         hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ,
1935                      caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET);
1936         hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ,
1937                      caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET);
1938         hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM,
1939                      to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts));
1940
1941         hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ,
1942                      caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1943         hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ,
1944                      caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1945         hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM,
1946                      to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps));
1947
1948         return hns_roce_cmq_send(hr_dev, &desc, 1);
1949 }
1950
1951 /* Use default caps when hns_roce_query_pf_caps() failed or init VF profile */
1952 static void set_default_caps(struct hns_roce_dev *hr_dev)
1953 {
1954         struct hns_roce_caps *caps = &hr_dev->caps;
1955
1956         caps->num_qps           = HNS_ROCE_V2_MAX_QP_NUM;
1957         caps->max_wqes          = HNS_ROCE_V2_MAX_WQE_NUM;
1958         caps->num_cqs           = HNS_ROCE_V2_MAX_CQ_NUM;
1959         caps->num_srqs          = HNS_ROCE_V2_MAX_SRQ_NUM;
1960         caps->min_cqes          = HNS_ROCE_MIN_CQE_NUM;
1961         caps->max_cqes          = HNS_ROCE_V2_MAX_CQE_NUM;
1962         caps->max_sq_sg         = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
1963         caps->max_rq_sg         = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1964
1965         caps->num_uars          = HNS_ROCE_V2_UAR_NUM;
1966         caps->phy_num_uars      = HNS_ROCE_V2_PHY_UAR_NUM;
1967         caps->num_aeq_vectors   = HNS_ROCE_V2_AEQE_VEC_NUM;
1968         caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
1969         caps->num_comp_vectors  = 0;
1970
1971         caps->num_mtpts         = HNS_ROCE_V2_MAX_MTPT_NUM;
1972         caps->num_pds           = HNS_ROCE_V2_MAX_PD_NUM;
1973         caps->qpc_timer_bt_num  = HNS_ROCE_V2_MAX_QPC_TIMER_BT_NUM;
1974         caps->cqc_timer_bt_num  = HNS_ROCE_V2_MAX_CQC_TIMER_BT_NUM;
1975
1976         caps->max_qp_init_rdma  = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1977         caps->max_qp_dest_rdma  = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1978         caps->max_sq_desc_sz    = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1979         caps->max_rq_desc_sz    = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1980         caps->irrl_entry_sz     = HNS_ROCE_V2_IRRL_ENTRY_SZ;
1981         caps->trrl_entry_sz     = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ;
1982         caps->cqc_entry_sz      = HNS_ROCE_V2_CQC_ENTRY_SZ;
1983         caps->srqc_entry_sz     = HNS_ROCE_V2_SRQC_ENTRY_SZ;
1984         caps->mtpt_entry_sz     = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1985         caps->idx_entry_sz      = HNS_ROCE_V2_IDX_ENTRY_SZ;
1986         caps->page_size_cap     = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1987         caps->reserved_lkey     = 0;
1988         caps->reserved_pds      = 0;
1989         caps->reserved_mrws     = 1;
1990         caps->reserved_uars     = 0;
1991         caps->reserved_cqs      = 0;
1992         caps->reserved_srqs     = 0;
1993         caps->reserved_qps      = HNS_ROCE_V2_RSV_QPS;
1994
1995         caps->qpc_hop_num       = HNS_ROCE_CONTEXT_HOP_NUM;
1996         caps->srqc_hop_num      = HNS_ROCE_CONTEXT_HOP_NUM;
1997         caps->cqc_hop_num       = HNS_ROCE_CONTEXT_HOP_NUM;
1998         caps->mpt_hop_num       = HNS_ROCE_CONTEXT_HOP_NUM;
1999         caps->sccc_hop_num      = HNS_ROCE_SCCC_HOP_NUM;
2000
2001         caps->mtt_hop_num       = HNS_ROCE_MTT_HOP_NUM;
2002         caps->wqe_sq_hop_num    = HNS_ROCE_SQWQE_HOP_NUM;
2003         caps->wqe_sge_hop_num   = HNS_ROCE_EXT_SGE_HOP_NUM;
2004         caps->wqe_rq_hop_num    = HNS_ROCE_RQWQE_HOP_NUM;
2005         caps->cqe_hop_num       = HNS_ROCE_CQE_HOP_NUM;
2006         caps->srqwqe_hop_num    = HNS_ROCE_SRQWQE_HOP_NUM;
2007         caps->idx_hop_num       = HNS_ROCE_IDX_HOP_NUM;
2008         caps->chunk_sz          = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
2009
2010         caps->flags             = HNS_ROCE_CAP_FLAG_REREG_MR |
2011                                   HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
2012                                   HNS_ROCE_CAP_FLAG_CQ_RECORD_DB |
2013                                   HNS_ROCE_CAP_FLAG_QP_RECORD_DB;
2014
2015         caps->pkey_table_len[0] = 1;
2016         caps->ceqe_depth        = HNS_ROCE_V2_COMP_EQE_NUM;
2017         caps->aeqe_depth        = HNS_ROCE_V2_ASYNC_EQE_NUM;
2018         caps->local_ca_ack_delay = 0;
2019         caps->max_mtu = IB_MTU_4096;
2020
2021         caps->max_srq_wrs       = HNS_ROCE_V2_MAX_SRQ_WR;
2022         caps->max_srq_sges      = HNS_ROCE_V2_MAX_SRQ_SGE;
2023
2024         caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW |
2025                        HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR |
2026                        HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL | HNS_ROCE_CAP_FLAG_XRC;
2027
2028         caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
2029
2030         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2031                 caps->flags |= HNS_ROCE_CAP_FLAG_STASH |
2032                                HNS_ROCE_CAP_FLAG_DIRECT_WQE;
2033                 caps->max_sq_inline = HNS_ROCE_V3_MAX_SQ_INLINE;
2034         } else {
2035                 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
2036
2037                 /* The following configuration are only valid for HIP08 */
2038                 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ;
2039                 caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ;
2040                 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE;
2041         }
2042 }
2043
2044 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num,
2045                        u32 *buf_page_size, u32 *bt_page_size, u32 hem_type)
2046 {
2047         u64 obj_per_chunk;
2048         u64 bt_chunk_size = PAGE_SIZE;
2049         u64 buf_chunk_size = PAGE_SIZE;
2050         u64 obj_per_chunk_default = buf_chunk_size / obj_size;
2051
2052         *buf_page_size = 0;
2053         *bt_page_size = 0;
2054
2055         switch (hop_num) {
2056         case 3:
2057                 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2058                                 (bt_chunk_size / BA_BYTE_LEN) *
2059                                 (bt_chunk_size / BA_BYTE_LEN) *
2060                                  obj_per_chunk_default;
2061                 break;
2062         case 2:
2063                 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2064                                 (bt_chunk_size / BA_BYTE_LEN) *
2065                                  obj_per_chunk_default;
2066                 break;
2067         case 1:
2068                 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2069                                 obj_per_chunk_default;
2070                 break;
2071         case HNS_ROCE_HOP_NUM_0:
2072                 obj_per_chunk = ctx_bt_num * obj_per_chunk_default;
2073                 break;
2074         default:
2075                 pr_err("table %u not support hop_num = %u!\n", hem_type,
2076                        hop_num);
2077                 return;
2078         }
2079
2080         if (hem_type >= HEM_TYPE_MTT)
2081                 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
2082         else
2083                 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
2084 }
2085
2086 static void set_hem_page_size(struct hns_roce_dev *hr_dev)
2087 {
2088         struct hns_roce_caps *caps = &hr_dev->caps;
2089
2090         /* EQ */
2091         caps->eqe_ba_pg_sz = 0;
2092         caps->eqe_buf_pg_sz = 0;
2093
2094         /* Link Table */
2095         caps->llm_buf_pg_sz = 0;
2096
2097         /* MR */
2098         caps->mpt_ba_pg_sz = 0;
2099         caps->mpt_buf_pg_sz = 0;
2100         caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K;
2101         caps->pbl_buf_pg_sz = 0;
2102         calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
2103                    caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
2104                    HEM_TYPE_MTPT);
2105
2106         /* QP */
2107         caps->qpc_ba_pg_sz = 0;
2108         caps->qpc_buf_pg_sz = 0;
2109         caps->qpc_timer_ba_pg_sz = 0;
2110         caps->qpc_timer_buf_pg_sz = 0;
2111         caps->sccc_ba_pg_sz = 0;
2112         caps->sccc_buf_pg_sz = 0;
2113         caps->mtt_ba_pg_sz = 0;
2114         caps->mtt_buf_pg_sz = 0;
2115         calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num,
2116                    caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
2117                    HEM_TYPE_QPC);
2118
2119         if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
2120                 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num,
2121                            caps->sccc_bt_num, &caps->sccc_buf_pg_sz,
2122                            &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC);
2123
2124         /* CQ */
2125         caps->cqc_ba_pg_sz = 0;
2126         caps->cqc_buf_pg_sz = 0;
2127         caps->cqc_timer_ba_pg_sz = 0;
2128         caps->cqc_timer_buf_pg_sz = 0;
2129         caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
2130         caps->cqe_buf_pg_sz = 0;
2131         calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
2132                    caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
2133                    HEM_TYPE_CQC);
2134         calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num,
2135                    1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
2136
2137         /* SRQ */
2138         if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) {
2139                 caps->srqc_ba_pg_sz = 0;
2140                 caps->srqc_buf_pg_sz = 0;
2141                 caps->srqwqe_ba_pg_sz = 0;
2142                 caps->srqwqe_buf_pg_sz = 0;
2143                 caps->idx_ba_pg_sz = 0;
2144                 caps->idx_buf_pg_sz = 0;
2145                 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz,
2146                            caps->srqc_hop_num, caps->srqc_bt_num,
2147                            &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz,
2148                            HEM_TYPE_SRQC);
2149                 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
2150                            caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
2151                            &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
2152                 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz,
2153                            caps->idx_hop_num, 1, &caps->idx_buf_pg_sz,
2154                            &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
2155         }
2156
2157         /* GMV */
2158         caps->gmv_ba_pg_sz = 0;
2159         caps->gmv_buf_pg_sz = 0;
2160 }
2161
2162 /* Apply all loaded caps before setting to hardware */
2163 static void apply_func_caps(struct hns_roce_dev *hr_dev)
2164 {
2165         struct hns_roce_caps *caps = &hr_dev->caps;
2166         struct hns_roce_v2_priv *priv = hr_dev->priv;
2167
2168         /* The following configurations don't need to be got from firmware. */
2169         caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
2170         caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
2171         caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
2172
2173         caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
2174         caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2175         caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2176
2177         caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM;
2178         caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM;
2179
2180         caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
2181         caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
2182
2183         if (!caps->num_comp_vectors)
2184                 caps->num_comp_vectors =
2185                         min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM,
2186                                 (u32)priv->handle->rinfo.num_vectors -
2187                 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM));
2188
2189         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2190                 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM;
2191                 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
2192                 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
2193
2194                 /* The following configurations will be overwritten */
2195                 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
2196                 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE;
2197                 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ;
2198
2199                 /* The following configurations are not got from firmware */
2200                 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ;
2201
2202                 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0;
2203                 caps->gid_table_len[0] = caps->gmv_bt_num *
2204                                         (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz);
2205
2206                 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE /
2207                                                           caps->gmv_entry_sz);
2208         } else {
2209                 u32 func_num = max_t(u32, 1, hr_dev->func_num);
2210
2211                 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM;
2212                 caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
2213                 caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
2214                 caps->gid_table_len[0] /= func_num;
2215         }
2216
2217         if (hr_dev->is_vf) {
2218                 caps->default_aeq_arm_st = 0x3;
2219                 caps->default_ceq_arm_st = 0x3;
2220                 caps->default_ceq_max_cnt = 0x1;
2221                 caps->default_ceq_period = 0x10;
2222                 caps->default_aeq_max_cnt = 0x1;
2223                 caps->default_aeq_period = 0x10;
2224         }
2225
2226         set_hem_page_size(hr_dev);
2227 }
2228
2229 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
2230 {
2231         struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM];
2232         struct hns_roce_caps *caps = &hr_dev->caps;
2233         struct hns_roce_query_pf_caps_a *resp_a;
2234         struct hns_roce_query_pf_caps_b *resp_b;
2235         struct hns_roce_query_pf_caps_c *resp_c;
2236         struct hns_roce_query_pf_caps_d *resp_d;
2237         struct hns_roce_query_pf_caps_e *resp_e;
2238         int ctx_hop_num;
2239         int pbl_hop_num;
2240         int ret;
2241         int i;
2242
2243         for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) {
2244                 hns_roce_cmq_setup_basic_desc(&desc[i],
2245                                               HNS_ROCE_OPC_QUERY_PF_CAPS_NUM,
2246                                               true);
2247                 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1))
2248                         desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2249                 else
2250                         desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2251         }
2252
2253         ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM);
2254         if (ret)
2255                 return ret;
2256
2257         resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data;
2258         resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data;
2259         resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data;
2260         resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data;
2261         resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data;
2262
2263         caps->local_ca_ack_delay     = resp_a->local_ca_ack_delay;
2264         caps->max_sq_sg              = le16_to_cpu(resp_a->max_sq_sg);
2265         caps->max_sq_inline          = le16_to_cpu(resp_a->max_sq_inline);
2266         caps->max_rq_sg              = le16_to_cpu(resp_a->max_rq_sg);
2267         caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg);
2268         caps->max_srq_sges           = le16_to_cpu(resp_a->max_srq_sges);
2269         caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges);
2270         caps->num_aeq_vectors        = resp_a->num_aeq_vectors;
2271         caps->num_other_vectors      = resp_a->num_other_vectors;
2272         caps->max_sq_desc_sz         = resp_a->max_sq_desc_sz;
2273         caps->max_rq_desc_sz         = resp_a->max_rq_desc_sz;
2274         caps->cqe_sz                 = resp_a->cqe_sz;
2275
2276         caps->mtpt_entry_sz          = resp_b->mtpt_entry_sz;
2277         caps->irrl_entry_sz          = resp_b->irrl_entry_sz;
2278         caps->trrl_entry_sz          = resp_b->trrl_entry_sz;
2279         caps->cqc_entry_sz           = resp_b->cqc_entry_sz;
2280         caps->srqc_entry_sz          = resp_b->srqc_entry_sz;
2281         caps->idx_entry_sz           = resp_b->idx_entry_sz;
2282         caps->sccc_sz                = resp_b->sccc_sz;
2283         caps->max_mtu                = resp_b->max_mtu;
2284         caps->qpc_sz                 = le16_to_cpu(resp_b->qpc_sz);
2285         caps->min_cqes               = resp_b->min_cqes;
2286         caps->min_wqes               = resp_b->min_wqes;
2287         caps->page_size_cap          = le32_to_cpu(resp_b->page_size_cap);
2288         caps->pkey_table_len[0]      = resp_b->pkey_table_len;
2289         caps->phy_num_uars           = resp_b->phy_num_uars;
2290         ctx_hop_num                  = resp_b->ctx_hop_num;
2291         pbl_hop_num                  = resp_b->pbl_hop_num;
2292
2293         caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS);
2294
2295         caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS);
2296         caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) <<
2297                        HNS_ROCE_CAP_FLAGS_EX_SHIFT;
2298
2299         caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS);
2300         caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID);
2301         caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH);
2302         caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS);
2303         caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS);
2304         caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD);
2305         caps->max_qp_dest_rdma = caps->max_qp_init_rdma;
2306         caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);
2307
2308         caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS);
2309         caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE);
2310         caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);
2311         caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH);
2312         caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS);
2313         caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH);
2314         caps->default_aeq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST);
2315         caps->default_ceq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST);
2316         caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS);
2317         caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS);
2318         caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS);
2319         caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS);
2320
2321         caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS);
2322         caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT);
2323         caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS);
2324         caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS);
2325         caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS);
2326         caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);
2327         caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);
2328         caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
2329         caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);
2330
2331         caps->qpc_hop_num = ctx_hop_num;
2332         caps->sccc_hop_num = ctx_hop_num;
2333         caps->srqc_hop_num = ctx_hop_num;
2334         caps->cqc_hop_num = ctx_hop_num;
2335         caps->mpt_hop_num = ctx_hop_num;
2336         caps->mtt_hop_num = pbl_hop_num;
2337         caps->cqe_hop_num = pbl_hop_num;
2338         caps->srqwqe_hop_num = pbl_hop_num;
2339         caps->idx_hop_num = pbl_hop_num;
2340         caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM);
2341         caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM);
2342         caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM);
2343
2344         return 0;
2345 }
2346
2347 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val)
2348 {
2349         struct hns_roce_cmq_desc desc;
2350         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
2351
2352         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE,
2353                                       false);
2354
2355         hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type);
2356         hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val);
2357
2358         return hns_roce_cmq_send(hr_dev, &desc, 1);
2359 }
2360
2361 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev)
2362 {
2363         struct hns_roce_caps *caps = &hr_dev->caps;
2364         int ret;
2365
2366         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
2367                 return 0;
2368
2369         ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE,
2370                                     caps->qpc_sz);
2371         if (ret) {
2372                 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret);
2373                 return ret;
2374         }
2375
2376         ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE,
2377                                     caps->sccc_sz);
2378         if (ret)
2379                 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret);
2380
2381         return ret;
2382 }
2383
2384 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev)
2385 {
2386         struct device *dev = hr_dev->dev;
2387         int ret;
2388
2389         hr_dev->func_num = 1;
2390
2391         set_default_caps(hr_dev);
2392
2393         ret = hns_roce_query_vf_resource(hr_dev);
2394         if (ret) {
2395                 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret);
2396                 return ret;
2397         }
2398
2399         apply_func_caps(hr_dev);
2400
2401         ret = hns_roce_v2_set_bt(hr_dev);
2402         if (ret)
2403                 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret);
2404
2405         return ret;
2406 }
2407
2408 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev)
2409 {
2410         struct device *dev = hr_dev->dev;
2411         int ret;
2412
2413         ret = hns_roce_query_func_info(hr_dev);
2414         if (ret) {
2415                 dev_err(dev, "failed to query func info, ret = %d.\n", ret);
2416                 return ret;
2417         }
2418
2419         ret = hns_roce_config_global_param(hr_dev);
2420         if (ret) {
2421                 dev_err(dev, "failed to config global param, ret = %d.\n", ret);
2422                 return ret;
2423         }
2424
2425         ret = hns_roce_set_vf_switch_param(hr_dev);
2426         if (ret) {
2427                 dev_err(dev, "failed to set switch param, ret = %d.\n", ret);
2428                 return ret;
2429         }
2430
2431         ret = hns_roce_query_pf_caps(hr_dev);
2432         if (ret)
2433                 set_default_caps(hr_dev);
2434
2435         ret = hns_roce_query_pf_resource(hr_dev);
2436         if (ret) {
2437                 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret);
2438                 return ret;
2439         }
2440
2441         apply_func_caps(hr_dev);
2442
2443         ret = hns_roce_alloc_vf_resource(hr_dev);
2444         if (ret) {
2445                 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret);
2446                 return ret;
2447         }
2448
2449         ret = hns_roce_v2_set_bt(hr_dev);
2450         if (ret) {
2451                 dev_err(dev, "failed to config BA table, ret = %d.\n", ret);
2452                 return ret;
2453         }
2454
2455         /* Configure the size of QPC, SCCC, etc. */
2456         return hns_roce_config_entry_size(hr_dev);
2457 }
2458
2459 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
2460 {
2461         struct device *dev = hr_dev->dev;
2462         int ret;
2463
2464         ret = hns_roce_cmq_query_hw_info(hr_dev);
2465         if (ret) {
2466                 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret);
2467                 return ret;
2468         }
2469
2470         ret = hns_roce_query_fw_ver(hr_dev);
2471         if (ret) {
2472                 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret);
2473                 return ret;
2474         }
2475
2476         hr_dev->vendor_part_id = hr_dev->pci_dev->device;
2477         hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
2478
2479         if (hr_dev->is_vf)
2480                 return hns_roce_v2_vf_profile(hr_dev);
2481         else
2482                 return hns_roce_v2_pf_profile(hr_dev);
2483 }
2484
2485 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf)
2486 {
2487         u32 i, next_ptr, page_num;
2488         __le64 *entry = cfg_buf;
2489         dma_addr_t addr;
2490         u64 val;
2491
2492         page_num = data_buf->npages;
2493         for (i = 0; i < page_num; i++) {
2494                 addr = hns_roce_buf_page(data_buf, i);
2495                 if (i == (page_num - 1))
2496                         next_ptr = 0;
2497                 else
2498                         next_ptr = i + 1;
2499
2500                 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr);
2501                 entry[i] = cpu_to_le64(val);
2502         }
2503 }
2504
2505 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev,
2506                              struct hns_roce_link_table *table)
2507 {
2508         struct hns_roce_cmq_desc desc[2];
2509         struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
2510         struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
2511         struct hns_roce_buf *buf = table->buf;
2512         enum hns_roce_opcode_type opcode;
2513         dma_addr_t addr;
2514
2515         opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
2516         hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
2517         desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2518         hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
2519
2520         hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map));
2521         hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map));
2522         hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages);
2523         hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift));
2524         hr_reg_enable(r_a, CFG_LLM_A_INIT_EN);
2525
2526         addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0));
2527         hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr));
2528         hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr));
2529         hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1);
2530         hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0);
2531
2532         addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1));
2533         hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr));
2534         hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr));
2535         hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1);
2536
2537         return hns_roce_cmq_send(hr_dev, desc, 2);
2538 }
2539
2540 static struct hns_roce_link_table *
2541 alloc_link_table_buf(struct hns_roce_dev *hr_dev)
2542 {
2543         struct hns_roce_v2_priv *priv = hr_dev->priv;
2544         struct hns_roce_link_table *link_tbl;
2545         u32 pg_shift, size, min_size;
2546
2547         link_tbl = &priv->ext_llm;
2548         pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT;
2549         size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ;
2550         min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift;
2551
2552         /* Alloc data table */
2553         size = max(size, min_size);
2554         link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0);
2555         if (IS_ERR(link_tbl->buf))
2556                 return ERR_PTR(-ENOMEM);
2557
2558         /* Alloc config table */
2559         size = link_tbl->buf->npages * sizeof(u64);
2560         link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size,
2561                                                  &link_tbl->table.map,
2562                                                  GFP_KERNEL);
2563         if (!link_tbl->table.buf) {
2564                 hns_roce_buf_free(hr_dev, link_tbl->buf);
2565                 return ERR_PTR(-ENOMEM);
2566         }
2567
2568         return link_tbl;
2569 }
2570
2571 static void free_link_table_buf(struct hns_roce_dev *hr_dev,
2572                                 struct hns_roce_link_table *tbl)
2573 {
2574         if (tbl->buf) {
2575                 u32 size = tbl->buf->npages * sizeof(u64);
2576
2577                 dma_free_coherent(hr_dev->dev, size, tbl->table.buf,
2578                                   tbl->table.map);
2579         }
2580
2581         hns_roce_buf_free(hr_dev, tbl->buf);
2582 }
2583
2584 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev)
2585 {
2586         struct hns_roce_link_table *link_tbl;
2587         int ret;
2588
2589         link_tbl = alloc_link_table_buf(hr_dev);
2590         if (IS_ERR(link_tbl))
2591                 return -ENOMEM;
2592
2593         if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) {
2594                 ret = -EINVAL;
2595                 goto err_alloc;
2596         }
2597
2598         config_llm_table(link_tbl->buf, link_tbl->table.buf);
2599         ret = set_llm_cfg_to_hw(hr_dev, link_tbl);
2600         if (ret)
2601                 goto err_alloc;
2602
2603         return 0;
2604
2605 err_alloc:
2606         free_link_table_buf(hr_dev, link_tbl);
2607         return ret;
2608 }
2609
2610 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev)
2611 {
2612         struct hns_roce_v2_priv *priv = hr_dev->priv;
2613
2614         free_link_table_buf(hr_dev, &priv->ext_llm);
2615 }
2616
2617 static void free_dip_list(struct hns_roce_dev *hr_dev)
2618 {
2619         struct hns_roce_dip *hr_dip;
2620         struct hns_roce_dip *tmp;
2621         unsigned long flags;
2622
2623         spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
2624
2625         list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) {
2626                 list_del(&hr_dip->node);
2627                 kfree(hr_dip);
2628         }
2629
2630         spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
2631 }
2632
2633 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev)
2634 {
2635         struct hns_roce_v2_priv *priv = hr_dev->priv;
2636         struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2637         struct ib_device *ibdev = &hr_dev->ib_dev;
2638         struct hns_roce_pd *hr_pd;
2639         struct ib_pd *pd;
2640
2641         hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL);
2642         if (ZERO_OR_NULL_PTR(hr_pd))
2643                 return NULL;
2644         pd = &hr_pd->ibpd;
2645         pd->device = ibdev;
2646
2647         if (hns_roce_alloc_pd(pd, NULL)) {
2648                 ibdev_err(ibdev, "failed to create pd for free mr.\n");
2649                 kfree(hr_pd);
2650                 return NULL;
2651         }
2652         free_mr->rsv_pd = to_hr_pd(pd);
2653         free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev;
2654         free_mr->rsv_pd->ibpd.uobject = NULL;
2655         free_mr->rsv_pd->ibpd.__internal_mr = NULL;
2656         atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0);
2657
2658         return pd;
2659 }
2660
2661 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev)
2662 {
2663         struct hns_roce_v2_priv *priv = hr_dev->priv;
2664         struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2665         struct ib_device *ibdev = &hr_dev->ib_dev;
2666         struct ib_cq_init_attr cq_init_attr = {};
2667         struct hns_roce_cq *hr_cq;
2668         struct ib_cq *cq;
2669
2670         cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM;
2671
2672         hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL);
2673         if (ZERO_OR_NULL_PTR(hr_cq))
2674                 return NULL;
2675
2676         cq = &hr_cq->ib_cq;
2677         cq->device = ibdev;
2678
2679         if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) {
2680                 ibdev_err(ibdev, "failed to create cq for free mr.\n");
2681                 kfree(hr_cq);
2682                 return NULL;
2683         }
2684         free_mr->rsv_cq = to_hr_cq(cq);
2685         free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev;
2686         free_mr->rsv_cq->ib_cq.uobject = NULL;
2687         free_mr->rsv_cq->ib_cq.comp_handler = NULL;
2688         free_mr->rsv_cq->ib_cq.event_handler = NULL;
2689         free_mr->rsv_cq->ib_cq.cq_context = NULL;
2690         atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0);
2691
2692         return cq;
2693 }
2694
2695 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq,
2696                            struct ib_qp_init_attr *init_attr, int i)
2697 {
2698         struct hns_roce_v2_priv *priv = hr_dev->priv;
2699         struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2700         struct ib_device *ibdev = &hr_dev->ib_dev;
2701         struct hns_roce_qp *hr_qp;
2702         struct ib_qp *qp;
2703         int ret;
2704
2705         hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL);
2706         if (ZERO_OR_NULL_PTR(hr_qp))
2707                 return -ENOMEM;
2708
2709         qp = &hr_qp->ibqp;
2710         qp->device = ibdev;
2711
2712         ret = hns_roce_create_qp(qp, init_attr, NULL);
2713         if (ret) {
2714                 ibdev_err(ibdev, "failed to create qp for free mr.\n");
2715                 kfree(hr_qp);
2716                 return ret;
2717         }
2718
2719         free_mr->rsv_qp[i] = hr_qp;
2720         free_mr->rsv_qp[i]->ibqp.recv_cq = cq;
2721         free_mr->rsv_qp[i]->ibqp.send_cq = cq;
2722
2723         return 0;
2724 }
2725
2726 static void free_mr_exit(struct hns_roce_dev *hr_dev)
2727 {
2728         struct hns_roce_v2_priv *priv = hr_dev->priv;
2729         struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2730         struct ib_qp *qp;
2731         int i;
2732
2733         for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2734                 if (free_mr->rsv_qp[i]) {
2735                         qp = &free_mr->rsv_qp[i]->ibqp;
2736                         hns_roce_v2_destroy_qp(qp, NULL);
2737                         kfree(free_mr->rsv_qp[i]);
2738                         free_mr->rsv_qp[i] = NULL;
2739                 }
2740         }
2741
2742         if (free_mr->rsv_cq) {
2743                 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL);
2744                 kfree(free_mr->rsv_cq);
2745                 free_mr->rsv_cq = NULL;
2746         }
2747
2748         if (free_mr->rsv_pd) {
2749                 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL);
2750                 kfree(free_mr->rsv_pd);
2751                 free_mr->rsv_pd = NULL;
2752         }
2753 }
2754
2755 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev)
2756 {
2757         struct hns_roce_v2_priv *priv = hr_dev->priv;
2758         struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2759         struct ib_qp_init_attr qp_init_attr = {};
2760         struct ib_pd *pd;
2761         struct ib_cq *cq;
2762         int ret;
2763         int i;
2764
2765         pd = free_mr_init_pd(hr_dev);
2766         if (!pd)
2767                 return -ENOMEM;
2768
2769         cq = free_mr_init_cq(hr_dev);
2770         if (!cq) {
2771                 ret = -ENOMEM;
2772                 goto create_failed_cq;
2773         }
2774
2775         qp_init_attr.qp_type = IB_QPT_RC;
2776         qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
2777         qp_init_attr.send_cq = cq;
2778         qp_init_attr.recv_cq = cq;
2779         for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2780                 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM;
2781                 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM;
2782                 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM;
2783                 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM;
2784
2785                 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i);
2786                 if (ret)
2787                         goto create_failed_qp;
2788         }
2789
2790         return 0;
2791
2792 create_failed_qp:
2793         hns_roce_destroy_cq(cq, NULL);
2794         kfree(cq);
2795
2796 create_failed_cq:
2797         hns_roce_dealloc_pd(pd, NULL);
2798         kfree(pd);
2799
2800         return ret;
2801 }
2802
2803 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev,
2804                                  struct ib_qp_attr *attr, int sl_num)
2805 {
2806         struct hns_roce_v2_priv *priv = hr_dev->priv;
2807         struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2808         struct ib_device *ibdev = &hr_dev->ib_dev;
2809         struct hns_roce_qp *hr_qp;
2810         int loopback;
2811         int mask;
2812         int ret;
2813
2814         hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp);
2815         hr_qp->free_mr_en = 1;
2816         hr_qp->ibqp.device = ibdev;
2817         hr_qp->ibqp.qp_type = IB_QPT_RC;
2818
2819         mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS;
2820         attr->qp_state = IB_QPS_INIT;
2821         attr->port_num = 1;
2822         attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE;
2823         ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT,
2824                                     IB_QPS_INIT);
2825         if (ret) {
2826                 ibdev_err(ibdev, "failed to modify qp to init, ret = %d.\n",
2827                           ret);
2828                 return ret;
2829         }
2830
2831         loopback = hr_dev->loop_idc;
2832         /* Set qpc lbi = 1 incidate loopback IO */
2833         hr_dev->loop_idc = 1;
2834
2835         mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN |
2836                IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER;
2837         attr->qp_state = IB_QPS_RTR;
2838         attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2839         attr->path_mtu = IB_MTU_256;
2840         attr->dest_qp_num = hr_qp->qpn;
2841         attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2842
2843         rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num);
2844
2845         ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT,
2846                                     IB_QPS_RTR);
2847         hr_dev->loop_idc = loopback;
2848         if (ret) {
2849                 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n",
2850                           ret);
2851                 return ret;
2852         }
2853
2854         mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT |
2855                IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC;
2856         attr->qp_state = IB_QPS_RTS;
2857         attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2858         attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT;
2859         attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT;
2860         ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR,
2861                                     IB_QPS_RTS);
2862         if (ret)
2863                 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n",
2864                           ret);
2865
2866         return ret;
2867 }
2868
2869 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev)
2870 {
2871         struct hns_roce_v2_priv *priv = hr_dev->priv;
2872         struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2873         struct ib_qp_attr attr = {};
2874         int ret;
2875         int i;
2876
2877         rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
2878         rdma_ah_set_static_rate(&attr.ah_attr, 3);
2879         rdma_ah_set_port_num(&attr.ah_attr, 1);
2880
2881         for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2882                 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i);
2883                 if (ret)
2884                         return ret;
2885         }
2886
2887         return 0;
2888 }
2889
2890 static int free_mr_init(struct hns_roce_dev *hr_dev)
2891 {
2892         struct hns_roce_v2_priv *priv = hr_dev->priv;
2893         struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2894         int ret;
2895
2896         mutex_init(&free_mr->mutex);
2897
2898         ret = free_mr_alloc_res(hr_dev);
2899         if (ret)
2900                 return ret;
2901
2902         ret = free_mr_modify_qp(hr_dev);
2903         if (ret)
2904                 goto err_modify_qp;
2905
2906         return 0;
2907
2908 err_modify_qp:
2909         free_mr_exit(hr_dev);
2910
2911         return ret;
2912 }
2913
2914 static int get_hem_table(struct hns_roce_dev *hr_dev)
2915 {
2916         unsigned int qpc_count;
2917         unsigned int cqc_count;
2918         unsigned int gmv_count;
2919         int ret;
2920         int i;
2921
2922         /* Alloc memory for source address table buffer space chunk */
2923         for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num;
2924              gmv_count++) {
2925                 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count);
2926                 if (ret)
2927                         goto err_gmv_failed;
2928         }
2929
2930         if (hr_dev->is_vf)
2931                 return 0;
2932
2933         /* Alloc memory for QPC Timer buffer space chunk */
2934         for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
2935              qpc_count++) {
2936                 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
2937                                          qpc_count);
2938                 if (ret) {
2939                         dev_err(hr_dev->dev, "QPC Timer get failed\n");
2940                         goto err_qpc_timer_failed;
2941                 }
2942         }
2943
2944         /* Alloc memory for CQC Timer buffer space chunk */
2945         for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
2946              cqc_count++) {
2947                 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
2948                                          cqc_count);
2949                 if (ret) {
2950                         dev_err(hr_dev->dev, "CQC Timer get failed\n");
2951                         goto err_cqc_timer_failed;
2952                 }
2953         }
2954
2955         return 0;
2956
2957 err_cqc_timer_failed:
2958         for (i = 0; i < cqc_count; i++)
2959                 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2960
2961 err_qpc_timer_failed:
2962         for (i = 0; i < qpc_count; i++)
2963                 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2964
2965 err_gmv_failed:
2966         for (i = 0; i < gmv_count; i++)
2967                 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2968
2969         return ret;
2970 }
2971
2972 static void put_hem_table(struct hns_roce_dev *hr_dev)
2973 {
2974         int i;
2975
2976         for (i = 0; i < hr_dev->caps.gmv_entry_num; i++)
2977                 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2978
2979         if (hr_dev->is_vf)
2980                 return;
2981
2982         for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++)
2983                 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2984
2985         for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++)
2986                 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2987 }
2988
2989 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
2990 {
2991         int ret;
2992
2993         /* The hns ROCEE requires the extdb info to be cleared before using */
2994         ret = hns_roce_clear_extdb_list_info(hr_dev);
2995         if (ret)
2996                 return ret;
2997
2998         ret = get_hem_table(hr_dev);
2999         if (ret)
3000                 return ret;
3001
3002         if (hr_dev->is_vf)
3003                 return 0;
3004
3005         ret = hns_roce_init_link_table(hr_dev);
3006         if (ret) {
3007                 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret);
3008                 goto err_llm_init_failed;
3009         }
3010
3011         return 0;
3012
3013 err_llm_init_failed:
3014         put_hem_table(hr_dev);
3015
3016         return ret;
3017 }
3018
3019 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
3020 {
3021         hns_roce_function_clear(hr_dev);
3022
3023         if (!hr_dev->is_vf)
3024                 hns_roce_free_link_table(hr_dev);
3025
3026         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09)
3027                 free_dip_list(hr_dev);
3028 }
3029
3030 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev,
3031                               struct hns_roce_mbox_msg *mbox_msg)
3032 {
3033         struct hns_roce_cmq_desc desc;
3034         struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
3035
3036         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
3037
3038         mb->in_param_l = cpu_to_le32(mbox_msg->in_param);
3039         mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32);
3040         mb->out_param_l = cpu_to_le32(mbox_msg->out_param);
3041         mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32);
3042         mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd);
3043         mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 |
3044                                          mbox_msg->token);
3045
3046         return hns_roce_cmq_send(hr_dev, &desc, 1);
3047 }
3048
3049 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout,
3050                                  u8 *complete_status)
3051 {
3052         struct hns_roce_mbox_status *mb_st;
3053         struct hns_roce_cmq_desc desc;
3054         unsigned long end;
3055         int ret = -EBUSY;
3056         u32 status;
3057         bool busy;
3058
3059         mb_st = (struct hns_roce_mbox_status *)desc.data;
3060         end = msecs_to_jiffies(timeout) + jiffies;
3061         while (v2_chk_mbox_is_avail(hr_dev, &busy)) {
3062                 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
3063                         return -EIO;
3064
3065                 status = 0;
3066                 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST,
3067                                               true);
3068                 ret = __hns_roce_cmq_send(hr_dev, &desc, 1);
3069                 if (!ret) {
3070                         status = le32_to_cpu(mb_st->mb_status_hw_run);
3071                         /* No pending message exists in ROCEE mbox. */
3072                         if (!(status & MB_ST_HW_RUN_M))
3073                                 break;
3074                 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
3075                         break;
3076                 }
3077
3078                 if (time_after(jiffies, end)) {
3079                         dev_err_ratelimited(hr_dev->dev,
3080                                             "failed to wait mbox status 0x%x\n",
3081                                             status);
3082                         return -ETIMEDOUT;
3083                 }
3084
3085                 cond_resched();
3086                 ret = -EBUSY;
3087         }
3088
3089         if (!ret) {
3090                 *complete_status = (u8)(status & MB_ST_COMPLETE_M);
3091         } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
3092                 /* Ignore all errors if the mbox is unavailable. */
3093                 ret = 0;
3094                 *complete_status = MB_ST_COMPLETE_M;
3095         }
3096
3097         return ret;
3098 }
3099
3100 static int v2_post_mbox(struct hns_roce_dev *hr_dev,
3101                         struct hns_roce_mbox_msg *mbox_msg)
3102 {
3103         u8 status = 0;
3104         int ret;
3105
3106         /* Waiting for the mbox to be idle */
3107         ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS,
3108                                     &status);
3109         if (unlikely(ret)) {
3110                 dev_err_ratelimited(hr_dev->dev,
3111                                     "failed to check post mbox status = 0x%x, ret = %d.\n",
3112                                     status, ret);
3113                 return ret;
3114         }
3115
3116         /* Post new message to mbox */
3117         ret = hns_roce_mbox_post(hr_dev, mbox_msg);
3118         if (ret)
3119                 dev_err_ratelimited(hr_dev->dev,
3120                                     "failed to post mailbox, ret = %d.\n", ret);
3121
3122         return ret;
3123 }
3124
3125 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev)
3126 {
3127         u8 status = 0;
3128         int ret;
3129
3130         ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS,
3131                                     &status);
3132         if (!ret) {
3133                 if (status != MB_ST_COMPLETE_SUCC)
3134                         return -EBUSY;
3135         } else {
3136                 dev_err_ratelimited(hr_dev->dev,
3137                                     "failed to check mbox status = 0x%x, ret = %d.\n",
3138                                     status, ret);
3139         }
3140
3141         return ret;
3142 }
3143
3144 static void copy_gid(void *dest, const union ib_gid *gid)
3145 {
3146 #define GID_SIZE 4
3147         const union ib_gid *src = gid;
3148         __le32 (*p)[GID_SIZE] = dest;
3149         int i;
3150
3151         if (!gid)
3152                 src = &zgid;
3153
3154         for (i = 0; i < GID_SIZE; i++)
3155                 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]);
3156 }
3157
3158 static int config_sgid_table(struct hns_roce_dev *hr_dev,
3159                              int gid_index, const union ib_gid *gid,
3160                              enum hns_roce_sgid_type sgid_type)
3161 {
3162         struct hns_roce_cmq_desc desc;
3163         struct hns_roce_cfg_sgid_tb *sgid_tb =
3164                                     (struct hns_roce_cfg_sgid_tb *)desc.data;
3165
3166         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
3167
3168         hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index);
3169         hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type);
3170
3171         copy_gid(&sgid_tb->vf_sgid_l, gid);
3172
3173         return hns_roce_cmq_send(hr_dev, &desc, 1);
3174 }
3175
3176 static int config_gmv_table(struct hns_roce_dev *hr_dev,
3177                             int gid_index, const union ib_gid *gid,
3178                             enum hns_roce_sgid_type sgid_type,
3179                             const struct ib_gid_attr *attr)
3180 {
3181         struct hns_roce_cmq_desc desc[2];
3182         struct hns_roce_cfg_gmv_tb_a *tb_a =
3183                                 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data;
3184         struct hns_roce_cfg_gmv_tb_b *tb_b =
3185                                 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data;
3186
3187         u16 vlan_id = VLAN_CFI_MASK;
3188         u8 mac[ETH_ALEN] = {};
3189         int ret;
3190
3191         if (gid) {
3192                 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac);
3193                 if (ret)
3194                         return ret;
3195         }
3196
3197         hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3198         desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
3199
3200         hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3201
3202         copy_gid(&tb_a->vf_sgid_l, gid);
3203
3204         hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type);
3205         hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK);
3206         hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id);
3207
3208         tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac);
3209
3210         hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]);
3211         hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index);
3212
3213         return hns_roce_cmq_send(hr_dev, desc, 2);
3214 }
3215
3216 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index,
3217                                const union ib_gid *gid,
3218                                const struct ib_gid_attr *attr)
3219 {
3220         enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
3221         int ret;
3222
3223         if (gid) {
3224                 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
3225                         if (ipv6_addr_v4mapped((void *)gid))
3226                                 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
3227                         else
3228                                 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
3229                 } else if (attr->gid_type == IB_GID_TYPE_ROCE) {
3230                         sgid_type = GID_TYPE_FLAG_ROCE_V1;
3231                 }
3232         }
3233
3234         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
3235                 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr);
3236         else
3237                 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type);
3238
3239         if (ret)
3240                 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n",
3241                           ret);
3242
3243         return ret;
3244 }
3245
3246 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
3247                                const u8 *addr)
3248 {
3249         struct hns_roce_cmq_desc desc;
3250         struct hns_roce_cfg_smac_tb *smac_tb =
3251                                     (struct hns_roce_cfg_smac_tb *)desc.data;
3252         u16 reg_smac_h;
3253         u32 reg_smac_l;
3254
3255         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
3256
3257         reg_smac_l = *(u32 *)(&addr[0]);
3258         reg_smac_h = *(u16 *)(&addr[4]);
3259
3260         hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port);
3261         hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h);
3262         smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l);
3263
3264         return hns_roce_cmq_send(hr_dev, &desc, 1);
3265 }
3266
3267 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev,
3268                         struct hns_roce_v2_mpt_entry *mpt_entry,
3269                         struct hns_roce_mr *mr)
3270 {
3271         u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 };
3272         struct ib_device *ibdev = &hr_dev->ib_dev;
3273         dma_addr_t pbl_ba;
3274         int i, count;
3275
3276         count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
3277                                   ARRAY_SIZE(pages), &pbl_ba);
3278         if (count < 1) {
3279                 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n",
3280                           count);
3281                 return -ENOBUFS;
3282         }
3283
3284         /* Aligned to the hardware address access unit */
3285         for (i = 0; i < count; i++)
3286                 pages[i] >>= 6;
3287
3288         mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3289         mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3);
3290         hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));
3291
3292         mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
3293         hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0]));
3294
3295         mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
3296         hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1]));
3297         hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3298                      to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3299
3300         return 0;
3301 }
3302
3303 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev,
3304                                   void *mb_buf, struct hns_roce_mr *mr)
3305 {
3306         struct hns_roce_v2_mpt_entry *mpt_entry;
3307
3308         mpt_entry = mb_buf;
3309         memset(mpt_entry, 0, sizeof(*mpt_entry));
3310
3311         hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3312         hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3313
3314         hr_reg_write_bool(mpt_entry, MPT_BIND_EN,
3315                           mr->access & IB_ACCESS_MW_BIND);
3316         hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN,
3317                           mr->access & IB_ACCESS_REMOTE_ATOMIC);
3318         hr_reg_write_bool(mpt_entry, MPT_RR_EN,
3319                           mr->access & IB_ACCESS_REMOTE_READ);
3320         hr_reg_write_bool(mpt_entry, MPT_RW_EN,
3321                           mr->access & IB_ACCESS_REMOTE_WRITE);
3322         hr_reg_write_bool(mpt_entry, MPT_LW_EN,
3323                           mr->access & IB_ACCESS_LOCAL_WRITE);
3324
3325         mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3326         mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3327         mpt_entry->lkey = cpu_to_le32(mr->key);
3328         mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3329         mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3330
3331         if (mr->type != MR_TYPE_MR)
3332                 hr_reg_enable(mpt_entry, MPT_PA);
3333
3334         if (mr->type == MR_TYPE_DMA)
3335                 return 0;
3336
3337         if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0)
3338                 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num);
3339
3340         hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3341                      to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3342         hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD);
3343
3344         return set_mtpt_pbl(hr_dev, mpt_entry, mr);
3345 }
3346
3347 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
3348                                         struct hns_roce_mr *mr, int flags,
3349                                         void *mb_buf)
3350 {
3351         struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
3352         u32 mr_access_flags = mr->access;
3353         int ret = 0;
3354
3355         hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3356         hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3357
3358         if (flags & IB_MR_REREG_ACCESS) {
3359                 hr_reg_write(mpt_entry, MPT_BIND_EN,
3360                              (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
3361                 hr_reg_write(mpt_entry, MPT_ATOMIC_EN,
3362                              mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3363                 hr_reg_write(mpt_entry, MPT_RR_EN,
3364                              mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
3365                 hr_reg_write(mpt_entry, MPT_RW_EN,
3366                              mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
3367                 hr_reg_write(mpt_entry, MPT_LW_EN,
3368                              mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
3369         }
3370
3371         if (flags & IB_MR_REREG_TRANS) {
3372                 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3373                 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3374                 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3375                 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3376
3377                 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
3378         }
3379
3380         return ret;
3381 }
3382
3383 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev,
3384                                        void *mb_buf, struct hns_roce_mr *mr)
3385 {
3386         struct ib_device *ibdev = &hr_dev->ib_dev;
3387         struct hns_roce_v2_mpt_entry *mpt_entry;
3388         dma_addr_t pbl_ba = 0;
3389
3390         mpt_entry = mb_buf;
3391         memset(mpt_entry, 0, sizeof(*mpt_entry));
3392
3393         if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) {
3394                 ibdev_err(ibdev, "failed to find frmr mtr.\n");
3395                 return -ENOBUFS;
3396         }
3397
3398         hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3399         hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3400
3401         hr_reg_enable(mpt_entry, MPT_RA_EN);
3402         hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3403
3404         hr_reg_enable(mpt_entry, MPT_FRE);
3405         hr_reg_clear(mpt_entry, MPT_MR_MW);
3406         hr_reg_enable(mpt_entry, MPT_BPD);
3407         hr_reg_clear(mpt_entry, MPT_PA);
3408
3409         hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1);
3410         hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3411                      to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3412         hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3413                      to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3414
3415         mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3416
3417         mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3));
3418         hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));
3419
3420         return 0;
3421 }
3422
3423 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
3424 {
3425         struct hns_roce_v2_mpt_entry *mpt_entry;
3426
3427         mpt_entry = mb_buf;
3428         memset(mpt_entry, 0, sizeof(*mpt_entry));
3429
3430         hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3431         hr_reg_write(mpt_entry, MPT_PD, mw->pdn);
3432
3433         hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3434         hr_reg_enable(mpt_entry, MPT_LW_EN);
3435
3436         hr_reg_enable(mpt_entry, MPT_MR_MW);
3437         hr_reg_enable(mpt_entry, MPT_BPD);
3438         hr_reg_clear(mpt_entry, MPT_PA);
3439         hr_reg_write(mpt_entry, MPT_BQP,
3440                      mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
3441
3442         mpt_entry->lkey = cpu_to_le32(mw->rkey);
3443
3444         hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM,
3445                      mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
3446                                                              mw->pbl_hop_num);
3447         hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3448                      mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3449         hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3450                      mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
3451
3452         return 0;
3453 }
3454
3455 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp)
3456 {
3457         struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
3458         struct ib_device *ibdev = &hr_dev->ib_dev;
3459         const struct ib_send_wr *bad_wr;
3460         struct ib_rdma_wr rdma_wr = {};
3461         struct ib_send_wr *send_wr;
3462         int ret;
3463
3464         send_wr = &rdma_wr.wr;
3465         send_wr->opcode = IB_WR_RDMA_WRITE;
3466
3467         ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr);
3468         if (ret) {
3469                 ibdev_err(ibdev, "failed to post wqe for free mr, ret = %d.\n",
3470                           ret);
3471                 return ret;
3472         }
3473
3474         return 0;
3475 }
3476
3477 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3478                                struct ib_wc *wc);
3479
3480 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev)
3481 {
3482         struct hns_roce_v2_priv *priv = hr_dev->priv;
3483         struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
3484         struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)];
3485         struct ib_device *ibdev = &hr_dev->ib_dev;
3486         struct hns_roce_qp *hr_qp;
3487         unsigned long end;
3488         int cqe_cnt = 0;
3489         int npolled;
3490         int ret;
3491         int i;
3492
3493         /*
3494          * If the device initialization is not complete or in the uninstall
3495          * process, then there is no need to execute free mr.
3496          */
3497         if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
3498             priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT ||
3499             hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT)
3500                 return;
3501
3502         mutex_lock(&free_mr->mutex);
3503
3504         for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
3505                 hr_qp = free_mr->rsv_qp[i];
3506
3507                 ret = free_mr_post_send_lp_wqe(hr_qp);
3508                 if (ret) {
3509                         ibdev_err(ibdev,
3510                                   "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n",
3511                                   hr_qp->qpn, ret);
3512                         break;
3513                 }
3514
3515                 cqe_cnt++;
3516         }
3517
3518         end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies;
3519         while (cqe_cnt) {
3520                 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc);
3521                 if (npolled < 0) {
3522                         ibdev_err(ibdev,
3523                                   "failed to poll cqe for free mr, remain %d cqe.\n",
3524                                   cqe_cnt);
3525                         goto out;
3526                 }
3527
3528                 if (time_after(jiffies, end)) {
3529                         ibdev_err(ibdev,
3530                                   "failed to poll cqe for free mr and timeout, remain %d cqe.\n",
3531                                   cqe_cnt);
3532                         goto out;
3533                 }
3534                 cqe_cnt -= npolled;
3535         }
3536
3537 out:
3538         mutex_unlock(&free_mr->mutex);
3539 }
3540
3541 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev)
3542 {
3543         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
3544                 free_mr_send_cmd_to_hw(hr_dev);
3545 }
3546
3547 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
3548 {
3549         return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);
3550 }
3551
3552 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n)
3553 {
3554         struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
3555
3556         /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
3557         return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe :
3558                                                                          NULL;
3559 }
3560
3561 static inline void update_cq_db(struct hns_roce_dev *hr_dev,
3562                                 struct hns_roce_cq *hr_cq)
3563 {
3564         if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) {
3565                 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M;
3566         } else {
3567                 struct hns_roce_v2_db cq_db = {};
3568
3569                 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3570                 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB);
3571                 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3572                 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1);
3573
3574                 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3575         }
3576 }
3577
3578 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3579                                    struct hns_roce_srq *srq)
3580 {
3581         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3582         struct hns_roce_v2_cqe *cqe, *dest;
3583         u32 prod_index;
3584         int nfreed = 0;
3585         int wqe_index;
3586         u8 owner_bit;
3587
3588         for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
3589              ++prod_index) {
3590                 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe)
3591                         break;
3592         }
3593
3594         /*
3595          * Now backwards through the CQ, removing CQ entries
3596          * that match our QP by overwriting them with next entries.
3597          */
3598         while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
3599                 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
3600                 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) {
3601                         if (srq && hr_reg_read(cqe, CQE_S_R)) {
3602                                 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX);
3603                                 hns_roce_free_srq_wqe(srq, wqe_index);
3604                         }
3605                         ++nfreed;
3606                 } else if (nfreed) {
3607                         dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
3608                                           hr_cq->ib_cq.cqe);
3609                         owner_bit = hr_reg_read(dest, CQE_OWNER);
3610                         memcpy(dest, cqe, hr_cq->cqe_size);
3611                         hr_reg_write(dest, CQE_OWNER, owner_bit);
3612                 }
3613         }
3614
3615         if (nfreed) {
3616                 hr_cq->cons_index += nfreed;
3617                 update_cq_db(hr_dev, hr_cq);
3618         }
3619 }
3620
3621 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3622                                  struct hns_roce_srq *srq)
3623 {
3624         spin_lock_irq(&hr_cq->lock);
3625         __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
3626         spin_unlock_irq(&hr_cq->lock);
3627 }
3628
3629 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
3630                                   struct hns_roce_cq *hr_cq, void *mb_buf,
3631                                   u64 *mtts, dma_addr_t dma_handle)
3632 {
3633         struct hns_roce_v2_cq_context *cq_context;
3634
3635         cq_context = mb_buf;
3636         memset(cq_context, 0, sizeof(*cq_context));
3637
3638         hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID);
3639         hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED);
3640         hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth));
3641         hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector);
3642         hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn);
3643
3644         if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE)
3645                 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B);
3646
3647         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
3648                 hr_reg_enable(cq_context, CQC_STASH);
3649
3650         hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L,
3651                      to_hr_hw_page_addr(mtts[0]));
3652         hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H,
3653                      upper_32_bits(to_hr_hw_page_addr(mtts[0])));
3654         hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num ==
3655                      HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
3656         hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L,
3657                      to_hr_hw_page_addr(mtts[1]));
3658         hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H,
3659                      upper_32_bits(to_hr_hw_page_addr(mtts[1])));
3660         hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ,
3661                      to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift));
3662         hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ,
3663                      to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift));
3664         hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3);
3665         hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3)));
3666         hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN,
3667                           hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB);
3668         hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L,
3669                      ((u32)hr_cq->db.dma) >> 1);
3670         hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H,
3671                      hr_cq->db.dma >> 32);
3672         hr_reg_write(cq_context, CQC_CQ_MAX_CNT,
3673                      HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
3674         hr_reg_write(cq_context, CQC_CQ_PERIOD,
3675                      HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
3676 }
3677
3678 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
3679                                      enum ib_cq_notify_flags flags)
3680 {
3681         struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3682         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3683         struct hns_roce_v2_db cq_db = {};
3684         u32 notify_flag;
3685
3686         /*
3687          * flags = 0, then notify_flag : next
3688          * flags = 1, then notify flag : solocited
3689          */
3690         notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
3691                       V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
3692
3693         hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3694         hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY);
3695         hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3696         hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn);
3697         hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag);
3698
3699         hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3700
3701         return 0;
3702 }
3703
3704 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
3705                                         struct hns_roce_qp *qp,
3706                                         struct ib_wc *wc)
3707 {
3708         struct hns_roce_rinl_sge *sge_list;
3709         u32 wr_num, wr_cnt, sge_num;
3710         u32 sge_cnt, data_len, size;
3711         void *wqe_buf;
3712
3713         wr_num = hr_reg_read(cqe, CQE_WQE_IDX);
3714         wr_cnt = wr_num & (qp->rq.wqe_cnt - 1);
3715
3716         sge_list = qp->rq_inl_buf.wqe_list[wr_cnt].sg_list;
3717         sge_num = qp->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
3718         wqe_buf = hns_roce_get_recv_wqe(qp, wr_cnt);
3719         data_len = wc->byte_len;
3720
3721         for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
3722                 size = min(sge_list[sge_cnt].len, data_len);
3723                 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
3724
3725                 data_len -= size;
3726                 wqe_buf += size;
3727         }
3728
3729         if (unlikely(data_len)) {
3730                 wc->status = IB_WC_LOC_LEN_ERR;
3731                 return -EAGAIN;
3732         }
3733
3734         return 0;
3735 }
3736
3737 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq,
3738                    int num_entries, struct ib_wc *wc)
3739 {
3740         unsigned int left;
3741         int npolled = 0;
3742
3743         left = wq->head - wq->tail;
3744         if (left == 0)
3745                 return 0;
3746
3747         left = min_t(unsigned int, (unsigned int)num_entries, left);
3748         while (npolled < left) {
3749                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3750                 wc->status = IB_WC_WR_FLUSH_ERR;
3751                 wc->vendor_err = 0;
3752                 wc->qp = &hr_qp->ibqp;
3753
3754                 wq->tail++;
3755                 wc++;
3756                 npolled++;
3757         }
3758
3759         return npolled;
3760 }
3761
3762 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
3763                                   struct ib_wc *wc)
3764 {
3765         struct hns_roce_qp *hr_qp;
3766         int npolled = 0;
3767
3768         list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) {
3769                 npolled += sw_comp(hr_qp, &hr_qp->sq,
3770                                    num_entries - npolled, wc + npolled);
3771                 if (npolled >= num_entries)
3772                         goto out;
3773         }
3774
3775         list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) {
3776                 npolled += sw_comp(hr_qp, &hr_qp->rq,
3777                                    num_entries - npolled, wc + npolled);
3778                 if (npolled >= num_entries)
3779                         goto out;
3780         }
3781
3782 out:
3783         return npolled;
3784 }
3785
3786 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
3787                            struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe,
3788                            struct ib_wc *wc)
3789 {
3790         static const struct {
3791                 u32 cqe_status;
3792                 enum ib_wc_status wc_status;
3793         } map[] = {
3794                 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS },
3795                 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR },
3796                 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR },
3797                 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR },
3798                 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR },
3799                 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR },
3800                 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR },
3801                 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR },
3802                 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR },
3803                 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR },
3804                 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR },
3805                 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR,
3806                   IB_WC_RETRY_EXC_ERR },
3807                 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR },
3808                 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR },
3809                 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR}
3810         };
3811
3812         u32 cqe_status = hr_reg_read(cqe, CQE_STATUS);
3813         int i;
3814
3815         wc->status = IB_WC_GENERAL_ERR;
3816         for (i = 0; i < ARRAY_SIZE(map); i++)
3817                 if (cqe_status == map[i].cqe_status) {
3818                         wc->status = map[i].wc_status;
3819                         break;
3820                 }
3821
3822         if (likely(wc->status == IB_WC_SUCCESS ||
3823                    wc->status == IB_WC_WR_FLUSH_ERR))
3824                 return;
3825
3826         ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status);
3827         print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe,
3828                        cq->cqe_size, false);
3829         wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS);
3830
3831         /*
3832          * For hns ROCEE, GENERAL_ERR is an error type that is not defined in
3833          * the standard protocol, the driver must ignore it and needn't to set
3834          * the QP to an error state.
3835          */
3836         if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR)
3837                 return;
3838
3839         flush_cqe(hr_dev, qp);
3840 }
3841
3842 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe,
3843                       struct hns_roce_qp **cur_qp)
3844 {
3845         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3846         struct hns_roce_qp *hr_qp = *cur_qp;
3847         u32 qpn;
3848
3849         qpn = hr_reg_read(cqe, CQE_LCL_QPN);
3850
3851         if (!hr_qp || qpn != hr_qp->qpn) {
3852                 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
3853                 if (unlikely(!hr_qp)) {
3854                         ibdev_err(&hr_dev->ib_dev,
3855                                   "CQ %06lx with entry for unknown QPN %06x\n",
3856                                   hr_cq->cqn, qpn);
3857                         return -EINVAL;
3858                 }
3859                 *cur_qp = hr_qp;
3860         }
3861
3862         return 0;
3863 }
3864
3865 /*
3866  * mapped-value = 1 + real-value
3867  * The ib wc opcode's real value is start from 0, In order to distinguish
3868  * between initialized and uninitialized map values, we plus 1 to the actual
3869  * value when defining the mapping, so that the validity can be identified by
3870  * checking whether the mapped value is greater than 0.
3871  */
3872 #define HR_WC_OP_MAP(hr_key, ib_key) \
3873                 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key
3874
3875 static const u32 wc_send_op_map[] = {
3876         HR_WC_OP_MAP(SEND,                      SEND),
3877         HR_WC_OP_MAP(SEND_WITH_INV,             SEND),
3878         HR_WC_OP_MAP(SEND_WITH_IMM,             SEND),
3879         HR_WC_OP_MAP(RDMA_READ,                 RDMA_READ),
3880         HR_WC_OP_MAP(RDMA_WRITE,                RDMA_WRITE),
3881         HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM,       RDMA_WRITE),
3882         HR_WC_OP_MAP(ATOM_CMP_AND_SWAP,         COMP_SWAP),
3883         HR_WC_OP_MAP(ATOM_FETCH_AND_ADD,        FETCH_ADD),
3884         HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP,     MASKED_COMP_SWAP),
3885         HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD,    MASKED_FETCH_ADD),
3886         HR_WC_OP_MAP(FAST_REG_PMR,              REG_MR),
3887         HR_WC_OP_MAP(BIND_MW,                   REG_MR),
3888 };
3889
3890 static int to_ib_wc_send_op(u32 hr_opcode)
3891 {
3892         if (hr_opcode >= ARRAY_SIZE(wc_send_op_map))
3893                 return -EINVAL;
3894
3895         return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 :
3896                                            -EINVAL;
3897 }
3898
3899 static const u32 wc_recv_op_map[] = {
3900         HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM,               WITH_IMM),
3901         HR_WC_OP_MAP(SEND,                              RECV),
3902         HR_WC_OP_MAP(SEND_WITH_IMM,                     WITH_IMM),
3903         HR_WC_OP_MAP(SEND_WITH_INV,                     RECV),
3904 };
3905
3906 static int to_ib_wc_recv_op(u32 hr_opcode)
3907 {
3908         if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map))
3909                 return -EINVAL;
3910
3911         return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 :
3912                                            -EINVAL;
3913 }
3914
3915 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3916 {
3917         u32 hr_opcode;
3918         int ib_opcode;
3919
3920         wc->wc_flags = 0;
3921
3922         hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3923         switch (hr_opcode) {
3924         case HNS_ROCE_V2_WQE_OP_RDMA_READ:
3925                 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3926                 break;
3927         case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM:
3928         case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM:
3929                 wc->wc_flags |= IB_WC_WITH_IMM;
3930                 break;
3931         case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP:
3932         case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD:
3933         case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP:
3934         case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD:
3935                 wc->byte_len  = 8;
3936                 break;
3937         default:
3938                 break;
3939         }
3940
3941         ib_opcode = to_ib_wc_send_op(hr_opcode);
3942         if (ib_opcode < 0)
3943                 wc->status = IB_WC_GENERAL_ERR;
3944         else
3945                 wc->opcode = ib_opcode;
3946 }
3947
3948 static inline bool is_rq_inl_enabled(struct ib_wc *wc, u32 hr_opcode,
3949                                      struct hns_roce_v2_cqe *cqe)
3950 {
3951         return wc->qp->qp_type != IB_QPT_UD && wc->qp->qp_type != IB_QPT_GSI &&
3952                (hr_opcode == HNS_ROCE_V2_OPCODE_SEND ||
3953                 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
3954                 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
3955                hr_reg_read(cqe, CQE_RQ_INLINE);
3956 }
3957
3958 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3959 {
3960         struct hns_roce_qp *qp = to_hr_qp(wc->qp);
3961         u32 hr_opcode;
3962         int ib_opcode;
3963         int ret;
3964
3965         wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3966
3967         hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3968         switch (hr_opcode) {
3969         case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
3970         case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
3971                 wc->wc_flags = IB_WC_WITH_IMM;
3972                 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata));
3973                 break;
3974         case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
3975                 wc->wc_flags = IB_WC_WITH_INVALIDATE;
3976                 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
3977                 break;
3978         default:
3979                 wc->wc_flags = 0;
3980         }
3981
3982         ib_opcode = to_ib_wc_recv_op(hr_opcode);
3983         if (ib_opcode < 0)
3984                 wc->status = IB_WC_GENERAL_ERR;
3985         else
3986                 wc->opcode = ib_opcode;
3987
3988         if (is_rq_inl_enabled(wc, hr_opcode, cqe)) {
3989                 ret = hns_roce_handle_recv_inl_wqe(cqe, qp, wc);
3990                 if (unlikely(ret))
3991                         return ret;
3992         }
3993
3994         wc->sl = hr_reg_read(cqe, CQE_SL);
3995         wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN);
3996         wc->slid = 0;
3997         wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0;
3998         wc->port_num = hr_reg_read(cqe, CQE_PORTN);
3999         wc->pkey_index = 0;
4000
4001         if (hr_reg_read(cqe, CQE_VID_VLD)) {
4002                 wc->vlan_id = hr_reg_read(cqe, CQE_VID);
4003                 wc->wc_flags |= IB_WC_WITH_VLAN;
4004         } else {
4005                 wc->vlan_id = 0xffff;
4006         }
4007
4008         wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE);
4009
4010         return 0;
4011 }
4012
4013 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
4014                                 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
4015 {
4016         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
4017         struct hns_roce_qp *qp = *cur_qp;
4018         struct hns_roce_srq *srq = NULL;
4019         struct hns_roce_v2_cqe *cqe;
4020         struct hns_roce_wq *wq;
4021         int is_send;
4022         u16 wqe_idx;
4023         int ret;
4024
4025         cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
4026         if (!cqe)
4027                 return -EAGAIN;
4028
4029         ++hr_cq->cons_index;
4030         /* Memory barrier */
4031         rmb();
4032
4033         ret = get_cur_qp(hr_cq, cqe, &qp);
4034         if (ret)
4035                 return ret;
4036
4037         wc->qp = &qp->ibqp;
4038         wc->vendor_err = 0;
4039
4040         wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX);
4041
4042         is_send = !hr_reg_read(cqe, CQE_S_R);
4043         if (is_send) {
4044                 wq = &qp->sq;
4045
4046                 /* If sg_signal_bit is set, tail pointer will be updated to
4047                  * the WQE corresponding to the current CQE.
4048                  */
4049                 if (qp->sq_signal_bits)
4050                         wq->tail += (wqe_idx - (u16)wq->tail) &
4051                                     (wq->wqe_cnt - 1);
4052
4053                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
4054                 ++wq->tail;
4055
4056                 fill_send_wc(wc, cqe);
4057         } else {
4058                 if (qp->ibqp.srq) {
4059                         srq = to_hr_srq(qp->ibqp.srq);
4060                         wc->wr_id = srq->wrid[wqe_idx];
4061                         hns_roce_free_srq_wqe(srq, wqe_idx);
4062                 } else {
4063                         wq = &qp->rq;
4064                         wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
4065                         ++wq->tail;
4066                 }
4067
4068                 ret = fill_recv_wc(wc, cqe);
4069         }
4070
4071         get_cqe_status(hr_dev, qp, hr_cq, cqe, wc);
4072         if (unlikely(wc->status != IB_WC_SUCCESS))
4073                 return 0;
4074
4075         return ret;
4076 }
4077
4078 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
4079                                struct ib_wc *wc)
4080 {
4081         struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
4082         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
4083         struct hns_roce_qp *cur_qp = NULL;
4084         unsigned long flags;
4085         int npolled;
4086
4087         spin_lock_irqsave(&hr_cq->lock, flags);
4088
4089         /*
4090          * When the device starts to reset, the state is RST_DOWN. At this time,
4091          * there may still be some valid CQEs in the hardware that are not
4092          * polled. Therefore, it is not allowed to switch to the software mode
4093          * immediately. When the state changes to UNINIT, CQE no longer exists
4094          * in the hardware, and then switch to software mode.
4095          */
4096         if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
4097                 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc);
4098                 goto out;
4099         }
4100
4101         for (npolled = 0; npolled < num_entries; ++npolled) {
4102                 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
4103                         break;
4104         }
4105
4106         if (npolled)
4107                 update_cq_db(hr_dev, hr_cq);
4108
4109 out:
4110         spin_unlock_irqrestore(&hr_cq->lock, flags);
4111
4112         return npolled;
4113 }
4114
4115 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
4116                               u32 step_idx, u8 *mbox_cmd)
4117 {
4118         u8 cmd;
4119
4120         switch (type) {
4121         case HEM_TYPE_QPC:
4122                 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0;
4123                 break;
4124         case HEM_TYPE_MTPT:
4125                 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0;
4126                 break;
4127         case HEM_TYPE_CQC:
4128                 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0;
4129                 break;
4130         case HEM_TYPE_SRQC:
4131                 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0;
4132                 break;
4133         case HEM_TYPE_SCCC:
4134                 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0;
4135                 break;
4136         case HEM_TYPE_QPC_TIMER:
4137                 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
4138                 break;
4139         case HEM_TYPE_CQC_TIMER:
4140                 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
4141                 break;
4142         default:
4143                 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type);
4144                 return -EINVAL;
4145         }
4146
4147         *mbox_cmd = cmd + step_idx;
4148
4149         return 0;
4150 }
4151
4152 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj,
4153                                dma_addr_t base_addr)
4154 {
4155         struct hns_roce_cmq_desc desc;
4156         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
4157         u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz);
4158         u64 addr = to_hr_hw_page_addr(base_addr);
4159
4160         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
4161
4162         hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr));
4163         hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr));
4164         hr_reg_write(req, CFG_GMV_BT_IDX, idx);
4165
4166         return hns_roce_cmq_send(hr_dev, &desc, 1);
4167 }
4168
4169 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj,
4170                          dma_addr_t base_addr, u32 hem_type, u32 step_idx)
4171 {
4172         int ret;
4173         u8 cmd;
4174
4175         if (unlikely(hem_type == HEM_TYPE_GMV))
4176                 return config_gmv_ba_to_hw(hr_dev, obj, base_addr);
4177
4178         if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx))
4179                 return 0;
4180
4181         ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd);
4182         if (ret < 0)
4183                 return ret;
4184
4185         return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj);
4186 }
4187
4188 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
4189                                struct hns_roce_hem_table *table, int obj,
4190                                u32 step_idx)
4191 {
4192         struct hns_roce_hem_iter iter;
4193         struct hns_roce_hem_mhop mhop;
4194         struct hns_roce_hem *hem;
4195         unsigned long mhop_obj = obj;
4196         int i, j, k;
4197         int ret = 0;
4198         u64 hem_idx = 0;
4199         u64 l1_idx = 0;
4200         u64 bt_ba = 0;
4201         u32 chunk_ba_num;
4202         u32 hop_num;
4203
4204         if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4205                 return 0;
4206
4207         hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
4208         i = mhop.l0_idx;
4209         j = mhop.l1_idx;
4210         k = mhop.l2_idx;
4211         hop_num = mhop.hop_num;
4212         chunk_ba_num = mhop.bt_chunk_size / 8;
4213
4214         if (hop_num == 2) {
4215                 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
4216                           k;
4217                 l1_idx = i * chunk_ba_num + j;
4218         } else if (hop_num == 1) {
4219                 hem_idx = i * chunk_ba_num + j;
4220         } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
4221                 hem_idx = i;
4222         }
4223
4224         if (table->type == HEM_TYPE_SCCC)
4225                 obj = mhop.l0_idx;
4226
4227         if (check_whether_last_step(hop_num, step_idx)) {
4228                 hem = table->hem[hem_idx];
4229                 for (hns_roce_hem_first(hem, &iter);
4230                      !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
4231                         bt_ba = hns_roce_hem_addr(&iter);
4232                         ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type,
4233                                             step_idx);
4234                 }
4235         } else {
4236                 if (step_idx == 0)
4237                         bt_ba = table->bt_l0_dma_addr[i];
4238                 else if (step_idx == 1 && hop_num == 2)
4239                         bt_ba = table->bt_l1_dma_addr[l1_idx];
4240
4241                 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx);
4242         }
4243
4244         return ret;
4245 }
4246
4247 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
4248                                  struct hns_roce_hem_table *table,
4249                                  int tag, u32 step_idx)
4250 {
4251         struct hns_roce_cmd_mailbox *mailbox;
4252         struct device *dev = hr_dev->dev;
4253         u8 cmd = 0xff;
4254         int ret;
4255
4256         if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4257                 return 0;
4258
4259         switch (table->type) {
4260         case HEM_TYPE_QPC:
4261                 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0;
4262                 break;
4263         case HEM_TYPE_MTPT:
4264                 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0;
4265                 break;
4266         case HEM_TYPE_CQC:
4267                 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0;
4268                 break;
4269         case HEM_TYPE_SRQC:
4270                 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
4271                 break;
4272         case HEM_TYPE_SCCC:
4273         case HEM_TYPE_QPC_TIMER:
4274         case HEM_TYPE_CQC_TIMER:
4275         case HEM_TYPE_GMV:
4276                 return 0;
4277         default:
4278                 dev_warn(dev, "table %u not to be destroyed by mailbox!\n",
4279                          table->type);
4280                 return 0;
4281         }
4282
4283         cmd += step_idx;
4284
4285         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4286         if (IS_ERR(mailbox))
4287                 return PTR_ERR(mailbox);
4288
4289         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag);
4290
4291         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4292         return ret;
4293 }
4294
4295 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
4296                                  struct hns_roce_v2_qp_context *context,
4297                                  struct hns_roce_v2_qp_context *qpc_mask,
4298                                  struct hns_roce_qp *hr_qp)
4299 {
4300         struct hns_roce_cmd_mailbox *mailbox;
4301         int qpc_size;
4302         int ret;
4303
4304         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4305         if (IS_ERR(mailbox))
4306                 return PTR_ERR(mailbox);
4307
4308         /* The qpc size of HIP08 is only 256B, which is half of HIP09 */
4309         qpc_size = hr_dev->caps.qpc_sz;
4310         memcpy(mailbox->buf, context, qpc_size);
4311         memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size);
4312
4313         ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
4314                                 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn);
4315
4316         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4317
4318         return ret;
4319 }
4320
4321 static void set_access_flags(struct hns_roce_qp *hr_qp,
4322                              struct hns_roce_v2_qp_context *context,
4323                              struct hns_roce_v2_qp_context *qpc_mask,
4324                              const struct ib_qp_attr *attr, int attr_mask)
4325 {
4326         u8 dest_rd_atomic;
4327         u32 access_flags;
4328
4329         dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
4330                          attr->max_dest_rd_atomic : hr_qp->resp_depth;
4331
4332         access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
4333                        attr->qp_access_flags : hr_qp->atomic_rd_en;
4334
4335         if (!dest_rd_atomic)
4336                 access_flags &= IB_ACCESS_REMOTE_WRITE;
4337
4338         hr_reg_write_bool(context, QPC_RRE,
4339                           access_flags & IB_ACCESS_REMOTE_READ);
4340         hr_reg_clear(qpc_mask, QPC_RRE);
4341
4342         hr_reg_write_bool(context, QPC_RWE,
4343                           access_flags & IB_ACCESS_REMOTE_WRITE);
4344         hr_reg_clear(qpc_mask, QPC_RWE);
4345
4346         hr_reg_write_bool(context, QPC_ATE,
4347                           access_flags & IB_ACCESS_REMOTE_ATOMIC);
4348         hr_reg_clear(qpc_mask, QPC_ATE);
4349         hr_reg_write_bool(context, QPC_EXT_ATE,
4350                           access_flags & IB_ACCESS_REMOTE_ATOMIC);
4351         hr_reg_clear(qpc_mask, QPC_EXT_ATE);
4352 }
4353
4354 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp,
4355                             struct hns_roce_v2_qp_context *context,
4356                             struct hns_roce_v2_qp_context *qpc_mask)
4357 {
4358         hr_reg_write(context, QPC_SGE_SHIFT,
4359                      to_hr_hem_entries_shift(hr_qp->sge.sge_cnt,
4360                                              hr_qp->sge.sge_shift));
4361
4362         hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt));
4363
4364         hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt));
4365 }
4366
4367 static inline int get_cqn(struct ib_cq *ib_cq)
4368 {
4369         return ib_cq ? to_hr_cq(ib_cq)->cqn : 0;
4370 }
4371
4372 static inline int get_pdn(struct ib_pd *ib_pd)
4373 {
4374         return ib_pd ? to_hr_pd(ib_pd)->pdn : 0;
4375 }
4376
4377 static void modify_qp_reset_to_init(struct ib_qp *ibqp,
4378                                     const struct ib_qp_attr *attr,
4379                                     struct hns_roce_v2_qp_context *context,
4380                                     struct hns_roce_v2_qp_context *qpc_mask)
4381 {
4382         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4383         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4384
4385         /*
4386          * In v2 engine, software pass context and context mask to hardware
4387          * when modifying qp. If software need modify some fields in context,
4388          * we should set all bits of the relevant fields in context mask to
4389          * 0 at the same time, else set them to 0x1.
4390          */
4391         hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4392
4393         hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4394
4395         hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs));
4396
4397         set_qpc_wqe_cnt(hr_qp, context, qpc_mask);
4398
4399         /* No VLAN need to set 0xFFF */
4400         hr_reg_write(context, QPC_VLAN_ID, 0xfff);
4401
4402         if (ibqp->qp_type == IB_QPT_XRC_TGT) {
4403                 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn);
4404
4405                 hr_reg_enable(context, QPC_XRC_QP_TYPE);
4406         }
4407
4408         if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
4409                 hr_reg_enable(context, QPC_RQ_RECORD_EN);
4410
4411         if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
4412                 hr_reg_enable(context, QPC_OWNER_MODE);
4413
4414         hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L,
4415                      lower_32_bits(hr_qp->rdb.dma) >> 1);
4416         hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H,
4417                      upper_32_bits(hr_qp->rdb.dma));
4418
4419         if (ibqp->qp_type != IB_QPT_UD && ibqp->qp_type != IB_QPT_GSI)
4420                 hr_reg_write_bool(context, QPC_RQIE,
4421                              hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE);
4422
4423         hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4424
4425         if (ibqp->srq) {
4426                 hr_reg_enable(context, QPC_SRQ_EN);
4427                 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4428         }
4429
4430         hr_reg_enable(context, QPC_FRE);
4431
4432         hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4433
4434         if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ)
4435                 return;
4436
4437         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
4438                 hr_reg_enable(&context->ext, QPCEX_STASH);
4439 }
4440
4441 static void modify_qp_init_to_init(struct ib_qp *ibqp,
4442                                    const struct ib_qp_attr *attr,
4443                                    struct hns_roce_v2_qp_context *context,
4444                                    struct hns_roce_v2_qp_context *qpc_mask)
4445 {
4446         /*
4447          * In v2 engine, software pass context and context mask to hardware
4448          * when modifying qp. If software need modify some fields in context,
4449          * we should set all bits of the relevant fields in context mask to
4450          * 0 at the same time, else set them to 0x1.
4451          */
4452         hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4453         hr_reg_clear(qpc_mask, QPC_TST);
4454
4455         hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4456         hr_reg_clear(qpc_mask, QPC_PD);
4457
4458         hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4459         hr_reg_clear(qpc_mask, QPC_RX_CQN);
4460
4461         hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4462         hr_reg_clear(qpc_mask, QPC_TX_CQN);
4463
4464         if (ibqp->srq) {
4465                 hr_reg_enable(context, QPC_SRQ_EN);
4466                 hr_reg_clear(qpc_mask, QPC_SRQ_EN);
4467                 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4468                 hr_reg_clear(qpc_mask, QPC_SRQN);
4469         }
4470 }
4471
4472 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev,
4473                             struct hns_roce_qp *hr_qp,
4474                             struct hns_roce_v2_qp_context *context,
4475                             struct hns_roce_v2_qp_context *qpc_mask)
4476 {
4477         u64 mtts[MTT_MIN_COUNT] = { 0 };
4478         u64 wqe_sge_ba;
4479         int count;
4480
4481         /* Search qp buf's mtts */
4482         count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts,
4483                                   MTT_MIN_COUNT, &wqe_sge_ba);
4484         if (hr_qp->rq.wqe_cnt && count < 1) {
4485                 ibdev_err(&hr_dev->ib_dev,
4486                           "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn);
4487                 return -EINVAL;
4488         }
4489
4490         context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3);
4491         qpc_mask->wqe_sge_ba = 0;
4492
4493         /*
4494          * In v2 engine, software pass context and context mask to hardware
4495          * when modifying qp. If software need modify some fields in context,
4496          * we should set all bits of the relevant fields in context mask to
4497          * 0 at the same time, else set them to 0x1.
4498          */
4499         hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3));
4500         hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H);
4501
4502         hr_reg_write(context, QPC_SQ_HOP_NUM,
4503                      to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num,
4504                                       hr_qp->sq.wqe_cnt));
4505         hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM);
4506
4507         hr_reg_write(context, QPC_SGE_HOP_NUM,
4508                      to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num,
4509                                       hr_qp->sge.sge_cnt));
4510         hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM);
4511
4512         hr_reg_write(context, QPC_RQ_HOP_NUM,
4513                      to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num,
4514                                       hr_qp->rq.wqe_cnt));
4515
4516         hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM);
4517
4518         hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ,
4519                      to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift));
4520         hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ);
4521
4522         hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ,
4523                      to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift));
4524         hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ);
4525
4526         context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
4527         qpc_mask->rq_cur_blk_addr = 0;
4528
4529         hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H,
4530                      upper_32_bits(to_hr_hw_page_addr(mtts[0])));
4531         hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H);
4532
4533         context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
4534         qpc_mask->rq_nxt_blk_addr = 0;
4535
4536         hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H,
4537                      upper_32_bits(to_hr_hw_page_addr(mtts[1])));
4538         hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H);
4539
4540         return 0;
4541 }
4542
4543 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev,
4544                             struct hns_roce_qp *hr_qp,
4545                             struct hns_roce_v2_qp_context *context,
4546                             struct hns_roce_v2_qp_context *qpc_mask)
4547 {
4548         struct ib_device *ibdev = &hr_dev->ib_dev;
4549         u64 sge_cur_blk = 0;
4550         u64 sq_cur_blk = 0;
4551         int count;
4552
4553         /* search qp buf's mtts */
4554         count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL);
4555         if (count < 1) {
4556                 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n",
4557                           hr_qp->qpn);
4558                 return -EINVAL;
4559         }
4560         if (hr_qp->sge.sge_cnt > 0) {
4561                 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
4562                                           hr_qp->sge.offset,
4563                                           &sge_cur_blk, 1, NULL);
4564                 if (count < 1) {
4565                         ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n",
4566                                   hr_qp->qpn);
4567                         return -EINVAL;
4568                 }
4569         }
4570
4571         /*
4572          * In v2 engine, software pass context and context mask to hardware
4573          * when modifying qp. If software need modify some fields in context,
4574          * we should set all bits of the relevant fields in context mask to
4575          * 0 at the same time, else set them to 0x1.
4576          */
4577         hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L,
4578                      lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4579         hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H,
4580                      upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4581         hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L);
4582         hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H);
4583
4584         hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L,
4585                      lower_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4586         hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H,
4587                      upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4588         hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L);
4589         hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H);
4590
4591         hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L,
4592                      lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4593         hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H,
4594                      upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4595         hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L);
4596         hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H);
4597
4598         return 0;
4599 }
4600
4601 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp,
4602                                   const struct ib_qp_attr *attr)
4603 {
4604         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
4605                 return IB_MTU_4096;
4606
4607         return attr->path_mtu;
4608 }
4609
4610 static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
4611                                  const struct ib_qp_attr *attr, int attr_mask,
4612                                  struct hns_roce_v2_qp_context *context,
4613                                  struct hns_roce_v2_qp_context *qpc_mask)
4614 {
4615         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4616         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4617         struct ib_device *ibdev = &hr_dev->ib_dev;
4618         dma_addr_t trrl_ba;
4619         dma_addr_t irrl_ba;
4620         enum ib_mtu ib_mtu;
4621         const u8 *smac;
4622         u8 lp_pktn_ini;
4623         u64 *mtts;
4624         u8 *dmac;
4625         u32 port;
4626         int mtu;
4627         int ret;
4628
4629         ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask);
4630         if (ret) {
4631                 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret);
4632                 return ret;
4633         }
4634
4635         /* Search IRRL's mtts */
4636         mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
4637                                    hr_qp->qpn, &irrl_ba);
4638         if (!mtts) {
4639                 ibdev_err(ibdev, "failed to find qp irrl_table.\n");
4640                 return -EINVAL;
4641         }
4642
4643         /* Search TRRL's mtts */
4644         mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
4645                                    hr_qp->qpn, &trrl_ba);
4646         if (!mtts) {
4647                 ibdev_err(ibdev, "failed to find qp trrl_table.\n");
4648                 return -EINVAL;
4649         }
4650
4651         if (attr_mask & IB_QP_ALT_PATH) {
4652                 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n",
4653                           attr_mask);
4654                 return -EINVAL;
4655         }
4656
4657         hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4);
4658         hr_reg_clear(qpc_mask, QPC_TRRL_BA_L);
4659         context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4));
4660         qpc_mask->trrl_ba = 0;
4661         hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4));
4662         hr_reg_clear(qpc_mask, QPC_TRRL_BA_H);
4663
4664         context->irrl_ba = cpu_to_le32(irrl_ba >> 6);
4665         qpc_mask->irrl_ba = 0;
4666         hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6));
4667         hr_reg_clear(qpc_mask, QPC_IRRL_BA_H);
4668
4669         hr_reg_enable(context, QPC_RMT_E2E);
4670         hr_reg_clear(qpc_mask, QPC_RMT_E2E);
4671
4672         hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits);
4673         hr_reg_clear(qpc_mask, QPC_SIG_TYPE);
4674
4675         port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
4676
4677         smac = (const u8 *)hr_dev->dev_addr[port];
4678         dmac = (u8 *)attr->ah_attr.roce.dmac;
4679         /* when dmac equals smac or loop_idc is 1, it should loopback */
4680         if (ether_addr_equal_unaligned(dmac, smac) ||
4681             hr_dev->loop_idc == 0x1) {
4682                 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc);
4683                 hr_reg_clear(qpc_mask, QPC_LBI);
4684         }
4685
4686         if (attr_mask & IB_QP_DEST_QPN) {
4687                 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num);
4688                 hr_reg_clear(qpc_mask, QPC_DQPN);
4689         }
4690
4691         memcpy(&context->dmac, dmac, sizeof(u32));
4692         hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4])));
4693         qpc_mask->dmac = 0;
4694         hr_reg_clear(qpc_mask, QPC_DMAC_H);
4695
4696         ib_mtu = get_mtu(ibqp, attr);
4697         hr_qp->path_mtu = ib_mtu;
4698
4699         mtu = ib_mtu_enum_to_int(ib_mtu);
4700         if (WARN_ON(mtu <= 0))
4701                 return -EINVAL;
4702 #define MAX_LP_MSG_LEN 16384
4703         /* MTU * (2 ^ LP_PKTN_INI) shouldn't be bigger than 16KB */
4704         lp_pktn_ini = ilog2(MAX_LP_MSG_LEN / mtu);
4705         if (WARN_ON(lp_pktn_ini >= 0xF))
4706                 return -EINVAL;
4707
4708         if (attr_mask & IB_QP_PATH_MTU) {
4709                 hr_reg_write(context, QPC_MTU, ib_mtu);
4710                 hr_reg_clear(qpc_mask, QPC_MTU);
4711         }
4712
4713         hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini);
4714         hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI);
4715
4716         /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */
4717         hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini);
4718         hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ);
4719
4720         hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR);
4721         hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN);
4722         hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE);
4723
4724         context->rq_rnr_timer = 0;
4725         qpc_mask->rq_rnr_timer = 0;
4726
4727         hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX);
4728         hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX);
4729
4730         /* rocee send 2^lp_sgen_ini segs every time */
4731         hr_reg_write(context, QPC_LP_SGEN_INI, 3);
4732         hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI);
4733
4734         return 0;
4735 }
4736
4737 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
4738                                 const struct ib_qp_attr *attr, int attr_mask,
4739                                 struct hns_roce_v2_qp_context *context,
4740                                 struct hns_roce_v2_qp_context *qpc_mask)
4741 {
4742         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4743         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4744         struct ib_device *ibdev = &hr_dev->ib_dev;
4745         int ret;
4746
4747         /* Not support alternate path and path migration */
4748         if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) {
4749                 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
4750                 return -EINVAL;
4751         }
4752
4753         ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask);
4754         if (ret) {
4755                 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret);
4756                 return ret;
4757         }
4758
4759         /*
4760          * Set some fields in context to zero, Because the default values
4761          * of all fields in context are zero, we need not set them to 0 again.
4762          * but we should set the relevant fields of context mask to 0.
4763          */
4764         hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX);
4765
4766         hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN);
4767
4768         hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE);
4769         hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD);
4770         hr_reg_clear(qpc_mask, QPC_IRRL_PSN);
4771
4772         hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL);
4773
4774         hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN);
4775
4776         hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG);
4777
4778         hr_reg_clear(qpc_mask, QPC_CHECK_FLG);
4779
4780         hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD);
4781
4782         return 0;
4783 }
4784
4785 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4786                            u32 *dip_idx)
4787 {
4788         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4789         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4790         u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx;
4791         u32 *head =  &hr_dev->qp_table.idx_table.head;
4792         u32 *tail =  &hr_dev->qp_table.idx_table.tail;
4793         struct hns_roce_dip *hr_dip;
4794         unsigned long flags;
4795         int ret = 0;
4796
4797         spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
4798
4799         spare_idx[*tail] = ibqp->qp_num;
4800         *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1);
4801
4802         list_for_each_entry(hr_dip, &hr_dev->dip_list, node) {
4803                 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) {
4804                         *dip_idx = hr_dip->dip_idx;
4805                         goto out;
4806                 }
4807         }
4808
4809         /* If no dgid is found, a new dip and a mapping between dgid and
4810          * dip_idx will be created.
4811          */
4812         hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC);
4813         if (!hr_dip) {
4814                 ret = -ENOMEM;
4815                 goto out;
4816         }
4817
4818         memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4819         hr_dip->dip_idx = *dip_idx = spare_idx[*head];
4820         *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1);
4821         list_add_tail(&hr_dip->node, &hr_dev->dip_list);
4822
4823 out:
4824         spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
4825         return ret;
4826 }
4827
4828 enum {
4829         CONG_DCQCN,
4830         CONG_WINDOW,
4831 };
4832
4833 enum {
4834         UNSUPPORT_CONG_LEVEL,
4835         SUPPORT_CONG_LEVEL,
4836 };
4837
4838 enum {
4839         CONG_LDCP,
4840         CONG_HC3,
4841 };
4842
4843 enum {
4844         DIP_INVALID,
4845         DIP_VALID,
4846 };
4847
4848 enum {
4849         WND_LIMIT,
4850         WND_UNLIMIT,
4851 };
4852
4853 static int check_cong_type(struct ib_qp *ibqp,
4854                            struct hns_roce_congestion_algorithm *cong_alg)
4855 {
4856         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4857
4858         /* different congestion types match different configurations */
4859         switch (hr_dev->caps.cong_type) {
4860         case CONG_TYPE_DCQCN:
4861                 cong_alg->alg_sel = CONG_DCQCN;
4862                 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4863                 cong_alg->dip_vld = DIP_INVALID;
4864                 cong_alg->wnd_mode_sel = WND_LIMIT;
4865                 break;
4866         case CONG_TYPE_LDCP:
4867                 cong_alg->alg_sel = CONG_WINDOW;
4868                 cong_alg->alg_sub_sel = CONG_LDCP;
4869                 cong_alg->dip_vld = DIP_INVALID;
4870                 cong_alg->wnd_mode_sel = WND_UNLIMIT;
4871                 break;
4872         case CONG_TYPE_HC3:
4873                 cong_alg->alg_sel = CONG_WINDOW;
4874                 cong_alg->alg_sub_sel = CONG_HC3;
4875                 cong_alg->dip_vld = DIP_INVALID;
4876                 cong_alg->wnd_mode_sel = WND_LIMIT;
4877                 break;
4878         case CONG_TYPE_DIP:
4879                 cong_alg->alg_sel = CONG_DCQCN;
4880                 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4881                 cong_alg->dip_vld = DIP_VALID;
4882                 cong_alg->wnd_mode_sel = WND_LIMIT;
4883                 break;
4884         default:
4885                 ibdev_err(&hr_dev->ib_dev,
4886                           "error type(%u) for congestion selection.\n",
4887                           hr_dev->caps.cong_type);
4888                 return -EINVAL;
4889         }
4890
4891         return 0;
4892 }
4893
4894 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4895                            struct hns_roce_v2_qp_context *context,
4896                            struct hns_roce_v2_qp_context *qpc_mask)
4897 {
4898         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4899         struct hns_roce_congestion_algorithm cong_field;
4900         struct ib_device *ibdev = ibqp->device;
4901         struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
4902         u32 dip_idx = 0;
4903         int ret;
4904
4905         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ||
4906             grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE)
4907                 return 0;
4908
4909         ret = check_cong_type(ibqp, &cong_field);
4910         if (ret)
4911                 return ret;
4912
4913         hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id +
4914                      hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE);
4915         hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID);
4916         hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel);
4917         hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL);
4918         hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL,
4919                      cong_field.alg_sub_sel);
4920         hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL);
4921         hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld);
4922         hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD);
4923         hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN,
4924                      cong_field.wnd_mode_sel);
4925         hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN);
4926
4927         /* if dip is disabled, there is no need to set dip idx */
4928         if (cong_field.dip_vld == 0)
4929                 return 0;
4930
4931         ret = get_dip_ctx_idx(ibqp, attr, &dip_idx);
4932         if (ret) {
4933                 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret);
4934                 return ret;
4935         }
4936
4937         hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx);
4938         hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0);
4939
4940         return 0;
4941 }
4942
4943 static int hns_roce_v2_set_path(struct ib_qp *ibqp,
4944                                 const struct ib_qp_attr *attr,
4945                                 int attr_mask,
4946                                 struct hns_roce_v2_qp_context *context,
4947                                 struct hns_roce_v2_qp_context *qpc_mask)
4948 {
4949         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4950         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4951         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4952         struct ib_device *ibdev = &hr_dev->ib_dev;
4953         const struct ib_gid_attr *gid_attr = NULL;
4954         int is_roce_protocol;
4955         u16 vlan_id = 0xffff;
4956         bool is_udp = false;
4957         u8 ib_port;
4958         u8 hr_port;
4959         int ret;
4960
4961         /*
4962          * If free_mr_en of qp is set, it means that this qp comes from
4963          * free mr. This qp will perform the loopback operation.
4964          * In the loopback scenario, only sl needs to be set.
4965          */
4966         if (hr_qp->free_mr_en) {
4967                 hr_reg_write(context, QPC_SL, rdma_ah_get_sl(&attr->ah_attr));
4968                 hr_reg_clear(qpc_mask, QPC_SL);
4969                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
4970                 return 0;
4971         }
4972
4973         ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
4974         hr_port = ib_port - 1;
4975         is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
4976                            rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
4977
4978         if (is_roce_protocol) {
4979                 gid_attr = attr->ah_attr.grh.sgid_attr;
4980                 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL);
4981                 if (ret)
4982                         return ret;
4983
4984                 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP);
4985         }
4986
4987         /* Only HIP08 needs to set the vlan_en bits in QPC */
4988         if (vlan_id < VLAN_N_VID &&
4989             hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
4990                 hr_reg_enable(context, QPC_RQ_VLAN_EN);
4991                 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN);
4992                 hr_reg_enable(context, QPC_SQ_VLAN_EN);
4993                 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN);
4994         }
4995
4996         hr_reg_write(context, QPC_VLAN_ID, vlan_id);
4997         hr_reg_clear(qpc_mask, QPC_VLAN_ID);
4998
4999         if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
5000                 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n",
5001                           grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]);
5002                 return -EINVAL;
5003         }
5004
5005         if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
5006                 ibdev_err(ibdev, "ah attr is not RDMA roce type\n");
5007                 return -EINVAL;
5008         }
5009
5010         hr_reg_write(context, QPC_UDPSPN,
5011                      is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num,
5012                                                  attr->dest_qp_num) :
5013                                     0);
5014
5015         hr_reg_clear(qpc_mask, QPC_UDPSPN);
5016
5017         hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index);
5018
5019         hr_reg_clear(qpc_mask, QPC_GMV_IDX);
5020
5021         hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit);
5022         hr_reg_clear(qpc_mask, QPC_HOPLIMIT);
5023
5024         ret = fill_cong_field(ibqp, attr, context, qpc_mask);
5025         if (ret)
5026                 return ret;
5027
5028         hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh));
5029         hr_reg_clear(qpc_mask, QPC_TC);
5030
5031         hr_reg_write(context, QPC_FL, grh->flow_label);
5032         hr_reg_clear(qpc_mask, QPC_FL);
5033         memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
5034         memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
5035
5036         hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
5037         if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) {
5038                 ibdev_err(ibdev,
5039                           "failed to fill QPC, sl (%u) shouldn't be larger than %d.\n",
5040                           hr_qp->sl, MAX_SERVICE_LEVEL);
5041                 return -EINVAL;
5042         }
5043
5044         hr_reg_write(context, QPC_SL, hr_qp->sl);
5045         hr_reg_clear(qpc_mask, QPC_SL);
5046
5047         return 0;
5048 }
5049
5050 static bool check_qp_state(enum ib_qp_state cur_state,
5051                            enum ib_qp_state new_state)
5052 {
5053         static const bool sm[][IB_QPS_ERR + 1] = {
5054                 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
5055                                    [IB_QPS_INIT] = true },
5056                 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
5057                                   [IB_QPS_INIT] = true,
5058                                   [IB_QPS_RTR] = true,
5059                                   [IB_QPS_ERR] = true },
5060                 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
5061                                  [IB_QPS_RTS] = true,
5062                                  [IB_QPS_ERR] = true },
5063                 [IB_QPS_RTS] = { [IB_QPS_RESET] = true,
5064                                  [IB_QPS_RTS] = true,
5065                                  [IB_QPS_ERR] = true },
5066                 [IB_QPS_SQD] = {},
5067                 [IB_QPS_SQE] = {},
5068                 [IB_QPS_ERR] = { [IB_QPS_RESET] = true,
5069                                  [IB_QPS_ERR] = true }
5070         };
5071
5072         return sm[cur_state][new_state];
5073 }
5074
5075 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
5076                                       const struct ib_qp_attr *attr,
5077                                       int attr_mask,
5078                                       enum ib_qp_state cur_state,
5079                                       enum ib_qp_state new_state,
5080                                       struct hns_roce_v2_qp_context *context,
5081                                       struct hns_roce_v2_qp_context *qpc_mask)
5082 {
5083         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5084         int ret = 0;
5085
5086         if (!check_qp_state(cur_state, new_state)) {
5087                 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n");
5088                 return -EINVAL;
5089         }
5090
5091         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
5092                 memset(qpc_mask, 0, hr_dev->caps.qpc_sz);
5093                 modify_qp_reset_to_init(ibqp, attr, context, qpc_mask);
5094         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
5095                 modify_qp_init_to_init(ibqp, attr, context, qpc_mask);
5096         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
5097                 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
5098                                             qpc_mask);
5099         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
5100                 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
5101                                            qpc_mask);
5102         }
5103
5104         return ret;
5105 }
5106
5107 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout)
5108 {
5109 #define QP_ACK_TIMEOUT_MAX_HIP08 20
5110 #define QP_ACK_TIMEOUT_OFFSET 10
5111 #define QP_ACK_TIMEOUT_MAX 31
5112
5113         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5114                 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) {
5115                         ibdev_warn(&hr_dev->ib_dev,
5116                                    "local ACK timeout shall be 0 to 20.\n");
5117                         return false;
5118                 }
5119                 *timeout += QP_ACK_TIMEOUT_OFFSET;
5120         } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) {
5121                 if (*timeout > QP_ACK_TIMEOUT_MAX) {
5122                         ibdev_warn(&hr_dev->ib_dev,
5123                                    "local ACK timeout shall be 0 to 31.\n");
5124                         return false;
5125                 }
5126         }
5127
5128         return true;
5129 }
5130
5131 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp,
5132                                       const struct ib_qp_attr *attr,
5133                                       int attr_mask,
5134                                       struct hns_roce_v2_qp_context *context,
5135                                       struct hns_roce_v2_qp_context *qpc_mask)
5136 {
5137         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5138         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5139         int ret = 0;
5140         u8 timeout;
5141
5142         if (attr_mask & IB_QP_AV) {
5143                 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context,
5144                                            qpc_mask);
5145                 if (ret)
5146                         return ret;
5147         }
5148
5149         if (attr_mask & IB_QP_TIMEOUT) {
5150                 timeout = attr->timeout;
5151                 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) {
5152                         hr_reg_write(context, QPC_AT, timeout);
5153                         hr_reg_clear(qpc_mask, QPC_AT);
5154                 }
5155         }
5156
5157         if (attr_mask & IB_QP_RETRY_CNT) {
5158                 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt);
5159                 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT);
5160
5161                 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt);
5162                 hr_reg_clear(qpc_mask, QPC_RETRY_CNT);
5163         }
5164
5165         if (attr_mask & IB_QP_RNR_RETRY) {
5166                 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry);
5167                 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT);
5168
5169                 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry);
5170                 hr_reg_clear(qpc_mask, QPC_RNR_CNT);
5171         }
5172
5173         if (attr_mask & IB_QP_SQ_PSN) {
5174                 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn);
5175                 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN);
5176
5177                 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn);
5178                 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN);
5179
5180                 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn);
5181                 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L);
5182
5183                 hr_reg_write(context, QPC_RETRY_MSG_PSN_H,
5184                              attr->sq_psn >> RETRY_MSG_PSN_SHIFT);
5185                 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H);
5186
5187                 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn);
5188                 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN);
5189
5190                 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn);
5191                 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN);
5192         }
5193
5194         if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
5195              attr->max_dest_rd_atomic) {
5196                 hr_reg_write(context, QPC_RR_MAX,
5197                              fls(attr->max_dest_rd_atomic - 1));
5198                 hr_reg_clear(qpc_mask, QPC_RR_MAX);
5199         }
5200
5201         if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
5202                 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1));
5203                 hr_reg_clear(qpc_mask, QPC_SR_MAX);
5204         }
5205
5206         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
5207                 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
5208
5209         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
5210                 hr_reg_write(context, QPC_MIN_RNR_TIME,
5211                             hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ?
5212                             HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer);
5213                 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME);
5214         }
5215
5216         if (attr_mask & IB_QP_RQ_PSN) {
5217                 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn);
5218                 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN);
5219
5220                 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1);
5221                 hr_reg_clear(qpc_mask, QPC_RAQ_PSN);
5222         }
5223
5224         if (attr_mask & IB_QP_QKEY) {
5225                 context->qkey_xrcd = cpu_to_le32(attr->qkey);
5226                 qpc_mask->qkey_xrcd = 0;
5227                 hr_qp->qkey = attr->qkey;
5228         }
5229
5230         return ret;
5231 }
5232
5233 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp,
5234                                           const struct ib_qp_attr *attr,
5235                                           int attr_mask)
5236 {
5237         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5238         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5239
5240         if (attr_mask & IB_QP_ACCESS_FLAGS)
5241                 hr_qp->atomic_rd_en = attr->qp_access_flags;
5242
5243         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
5244                 hr_qp->resp_depth = attr->max_dest_rd_atomic;
5245         if (attr_mask & IB_QP_PORT) {
5246                 hr_qp->port = attr->port_num - 1;
5247                 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
5248         }
5249 }
5250
5251 static void clear_qp(struct hns_roce_qp *hr_qp)
5252 {
5253         struct ib_qp *ibqp = &hr_qp->ibqp;
5254
5255         if (ibqp->send_cq)
5256                 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
5257                                      hr_qp->qpn, NULL);
5258
5259         if (ibqp->recv_cq  && ibqp->recv_cq != ibqp->send_cq)
5260                 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq),
5261                                      hr_qp->qpn, ibqp->srq ?
5262                                      to_hr_srq(ibqp->srq) : NULL);
5263
5264         if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
5265                 *hr_qp->rdb.db_record = 0;
5266
5267         hr_qp->rq.head = 0;
5268         hr_qp->rq.tail = 0;
5269         hr_qp->sq.head = 0;
5270         hr_qp->sq.tail = 0;
5271         hr_qp->next_sge = 0;
5272 }
5273
5274 static void v2_set_flushed_fields(struct ib_qp *ibqp,
5275                                   struct hns_roce_v2_qp_context *context,
5276                                   struct hns_roce_v2_qp_context *qpc_mask)
5277 {
5278         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5279         unsigned long sq_flag = 0;
5280         unsigned long rq_flag = 0;
5281
5282         if (ibqp->qp_type == IB_QPT_XRC_TGT)
5283                 return;
5284
5285         spin_lock_irqsave(&hr_qp->sq.lock, sq_flag);
5286         hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head);
5287         hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX);
5288         hr_qp->state = IB_QPS_ERR;
5289         spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag);
5290
5291         if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */
5292                 return;
5293
5294         spin_lock_irqsave(&hr_qp->rq.lock, rq_flag);
5295         hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head);
5296         hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX);
5297         spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag);
5298 }
5299
5300 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
5301                                  const struct ib_qp_attr *attr,
5302                                  int attr_mask, enum ib_qp_state cur_state,
5303                                  enum ib_qp_state new_state)
5304 {
5305         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5306         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5307         struct hns_roce_v2_qp_context ctx[2];
5308         struct hns_roce_v2_qp_context *context = ctx;
5309         struct hns_roce_v2_qp_context *qpc_mask = ctx + 1;
5310         struct ib_device *ibdev = &hr_dev->ib_dev;
5311         int ret;
5312
5313         if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
5314                 return -EOPNOTSUPP;
5315
5316         /*
5317          * In v2 engine, software pass context and context mask to hardware
5318          * when modifying qp. If software need modify some fields in context,
5319          * we should set all bits of the relevant fields in context mask to
5320          * 0 at the same time, else set them to 0x1.
5321          */
5322         memset(context, 0, hr_dev->caps.qpc_sz);
5323         memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz);
5324
5325         ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
5326                                          new_state, context, qpc_mask);
5327         if (ret)
5328                 goto out;
5329
5330         /* When QP state is err, SQ and RQ WQE should be flushed */
5331         if (new_state == IB_QPS_ERR)
5332                 v2_set_flushed_fields(ibqp, context, qpc_mask);
5333
5334         /* Configure the optional fields */
5335         ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context,
5336                                          qpc_mask);
5337         if (ret)
5338                 goto out;
5339
5340         hr_reg_write_bool(context, QPC_INV_CREDIT,
5341                           to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC ||
5342                           ibqp->srq);
5343         hr_reg_clear(qpc_mask, QPC_INV_CREDIT);
5344
5345         /* Every status migrate must change state */
5346         hr_reg_write(context, QPC_QP_ST, new_state);
5347         hr_reg_clear(qpc_mask, QPC_QP_ST);
5348
5349         /* SW pass context to HW */
5350         ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp);
5351         if (ret) {
5352                 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret);
5353                 goto out;
5354         }
5355
5356         hr_qp->state = new_state;
5357
5358         hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask);
5359
5360         if (new_state == IB_QPS_RESET && !ibqp->uobject)
5361                 clear_qp(hr_qp);
5362
5363 out:
5364         return ret;
5365 }
5366
5367 static int to_ib_qp_st(enum hns_roce_v2_qp_state state)
5368 {
5369         static const enum ib_qp_state map[] = {
5370                 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET,
5371                 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT,
5372                 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR,
5373                 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS,
5374                 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD,
5375                 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE,
5376                 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR,
5377                 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD
5378         };
5379
5380         return (state < ARRAY_SIZE(map)) ? map[state] : -1;
5381 }
5382
5383 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn,
5384                                  void *buffer)
5385 {
5386         struct hns_roce_cmd_mailbox *mailbox;
5387         int ret;
5388
5389         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5390         if (IS_ERR(mailbox))
5391                 return PTR_ERR(mailbox);
5392
5393         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC,
5394                                 qpn);
5395         if (ret)
5396                 goto out;
5397
5398         memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz);
5399
5400 out:
5401         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5402         return ret;
5403 }
5404
5405 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5406                                 int qp_attr_mask,
5407                                 struct ib_qp_init_attr *qp_init_attr)
5408 {
5409         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5410         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5411         struct hns_roce_v2_qp_context context = {};
5412         struct ib_device *ibdev = &hr_dev->ib_dev;
5413         int tmp_qp_state;
5414         int state;
5415         int ret;
5416
5417         memset(qp_attr, 0, sizeof(*qp_attr));
5418         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5419
5420         mutex_lock(&hr_qp->mutex);
5421
5422         if (hr_qp->state == IB_QPS_RESET) {
5423                 qp_attr->qp_state = IB_QPS_RESET;
5424                 ret = 0;
5425                 goto done;
5426         }
5427
5428         ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context);
5429         if (ret) {
5430                 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret);
5431                 ret = -EINVAL;
5432                 goto out;
5433         }
5434
5435         state = hr_reg_read(&context, QPC_QP_ST);
5436         tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
5437         if (tmp_qp_state == -1) {
5438                 ibdev_err(ibdev, "Illegal ib_qp_state\n");
5439                 ret = -EINVAL;
5440                 goto out;
5441         }
5442         hr_qp->state = (u8)tmp_qp_state;
5443         qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
5444         qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU);
5445         qp_attr->path_mig_state = IB_MIG_ARMED;
5446         qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
5447         if (hr_qp->ibqp.qp_type == IB_QPT_UD)
5448                 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd);
5449
5450         qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN);
5451         qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN);
5452         qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN);
5453         qp_attr->qp_access_flags =
5454                 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) |
5455                 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) |
5456                 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S);
5457
5458         if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
5459             hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5460             hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) {
5461                 struct ib_global_route *grh =
5462                         rdma_ah_retrieve_grh(&qp_attr->ah_attr);
5463
5464                 rdma_ah_set_sl(&qp_attr->ah_attr,
5465                                hr_reg_read(&context, QPC_SL));
5466                 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1);
5467                 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
5468                 grh->flow_label = hr_reg_read(&context, QPC_FL);
5469                 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX);
5470                 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT);
5471                 grh->traffic_class = hr_reg_read(&context, QPC_TC);
5472
5473                 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw));
5474         }
5475
5476         qp_attr->port_num = hr_qp->port + 1;
5477         qp_attr->sq_draining = 0;
5478         qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX);
5479         qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX);
5480
5481         qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME);
5482         qp_attr->timeout = (u8)hr_reg_read(&context, QPC_AT);
5483         qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT);
5484         qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT);
5485
5486 done:
5487         qp_attr->cur_qp_state = qp_attr->qp_state;
5488         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
5489         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
5490         qp_attr->cap.max_inline_data = hr_qp->max_inline_data;
5491
5492         qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
5493         qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
5494
5495         qp_init_attr->qp_context = ibqp->qp_context;
5496         qp_init_attr->qp_type = ibqp->qp_type;
5497         qp_init_attr->recv_cq = ibqp->recv_cq;
5498         qp_init_attr->send_cq = ibqp->send_cq;
5499         qp_init_attr->srq = ibqp->srq;
5500         qp_init_attr->cap = qp_attr->cap;
5501         qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits;
5502
5503 out:
5504         mutex_unlock(&hr_qp->mutex);
5505         return ret;
5506 }
5507
5508 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp)
5509 {
5510         return ((hr_qp->ibqp.qp_type == IB_QPT_RC ||
5511                  hr_qp->ibqp.qp_type == IB_QPT_UD ||
5512                  hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5513                  hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
5514                 hr_qp->state != IB_QPS_RESET);
5515 }
5516
5517 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
5518                                          struct hns_roce_qp *hr_qp,
5519                                          struct ib_udata *udata)
5520 {
5521         struct ib_device *ibdev = &hr_dev->ib_dev;
5522         struct hns_roce_cq *send_cq, *recv_cq;
5523         unsigned long flags;
5524         int ret = 0;
5525
5526         if (modify_qp_is_ok(hr_qp)) {
5527                 /* Modify qp to reset before destroying qp */
5528                 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
5529                                             hr_qp->state, IB_QPS_RESET);
5530                 if (ret)
5531                         ibdev_err(ibdev,
5532                                   "failed to modify QP to RST, ret = %d.\n",
5533                                   ret);
5534         }
5535
5536         send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
5537         recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
5538
5539         spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
5540         hns_roce_lock_cqs(send_cq, recv_cq);
5541
5542         if (!udata) {
5543                 if (recv_cq)
5544                         __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn,
5545                                                (hr_qp->ibqp.srq ?
5546                                                 to_hr_srq(hr_qp->ibqp.srq) :
5547                                                 NULL));
5548
5549                 if (send_cq && send_cq != recv_cq)
5550                         __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
5551         }
5552
5553         hns_roce_qp_remove(hr_dev, hr_qp);
5554
5555         hns_roce_unlock_cqs(send_cq, recv_cq);
5556         spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
5557
5558         return ret;
5559 }
5560
5561 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
5562 {
5563         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5564         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5565         int ret;
5566
5567         ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
5568         if (ret)
5569                 ibdev_err(&hr_dev->ib_dev,
5570                           "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n",
5571                           hr_qp->qpn, ret);
5572
5573         hns_roce_qp_destroy(hr_dev, hr_qp, udata);
5574
5575         return 0;
5576 }
5577
5578 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
5579                                             struct hns_roce_qp *hr_qp)
5580 {
5581         struct ib_device *ibdev = &hr_dev->ib_dev;
5582         struct hns_roce_sccc_clr_done *resp;
5583         struct hns_roce_sccc_clr *clr;
5584         struct hns_roce_cmq_desc desc;
5585         int ret, i;
5586
5587         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
5588                 return 0;
5589
5590         mutex_lock(&hr_dev->qp_table.scc_mutex);
5591
5592         /* set scc ctx clear done flag */
5593         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
5594         ret =  hns_roce_cmq_send(hr_dev, &desc, 1);
5595         if (ret) {
5596                 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret);
5597                 goto out;
5598         }
5599
5600         /* clear scc context */
5601         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
5602         clr = (struct hns_roce_sccc_clr *)desc.data;
5603         clr->qpn = cpu_to_le32(hr_qp->qpn);
5604         ret =  hns_roce_cmq_send(hr_dev, &desc, 1);
5605         if (ret) {
5606                 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret);
5607                 goto out;
5608         }
5609
5610         /* query scc context clear is done or not */
5611         resp = (struct hns_roce_sccc_clr_done *)desc.data;
5612         for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
5613                 hns_roce_cmq_setup_basic_desc(&desc,
5614                                               HNS_ROCE_OPC_QUERY_SCCC, true);
5615                 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5616                 if (ret) {
5617                         ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
5618                                   ret);
5619                         goto out;
5620                 }
5621
5622                 if (resp->clr_done)
5623                         goto out;
5624
5625                 msleep(20);
5626         }
5627
5628         ibdev_err(ibdev, "query SCC clr done flag overtime.\n");
5629         ret = -ETIMEDOUT;
5630
5631 out:
5632         mutex_unlock(&hr_dev->qp_table.scc_mutex);
5633         return ret;
5634 }
5635
5636 #define DMA_IDX_SHIFT 3
5637 #define DMA_WQE_SHIFT 3
5638
5639 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq,
5640                                               struct hns_roce_srq_context *ctx)
5641 {
5642         struct hns_roce_idx_que *idx_que = &srq->idx_que;
5643         struct ib_device *ibdev = srq->ibsrq.device;
5644         struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5645         u64 mtts_idx[MTT_MIN_COUNT] = {};
5646         dma_addr_t dma_handle_idx = 0;
5647         int ret;
5648
5649         /* Get physical address of idx que buf */
5650         ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx,
5651                                 ARRAY_SIZE(mtts_idx), &dma_handle_idx);
5652         if (ret < 1) {
5653                 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n",
5654                           ret);
5655                 return -ENOBUFS;
5656         }
5657
5658         hr_reg_write(ctx, SRQC_IDX_HOP_NUM,
5659                      to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt));
5660
5661         hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT);
5662         hr_reg_write(ctx, SRQC_IDX_BT_BA_H,
5663                      upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT));
5664
5665         hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ,
5666                      to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift));
5667         hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ,
5668                      to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift));
5669
5670         hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L,
5671                      to_hr_hw_page_addr(mtts_idx[0]));
5672         hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H,
5673                      upper_32_bits(to_hr_hw_page_addr(mtts_idx[0])));
5674
5675         hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L,
5676                      to_hr_hw_page_addr(mtts_idx[1]));
5677         hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H,
5678                      upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
5679
5680         return 0;
5681 }
5682
5683 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf)
5684 {
5685         struct ib_device *ibdev = srq->ibsrq.device;
5686         struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5687         struct hns_roce_srq_context *ctx = mb_buf;
5688         u64 mtts_wqe[MTT_MIN_COUNT] = {};
5689         dma_addr_t dma_handle_wqe = 0;
5690         int ret;
5691
5692         memset(ctx, 0, sizeof(*ctx));
5693
5694         /* Get the physical address of srq buf */
5695         ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe,
5696                                 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe);
5697         if (ret < 1) {
5698                 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n",
5699                           ret);
5700                 return -ENOBUFS;
5701         }
5702
5703         hr_reg_write(ctx, SRQC_SRQ_ST, 1);
5704         hr_reg_write_bool(ctx, SRQC_SRQ_TYPE,
5705                           srq->ibsrq.srq_type == IB_SRQT_XRC);
5706         hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn);
5707         hr_reg_write(ctx, SRQC_SRQN, srq->srqn);
5708         hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn);
5709         hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn);
5710         hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt));
5711         hr_reg_write(ctx, SRQC_RQWS,
5712                      srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1));
5713
5714         hr_reg_write(ctx, SRQC_WQE_HOP_NUM,
5715                      to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num,
5716                                       srq->wqe_cnt));
5717
5718         hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT);
5719         hr_reg_write(ctx, SRQC_WQE_BT_BA_H,
5720                      upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT));
5721
5722         hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ,
5723                      to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift));
5724         hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ,
5725                      to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift));
5726
5727         return hns_roce_v2_write_srqc_index_queue(srq, ctx);
5728 }
5729
5730 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5731                                   struct ib_srq_attr *srq_attr,
5732                                   enum ib_srq_attr_mask srq_attr_mask,
5733                                   struct ib_udata *udata)
5734 {
5735         struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5736         struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5737         struct hns_roce_srq_context *srq_context;
5738         struct hns_roce_srq_context *srqc_mask;
5739         struct hns_roce_cmd_mailbox *mailbox;
5740         int ret;
5741
5742         /* Resizing SRQs is not supported yet */
5743         if (srq_attr_mask & IB_SRQ_MAX_WR)
5744                 return -EINVAL;
5745
5746         if (srq_attr_mask & IB_SRQ_LIMIT) {
5747                 if (srq_attr->srq_limit > srq->wqe_cnt)
5748                         return -EINVAL;
5749
5750                 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5751                 if (IS_ERR(mailbox))
5752                         return PTR_ERR(mailbox);
5753
5754                 srq_context = mailbox->buf;
5755                 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5756
5757                 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5758
5759                 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit);
5760                 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL);
5761
5762                 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5763                                         HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn);
5764                 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5765                 if (ret) {
5766                         ibdev_err(&hr_dev->ib_dev,
5767                                   "failed to handle cmd of modifying SRQ, ret = %d.\n",
5768                                   ret);
5769                         return ret;
5770                 }
5771         }
5772
5773         return 0;
5774 }
5775
5776 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
5777 {
5778         struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5779         struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5780         struct hns_roce_srq_context *srq_context;
5781         struct hns_roce_cmd_mailbox *mailbox;
5782         int ret;
5783
5784         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5785         if (IS_ERR(mailbox))
5786                 return PTR_ERR(mailbox);
5787
5788         srq_context = mailbox->buf;
5789         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5790                                 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn);
5791         if (ret) {
5792                 ibdev_err(&hr_dev->ib_dev,
5793                           "failed to process cmd of querying SRQ, ret = %d.\n",
5794                           ret);
5795                 goto out;
5796         }
5797
5798         attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL);
5799         attr->max_wr = srq->wqe_cnt;
5800         attr->max_sge = srq->max_gs - srq->rsv_sge;
5801
5802 out:
5803         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5804         return ret;
5805 }
5806
5807 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
5808 {
5809         struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
5810         struct hns_roce_v2_cq_context *cq_context;
5811         struct hns_roce_cq *hr_cq = to_hr_cq(cq);
5812         struct hns_roce_v2_cq_context *cqc_mask;
5813         struct hns_roce_cmd_mailbox *mailbox;
5814         int ret;
5815
5816         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5817         if (IS_ERR(mailbox))
5818                 return PTR_ERR(mailbox);
5819
5820         cq_context = mailbox->buf;
5821         cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
5822
5823         memset(cqc_mask, 0xff, sizeof(*cqc_mask));
5824
5825         hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count);
5826         hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT);
5827
5828         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5829                 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
5830                         dev_info(hr_dev->dev,
5831                                  "cq_period(%u) reached the upper limit, adjusted to 65.\n",
5832                                  cq_period);
5833                         cq_period = HNS_ROCE_MAX_CQ_PERIOD;
5834                 }
5835                 cq_period *= HNS_ROCE_CLOCK_ADJUST;
5836         }
5837         hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period);
5838         hr_reg_clear(cqc_mask, CQC_CQ_PERIOD);
5839
5840         ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5841                                 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn);
5842         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5843         if (ret)
5844                 ibdev_err(&hr_dev->ib_dev,
5845                           "failed to process cmd when modifying CQ, ret = %d.\n",
5846                           ret);
5847
5848         return ret;
5849 }
5850
5851 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn,
5852                                  void *buffer)
5853 {
5854         struct hns_roce_v2_cq_context *context;
5855         struct hns_roce_cmd_mailbox *mailbox;
5856         int ret;
5857
5858         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5859         if (IS_ERR(mailbox))
5860                 return PTR_ERR(mailbox);
5861
5862         context = mailbox->buf;
5863         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5864                                 HNS_ROCE_CMD_QUERY_CQC, cqn);
5865         if (ret) {
5866                 ibdev_err(&hr_dev->ib_dev,
5867                           "failed to process cmd when querying CQ, ret = %d.\n",
5868                           ret);
5869                 goto err_mailbox;
5870         }
5871
5872         memcpy(buffer, context, sizeof(*context));
5873
5874 err_mailbox:
5875         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5876
5877         return ret;
5878 }
5879
5880 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key,
5881                                  void *buffer)
5882 {
5883         struct hns_roce_v2_mpt_entry *context;
5884         struct hns_roce_cmd_mailbox *mailbox;
5885         int ret;
5886
5887         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5888         if (IS_ERR(mailbox))
5889                 return PTR_ERR(mailbox);
5890
5891         context = mailbox->buf;
5892         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT,
5893                                 key_to_hw_index(key));
5894         if (ret) {
5895                 ibdev_err(&hr_dev->ib_dev,
5896                           "failed to process cmd when querying MPT, ret = %d.\n",
5897                           ret);
5898                 goto err_mailbox;
5899         }
5900
5901         memcpy(buffer, context, sizeof(*context));
5902
5903 err_mailbox:
5904         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5905
5906         return ret;
5907 }
5908
5909 static void hns_roce_irq_work_handle(struct work_struct *work)
5910 {
5911         struct hns_roce_work *irq_work =
5912                                 container_of(work, struct hns_roce_work, work);
5913         struct ib_device *ibdev = &irq_work->hr_dev->ib_dev;
5914
5915         switch (irq_work->event_type) {
5916         case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5917                 ibdev_info(ibdev, "path migrated succeeded.\n");
5918                 break;
5919         case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5920                 ibdev_warn(ibdev, "path migration failed.\n");
5921                 break;
5922         case HNS_ROCE_EVENT_TYPE_COMM_EST:
5923                 break;
5924         case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5925                 ibdev_warn(ibdev, "send queue drained.\n");
5926                 break;
5927         case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5928                 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n",
5929                           irq_work->queue_num, irq_work->sub_type);
5930                 break;
5931         case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5932                 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n",
5933                           irq_work->queue_num);
5934                 break;
5935         case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5936                 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n",
5937                           irq_work->queue_num, irq_work->sub_type);
5938                 break;
5939         case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5940                 ibdev_warn(ibdev, "SRQ limit reach.\n");
5941                 break;
5942         case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5943                 ibdev_warn(ibdev, "SRQ last wqe reach.\n");
5944                 break;
5945         case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5946                 ibdev_err(ibdev, "SRQ catas error.\n");
5947                 break;
5948         case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5949                 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num);
5950                 break;
5951         case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5952                 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num);
5953                 break;
5954         case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5955                 ibdev_warn(ibdev, "DB overflow.\n");
5956                 break;
5957         case HNS_ROCE_EVENT_TYPE_FLR:
5958                 ibdev_warn(ibdev, "function level reset.\n");
5959                 break;
5960         case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5961                 ibdev_err(ibdev, "xrc domain violation error.\n");
5962                 break;
5963         case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5964                 ibdev_err(ibdev, "invalid xrceth error.\n");
5965                 break;
5966         default:
5967                 break;
5968         }
5969
5970         kfree(irq_work);
5971 }
5972
5973 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
5974                                       struct hns_roce_eq *eq, u32 queue_num)
5975 {
5976         struct hns_roce_work *irq_work;
5977
5978         irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
5979         if (!irq_work)
5980                 return;
5981
5982         INIT_WORK(&irq_work->work, hns_roce_irq_work_handle);
5983         irq_work->hr_dev = hr_dev;
5984         irq_work->event_type = eq->event_type;
5985         irq_work->sub_type = eq->sub_type;
5986         irq_work->queue_num = queue_num;
5987         queue_work(hr_dev->irq_workq, &irq_work->work);
5988 }
5989
5990 static void update_eq_db(struct hns_roce_eq *eq)
5991 {
5992         struct hns_roce_dev *hr_dev = eq->hr_dev;
5993         struct hns_roce_v2_db eq_db = {};
5994
5995         if (eq->type_flag == HNS_ROCE_AEQ) {
5996                 hr_reg_write(&eq_db, EQ_DB_CMD,
5997                              eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5998                              HNS_ROCE_EQ_DB_CMD_AEQ :
5999                              HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
6000         } else {
6001                 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn);
6002
6003                 hr_reg_write(&eq_db, EQ_DB_CMD,
6004                              eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
6005                              HNS_ROCE_EQ_DB_CMD_CEQ :
6006                              HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
6007         }
6008
6009         hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index);
6010
6011         hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg);
6012 }
6013
6014 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
6015 {
6016         struct hns_roce_aeqe *aeqe;
6017
6018         aeqe = hns_roce_buf_offset(eq->mtr.kmem,
6019                                    (eq->cons_index & (eq->entries - 1)) *
6020                                    eq->eqe_size);
6021
6022         return (hr_reg_read(aeqe, AEQE_OWNER) ^
6023                 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
6024 }
6025
6026 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
6027                                        struct hns_roce_eq *eq)
6028 {
6029         struct device *dev = hr_dev->dev;
6030         struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);
6031         irqreturn_t aeqe_found = IRQ_NONE;
6032         int event_type;
6033         u32 queue_num;
6034         int sub_type;
6035
6036         while (aeqe) {
6037                 /* Make sure we read AEQ entry after we have checked the
6038                  * ownership bit
6039                  */
6040                 dma_rmb();
6041
6042                 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE);
6043                 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE);
6044                 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM);
6045
6046                 switch (event_type) {
6047                 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
6048                 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
6049                 case HNS_ROCE_EVENT_TYPE_COMM_EST:
6050                 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
6051                 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
6052                 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
6053                 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
6054                 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
6055                 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
6056                 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
6057                         hns_roce_qp_event(hr_dev, queue_num, event_type);
6058                         break;
6059                 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
6060                 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
6061                         hns_roce_srq_event(hr_dev, queue_num, event_type);
6062                         break;
6063                 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
6064                 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
6065                         hns_roce_cq_event(hr_dev, queue_num, event_type);
6066                         break;
6067                 case HNS_ROCE_EVENT_TYPE_MB:
6068                         hns_roce_cmd_event(hr_dev,
6069                                         le16_to_cpu(aeqe->event.cmd.token),
6070                                         aeqe->event.cmd.status,
6071                                         le64_to_cpu(aeqe->event.cmd.out_param));
6072                         break;
6073                 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
6074                 case HNS_ROCE_EVENT_TYPE_FLR:
6075                         break;
6076                 default:
6077                         dev_err(dev, "unhandled event %d on EQ %d at idx %u.\n",
6078                                 event_type, eq->eqn, eq->cons_index);
6079                         break;
6080                 }
6081
6082                 eq->event_type = event_type;
6083                 eq->sub_type = sub_type;
6084                 ++eq->cons_index;
6085                 aeqe_found = IRQ_HANDLED;
6086
6087                 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num);
6088
6089                 aeqe = next_aeqe_sw_v2(eq);
6090         }
6091
6092         update_eq_db(eq);
6093
6094         return IRQ_RETVAL(aeqe_found);
6095 }
6096
6097 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
6098 {
6099         struct hns_roce_ceqe *ceqe;
6100
6101         ceqe = hns_roce_buf_offset(eq->mtr.kmem,
6102                                    (eq->cons_index & (eq->entries - 1)) *
6103                                    eq->eqe_size);
6104
6105         return (hr_reg_read(ceqe, CEQE_OWNER) ^
6106                 !!(eq->cons_index & eq->entries)) ? ceqe : NULL;
6107 }
6108
6109 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
6110                                        struct hns_roce_eq *eq)
6111 {
6112         struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
6113         irqreturn_t ceqe_found = IRQ_NONE;
6114         u32 cqn;
6115
6116         while (ceqe) {
6117                 /* Make sure we read CEQ entry after we have checked the
6118                  * ownership bit
6119                  */
6120                 dma_rmb();
6121
6122                 cqn = hr_reg_read(ceqe, CEQE_CQN);
6123
6124                 hns_roce_cq_completion(hr_dev, cqn);
6125
6126                 ++eq->cons_index;
6127                 ceqe_found = IRQ_HANDLED;
6128
6129                 ceqe = next_ceqe_sw_v2(eq);
6130         }
6131
6132         update_eq_db(eq);
6133
6134         return IRQ_RETVAL(ceqe_found);
6135 }
6136
6137 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
6138 {
6139         struct hns_roce_eq *eq = eq_ptr;
6140         struct hns_roce_dev *hr_dev = eq->hr_dev;
6141         irqreturn_t int_work;
6142
6143         if (eq->type_flag == HNS_ROCE_CEQ)
6144                 /* Completion event interrupt */
6145                 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
6146         else
6147                 /* Asynchronous event interrupt */
6148                 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
6149
6150         return IRQ_RETVAL(int_work);
6151 }
6152
6153 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev,
6154                                             u32 int_st)
6155 {
6156         struct pci_dev *pdev = hr_dev->pci_dev;
6157         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
6158         const struct hnae3_ae_ops *ops = ae_dev->ops;
6159         irqreturn_t int_work = IRQ_NONE;
6160         u32 int_en;
6161
6162         int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
6163
6164         if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
6165                 dev_err(hr_dev->dev, "AEQ overflow!\n");
6166
6167                 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG,
6168                            1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S);
6169
6170                 /* Set reset level for reset_event() */
6171                 if (ops->set_default_reset_request)
6172                         ops->set_default_reset_request(ae_dev,
6173                                                        HNAE3_FUNC_RESET);
6174                 if (ops->reset_event)
6175                         ops->reset_event(pdev, NULL);
6176
6177                 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
6178                 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
6179
6180                 int_work = IRQ_HANDLED;
6181         } else {
6182                 dev_err(hr_dev->dev, "there is no basic abn irq found.\n");
6183         }
6184
6185         return IRQ_RETVAL(int_work);
6186 }
6187
6188 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev,
6189                                struct fmea_ram_ecc *ecc_info)
6190 {
6191         struct hns_roce_cmq_desc desc;
6192         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6193         int ret;
6194
6195         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true);
6196         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6197         if (ret)
6198                 return ret;
6199
6200         ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR);
6201         ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE);
6202         ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG);
6203
6204         return 0;
6205 }
6206
6207 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx)
6208 {
6209         struct hns_roce_cmq_desc desc;
6210         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6211         u32 addr_upper;
6212         u32 addr_low;
6213         int ret;
6214
6215         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true);
6216         hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6217
6218         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6219         if (ret) {
6220                 dev_err(hr_dev->dev,
6221                         "failed to execute cmd to read gmv, ret = %d.\n", ret);
6222                 return ret;
6223         }
6224
6225         addr_low =  hr_reg_read(req, CFG_GMV_BT_BA_L);
6226         addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H);
6227
6228         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
6229         hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low);
6230         hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper);
6231         hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6232
6233         return hns_roce_cmq_send(hr_dev, &desc, 1);
6234 }
6235
6236 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data)
6237 {
6238         if (res_type == ECC_RESOURCE_QPC_TIMER ||
6239             res_type == ECC_RESOURCE_CQC_TIMER ||
6240             res_type == ECC_RESOURCE_SCCC)
6241                 return le64_to_cpu(*data);
6242
6243         return le64_to_cpu(*data) << PAGE_SHIFT;
6244 }
6245
6246 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type,
6247                                u32 index)
6248 {
6249         u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op;
6250         u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op;
6251         struct hns_roce_cmd_mailbox *mailbox;
6252         u64 addr;
6253         int ret;
6254
6255         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6256         if (IS_ERR(mailbox))
6257                 return PTR_ERR(mailbox);
6258
6259         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index);
6260         if (ret) {
6261                 dev_err(hr_dev->dev,
6262                         "failed to execute cmd to read fmea ram, ret = %d.\n",
6263                         ret);
6264                 goto out;
6265         }
6266
6267         addr = fmea_get_ram_res_addr(res_type, mailbox->buf);
6268
6269         ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index);
6270         if (ret)
6271                 dev_err(hr_dev->dev,
6272                         "failed to execute cmd to write fmea ram, ret = %d.\n",
6273                         ret);
6274
6275 out:
6276         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6277         return ret;
6278 }
6279
6280 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev,
6281                                  struct fmea_ram_ecc *ecc_info)
6282 {
6283         u32 res_type = ecc_info->res_type;
6284         u32 index = ecc_info->index;
6285         int ret;
6286
6287         BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT);
6288
6289         if (res_type >= ECC_RESOURCE_COUNT) {
6290                 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n",
6291                         res_type);
6292                 return;
6293         }
6294
6295         if (res_type == ECC_RESOURCE_GMV)
6296                 ret = fmea_recover_gmv(hr_dev, index);
6297         else
6298                 ret = fmea_recover_others(hr_dev, res_type, index);
6299         if (ret)
6300                 dev_err(hr_dev->dev,
6301                         "failed to recover %s, index = %u, ret = %d.\n",
6302                         fmea_ram_res[res_type].name, index, ret);
6303 }
6304
6305 static void fmea_ram_ecc_work(struct work_struct *ecc_work)
6306 {
6307         struct hns_roce_dev *hr_dev =
6308                 container_of(ecc_work, struct hns_roce_dev, ecc_work);
6309         struct fmea_ram_ecc ecc_info = {};
6310
6311         if (fmea_ram_ecc_query(hr_dev, &ecc_info)) {
6312                 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n");
6313                 return;
6314         }
6315
6316         if (!ecc_info.is_ecc_err) {
6317                 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n");
6318                 return;
6319         }
6320
6321         fmea_ram_ecc_recover(hr_dev, &ecc_info);
6322 }
6323
6324 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
6325 {
6326         struct hns_roce_dev *hr_dev = dev_id;
6327         irqreturn_t int_work = IRQ_NONE;
6328         u32 int_st;
6329
6330         int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
6331
6332         if (int_st) {
6333                 int_work = abnormal_interrupt_basic(hr_dev, int_st);
6334         } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
6335                 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work);
6336                 int_work = IRQ_HANDLED;
6337         } else {
6338                 dev_err(hr_dev->dev, "there is no abnormal irq found.\n");
6339         }
6340
6341         return IRQ_RETVAL(int_work);
6342 }
6343
6344 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
6345                                         int eq_num, u32 enable_flag)
6346 {
6347         int i;
6348
6349         for (i = 0; i < eq_num; i++)
6350                 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
6351                            i * EQ_REG_OFFSET, enable_flag);
6352
6353         roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag);
6354         roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag);
6355 }
6356
6357 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn)
6358 {
6359         struct device *dev = hr_dev->dev;
6360         int ret;
6361         u8 cmd;
6362
6363         if (eqn < hr_dev->caps.num_comp_vectors)
6364                 cmd = HNS_ROCE_CMD_DESTROY_CEQC;
6365         else
6366                 cmd = HNS_ROCE_CMD_DESTROY_AEQC;
6367
6368         ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M);
6369         if (ret)
6370                 dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn);
6371 }
6372
6373 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6374 {
6375         hns_roce_mtr_destroy(hr_dev, &eq->mtr);
6376 }
6377
6378 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6379 {
6380         eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
6381         eq->cons_index = 0;
6382         eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
6383         eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
6384         eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
6385         eq->shift = ilog2((unsigned int)eq->entries);
6386 }
6387
6388 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
6389                       void *mb_buf)
6390 {
6391         u64 eqe_ba[MTT_MIN_COUNT] = { 0 };
6392         struct hns_roce_eq_context *eqc;
6393         u64 bt_ba = 0;
6394         int count;
6395
6396         eqc = mb_buf;
6397         memset(eqc, 0, sizeof(struct hns_roce_eq_context));
6398
6399         init_eq_config(hr_dev, eq);
6400
6401         /* if not multi-hop, eqe buffer only use one trunk */
6402         count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT,
6403                                   &bt_ba);
6404         if (count < 1) {
6405                 dev_err(hr_dev->dev, "failed to find EQE mtr\n");
6406                 return -ENOBUFS;
6407         }
6408
6409         hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID);
6410         hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num);
6411         hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore);
6412         hr_reg_write(eqc, EQC_COALESCE, eq->coalesce);
6413         hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st);
6414         hr_reg_write(eqc, EQC_EQN, eq->eqn);
6415         hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT);
6416         hr_reg_write(eqc, EQC_EQE_BA_PG_SZ,
6417                      to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
6418         hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ,
6419                      to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
6420         hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX);
6421         hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt);
6422
6423         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6424                 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
6425                         dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n",
6426                                  eq->eq_period);
6427                         eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD;
6428                 }
6429                 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST;
6430         }
6431
6432         hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period);
6433         hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER);
6434         hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3);
6435         hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35);
6436         hr_reg_write(eqc, EQC_SHIFT, eq->shift);
6437         hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX);
6438         hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12);
6439         hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28);
6440         hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60);
6441         hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX);
6442         hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12);
6443         hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44);
6444         hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE);
6445
6446         return 0;
6447 }
6448
6449 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6450 {
6451         struct hns_roce_buf_attr buf_attr = {};
6452         int err;
6453
6454         if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0)
6455                 eq->hop_num = 0;
6456         else
6457                 eq->hop_num = hr_dev->caps.eqe_hop_num;
6458
6459         buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT;
6460         buf_attr.region[0].size = eq->entries * eq->eqe_size;
6461         buf_attr.region[0].hopnum = eq->hop_num;
6462         buf_attr.region_count = 1;
6463
6464         err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr,
6465                                   hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL,
6466                                   0);
6467         if (err)
6468                 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err);
6469
6470         return err;
6471 }
6472
6473 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
6474                                  struct hns_roce_eq *eq, u8 eq_cmd)
6475 {
6476         struct hns_roce_cmd_mailbox *mailbox;
6477         int ret;
6478
6479         /* Allocate mailbox memory */
6480         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6481         if (IS_ERR(mailbox))
6482                 return PTR_ERR(mailbox);
6483
6484         ret = alloc_eq_buf(hr_dev, eq);
6485         if (ret)
6486                 goto free_cmd_mbox;
6487
6488         ret = config_eqc(hr_dev, eq, mailbox->buf);
6489         if (ret)
6490                 goto err_cmd_mbox;
6491
6492         ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn);
6493         if (ret) {
6494                 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
6495                 goto err_cmd_mbox;
6496         }
6497
6498         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6499
6500         return 0;
6501
6502 err_cmd_mbox:
6503         free_eq_buf(hr_dev, eq);
6504
6505 free_cmd_mbox:
6506         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6507
6508         return ret;
6509 }
6510
6511 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
6512                                   int comp_num, int aeq_num, int other_num)
6513 {
6514         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6515         int i, j;
6516         int ret;
6517
6518         for (i = 0; i < irq_num; i++) {
6519                 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
6520                                                GFP_KERNEL);
6521                 if (!hr_dev->irq_names[i]) {
6522                         ret = -ENOMEM;
6523                         goto err_kzalloc_failed;
6524                 }
6525         }
6526
6527         /* irq contains: abnormal + AEQ + CEQ */
6528         for (j = 0; j < other_num; j++)
6529                 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6530                          "hns-abn-%d", j);
6531
6532         for (j = other_num; j < (other_num + aeq_num); j++)
6533                 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6534                          "hns-aeq-%d", j - other_num);
6535
6536         for (j = (other_num + aeq_num); j < irq_num; j++)
6537                 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6538                          "hns-ceq-%d", j - other_num - aeq_num);
6539
6540         for (j = 0; j < irq_num; j++) {
6541                 if (j < other_num)
6542                         ret = request_irq(hr_dev->irq[j],
6543                                           hns_roce_v2_msix_interrupt_abn,
6544                                           0, hr_dev->irq_names[j], hr_dev);
6545
6546                 else if (j < (other_num + comp_num))
6547                         ret = request_irq(eq_table->eq[j - other_num].irq,
6548                                           hns_roce_v2_msix_interrupt_eq,
6549                                           0, hr_dev->irq_names[j + aeq_num],
6550                                           &eq_table->eq[j - other_num]);
6551                 else
6552                         ret = request_irq(eq_table->eq[j - other_num].irq,
6553                                           hns_roce_v2_msix_interrupt_eq,
6554                                           0, hr_dev->irq_names[j - comp_num],
6555                                           &eq_table->eq[j - other_num]);
6556                 if (ret) {
6557                         dev_err(hr_dev->dev, "request irq error!\n");
6558                         goto err_request_failed;
6559                 }
6560         }
6561
6562         return 0;
6563
6564 err_request_failed:
6565         for (j -= 1; j >= 0; j--)
6566                 if (j < other_num)
6567                         free_irq(hr_dev->irq[j], hr_dev);
6568                 else
6569                         free_irq(eq_table->eq[j - other_num].irq,
6570                                  &eq_table->eq[j - other_num]);
6571
6572 err_kzalloc_failed:
6573         for (i -= 1; i >= 0; i--)
6574                 kfree(hr_dev->irq_names[i]);
6575
6576         return ret;
6577 }
6578
6579 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev)
6580 {
6581         int irq_num;
6582         int eq_num;
6583         int i;
6584
6585         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6586         irq_num = eq_num + hr_dev->caps.num_other_vectors;
6587
6588         for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
6589                 free_irq(hr_dev->irq[i], hr_dev);
6590
6591         for (i = 0; i < eq_num; i++)
6592                 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
6593
6594         for (i = 0; i < irq_num; i++)
6595                 kfree(hr_dev->irq_names[i]);
6596 }
6597
6598 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
6599 {
6600         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6601         struct device *dev = hr_dev->dev;
6602         struct hns_roce_eq *eq;
6603         int other_num;
6604         int comp_num;
6605         int aeq_num;
6606         int irq_num;
6607         int eq_num;
6608         u8 eq_cmd;
6609         int ret;
6610         int i;
6611
6612         other_num = hr_dev->caps.num_other_vectors;
6613         comp_num = hr_dev->caps.num_comp_vectors;
6614         aeq_num = hr_dev->caps.num_aeq_vectors;
6615
6616         eq_num = comp_num + aeq_num;
6617         irq_num = eq_num + other_num;
6618
6619         eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
6620         if (!eq_table->eq)
6621                 return -ENOMEM;
6622
6623         /* create eq */
6624         for (i = 0; i < eq_num; i++) {
6625                 eq = &eq_table->eq[i];
6626                 eq->hr_dev = hr_dev;
6627                 eq->eqn = i;
6628                 if (i < comp_num) {
6629                         /* CEQ */
6630                         eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
6631                         eq->type_flag = HNS_ROCE_CEQ;
6632                         eq->entries = hr_dev->caps.ceqe_depth;
6633                         eq->eqe_size = hr_dev->caps.ceqe_size;
6634                         eq->irq = hr_dev->irq[i + other_num + aeq_num];
6635                         eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
6636                         eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
6637                 } else {
6638                         /* AEQ */
6639                         eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
6640                         eq->type_flag = HNS_ROCE_AEQ;
6641                         eq->entries = hr_dev->caps.aeqe_depth;
6642                         eq->eqe_size = hr_dev->caps.aeqe_size;
6643                         eq->irq = hr_dev->irq[i - comp_num + other_num];
6644                         eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
6645                         eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
6646                 }
6647
6648                 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
6649                 if (ret) {
6650                         dev_err(dev, "failed to create eq.\n");
6651                         goto err_create_eq_fail;
6652                 }
6653         }
6654
6655         INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work);
6656
6657         hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0);
6658         if (!hr_dev->irq_workq) {
6659                 dev_err(dev, "failed to create irq workqueue.\n");
6660                 ret = -ENOMEM;
6661                 goto err_create_eq_fail;
6662         }
6663
6664         ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num,
6665                                      other_num);
6666         if (ret) {
6667                 dev_err(dev, "failed to request irq.\n");
6668                 goto err_request_irq_fail;
6669         }
6670
6671         /* enable irq */
6672         hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
6673
6674         return 0;
6675
6676 err_request_irq_fail:
6677         destroy_workqueue(hr_dev->irq_workq);
6678
6679 err_create_eq_fail:
6680         for (i -= 1; i >= 0; i--)
6681                 free_eq_buf(hr_dev, &eq_table->eq[i]);
6682         kfree(eq_table->eq);
6683
6684         return ret;
6685 }
6686
6687 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
6688 {
6689         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6690         int eq_num;
6691         int i;
6692
6693         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6694
6695         /* Disable irq */
6696         hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
6697
6698         __hns_roce_free_irq(hr_dev);
6699         destroy_workqueue(hr_dev->irq_workq);
6700
6701         for (i = 0; i < eq_num; i++) {
6702                 hns_roce_v2_destroy_eqc(hr_dev, i);
6703
6704                 free_eq_buf(hr_dev, &eq_table->eq[i]);
6705         }
6706
6707         kfree(eq_table->eq);
6708 }
6709
6710 static const struct ib_device_ops hns_roce_v2_dev_ops = {
6711         .destroy_qp = hns_roce_v2_destroy_qp,
6712         .modify_cq = hns_roce_v2_modify_cq,
6713         .poll_cq = hns_roce_v2_poll_cq,
6714         .post_recv = hns_roce_v2_post_recv,
6715         .post_send = hns_roce_v2_post_send,
6716         .query_qp = hns_roce_v2_query_qp,
6717         .req_notify_cq = hns_roce_v2_req_notify_cq,
6718 };
6719
6720 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
6721         .modify_srq = hns_roce_v2_modify_srq,
6722         .post_srq_recv = hns_roce_v2_post_srq_recv,
6723         .query_srq = hns_roce_v2_query_srq,
6724 };
6725
6726 static const struct hns_roce_hw hns_roce_hw_v2 = {
6727         .cmq_init = hns_roce_v2_cmq_init,
6728         .cmq_exit = hns_roce_v2_cmq_exit,
6729         .hw_profile = hns_roce_v2_profile,
6730         .hw_init = hns_roce_v2_init,
6731         .hw_exit = hns_roce_v2_exit,
6732         .post_mbox = v2_post_mbox,
6733         .poll_mbox_done = v2_poll_mbox_done,
6734         .chk_mbox_avail = v2_chk_mbox_is_avail,
6735         .set_gid = hns_roce_v2_set_gid,
6736         .set_mac = hns_roce_v2_set_mac,
6737         .write_mtpt = hns_roce_v2_write_mtpt,
6738         .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
6739         .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
6740         .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
6741         .write_cqc = hns_roce_v2_write_cqc,
6742         .set_hem = hns_roce_v2_set_hem,
6743         .clear_hem = hns_roce_v2_clear_hem,
6744         .modify_qp = hns_roce_v2_modify_qp,
6745         .dereg_mr = hns_roce_v2_dereg_mr,
6746         .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
6747         .init_eq = hns_roce_v2_init_eq_table,
6748         .cleanup_eq = hns_roce_v2_cleanup_eq_table,
6749         .write_srqc = hns_roce_v2_write_srqc,
6750         .query_cqc = hns_roce_v2_query_cqc,
6751         .query_qpc = hns_roce_v2_query_qpc,
6752         .query_mpt = hns_roce_v2_query_mpt,
6753         .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
6754         .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
6755 };
6756
6757 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
6758         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
6759         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
6760         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
6761         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
6762         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
6763         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
6764         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
6765          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
6766         /* required last entry */
6767         {0, }
6768 };
6769
6770 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
6771
6772 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
6773                                   struct hnae3_handle *handle)
6774 {
6775         struct hns_roce_v2_priv *priv = hr_dev->priv;
6776         const struct pci_device_id *id;
6777         int i;
6778
6779         hr_dev->pci_dev = handle->pdev;
6780         id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
6781         hr_dev->is_vf = id->driver_data;
6782         hr_dev->dev = &handle->pdev->dev;
6783         hr_dev->hw = &hns_roce_hw_v2;
6784         hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
6785         hr_dev->odb_offset = hr_dev->sdb_offset;
6786
6787         /* Get info from NIC driver. */
6788         hr_dev->reg_base = handle->rinfo.roce_io_base;
6789         hr_dev->mem_base = handle->rinfo.roce_mem_base;
6790         hr_dev->caps.num_ports = 1;
6791         hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
6792         hr_dev->iboe.phy_port[0] = 0;
6793
6794         addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
6795                             hr_dev->iboe.netdevs[0]->dev_addr);
6796
6797         for (i = 0; i < handle->rinfo.num_vectors; i++)
6798                 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
6799                                                 i + handle->rinfo.base_vector);
6800
6801         /* cmd issue mode: 0 is poll, 1 is event */
6802         hr_dev->cmd_mod = 1;
6803         hr_dev->loop_idc = 0;
6804
6805         hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
6806         priv->handle = handle;
6807 }
6808
6809 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6810 {
6811         struct hns_roce_dev *hr_dev;
6812         int ret;
6813
6814         hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
6815         if (!hr_dev)
6816                 return -ENOMEM;
6817
6818         hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
6819         if (!hr_dev->priv) {
6820                 ret = -ENOMEM;
6821                 goto error_failed_kzalloc;
6822         }
6823
6824         hns_roce_hw_v2_get_cfg(hr_dev, handle);
6825
6826         ret = hns_roce_init(hr_dev);
6827         if (ret) {
6828                 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6829                 goto error_failed_cfg;
6830         }
6831
6832         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6833                 ret = free_mr_init(hr_dev);
6834                 if (ret) {
6835                         dev_err(hr_dev->dev, "failed to init free mr!\n");
6836                         goto error_failed_roce_init;
6837                 }
6838         }
6839
6840         handle->priv = hr_dev;
6841
6842         return 0;
6843
6844 error_failed_roce_init:
6845         hns_roce_exit(hr_dev);
6846
6847 error_failed_cfg:
6848         kfree(hr_dev->priv);
6849
6850 error_failed_kzalloc:
6851         ib_dealloc_device(&hr_dev->ib_dev);
6852
6853         return ret;
6854 }
6855
6856 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6857                                            bool reset)
6858 {
6859         struct hns_roce_dev *hr_dev = handle->priv;
6860
6861         if (!hr_dev)
6862                 return;
6863
6864         handle->priv = NULL;
6865
6866         hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
6867         hns_roce_handle_device_err(hr_dev);
6868
6869         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
6870                 free_mr_exit(hr_dev);
6871
6872         hns_roce_exit(hr_dev);
6873         kfree(hr_dev->priv);
6874         ib_dealloc_device(&hr_dev->ib_dev);
6875 }
6876
6877 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6878 {
6879         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
6880         const struct pci_device_id *id;
6881         struct device *dev = &handle->pdev->dev;
6882         int ret;
6883
6884         handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
6885
6886         if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
6887                 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6888                 goto reset_chk_err;
6889         }
6890
6891         id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
6892         if (!id)
6893                 return 0;
6894
6895         if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08)
6896                 return 0;
6897
6898         ret = __hns_roce_hw_v2_init_instance(handle);
6899         if (ret) {
6900                 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6901                 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
6902                 if (ops->ae_dev_resetting(handle) ||
6903                     ops->get_hw_reset_stat(handle))
6904                         goto reset_chk_err;
6905                 else
6906                         return ret;
6907         }
6908
6909         handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
6910
6911         return 0;
6912
6913 reset_chk_err:
6914         dev_err(dev, "Device is busy in resetting state.\n"
6915                      "please retry later.\n");
6916
6917         return -EBUSY;
6918 }
6919
6920 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6921                                            bool reset)
6922 {
6923         if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
6924                 return;
6925
6926         handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
6927
6928         __hns_roce_hw_v2_uninit_instance(handle, reset);
6929
6930         handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6931 }
6932 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
6933 {
6934         struct hns_roce_dev *hr_dev;
6935
6936         if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
6937                 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6938                 return 0;
6939         }
6940
6941         handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
6942         clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6943
6944         hr_dev = handle->priv;
6945         if (!hr_dev)
6946                 return 0;
6947
6948         hr_dev->active = false;
6949         hr_dev->dis_db = true;
6950         hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN;
6951
6952         return 0;
6953 }
6954
6955 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
6956 {
6957         struct device *dev = &handle->pdev->dev;
6958         int ret;
6959
6960         if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
6961                                &handle->rinfo.state)) {
6962                 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6963                 return 0;
6964         }
6965
6966         handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
6967
6968         dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
6969         ret = __hns_roce_hw_v2_init_instance(handle);
6970         if (ret) {
6971                 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
6972                  * callback function, RoCE Engine reinitialize. If RoCE reinit
6973                  * failed, we should inform NIC driver.
6974                  */
6975                 handle->priv = NULL;
6976                 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
6977         } else {
6978                 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6979                 dev_info(dev, "reset done, RoCE client reinit finished.\n");
6980         }
6981
6982         return ret;
6983 }
6984
6985 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
6986 {
6987         if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
6988                 return 0;
6989
6990         handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
6991         dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
6992         msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
6993         __hns_roce_hw_v2_uninit_instance(handle, false);
6994
6995         return 0;
6996 }
6997
6998 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
6999                                        enum hnae3_reset_notify_type type)
7000 {
7001         int ret = 0;
7002
7003         switch (type) {
7004         case HNAE3_DOWN_CLIENT:
7005                 ret = hns_roce_hw_v2_reset_notify_down(handle);
7006                 break;
7007         case HNAE3_INIT_CLIENT:
7008                 ret = hns_roce_hw_v2_reset_notify_init(handle);
7009                 break;
7010         case HNAE3_UNINIT_CLIENT:
7011                 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
7012                 break;
7013         default:
7014                 break;
7015         }
7016
7017         return ret;
7018 }
7019
7020 static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
7021         .init_instance = hns_roce_hw_v2_init_instance,
7022         .uninit_instance = hns_roce_hw_v2_uninit_instance,
7023         .reset_notify = hns_roce_hw_v2_reset_notify,
7024 };
7025
7026 static struct hnae3_client hns_roce_hw_v2_client = {
7027         .name = "hns_roce_hw_v2",
7028         .type = HNAE3_CLIENT_ROCE,
7029         .ops = &hns_roce_hw_v2_ops,
7030 };
7031
7032 static int __init hns_roce_hw_v2_init(void)
7033 {
7034         return hnae3_register_client(&hns_roce_hw_v2_client);
7035 }
7036
7037 static void __exit hns_roce_hw_v2_exit(void)
7038 {
7039         hnae3_unregister_client(&hns_roce_hw_v2_client);
7040 }
7041
7042 module_init(hns_roce_hw_v2_init);
7043 module_exit(hns_roce_hw_v2_exit);
7044
7045 MODULE_LICENSE("Dual BSD/GPL");
7046 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
7047 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
7048 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
7049 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");