drivers/infiniband/hw/hns/hns_roce_hw_v2.c

   1 /*
   2  * Copyright (c) 2016-2017 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/acpi.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/iopoll.h>
  37 #include <linux/kernel.h>
  38 #include <linux/types.h>
  39 #include <net/addrconf.h>
  40 #include <rdma/ib_addr.h>
  41 #include <rdma/ib_cache.h>
  42 #include <rdma/ib_umem.h>
  43 #include <rdma/uverbs_ioctl.h>
  44
  45 #include "hnae3.h"
  46 #include "hns_roce_common.h"
  47 #include "hns_roce_device.h"
  48 #include "hns_roce_cmd.h"
  49 #include "hns_roce_hem.h"
  50 #include "hns_roce_hw_v2.h"
  51
  52 enum {
  53         CMD_RST_PRC_OTHERS,
  54         CMD_RST_PRC_SUCCESS,
  55         CMD_RST_PRC_EBUSY,
  56 };
  57
  58 enum ecc_resource_type {
  59         ECC_RESOURCE_QPC,
  60         ECC_RESOURCE_CQC,
  61         ECC_RESOURCE_MPT,
  62         ECC_RESOURCE_SRQC,
  63         ECC_RESOURCE_GMV,
  64         ECC_RESOURCE_QPC_TIMER,
  65         ECC_RESOURCE_CQC_TIMER,
  66         ECC_RESOURCE_SCCC,
  67         ECC_RESOURCE_COUNT,
  68 };
  69
  70 static const struct {
  71         const char *name;
  72         u8 read_bt0_op;
  73         u8 write_bt0_op;
  74 } fmea_ram_res[] = {
  75         { "ECC_RESOURCE_QPC",
  76           HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 },
  77         { "ECC_RESOURCE_CQC",
  78           HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 },
  79         { "ECC_RESOURCE_MPT",
  80           HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 },
  81         { "ECC_RESOURCE_SRQC",
  82           HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 },
  83         /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */
  84         { "ECC_RESOURCE_GMV",
  85           0, 0 },
  86         { "ECC_RESOURCE_QPC_TIMER",
  87           HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 },
  88         { "ECC_RESOURCE_CQC_TIMER",
  89           HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 },
  90         { "ECC_RESOURCE_SCCC",
  91           HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 },
  92 };
  93
  94 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
  95                                    struct ib_sge *sg)
  96 {
  97         dseg->lkey = cpu_to_le32(sg->lkey);
  98         dseg->addr = cpu_to_le64(sg->addr);
  99         dseg->len  = cpu_to_le32(sg->length);
 100 }
 101
 102 /*
 103  * mapped-value = 1 + real-value
 104  * The hns wr opcode real value is start from 0, In order to distinguish between
 105  * initialized and uninitialized map values, we plus 1 to the actual value when
 106  * defining the mapping, so that the validity can be identified by checking the
 107  * mapped value is greater than 0.
 108  */
 109 #define HR_OPC_MAP(ib_key, hr_key) \
 110                 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key
 111
 112 static const u32 hns_roce_op_code[] = {
 113         HR_OPC_MAP(RDMA_WRITE,                  RDMA_WRITE),
 114         HR_OPC_MAP(RDMA_WRITE_WITH_IMM,         RDMA_WRITE_WITH_IMM),
 115         HR_OPC_MAP(SEND,                        SEND),
 116         HR_OPC_MAP(SEND_WITH_IMM,               SEND_WITH_IMM),
 117         HR_OPC_MAP(RDMA_READ,                   RDMA_READ),
 118         HR_OPC_MAP(ATOMIC_CMP_AND_SWP,          ATOM_CMP_AND_SWAP),
 119         HR_OPC_MAP(ATOMIC_FETCH_AND_ADD,        ATOM_FETCH_AND_ADD),
 120         HR_OPC_MAP(SEND_WITH_INV,               SEND_WITH_INV),
 121         HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP,   ATOM_MSK_CMP_AND_SWAP),
 122         HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD),
 123         HR_OPC_MAP(REG_MR,                      FAST_REG_PMR),
 124 };
 125
 126 static u32 to_hr_opcode(u32 ib_opcode)
 127 {
 128         if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code))
 129                 return HNS_ROCE_V2_WQE_OP_MASK;
 130
 131         return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 :
 132                                              HNS_ROCE_V2_WQE_OP_MASK;
 133 }
 134
 135 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
 136                          const struct ib_reg_wr *wr)
 137 {
 138         struct hns_roce_wqe_frmr_seg *fseg =
 139                 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
 140         struct hns_roce_mr *mr = to_hr_mr(wr->mr);
 141         u64 pbl_ba;
 142
 143         /* use ib_access_flags */
 144         hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND);
 145         hr_reg_write_bool(fseg, FRMR_ATOMIC,
 146                           wr->access & IB_ACCESS_REMOTE_ATOMIC);
 147         hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ);
 148         hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE);
 149         hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE);
 150
 151         /* Data structure reuse may lead to confusion */
 152         pbl_ba = mr->pbl_mtr.hem_cfg.root_ba;
 153         rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba));
 154         rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba));
 155
 156         rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
 157         rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
 158         rc_sq_wqe->rkey = cpu_to_le32(wr->key);
 159         rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
 160
 161         hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages);
 162         hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ,
 163                      to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
 164         hr_reg_clear(fseg, FRMR_BLK_MODE);
 165 }
 166
 167 static void set_atomic_seg(const struct ib_send_wr *wr,
 168                            struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
 169                            unsigned int valid_num_sge)
 170 {
 171         struct hns_roce_v2_wqe_data_seg *dseg =
 172                 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
 173         struct hns_roce_wqe_atomic_seg *aseg =
 174                 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg);
 175
 176         set_data_seg_v2(dseg, wr->sg_list);
 177
 178         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
 179                 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap);
 180                 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add);
 181         } else {
 182                 aseg->fetchadd_swap_data =
 183                         cpu_to_le64(atomic_wr(wr)->compare_add);
 184                 aseg->cmp_data = 0;
 185         }
 186
 187         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
 188 }
 189
 190 static unsigned int get_std_sge_num(struct hns_roce_qp *qp)
 191 {
 192         if (qp->ibqp.qp_type == IB_QPT_GSI || qp->ibqp.qp_type == IB_QPT_UD)
 193                 return 0;
 194
 195         return HNS_ROCE_SGE_IN_WQE;
 196 }
 197
 198 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp,
 199                                  const struct ib_send_wr *wr,
 200                                  unsigned int *sge_idx, u32 msg_len)
 201 {
 202         struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev;
 203         unsigned int left_len_in_pg;
 204         unsigned int idx = *sge_idx;
 205         unsigned int std_sge_num;
 206         unsigned int i = 0;
 207         unsigned int len;
 208         void *addr;
 209         void *dseg;
 210
 211         std_sge_num = get_std_sge_num(qp);
 212         if (msg_len > (qp->sq.max_gs - std_sge_num) * HNS_ROCE_SGE_SIZE) {
 213                 ibdev_err(ibdev,
 214                           "no enough extended sge space for inline data.\n");
 215                 return -EINVAL;
 216         }
 217
 218         dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
 219         left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg;
 220         len = wr->sg_list[0].length;
 221         addr = (void *)(unsigned long)(wr->sg_list[0].addr);
 222
 223         /* When copying data to extended sge space, the left length in page may
 224          * not long enough for current user's sge. So the data should be
 225          * splited into several parts, one in the first page, and the others in
 226          * the subsequent pages.
 227          */
 228         while (1) {
 229                 if (len <= left_len_in_pg) {
 230                         memcpy(dseg, addr, len);
 231
 232                         idx += len / HNS_ROCE_SGE_SIZE;
 233
 234                         i++;
 235                         if (i >= wr->num_sge)
 236                                 break;
 237
 238                         left_len_in_pg -= len;
 239                         len = wr->sg_list[i].length;
 240                         addr = (void *)(unsigned long)(wr->sg_list[i].addr);
 241                         dseg += len;
 242                 } else {
 243                         memcpy(dseg, addr, left_len_in_pg);
 244
 245                         len -= left_len_in_pg;
 246                         addr += left_len_in_pg;
 247                         idx += left_len_in_pg / HNS_ROCE_SGE_SIZE;
 248                         dseg = hns_roce_get_extend_sge(qp,
 249                                                 idx & (qp->sge.sge_cnt - 1));
 250                         left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT;
 251                 }
 252         }
 253
 254         *sge_idx = idx;
 255
 256         return 0;
 257 }
 258
 259 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge,
 260                            unsigned int *sge_ind, unsigned int cnt)
 261 {
 262         struct hns_roce_v2_wqe_data_seg *dseg;
 263         unsigned int idx = *sge_ind;
 264
 265         while (cnt > 0) {
 266                 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
 267                 if (likely(sge->length)) {
 268                         set_data_seg_v2(dseg, sge);
 269                         idx++;
 270                         cnt--;
 271                 }
 272                 sge++;
 273         }
 274
 275         *sge_ind = idx;
 276 }
 277
 278 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len)
 279 {
 280         struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
 281         int mtu = ib_mtu_enum_to_int(qp->path_mtu);
 282
 283         if (len > qp->max_inline_data || len > mtu) {
 284                 ibdev_err(&hr_dev->ib_dev,
 285                           "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n",
 286                           len, qp->max_inline_data, mtu);
 287                 return false;
 288         }
 289
 290         return true;
 291 }
 292
 293 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
 294                       struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
 295                       unsigned int *sge_idx)
 296 {
 297         struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
 298         u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len);
 299         struct ib_device *ibdev = &hr_dev->ib_dev;
 300         unsigned int curr_idx = *sge_idx;
 301         void *dseg = rc_sq_wqe;
 302         unsigned int i;
 303         int ret;
 304
 305         if (unlikely(wr->opcode == IB_WR_RDMA_READ)) {
 306                 ibdev_err(ibdev, "invalid inline parameters!\n");
 307                 return -EINVAL;
 308         }
 309
 310         if (!check_inl_data_len(qp, msg_len))
 311                 return -EINVAL;
 312
 313         dseg += sizeof(struct hns_roce_v2_rc_send_wqe);
 314
 315         if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) {
 316                 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
 317
 318                 for (i = 0; i < wr->num_sge; i++) {
 319                         memcpy(dseg, ((void *)wr->sg_list[i].addr),
 320                                wr->sg_list[i].length);
 321                         dseg += wr->sg_list[i].length;
 322                 }
 323         } else {
 324                 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
 325
 326                 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len);
 327                 if (ret)
 328                         return ret;
 329
 330                 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx);
 331         }
 332
 333         *sge_idx = curr_idx;
 334
 335         return 0;
 336 }
 337
 338 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
 339                              struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
 340                              unsigned int *sge_ind,
 341                              unsigned int valid_num_sge)
 342 {
 343         struct hns_roce_v2_wqe_data_seg *dseg =
 344                 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
 345         struct hns_roce_qp *qp = to_hr_qp(ibqp);
 346         int j = 0;
 347         int i;
 348
 349         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX,
 350                      (*sge_ind) & (qp->sge.sge_cnt - 1));
 351
 352         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE,
 353                      !!(wr->send_flags & IB_SEND_INLINE));
 354         if (wr->send_flags & IB_SEND_INLINE)
 355                 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind);
 356
 357         if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) {
 358                 for (i = 0; i < wr->num_sge; i++) {
 359                         if (likely(wr->sg_list[i].length)) {
 360                                 set_data_seg_v2(dseg, wr->sg_list + i);
 361                                 dseg++;
 362                         }
 363                 }
 364         } else {
 365                 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) {
 366                         if (likely(wr->sg_list[i].length)) {
 367                                 set_data_seg_v2(dseg, wr->sg_list + i);
 368                                 dseg++;
 369                                 j++;
 370                         }
 371                 }
 372
 373                 set_extend_sge(qp, wr->sg_list + i, sge_ind,
 374                                valid_num_sge - HNS_ROCE_SGE_IN_WQE);
 375         }
 376
 377         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
 378
 379         return 0;
 380 }
 381
 382 static int check_send_valid(struct hns_roce_dev *hr_dev,
 383                             struct hns_roce_qp *hr_qp)
 384 {
 385         struct ib_device *ibdev = &hr_dev->ib_dev;
 386         struct ib_qp *ibqp = &hr_qp->ibqp;
 387
 388         if (unlikely(ibqp->qp_type != IB_QPT_RC &&
 389                      ibqp->qp_type != IB_QPT_GSI &&
 390                      ibqp->qp_type != IB_QPT_UD)) {
 391                 ibdev_err(ibdev, "not supported QP(0x%x)type!\n",
 392                           ibqp->qp_type);
 393                 return -EOPNOTSUPP;
 394         } else if (unlikely(hr_qp->state == IB_QPS_RESET ||
 395                    hr_qp->state == IB_QPS_INIT ||
 396                    hr_qp->state == IB_QPS_RTR)) {
 397                 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n",
 398                           hr_qp->state);
 399                 return -EINVAL;
 400         } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) {
 401                 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n",
 402                           hr_dev->state);
 403                 return -EIO;
 404         }
 405
 406         return 0;
 407 }
 408
 409 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr,
 410                                     unsigned int *sge_len)
 411 {
 412         unsigned int valid_num = 0;
 413         unsigned int len = 0;
 414         int i;
 415
 416         for (i = 0; i < wr->num_sge; i++) {
 417                 if (likely(wr->sg_list[i].length)) {
 418                         len += wr->sg_list[i].length;
 419                         valid_num++;
 420                 }
 421         }
 422
 423         *sge_len = len;
 424         return valid_num;
 425 }
 426
 427 static __le32 get_immtdata(const struct ib_send_wr *wr)
 428 {
 429         switch (wr->opcode) {
 430         case IB_WR_SEND_WITH_IMM:
 431         case IB_WR_RDMA_WRITE_WITH_IMM:
 432                 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
 433         default:
 434                 return 0;
 435         }
 436 }
 437
 438 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
 439                          const struct ib_send_wr *wr)
 440 {
 441         u32 ib_op = wr->opcode;
 442
 443         if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM)
 444                 return -EINVAL;
 445
 446         ud_sq_wqe->immtdata = get_immtdata(wr);
 447
 448         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
 449
 450         return 0;
 451 }
 452
 453 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
 454                       struct hns_roce_ah *ah)
 455 {
 456         struct ib_device *ib_dev = ah->ibah.device;
 457         struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
 458
 459         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport);
 460         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit);
 461         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass);
 462         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel);
 463
 464         if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL))
 465                 return -EINVAL;
 466
 467         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl);
 468
 469         ud_sq_wqe->sgid_index = ah->av.gid_index;
 470
 471         memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN);
 472         memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2);
 473
 474         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
 475                 return 0;
 476
 477         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en);
 478         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id);
 479
 480         return 0;
 481 }
 482
 483 static inline int set_ud_wqe(struct hns_roce_qp *qp,
 484                              const struct ib_send_wr *wr,
 485                              void *wqe, unsigned int *sge_idx,
 486                              unsigned int owner_bit)
 487 {
 488         struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
 489         struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe;
 490         unsigned int curr_idx = *sge_idx;
 491         unsigned int valid_num_sge;
 492         u32 msg_len = 0;
 493         int ret;
 494
 495         valid_num_sge = calc_wr_sge_num(wr, &msg_len);
 496
 497         ret = set_ud_opcode(ud_sq_wqe, wr);
 498         if (WARN_ON(ret))
 499                 return ret;
 500
 501         ud_sq_wqe->msg_len = cpu_to_le32(msg_len);
 502
 503         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE,
 504                      !!(wr->send_flags & IB_SEND_SIGNALED));
 505         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE,
 506                      !!(wr->send_flags & IB_SEND_SOLICITED));
 507
 508         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn);
 509         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge);
 510         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX,
 511                      curr_idx & (qp->sge.sge_cnt - 1));
 512
 513         ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
 514                           qp->qkey : ud_wr(wr)->remote_qkey);
 515         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn);
 516
 517         ret = fill_ud_av(ud_sq_wqe, ah);
 518         if (ret)
 519                 return ret;
 520
 521         qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl;
 522
 523         set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge);
 524
 525         /*
 526          * The pipeline can sequentially post all valid WQEs into WQ buffer,
 527          * including new WQEs waiting for the doorbell to update the PI again.
 528          * Therefore, the owner bit of WQE MUST be updated after all fields
 529          * and extSGEs have been written into DDR instead of cache.
 530          */
 531         if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
 532                 dma_wmb();
 533
 534         *sge_idx = curr_idx;
 535         hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit);
 536
 537         return 0;
 538 }
 539
 540 static int set_rc_opcode(struct hns_roce_dev *hr_dev,
 541                          struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
 542                          const struct ib_send_wr *wr)
 543 {
 544         u32 ib_op = wr->opcode;
 545         int ret = 0;
 546
 547         rc_sq_wqe->immtdata = get_immtdata(wr);
 548
 549         switch (ib_op) {
 550         case IB_WR_RDMA_READ:
 551         case IB_WR_RDMA_WRITE:
 552         case IB_WR_RDMA_WRITE_WITH_IMM:
 553                 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
 554                 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
 555                 break;
 556         case IB_WR_SEND:
 557         case IB_WR_SEND_WITH_IMM:
 558                 break;
 559         case IB_WR_ATOMIC_CMP_AND_SWP:
 560         case IB_WR_ATOMIC_FETCH_AND_ADD:
 561                 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey);
 562                 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr);
 563                 break;
 564         case IB_WR_REG_MR:
 565                 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
 566                         set_frmr_seg(rc_sq_wqe, reg_wr(wr));
 567                 else
 568                         ret = -EOPNOTSUPP;
 569                 break;
 570         case IB_WR_SEND_WITH_INV:
 571                 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
 572                 break;
 573         default:
 574                 ret = -EINVAL;
 575         }
 576
 577         if (unlikely(ret))
 578                 return ret;
 579
 580         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
 581
 582         return ret;
 583 }
 584
 585 static inline int set_rc_wqe(struct hns_roce_qp *qp,
 586                              const struct ib_send_wr *wr,
 587                              void *wqe, unsigned int *sge_idx,
 588                              unsigned int owner_bit)
 589 {
 590         struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
 591         struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
 592         unsigned int curr_idx = *sge_idx;
 593         unsigned int valid_num_sge;
 594         u32 msg_len = 0;
 595         int ret;
 596
 597         valid_num_sge = calc_wr_sge_num(wr, &msg_len);
 598
 599         rc_sq_wqe->msg_len = cpu_to_le32(msg_len);
 600
 601         ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr);
 602         if (WARN_ON(ret))
 603                 return ret;
 604
 605         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_FENCE,
 606                      (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
 607
 608         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE,
 609                      (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
 610
 611         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE,
 612                      (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
 613
 614         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
 615             wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
 616                 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge);
 617         else if (wr->opcode != IB_WR_REG_MR)
 618                 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
 619                                         &curr_idx, valid_num_sge);
 620
 621         /*
 622          * The pipeline can sequentially post all valid WQEs into WQ buffer,
 623          * including new WQEs waiting for the doorbell to update the PI again.
 624          * Therefore, the owner bit of WQE MUST be updated after all fields
 625          * and extSGEs have been written into DDR instead of cache.
 626          */
 627         if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
 628                 dma_wmb();
 629
 630         *sge_idx = curr_idx;
 631         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit);
 632
 633         return ret;
 634 }
 635
 636 static inline void update_sq_db(struct hns_roce_dev *hr_dev,
 637                                 struct hns_roce_qp *qp)
 638 {
 639         if (unlikely(qp->state == IB_QPS_ERR)) {
 640                 flush_cqe(hr_dev, qp);
 641         } else {
 642                 struct hns_roce_v2_db sq_db = {};
 643
 644                 hr_reg_write(&sq_db, DB_TAG, qp->qpn);
 645                 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB);
 646                 hr_reg_write(&sq_db, DB_PI, qp->sq.head);
 647                 hr_reg_write(&sq_db, DB_SL, qp->sl);
 648
 649                 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg);
 650         }
 651 }
 652
 653 static inline void update_rq_db(struct hns_roce_dev *hr_dev,
 654                                 struct hns_roce_qp *qp)
 655 {
 656         if (unlikely(qp->state == IB_QPS_ERR)) {
 657                 flush_cqe(hr_dev, qp);
 658         } else {
 659                 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) {
 660                         *qp->rdb.db_record =
 661                                         qp->rq.head & V2_DB_PRODUCER_IDX_M;
 662                 } else {
 663                         struct hns_roce_v2_db rq_db = {};
 664
 665                         hr_reg_write(&rq_db, DB_TAG, qp->qpn);
 666                         hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB);
 667                         hr_reg_write(&rq_db, DB_PI, qp->rq.head);
 668
 669                         hns_roce_write64(hr_dev, (__le32 *)&rq_db,
 670                                          qp->rq.db_reg);
 671                 }
 672         }
 673 }
 674
 675 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val,
 676                               u64 __iomem *dest)
 677 {
 678 #define HNS_ROCE_WRITE_TIMES 8
 679         struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
 680         struct hnae3_handle *handle = priv->handle;
 681         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
 682         int i;
 683
 684         if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
 685                 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++)
 686                         writeq_relaxed(*(val + i), dest + i);
 687 }
 688
 689 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
 690                        void *wqe)
 691 {
 692 #define HNS_ROCE_SL_SHIFT 2
 693         struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
 694
 695         /* All kinds of DirectWQE have the same header field layout */
 696         hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG);
 697         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl);
 698         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H,
 699                      qp->sl >> HNS_ROCE_SL_SHIFT);
 700         hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head);
 701
 702         hns_roce_write512(hr_dev, wqe, qp->sq.db_reg);
 703 }
 704
 705 static int hns_roce_v2_post_send(struct ib_qp *ibqp,
 706                                  const struct ib_send_wr *wr,
 707                                  const struct ib_send_wr **bad_wr)
 708 {
 709         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
 710         struct ib_device *ibdev = &hr_dev->ib_dev;
 711         struct hns_roce_qp *qp = to_hr_qp(ibqp);
 712         unsigned long flags = 0;
 713         unsigned int owner_bit;
 714         unsigned int sge_idx;
 715         unsigned int wqe_idx;
 716         void *wqe = NULL;
 717         u32 nreq;
 718         int ret;
 719
 720         spin_lock_irqsave(&qp->sq.lock, flags);
 721
 722         ret = check_send_valid(hr_dev, qp);
 723         if (unlikely(ret)) {
 724                 *bad_wr = wr;
 725                 nreq = 0;
 726                 goto out;
 727         }
 728
 729         sge_idx = qp->next_sge;
 730
 731         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 732                 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
 733                         ret = -ENOMEM;
 734                         *bad_wr = wr;
 735                         goto out;
 736                 }
 737
 738                 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
 739
 740                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
 741                         ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n",
 742                                   wr->num_sge, qp->sq.max_gs);
 743                         ret = -EINVAL;
 744                         *bad_wr = wr;
 745                         goto out;
 746                 }
 747
 748                 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
 749                 qp->sq.wrid[wqe_idx] = wr->wr_id;
 750                 owner_bit =
 751                        ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
 752
 753                 /* Corresponding to the QP type, wqe process separately */
 754                 if (ibqp->qp_type == IB_QPT_RC)
 755                         ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit);
 756                 else
 757                         ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit);
 758
 759                 if (unlikely(ret)) {
 760                         *bad_wr = wr;
 761                         goto out;
 762                 }
 763         }
 764
 765 out:
 766         if (likely(nreq)) {
 767                 qp->sq.head += nreq;
 768                 qp->next_sge = sge_idx;
 769
 770                 if (nreq == 1 && (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE))
 771                         write_dwqe(hr_dev, qp, wqe);
 772                 else
 773                         update_sq_db(hr_dev, qp);
 774         }
 775
 776         spin_unlock_irqrestore(&qp->sq.lock, flags);
 777
 778         return ret;
 779 }
 780
 781 static int check_recv_valid(struct hns_roce_dev *hr_dev,
 782                             struct hns_roce_qp *hr_qp)
 783 {
 784         struct ib_device *ibdev = &hr_dev->ib_dev;
 785         struct ib_qp *ibqp = &hr_qp->ibqp;
 786
 787         if (unlikely(ibqp->qp_type != IB_QPT_RC &&
 788                      ibqp->qp_type != IB_QPT_GSI &&
 789                      ibqp->qp_type != IB_QPT_UD)) {
 790                 ibdev_err(ibdev, "unsupported qp type, qp_type = %d.\n",
 791                           ibqp->qp_type);
 792                 return -EOPNOTSUPP;
 793         }
 794
 795         if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
 796                 return -EIO;
 797
 798         if (hr_qp->state == IB_QPS_RESET)
 799                 return -EINVAL;
 800
 801         return 0;
 802 }
 803
 804 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe,
 805                                  u32 max_sge, bool rsv)
 806 {
 807         struct hns_roce_v2_wqe_data_seg *dseg = wqe;
 808         u32 i, cnt;
 809
 810         for (i = 0, cnt = 0; i < wr->num_sge; i++) {
 811                 /* Skip zero-length sge */
 812                 if (!wr->sg_list[i].length)
 813                         continue;
 814                 set_data_seg_v2(dseg + cnt, wr->sg_list + i);
 815                 cnt++;
 816         }
 817
 818         /* Fill a reserved sge to make hw stop reading remaining segments */
 819         if (rsv) {
 820                 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
 821                 dseg[cnt].addr = 0;
 822                 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH);
 823         } else {
 824                 /* Clear remaining segments to make ROCEE ignore sges */
 825                 if (cnt < max_sge)
 826                         memset(dseg + cnt, 0,
 827                                (max_sge - cnt) * HNS_ROCE_SGE_SIZE);
 828         }
 829 }
 830
 831 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr,
 832                         u32 wqe_idx, u32 max_sge)
 833 {
 834         struct hns_roce_rinl_sge *sge_list;
 835         void *wqe = NULL;
 836         u32 i;
 837
 838         wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
 839         fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge);
 840
 841         /* rq support inline data */
 842         if (hr_qp->rq_inl_buf.wqe_cnt) {
 843                 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list;
 844                 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt = (u32)wr->num_sge;
 845                 for (i = 0; i < wr->num_sge; i++) {
 846                         sge_list[i].addr = (void *)(u64)wr->sg_list[i].addr;
 847                         sge_list[i].len = wr->sg_list[i].length;
 848                 }
 849         }
 850 }
 851
 852 static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
 853                                  const struct ib_recv_wr *wr,
 854                                  const struct ib_recv_wr **bad_wr)
 855 {
 856         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
 857         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
 858         struct ib_device *ibdev = &hr_dev->ib_dev;
 859         u32 wqe_idx, nreq, max_sge;
 860         unsigned long flags;
 861         int ret;
 862
 863         spin_lock_irqsave(&hr_qp->rq.lock, flags);
 864
 865         ret = check_recv_valid(hr_dev, hr_qp);
 866         if (unlikely(ret)) {
 867                 *bad_wr = wr;
 868                 nreq = 0;
 869                 goto out;
 870         }
 871
 872         max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
 873         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 874                 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq,
 875                                                   hr_qp->ibqp.recv_cq))) {
 876                         ret = -ENOMEM;
 877                         *bad_wr = wr;
 878                         goto out;
 879                 }
 880
 881                 if (unlikely(wr->num_sge > max_sge)) {
 882                         ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n",
 883                                   wr->num_sge, max_sge);
 884                         ret = -EINVAL;
 885                         *bad_wr = wr;
 886                         goto out;
 887                 }
 888
 889                 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
 890                 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge);
 891                 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
 892         }
 893
 894 out:
 895         if (likely(nreq)) {
 896                 hr_qp->rq.head += nreq;
 897
 898                 update_rq_db(hr_dev, hr_qp);
 899         }
 900         spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
 901
 902         return ret;
 903 }
 904
 905 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n)
 906 {
 907         return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
 908 }
 909
 910 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n)
 911 {
 912         return hns_roce_buf_offset(idx_que->mtr.kmem,
 913                                    n << idx_que->entry_shift);
 914 }
 915
 916 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index)
 917 {
 918         /* always called with interrupts disabled. */
 919         spin_lock(&srq->lock);
 920
 921         bitmap_clear(srq->idx_que.bitmap, wqe_index, 1);
 922         srq->idx_que.tail++;
 923
 924         spin_unlock(&srq->lock);
 925 }
 926
 927 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq)
 928 {
 929         struct hns_roce_idx_que *idx_que = &srq->idx_que;
 930
 931         return idx_que->head - idx_que->tail >= srq->wqe_cnt;
 932 }
 933
 934 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge,
 935                                 const struct ib_recv_wr *wr)
 936 {
 937         struct ib_device *ib_dev = srq->ibsrq.device;
 938
 939         if (unlikely(wr->num_sge > max_sge)) {
 940                 ibdev_err(ib_dev,
 941                           "failed to check sge, wr->num_sge = %d, max_sge = %u.\n",
 942                           wr->num_sge, max_sge);
 943                 return -EINVAL;
 944         }
 945
 946         if (unlikely(hns_roce_srqwq_overflow(srq))) {
 947                 ibdev_err(ib_dev,
 948                           "failed to check srqwq status, srqwq is full.\n");
 949                 return -ENOMEM;
 950         }
 951
 952         return 0;
 953 }
 954
 955 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx)
 956 {
 957         struct hns_roce_idx_que *idx_que = &srq->idx_que;
 958         u32 pos;
 959
 960         pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt);
 961         if (unlikely(pos == srq->wqe_cnt))
 962                 return -ENOSPC;
 963
 964         bitmap_set(idx_que->bitmap, pos, 1);
 965         *wqe_idx = pos;
 966         return 0;
 967 }
 968
 969 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx)
 970 {
 971         struct hns_roce_idx_que *idx_que = &srq->idx_que;
 972         unsigned int head;
 973         __le32 *buf;
 974
 975         head = idx_que->head & (srq->wqe_cnt - 1);
 976
 977         buf = get_idx_buf(idx_que, head);
 978         *buf = cpu_to_le32(wqe_idx);
 979
 980         idx_que->head++;
 981 }
 982
 983 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq)
 984 {
 985         hr_reg_write(db, DB_TAG, srq->srqn);
 986         hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB);
 987         hr_reg_write(db, DB_PI, srq->idx_que.head);
 988 }
 989
 990 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
 991                                      const struct ib_recv_wr *wr,
 992                                      const struct ib_recv_wr **bad_wr)
 993 {
 994         struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
 995         struct hns_roce_srq *srq = to_hr_srq(ibsrq);
 996         struct hns_roce_v2_db srq_db;
 997         unsigned long flags;
 998         int ret = 0;
 999         u32 max_sge;
1000         u32 wqe_idx;
1001         void *wqe;
1002         u32 nreq;
1003
1004         spin_lock_irqsave(&srq->lock, flags);
1005
1006         max_sge = srq->max_gs - srq->rsv_sge;
1007         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1008                 ret = check_post_srq_valid(srq, max_sge, wr);
1009                 if (ret) {
1010                         *bad_wr = wr;
1011                         break;
1012                 }
1013
1014                 ret = get_srq_wqe_idx(srq, &wqe_idx);
1015                 if (unlikely(ret)) {
1016                         *bad_wr = wr;
1017                         break;
1018                 }
1019
1020                 wqe = get_srq_wqe_buf(srq, wqe_idx);
1021                 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge);
1022                 fill_wqe_idx(srq, wqe_idx);
1023                 srq->wrid[wqe_idx] = wr->wr_id;
1024         }
1025
1026         if (likely(nreq)) {
1027                 update_srq_db(&srq_db, srq);
1028
1029                 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg);
1030         }
1031
1032         spin_unlock_irqrestore(&srq->lock, flags);
1033
1034         return ret;
1035 }
1036
1037 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
1038                                       unsigned long instance_stage,
1039                                       unsigned long reset_stage)
1040 {
1041         /* When hardware reset has been completed once or more, we should stop
1042          * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
1043          * function, we should exit with error. If now at HNAE3_INIT_CLIENT
1044          * stage of soft reset process, we should exit with error, and then
1045          * HNAE3_INIT_CLIENT related process can rollback the operation like
1046          * notifing hardware to free resources, HNAE3_INIT_CLIENT related
1047          * process will exit with error to notify NIC driver to reschedule soft
1048          * reset process once again.
1049          */
1050         hr_dev->is_reset = true;
1051         hr_dev->dis_db = true;
1052
1053         if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
1054             instance_stage == HNS_ROCE_STATE_INIT)
1055                 return CMD_RST_PRC_EBUSY;
1056
1057         return CMD_RST_PRC_SUCCESS;
1058 }
1059
1060 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
1061                                         unsigned long instance_stage,
1062                                         unsigned long reset_stage)
1063 {
1064 #define HW_RESET_TIMEOUT_US 1000000
1065 #define HW_RESET_SLEEP_US 1000
1066
1067         struct hns_roce_v2_priv *priv = hr_dev->priv;
1068         struct hnae3_handle *handle = priv->handle;
1069         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1070         unsigned long val;
1071         int ret;
1072
1073         /* When hardware reset is detected, we should stop sending mailbox&cmq&
1074          * doorbell to hardware. If now in .init_instance() function, we should
1075          * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
1076          * process, we should exit with error, and then HNAE3_INIT_CLIENT
1077          * related process can rollback the operation like notifing hardware to
1078          * free resources, HNAE3_INIT_CLIENT related process will exit with
1079          * error to notify NIC driver to reschedule soft reset process once
1080          * again.
1081          */
1082         hr_dev->dis_db = true;
1083
1084         ret = read_poll_timeout(ops->ae_dev_reset_cnt, val,
1085                                 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US,
1086                                 HW_RESET_TIMEOUT_US, false, handle);
1087         if (!ret)
1088                 hr_dev->is_reset = true;
1089
1090         if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
1091             instance_stage == HNS_ROCE_STATE_INIT)
1092                 return CMD_RST_PRC_EBUSY;
1093
1094         return CMD_RST_PRC_SUCCESS;
1095 }
1096
1097 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
1098 {
1099         struct hns_roce_v2_priv *priv = hr_dev->priv;
1100         struct hnae3_handle *handle = priv->handle;
1101         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1102
1103         /* When software reset is detected at .init_instance() function, we
1104          * should stop sending mailbox&cmq&doorbell to hardware, and exit
1105          * with error.
1106          */
1107         hr_dev->dis_db = true;
1108         if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
1109                 hr_dev->is_reset = true;
1110
1111         return CMD_RST_PRC_EBUSY;
1112 }
1113
1114 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev,
1115                                     struct hnae3_handle *handle)
1116 {
1117         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1118         unsigned long instance_stage; /* the current instance stage */
1119         unsigned long reset_stage; /* the current reset stage */
1120         unsigned long reset_cnt;
1121         bool sw_resetting;
1122         bool hw_resetting;
1123
1124         /* Get information about reset from NIC driver or RoCE driver itself,
1125          * the meaning of the following variables from NIC driver are described
1126          * as below:
1127          * reset_cnt -- The count value of completed hardware reset.
1128          * hw_resetting -- Whether hardware device is resetting now.
1129          * sw_resetting -- Whether NIC's software reset process is running now.
1130          */
1131         instance_stage = handle->rinfo.instance_state;
1132         reset_stage = handle->rinfo.reset_state;
1133         reset_cnt = ops->ae_dev_reset_cnt(handle);
1134         if (reset_cnt != hr_dev->reset_cnt)
1135                 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
1136                                                   reset_stage);
1137
1138         hw_resetting = ops->get_cmdq_stat(handle);
1139         if (hw_resetting)
1140                 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
1141                                                     reset_stage);
1142
1143         sw_resetting = ops->ae_dev_resetting(handle);
1144         if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
1145                 return hns_roce_v2_cmd_sw_resetting(hr_dev);
1146
1147         return CMD_RST_PRC_OTHERS;
1148 }
1149
1150 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev)
1151 {
1152         struct hns_roce_v2_priv *priv = hr_dev->priv;
1153         struct hnae3_handle *handle = priv->handle;
1154         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1155
1156         if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle))
1157                 return true;
1158
1159         if (ops->get_hw_reset_stat(handle))
1160                 return true;
1161
1162         if (ops->ae_dev_resetting(handle))
1163                 return true;
1164
1165         return false;
1166 }
1167
1168 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy)
1169 {
1170         struct hns_roce_v2_priv *priv = hr_dev->priv;
1171         u32 status;
1172
1173         if (hr_dev->is_reset)
1174                 status = CMD_RST_PRC_SUCCESS;
1175         else
1176                 status = check_aedev_reset_status(hr_dev, priv->handle);
1177
1178         *busy = (status == CMD_RST_PRC_EBUSY);
1179
1180         return status == CMD_RST_PRC_OTHERS;
1181 }
1182
1183 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
1184                                    struct hns_roce_v2_cmq_ring *ring)
1185 {
1186         int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
1187
1188         ring->desc = dma_alloc_coherent(hr_dev->dev, size,
1189                                         &ring->desc_dma_addr, GFP_KERNEL);
1190         if (!ring->desc)
1191                 return -ENOMEM;
1192
1193         return 0;
1194 }
1195
1196 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
1197                                    struct hns_roce_v2_cmq_ring *ring)
1198 {
1199         dma_free_coherent(hr_dev->dev,
1200                           ring->desc_num * sizeof(struct hns_roce_cmq_desc),
1201                           ring->desc, ring->desc_dma_addr);
1202
1203         ring->desc_dma_addr = 0;
1204 }
1205
1206 static int init_csq(struct hns_roce_dev *hr_dev,
1207                     struct hns_roce_v2_cmq_ring *csq)
1208 {
1209         dma_addr_t dma;
1210         int ret;
1211
1212         csq->desc_num = CMD_CSQ_DESC_NUM;
1213         spin_lock_init(&csq->lock);
1214         csq->flag = TYPE_CSQ;
1215         csq->head = 0;
1216
1217         ret = hns_roce_alloc_cmq_desc(hr_dev, csq);
1218         if (ret)
1219                 return ret;
1220
1221         dma = csq->desc_dma_addr;
1222         roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma));
1223         roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma));
1224         roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
1225                    (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1226
1227         /* Make sure to write CI first and then PI */
1228         roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0);
1229         roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0);
1230
1231         return 0;
1232 }
1233
1234 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
1235 {
1236         struct hns_roce_v2_priv *priv = hr_dev->priv;
1237         int ret;
1238
1239         priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
1240
1241         ret = init_csq(hr_dev, &priv->cmq.csq);
1242         if (ret)
1243                 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret);
1244
1245         return ret;
1246 }
1247
1248 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
1249 {
1250         struct hns_roce_v2_priv *priv = hr_dev->priv;
1251
1252         hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1253 }
1254
1255 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
1256                                           enum hns_roce_opcode_type opcode,
1257                                           bool is_read)
1258 {
1259         memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
1260         desc->opcode = cpu_to_le16(opcode);
1261         desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1262         if (is_read)
1263                 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
1264         else
1265                 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1266 }
1267
1268 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
1269 {
1270         u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1271         struct hns_roce_v2_priv *priv = hr_dev->priv;
1272
1273         return tail == priv->cmq.csq.head;
1274 }
1275
1276 static void update_cmdq_status(struct hns_roce_dev *hr_dev)
1277 {
1278         struct hns_roce_v2_priv *priv = hr_dev->priv;
1279         struct hnae3_handle *handle = priv->handle;
1280
1281         if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
1282             handle->rinfo.instance_state == HNS_ROCE_STATE_INIT)
1283                 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR;
1284 }
1285
1286 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1287                                struct hns_roce_cmq_desc *desc, int num)
1288 {
1289         struct hns_roce_v2_priv *priv = hr_dev->priv;
1290         struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1291         u32 timeout = 0;
1292         u16 desc_ret;
1293         u32 tail;
1294         int ret;
1295         int i;
1296
1297         spin_lock_bh(&csq->lock);
1298
1299         tail = csq->head;
1300
1301         for (i = 0; i < num; i++) {
1302                 csq->desc[csq->head++] = desc[i];
1303                 if (csq->head == csq->desc_num)
1304                         csq->head = 0;
1305         }
1306
1307         /* Write to hardware */
1308         roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head);
1309
1310         do {
1311                 if (hns_roce_cmq_csq_done(hr_dev))
1312                         break;
1313                 udelay(1);
1314         } while (++timeout < priv->cmq.tx_timeout);
1315
1316         if (hns_roce_cmq_csq_done(hr_dev)) {
1317                 ret = 0;
1318                 for (i = 0; i < num; i++) {
1319                         /* check the result of hardware write back */
1320                         desc[i] = csq->desc[tail++];
1321                         if (tail == csq->desc_num)
1322                                 tail = 0;
1323
1324                         desc_ret = le16_to_cpu(desc[i].retval);
1325                         if (likely(desc_ret == CMD_EXEC_SUCCESS))
1326                                 continue;
1327
1328                         dev_err_ratelimited(hr_dev->dev,
1329                                             "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n",
1330                                             desc->opcode, desc_ret);
1331                         ret = -EIO;
1332                 }
1333         } else {
1334                 /* FW/HW reset or incorrect number of desc */
1335                 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1336                 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n",
1337                          csq->head, tail);
1338                 csq->head = tail;
1339
1340                 update_cmdq_status(hr_dev);
1341
1342                 ret = -EAGAIN;
1343         }
1344
1345         spin_unlock_bh(&csq->lock);
1346
1347         return ret;
1348 }
1349
1350 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1351                              struct hns_roce_cmq_desc *desc, int num)
1352 {
1353         bool busy;
1354         int ret;
1355
1356         if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1357                 return -EIO;
1358
1359         if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1360                 return busy ? -EBUSY : 0;
1361
1362         ret = __hns_roce_cmq_send(hr_dev, desc, num);
1363         if (ret) {
1364                 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1365                         return busy ? -EBUSY : 0;
1366         }
1367
1368         return ret;
1369 }
1370
1371 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev,
1372                                dma_addr_t base_addr, u8 cmd, unsigned long tag)
1373 {
1374         struct hns_roce_cmd_mailbox *mbox;
1375         int ret;
1376
1377         mbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1378         if (IS_ERR(mbox))
1379                 return PTR_ERR(mbox);
1380
1381         ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag);
1382         hns_roce_free_cmd_mailbox(hr_dev, mbox);
1383         return ret;
1384 }
1385
1386 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
1387 {
1388         struct hns_roce_query_version *resp;
1389         struct hns_roce_cmq_desc desc;
1390         int ret;
1391
1392         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1393         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1394         if (ret)
1395                 return ret;
1396
1397         resp = (struct hns_roce_query_version *)desc.data;
1398         hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version);
1399         hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1400
1401         return 0;
1402 }
1403
1404 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev,
1405                                         struct hnae3_handle *handle)
1406 {
1407         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1408         unsigned long end;
1409
1410         hr_dev->dis_db = true;
1411
1412         dev_warn(hr_dev->dev,
1413                  "func clear is pending, device in resetting state.\n");
1414         end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1415         while (end) {
1416                 if (!ops->get_hw_reset_stat(handle)) {
1417                         hr_dev->is_reset = true;
1418                         dev_info(hr_dev->dev,
1419                                  "func clear success after reset.\n");
1420                         return;
1421                 }
1422                 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1423                 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1424         }
1425
1426         dev_warn(hr_dev->dev, "func clear failed.\n");
1427 }
1428
1429 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev,
1430                                         struct hnae3_handle *handle)
1431 {
1432         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1433         unsigned long end;
1434
1435         hr_dev->dis_db = true;
1436
1437         dev_warn(hr_dev->dev,
1438                  "func clear is pending, device in resetting state.\n");
1439         end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1440         while (end) {
1441                 if (ops->ae_dev_reset_cnt(handle) !=
1442                     hr_dev->reset_cnt) {
1443                         hr_dev->is_reset = true;
1444                         dev_info(hr_dev->dev,
1445                                  "func clear success after sw reset\n");
1446                         return;
1447                 }
1448                 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1449                 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1450         }
1451
1452         dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n");
1453 }
1454
1455 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval,
1456                                        int flag)
1457 {
1458         struct hns_roce_v2_priv *priv = hr_dev->priv;
1459         struct hnae3_handle *handle = priv->handle;
1460         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1461
1462         if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) {
1463                 hr_dev->dis_db = true;
1464                 hr_dev->is_reset = true;
1465                 dev_info(hr_dev->dev, "func clear success after reset.\n");
1466                 return;
1467         }
1468
1469         if (ops->get_hw_reset_stat(handle)) {
1470                 func_clr_hw_resetting_state(hr_dev, handle);
1471                 return;
1472         }
1473
1474         if (ops->ae_dev_resetting(handle) &&
1475             handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) {
1476                 func_clr_sw_resetting_state(hr_dev, handle);
1477                 return;
1478         }
1479
1480         if (retval && !flag)
1481                 dev_warn(hr_dev->dev,
1482                          "func clear read failed, ret = %d.\n", retval);
1483
1484         dev_warn(hr_dev->dev, "func clear failed.\n");
1485 }
1486
1487 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id)
1488 {
1489         bool fclr_write_fail_flag = false;
1490         struct hns_roce_func_clear *resp;
1491         struct hns_roce_cmq_desc desc;
1492         unsigned long end;
1493         int ret = 0;
1494
1495         if (check_device_is_in_reset(hr_dev))
1496                 goto out;
1497
1498         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
1499         resp = (struct hns_roce_func_clear *)desc.data;
1500         resp->rst_funcid_en = cpu_to_le32(vf_id);
1501
1502         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1503         if (ret) {
1504                 fclr_write_fail_flag = true;
1505                 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n",
1506                          ret);
1507                 goto out;
1508         }
1509
1510         msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
1511         end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
1512         while (end) {
1513                 if (check_device_is_in_reset(hr_dev))
1514                         goto out;
1515                 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
1516                 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
1517
1518                 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR,
1519                                               true);
1520
1521                 resp->rst_funcid_en = cpu_to_le32(vf_id);
1522                 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1523                 if (ret)
1524                         continue;
1525
1526                 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) {
1527                         if (vf_id == 0)
1528                                 hr_dev->is_reset = true;
1529                         return;
1530                 }
1531         }
1532
1533 out:
1534         hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag);
1535 }
1536
1537 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id)
1538 {
1539         enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1540         struct hns_roce_cmq_desc desc[2];
1541         struct hns_roce_cmq_req *req_a;
1542
1543         req_a = (struct hns_roce_cmq_req *)desc[0].data;
1544         hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1545         desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1546         hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1547         hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id);
1548
1549         return hns_roce_cmq_send(hr_dev, desc, 2);
1550 }
1551
1552 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
1553 {
1554         int ret;
1555         int i;
1556
1557         if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1558                 return;
1559
1560         for (i = hr_dev->func_num - 1; i >= 0; i--) {
1561                 __hns_roce_function_clear(hr_dev, i);
1562
1563                 if (i == 0)
1564                         continue;
1565
1566                 ret = hns_roce_free_vf_resource(hr_dev, i);
1567                 if (ret)
1568                         ibdev_err(&hr_dev->ib_dev,
1569                                   "failed to free vf resource, vf_id = %d, ret = %d.\n",
1570                                   i, ret);
1571         }
1572 }
1573
1574 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev)
1575 {
1576         struct hns_roce_cmq_desc desc;
1577         int ret;
1578
1579         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO,
1580                                       false);
1581         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1582         if (ret)
1583                 ibdev_err(&hr_dev->ib_dev,
1584                           "failed to clear extended doorbell info, ret = %d.\n",
1585                           ret);
1586
1587         return ret;
1588 }
1589
1590 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1591 {
1592         struct hns_roce_query_fw_info *resp;
1593         struct hns_roce_cmq_desc desc;
1594         int ret;
1595
1596         hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1597         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1598         if (ret)
1599                 return ret;
1600
1601         resp = (struct hns_roce_query_fw_info *)desc.data;
1602         hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
1603
1604         return 0;
1605 }
1606
1607 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev)
1608 {
1609         struct hns_roce_cmq_desc desc;
1610         int ret;
1611
1612         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
1613                 hr_dev->func_num = 1;
1614                 return 0;
1615         }
1616
1617         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO,
1618                                       true);
1619         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1620         if (ret) {
1621                 hr_dev->func_num = 1;
1622                 return ret;
1623         }
1624
1625         hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num);
1626         hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id);
1627
1628         return 0;
1629 }
1630
1631 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1632 {
1633         struct hns_roce_cmq_desc desc;
1634         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1635         u32 clock_cycles_of_1us;
1636
1637         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1638                                       false);
1639
1640         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
1641                 clock_cycles_of_1us = HNS_ROCE_1NS_CFG;
1642         else
1643                 clock_cycles_of_1us = HNS_ROCE_1US_CFG;
1644
1645         hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us);
1646         hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT);
1647
1648         return hns_roce_cmq_send(hr_dev, &desc, 1);
1649 }
1650
1651 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1652 {
1653         struct hns_roce_cmq_desc desc[2];
1654         struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1655         struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1656         struct hns_roce_caps *caps = &hr_dev->caps;
1657         enum hns_roce_opcode_type opcode;
1658         u32 func_num;
1659         int ret;
1660
1661         if (is_vf) {
1662                 opcode = HNS_ROCE_OPC_QUERY_VF_RES;
1663                 func_num = 1;
1664         } else {
1665                 opcode = HNS_ROCE_OPC_QUERY_PF_RES;
1666                 func_num = hr_dev->func_num;
1667         }
1668
1669         hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true);
1670         desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1671         hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true);
1672
1673         ret = hns_roce_cmq_send(hr_dev, desc, 2);
1674         if (ret)
1675                 return ret;
1676
1677         caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num;
1678         caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num;
1679         caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num;
1680         caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num;
1681         caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num;
1682         caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num;
1683         caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num;
1684         caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num;
1685
1686         if (is_vf) {
1687                 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num;
1688                 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) /
1689                                                func_num;
1690         } else {
1691                 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num;
1692                 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) /
1693                                                func_num;
1694         }
1695
1696         return 0;
1697 }
1698
1699 static int load_ext_cfg_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1700 {
1701         struct hns_roce_cmq_desc desc;
1702         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1703         struct hns_roce_caps *caps = &hr_dev->caps;
1704         u32 func_num, qp_num;
1705         int ret;
1706
1707         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, true);
1708         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1709         if (ret)
1710                 return ret;
1711
1712         func_num = is_vf ? 1 : max_t(u32, 1, hr_dev->func_num);
1713         qp_num = hr_reg_read(req, EXT_CFG_QP_PI_NUM) / func_num;
1714         caps->num_pi_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM);
1715
1716         qp_num = hr_reg_read(req, EXT_CFG_QP_NUM) / func_num;
1717         caps->num_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM);
1718
1719         return 0;
1720 }
1721
1722 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev)
1723 {
1724         struct hns_roce_cmq_desc desc;
1725         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1726         struct hns_roce_caps *caps = &hr_dev->caps;
1727         int ret;
1728
1729         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1730                                       true);
1731
1732         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1733         if (ret)
1734                 return ret;
1735
1736         caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM);
1737         caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM);
1738
1739         return 0;
1740 }
1741
1742 static int query_func_resource_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1743 {
1744         struct device *dev = hr_dev->dev;
1745         int ret;
1746
1747         ret = load_func_res_caps(hr_dev, is_vf);
1748         if (ret) {
1749                 dev_err(dev, "failed to load res caps, ret = %d (%s).\n", ret,
1750                         is_vf ? "vf" : "pf");
1751                 return ret;
1752         }
1753
1754         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1755                 ret = load_ext_cfg_caps(hr_dev, is_vf);
1756                 if (ret)
1757                         dev_err(dev, "failed to load ext cfg, ret = %d (%s).\n",
1758                                 ret, is_vf ? "vf" : "pf");
1759         }
1760
1761         return ret;
1762 }
1763
1764 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1765 {
1766         struct device *dev = hr_dev->dev;
1767         int ret;
1768
1769         ret = query_func_resource_caps(hr_dev, false);
1770         if (ret)
1771                 return ret;
1772
1773         ret = load_pf_timer_res_caps(hr_dev);
1774         if (ret)
1775                 dev_err(dev, "failed to load pf timer resource, ret = %d.\n",
1776                         ret);
1777
1778         return ret;
1779 }
1780
1781 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev)
1782 {
1783         return query_func_resource_caps(hr_dev, true);
1784 }
1785
1786 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev,
1787                                           u32 vf_id)
1788 {
1789         struct hns_roce_vf_switch *swt;
1790         struct hns_roce_cmq_desc desc;
1791         int ret;
1792
1793         swt = (struct hns_roce_vf_switch *)desc.data;
1794         hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
1795         swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
1796         hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id);
1797         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1798         if (ret)
1799                 return ret;
1800
1801         desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1802         desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1803         hr_reg_enable(swt, VF_SWITCH_ALW_LPBK);
1804         hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK);
1805         hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD);
1806
1807         return hns_roce_cmq_send(hr_dev, &desc, 1);
1808 }
1809
1810 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev)
1811 {
1812         u32 vf_id;
1813         int ret;
1814
1815         for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) {
1816                 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id);
1817                 if (ret)
1818                         return ret;
1819         }
1820         return 0;
1821 }
1822
1823 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id)
1824 {
1825         struct hns_roce_cmq_desc desc[2];
1826         struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1827         struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1828         enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1829         struct hns_roce_caps *caps = &hr_dev->caps;
1830
1831         hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1832         desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1833         hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1834
1835         hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id);
1836
1837         hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num);
1838         hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num);
1839         hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num);
1840         hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num);
1841         hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num);
1842         hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num);
1843         hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num);
1844         hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num);
1845         hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num);
1846         hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num);
1847         hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num);
1848         hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num);
1849         hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num);
1850         hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num);
1851
1852         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1853                 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num);
1854                 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX,
1855                              vf_id * caps->gmv_bt_num);
1856         } else {
1857                 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num);
1858                 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX,
1859                              vf_id * caps->sgid_bt_num);
1860                 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num);
1861                 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX,
1862                              vf_id * caps->smac_bt_num);
1863         }
1864
1865         return hns_roce_cmq_send(hr_dev, desc, 2);
1866 }
1867
1868 static int config_vf_ext_resource(struct hns_roce_dev *hr_dev, u32 vf_id)
1869 {
1870         struct hns_roce_cmq_desc desc;
1871         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1872         struct hns_roce_caps *caps = &hr_dev->caps;
1873
1874         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, false);
1875
1876         hr_reg_write(req, EXT_CFG_VF_ID, vf_id);
1877
1878         hr_reg_write(req, EXT_CFG_QP_PI_NUM, caps->num_pi_qps);
1879         hr_reg_write(req, EXT_CFG_QP_PI_IDX, vf_id * caps->num_pi_qps);
1880         hr_reg_write(req, EXT_CFG_QP_NUM, caps->num_qps);
1881         hr_reg_write(req, EXT_CFG_QP_IDX, vf_id * caps->num_qps);
1882
1883         return hns_roce_cmq_send(hr_dev, &desc, 1);
1884 }
1885
1886 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1887 {
1888         u32 func_num = max_t(u32, 1, hr_dev->func_num);
1889         u32 vf_id;
1890         int ret;
1891
1892         for (vf_id = 0; vf_id < func_num; vf_id++) {
1893                 ret = config_vf_hem_resource(hr_dev, vf_id);
1894                 if (ret) {
1895                         dev_err(hr_dev->dev,
1896                                 "failed to config vf-%u hem res, ret = %d.\n",
1897                                 vf_id, ret);
1898                         return ret;
1899                 }
1900
1901                 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1902                         ret = config_vf_ext_resource(hr_dev, vf_id);
1903                         if (ret) {
1904                                 dev_err(hr_dev->dev,
1905                                         "failed to config vf-%u ext res, ret = %d.\n",
1906                                         vf_id, ret);
1907                                 return ret;
1908                         }
1909                 }
1910         }
1911
1912         return 0;
1913 }
1914
1915 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1916 {
1917         struct hns_roce_cmq_desc desc;
1918         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1919         struct hns_roce_caps *caps = &hr_dev->caps;
1920
1921         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1922
1923         hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ,
1924                      caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET);
1925         hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ,
1926                      caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET);
1927         hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM,
1928                      to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps));
1929
1930         hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ,
1931                      caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET);
1932         hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ,
1933                      caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET);
1934         hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM,
1935                      to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs));
1936
1937         hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ,
1938                      caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET);
1939         hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ,
1940                      caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET);
1941         hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM,
1942                      to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs));
1943
1944         hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ,
1945                      caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET);
1946         hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ,
1947                      caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET);
1948         hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM,
1949                      to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts));
1950
1951         hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ,
1952                      caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1953         hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ,
1954                      caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1955         hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM,
1956                      to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps));
1957
1958         return hns_roce_cmq_send(hr_dev, &desc, 1);
1959 }
1960
1961 /* Use default caps when hns_roce_query_pf_caps() failed or init VF profile */
1962 static void set_default_caps(struct hns_roce_dev *hr_dev)
1963 {
1964         struct hns_roce_caps *caps = &hr_dev->caps;
1965
1966         caps->num_qps           = HNS_ROCE_V2_MAX_QP_NUM;
1967         caps->max_wqes          = HNS_ROCE_V2_MAX_WQE_NUM;
1968         caps->num_cqs           = HNS_ROCE_V2_MAX_CQ_NUM;
1969         caps->num_srqs          = HNS_ROCE_V2_MAX_SRQ_NUM;
1970         caps->min_cqes          = HNS_ROCE_MIN_CQE_NUM;
1971         caps->max_cqes          = HNS_ROCE_V2_MAX_CQE_NUM;
1972         caps->max_sq_sg         = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
1973         caps->max_rq_sg         = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1974
1975         caps->num_uars          = HNS_ROCE_V2_UAR_NUM;
1976         caps->phy_num_uars      = HNS_ROCE_V2_PHY_UAR_NUM;
1977         caps->num_aeq_vectors   = HNS_ROCE_V2_AEQE_VEC_NUM;
1978         caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
1979         caps->num_comp_vectors  = 0;
1980
1981         caps->num_mtpts         = HNS_ROCE_V2_MAX_MTPT_NUM;
1982         caps->num_pds           = HNS_ROCE_V2_MAX_PD_NUM;
1983         caps->qpc_timer_bt_num  = HNS_ROCE_V2_MAX_QPC_TIMER_BT_NUM;
1984         caps->cqc_timer_bt_num  = HNS_ROCE_V2_MAX_CQC_TIMER_BT_NUM;
1985
1986         caps->max_qp_init_rdma  = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1987         caps->max_qp_dest_rdma  = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1988         caps->max_sq_desc_sz    = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1989         caps->max_rq_desc_sz    = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1990         caps->irrl_entry_sz     = HNS_ROCE_V2_IRRL_ENTRY_SZ;
1991         caps->trrl_entry_sz     = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ;
1992         caps->cqc_entry_sz      = HNS_ROCE_V2_CQC_ENTRY_SZ;
1993         caps->srqc_entry_sz     = HNS_ROCE_V2_SRQC_ENTRY_SZ;
1994         caps->mtpt_entry_sz     = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1995         caps->idx_entry_sz      = HNS_ROCE_V2_IDX_ENTRY_SZ;
1996         caps->page_size_cap     = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1997         caps->reserved_lkey     = 0;
1998         caps->reserved_pds      = 0;
1999         caps->reserved_mrws     = 1;
2000         caps->reserved_uars     = 0;
2001         caps->reserved_cqs      = 0;
2002         caps->reserved_srqs     = 0;
2003         caps->reserved_qps      = HNS_ROCE_V2_RSV_QPS;
2004
2005         caps->qpc_hop_num       = HNS_ROCE_CONTEXT_HOP_NUM;
2006         caps->srqc_hop_num      = HNS_ROCE_CONTEXT_HOP_NUM;
2007         caps->cqc_hop_num       = HNS_ROCE_CONTEXT_HOP_NUM;
2008         caps->mpt_hop_num       = HNS_ROCE_CONTEXT_HOP_NUM;
2009         caps->sccc_hop_num      = HNS_ROCE_SCCC_HOP_NUM;
2010
2011         caps->mtt_hop_num       = HNS_ROCE_MTT_HOP_NUM;
2012         caps->wqe_sq_hop_num    = HNS_ROCE_SQWQE_HOP_NUM;
2013         caps->wqe_sge_hop_num   = HNS_ROCE_EXT_SGE_HOP_NUM;
2014         caps->wqe_rq_hop_num    = HNS_ROCE_RQWQE_HOP_NUM;
2015         caps->cqe_hop_num       = HNS_ROCE_CQE_HOP_NUM;
2016         caps->srqwqe_hop_num    = HNS_ROCE_SRQWQE_HOP_NUM;
2017         caps->idx_hop_num       = HNS_ROCE_IDX_HOP_NUM;
2018         caps->chunk_sz          = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
2019
2020         caps->flags             = HNS_ROCE_CAP_FLAG_REREG_MR |
2021                                   HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
2022                                   HNS_ROCE_CAP_FLAG_CQ_RECORD_DB |
2023                                   HNS_ROCE_CAP_FLAG_QP_RECORD_DB;
2024
2025         caps->pkey_table_len[0] = 1;
2026         caps->ceqe_depth        = HNS_ROCE_V2_COMP_EQE_NUM;
2027         caps->aeqe_depth        = HNS_ROCE_V2_ASYNC_EQE_NUM;
2028         caps->local_ca_ack_delay = 0;
2029         caps->max_mtu = IB_MTU_4096;
2030
2031         caps->max_srq_wrs       = HNS_ROCE_V2_MAX_SRQ_WR;
2032         caps->max_srq_sges      = HNS_ROCE_V2_MAX_SRQ_SGE;
2033
2034         caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW |
2035                        HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR |
2036                        HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL | HNS_ROCE_CAP_FLAG_XRC;
2037
2038         caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
2039
2040         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2041                 caps->flags |= HNS_ROCE_CAP_FLAG_STASH |
2042                                HNS_ROCE_CAP_FLAG_DIRECT_WQE;
2043                 caps->max_sq_inline = HNS_ROCE_V3_MAX_SQ_INLINE;
2044         } else {
2045                 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
2046
2047                 /* The following configuration are only valid for HIP08 */
2048                 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ;
2049                 caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ;
2050                 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE;
2051         }
2052 }
2053
2054 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num,
2055                        u32 *buf_page_size, u32 *bt_page_size, u32 hem_type)
2056 {
2057         u64 obj_per_chunk;
2058         u64 bt_chunk_size = PAGE_SIZE;
2059         u64 buf_chunk_size = PAGE_SIZE;
2060         u64 obj_per_chunk_default = buf_chunk_size / obj_size;
2061
2062         *buf_page_size = 0;
2063         *bt_page_size = 0;
2064
2065         switch (hop_num) {
2066         case 3:
2067                 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2068                                 (bt_chunk_size / BA_BYTE_LEN) *
2069                                 (bt_chunk_size / BA_BYTE_LEN) *
2070                                  obj_per_chunk_default;
2071                 break;
2072         case 2:
2073                 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2074                                 (bt_chunk_size / BA_BYTE_LEN) *
2075                                  obj_per_chunk_default;
2076                 break;
2077         case 1:
2078                 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2079                                 obj_per_chunk_default;
2080                 break;
2081         case HNS_ROCE_HOP_NUM_0:
2082                 obj_per_chunk = ctx_bt_num * obj_per_chunk_default;
2083                 break;
2084         default:
2085                 pr_err("table %u not support hop_num = %u!\n", hem_type,
2086                        hop_num);
2087                 return;
2088         }
2089
2090         if (hem_type >= HEM_TYPE_MTT)
2091                 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
2092         else
2093                 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
2094 }
2095
2096 static void set_hem_page_size(struct hns_roce_dev *hr_dev)
2097 {
2098         struct hns_roce_caps *caps = &hr_dev->caps;
2099
2100         /* EQ */
2101         caps->eqe_ba_pg_sz = 0;
2102         caps->eqe_buf_pg_sz = 0;
2103
2104         /* Link Table */
2105         caps->llm_buf_pg_sz = 0;
2106
2107         /* MR */
2108         caps->mpt_ba_pg_sz = 0;
2109         caps->mpt_buf_pg_sz = 0;
2110         caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K;
2111         caps->pbl_buf_pg_sz = 0;
2112         calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
2113                    caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
2114                    HEM_TYPE_MTPT);
2115
2116         /* QP */
2117         caps->qpc_ba_pg_sz = 0;
2118         caps->qpc_buf_pg_sz = 0;
2119         caps->qpc_timer_ba_pg_sz = 0;
2120         caps->qpc_timer_buf_pg_sz = 0;
2121         caps->sccc_ba_pg_sz = 0;
2122         caps->sccc_buf_pg_sz = 0;
2123         caps->mtt_ba_pg_sz = 0;
2124         caps->mtt_buf_pg_sz = 0;
2125         calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num,
2126                    caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
2127                    HEM_TYPE_QPC);
2128
2129         if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
2130                 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num,
2131                            caps->sccc_bt_num, &caps->sccc_buf_pg_sz,
2132                            &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC);
2133
2134         /* CQ */
2135         caps->cqc_ba_pg_sz = 0;
2136         caps->cqc_buf_pg_sz = 0;
2137         caps->cqc_timer_ba_pg_sz = 0;
2138         caps->cqc_timer_buf_pg_sz = 0;
2139         caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
2140         caps->cqe_buf_pg_sz = 0;
2141         calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
2142                    caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
2143                    HEM_TYPE_CQC);
2144         calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num,
2145                    1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
2146
2147         /* SRQ */
2148         if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) {
2149                 caps->srqc_ba_pg_sz = 0;
2150                 caps->srqc_buf_pg_sz = 0;
2151                 caps->srqwqe_ba_pg_sz = 0;
2152                 caps->srqwqe_buf_pg_sz = 0;
2153                 caps->idx_ba_pg_sz = 0;
2154                 caps->idx_buf_pg_sz = 0;
2155                 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz,
2156                            caps->srqc_hop_num, caps->srqc_bt_num,
2157                            &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz,
2158                            HEM_TYPE_SRQC);
2159                 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
2160                            caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
2161                            &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
2162                 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz,
2163                            caps->idx_hop_num, 1, &caps->idx_buf_pg_sz,
2164                            &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
2165         }
2166
2167         /* GMV */
2168         caps->gmv_ba_pg_sz = 0;
2169         caps->gmv_buf_pg_sz = 0;
2170 }
2171
2172 /* Apply all loaded caps before setting to hardware */
2173 static void apply_func_caps(struct hns_roce_dev *hr_dev)
2174 {
2175         struct hns_roce_caps *caps = &hr_dev->caps;
2176         struct hns_roce_v2_priv *priv = hr_dev->priv;
2177
2178         /* The following configurations don't need to be got from firmware. */
2179         caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
2180         caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
2181         caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
2182
2183         caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
2184         caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2185         caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2186
2187         caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM;
2188         caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM;
2189
2190         caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
2191         caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
2192
2193         if (!caps->num_comp_vectors)
2194                 caps->num_comp_vectors =
2195                         min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM,
2196                                 (u32)priv->handle->rinfo.num_vectors -
2197                 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM));
2198
2199         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2200                 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM;
2201                 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
2202                 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
2203
2204                 /* The following configurations will be overwritten */
2205                 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
2206                 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE;
2207                 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ;
2208
2209                 /* The following configurations are not got from firmware */
2210                 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ;
2211
2212                 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0;
2213                 caps->gid_table_len[0] = caps->gmv_bt_num *
2214                                         (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz);
2215
2216                 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE /
2217                                                           caps->gmv_entry_sz);
2218         } else {
2219                 u32 func_num = max_t(u32, 1, hr_dev->func_num);
2220
2221                 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM;
2222                 caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
2223                 caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
2224                 caps->gid_table_len[0] /= func_num;
2225         }
2226
2227         if (hr_dev->is_vf) {
2228                 caps->default_aeq_arm_st = 0x3;
2229                 caps->default_ceq_arm_st = 0x3;
2230                 caps->default_ceq_max_cnt = 0x1;
2231                 caps->default_ceq_period = 0x10;
2232                 caps->default_aeq_max_cnt = 0x1;
2233                 caps->default_aeq_period = 0x10;
2234         }
2235
2236         set_hem_page_size(hr_dev);
2237 }
2238
2239 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
2240 {
2241         struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM];
2242         struct hns_roce_caps *caps = &hr_dev->caps;
2243         struct hns_roce_query_pf_caps_a *resp_a;
2244         struct hns_roce_query_pf_caps_b *resp_b;
2245         struct hns_roce_query_pf_caps_c *resp_c;
2246         struct hns_roce_query_pf_caps_d *resp_d;
2247         struct hns_roce_query_pf_caps_e *resp_e;
2248         int ctx_hop_num;
2249         int pbl_hop_num;
2250         int ret;
2251         int i;
2252
2253         for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) {
2254                 hns_roce_cmq_setup_basic_desc(&desc[i],
2255                                               HNS_ROCE_OPC_QUERY_PF_CAPS_NUM,
2256                                               true);
2257                 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1))
2258                         desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2259                 else
2260                         desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2261         }
2262
2263         ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM);
2264         if (ret)
2265                 return ret;
2266
2267         resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data;
2268         resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data;
2269         resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data;
2270         resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data;
2271         resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data;
2272
2273         caps->local_ca_ack_delay     = resp_a->local_ca_ack_delay;
2274         caps->max_sq_sg              = le16_to_cpu(resp_a->max_sq_sg);
2275         caps->max_sq_inline          = le16_to_cpu(resp_a->max_sq_inline);
2276         caps->max_rq_sg              = le16_to_cpu(resp_a->max_rq_sg);
2277         caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg);
2278         caps->max_srq_sges           = le16_to_cpu(resp_a->max_srq_sges);
2279         caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges);
2280         caps->num_aeq_vectors        = resp_a->num_aeq_vectors;
2281         caps->num_other_vectors      = resp_a->num_other_vectors;
2282         caps->max_sq_desc_sz         = resp_a->max_sq_desc_sz;
2283         caps->max_rq_desc_sz         = resp_a->max_rq_desc_sz;
2284         caps->cqe_sz                 = resp_a->cqe_sz;
2285
2286         caps->mtpt_entry_sz          = resp_b->mtpt_entry_sz;
2287         caps->irrl_entry_sz          = resp_b->irrl_entry_sz;
2288         caps->trrl_entry_sz          = resp_b->trrl_entry_sz;
2289         caps->cqc_entry_sz           = resp_b->cqc_entry_sz;
2290         caps->srqc_entry_sz          = resp_b->srqc_entry_sz;
2291         caps->idx_entry_sz           = resp_b->idx_entry_sz;
2292         caps->sccc_sz                = resp_b->sccc_sz;
2293         caps->max_mtu                = resp_b->max_mtu;
2294         caps->qpc_sz                 = le16_to_cpu(resp_b->qpc_sz);
2295         caps->min_cqes               = resp_b->min_cqes;
2296         caps->min_wqes               = resp_b->min_wqes;
2297         caps->page_size_cap          = le32_to_cpu(resp_b->page_size_cap);
2298         caps->pkey_table_len[0]      = resp_b->pkey_table_len;
2299         caps->phy_num_uars           = resp_b->phy_num_uars;
2300         ctx_hop_num                  = resp_b->ctx_hop_num;
2301         pbl_hop_num                  = resp_b->pbl_hop_num;
2302
2303         caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS);
2304
2305         caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS);
2306         caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) <<
2307                        HNS_ROCE_CAP_FLAGS_EX_SHIFT;
2308
2309         caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS);
2310         caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID);
2311         caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH);
2312         caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS);
2313         caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS);
2314         caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD);
2315         caps->max_qp_dest_rdma = caps->max_qp_init_rdma;
2316         caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);
2317
2318         caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS);
2319         caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE);
2320         caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);
2321         caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH);
2322         caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS);
2323         caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH);
2324         caps->default_aeq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST);
2325         caps->default_ceq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST);
2326         caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS);
2327         caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS);
2328         caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS);
2329         caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS);
2330
2331         caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS);
2332         caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT);
2333         caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS);
2334         caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS);
2335         caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS);
2336         caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);
2337         caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);
2338         caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
2339         caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);
2340
2341         caps->qpc_hop_num = ctx_hop_num;
2342         caps->sccc_hop_num = ctx_hop_num;
2343         caps->srqc_hop_num = ctx_hop_num;
2344         caps->cqc_hop_num = ctx_hop_num;
2345         caps->mpt_hop_num = ctx_hop_num;
2346         caps->mtt_hop_num = pbl_hop_num;
2347         caps->cqe_hop_num = pbl_hop_num;
2348         caps->srqwqe_hop_num = pbl_hop_num;
2349         caps->idx_hop_num = pbl_hop_num;
2350         caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM);
2351         caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM);
2352         caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM);
2353
2354         return 0;
2355 }
2356
2357 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val)
2358 {
2359         struct hns_roce_cmq_desc desc;
2360         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
2361
2362         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE,
2363                                       false);
2364
2365         hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type);
2366         hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val);
2367
2368         return hns_roce_cmq_send(hr_dev, &desc, 1);
2369 }
2370
2371 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev)
2372 {
2373         struct hns_roce_caps *caps = &hr_dev->caps;
2374         int ret;
2375
2376         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
2377                 return 0;
2378
2379         ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE,
2380                                     caps->qpc_sz);
2381         if (ret) {
2382                 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret);
2383                 return ret;
2384         }
2385
2386         ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE,
2387                                     caps->sccc_sz);
2388         if (ret)
2389                 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret);
2390
2391         return ret;
2392 }
2393
2394 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev)
2395 {
2396         struct device *dev = hr_dev->dev;
2397         int ret;
2398
2399         hr_dev->func_num = 1;
2400
2401         set_default_caps(hr_dev);
2402
2403         ret = hns_roce_query_vf_resource(hr_dev);
2404         if (ret) {
2405                 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret);
2406                 return ret;
2407         }
2408
2409         apply_func_caps(hr_dev);
2410
2411         ret = hns_roce_v2_set_bt(hr_dev);
2412         if (ret)
2413                 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret);
2414
2415         return ret;
2416 }
2417
2418 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev)
2419 {
2420         struct device *dev = hr_dev->dev;
2421         int ret;
2422
2423         ret = hns_roce_query_func_info(hr_dev);
2424         if (ret) {
2425                 dev_err(dev, "failed to query func info, ret = %d.\n", ret);
2426                 return ret;
2427         }
2428
2429         ret = hns_roce_config_global_param(hr_dev);
2430         if (ret) {
2431                 dev_err(dev, "failed to config global param, ret = %d.\n", ret);
2432                 return ret;
2433         }
2434
2435         ret = hns_roce_set_vf_switch_param(hr_dev);
2436         if (ret) {
2437                 dev_err(dev, "failed to set switch param, ret = %d.\n", ret);
2438                 return ret;
2439         }
2440
2441         ret = hns_roce_query_pf_caps(hr_dev);
2442         if (ret)
2443                 set_default_caps(hr_dev);
2444
2445         ret = hns_roce_query_pf_resource(hr_dev);
2446         if (ret) {
2447                 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret);
2448                 return ret;
2449         }
2450
2451         apply_func_caps(hr_dev);
2452
2453         ret = hns_roce_alloc_vf_resource(hr_dev);
2454         if (ret) {
2455                 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret);
2456                 return ret;
2457         }
2458
2459         ret = hns_roce_v2_set_bt(hr_dev);
2460         if (ret) {
2461                 dev_err(dev, "failed to config BA table, ret = %d.\n", ret);
2462                 return ret;
2463         }
2464
2465         /* Configure the size of QPC, SCCC, etc. */
2466         return hns_roce_config_entry_size(hr_dev);
2467 }
2468
2469 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
2470 {
2471         struct device *dev = hr_dev->dev;
2472         int ret;
2473
2474         ret = hns_roce_cmq_query_hw_info(hr_dev);
2475         if (ret) {
2476                 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret);
2477                 return ret;
2478         }
2479
2480         ret = hns_roce_query_fw_ver(hr_dev);
2481         if (ret) {
2482                 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret);
2483                 return ret;
2484         }
2485
2486         hr_dev->vendor_part_id = hr_dev->pci_dev->device;
2487         hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
2488
2489         if (hr_dev->is_vf)
2490                 return hns_roce_v2_vf_profile(hr_dev);
2491         else
2492                 return hns_roce_v2_pf_profile(hr_dev);
2493 }
2494
2495 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf)
2496 {
2497         u32 i, next_ptr, page_num;
2498         __le64 *entry = cfg_buf;
2499         dma_addr_t addr;
2500         u64 val;
2501
2502         page_num = data_buf->npages;
2503         for (i = 0; i < page_num; i++) {
2504                 addr = hns_roce_buf_page(data_buf, i);
2505                 if (i == (page_num - 1))
2506                         next_ptr = 0;
2507                 else
2508                         next_ptr = i + 1;
2509
2510                 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr);
2511                 entry[i] = cpu_to_le64(val);
2512         }
2513 }
2514
2515 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev,
2516                              struct hns_roce_link_table *table)
2517 {
2518         struct hns_roce_cmq_desc desc[2];
2519         struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
2520         struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
2521         struct hns_roce_buf *buf = table->buf;
2522         enum hns_roce_opcode_type opcode;
2523         dma_addr_t addr;
2524
2525         opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
2526         hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
2527         desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2528         hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
2529
2530         hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map));
2531         hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map));
2532         hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages);
2533         hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift));
2534         hr_reg_enable(r_a, CFG_LLM_A_INIT_EN);
2535
2536         addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0));
2537         hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr));
2538         hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr));
2539         hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1);
2540         hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0);
2541
2542         addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1));
2543         hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr));
2544         hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr));
2545         hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1);
2546
2547         return hns_roce_cmq_send(hr_dev, desc, 2);
2548 }
2549
2550 static struct hns_roce_link_table *
2551 alloc_link_table_buf(struct hns_roce_dev *hr_dev)
2552 {
2553         struct hns_roce_v2_priv *priv = hr_dev->priv;
2554         struct hns_roce_link_table *link_tbl;
2555         u32 pg_shift, size, min_size;
2556
2557         link_tbl = &priv->ext_llm;
2558         pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT;
2559         size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ;
2560         min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift;
2561
2562         /* Alloc data table */
2563         size = max(size, min_size);
2564         link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0);
2565         if (IS_ERR(link_tbl->buf))
2566                 return ERR_PTR(-ENOMEM);
2567
2568         /* Alloc config table */
2569         size = link_tbl->buf->npages * sizeof(u64);
2570         link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size,
2571                                                  &link_tbl->table.map,
2572                                                  GFP_KERNEL);
2573         if (!link_tbl->table.buf) {
2574                 hns_roce_buf_free(hr_dev, link_tbl->buf);
2575                 return ERR_PTR(-ENOMEM);
2576         }
2577
2578         return link_tbl;
2579 }
2580
2581 static void free_link_table_buf(struct hns_roce_dev *hr_dev,
2582                                 struct hns_roce_link_table *tbl)
2583 {
2584         if (tbl->buf) {
2585                 u32 size = tbl->buf->npages * sizeof(u64);
2586
2587                 dma_free_coherent(hr_dev->dev, size, tbl->table.buf,
2588                                   tbl->table.map);
2589         }
2590
2591         hns_roce_buf_free(hr_dev, tbl->buf);
2592 }
2593
2594 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev)
2595 {
2596         struct hns_roce_link_table *link_tbl;
2597         int ret;
2598
2599         link_tbl = alloc_link_table_buf(hr_dev);
2600         if (IS_ERR(link_tbl))
2601                 return -ENOMEM;
2602
2603         if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) {
2604                 ret = -EINVAL;
2605                 goto err_alloc;
2606         }
2607
2608         config_llm_table(link_tbl->buf, link_tbl->table.buf);
2609         ret = set_llm_cfg_to_hw(hr_dev, link_tbl);
2610         if (ret)
2611                 goto err_alloc;
2612
2613         return 0;
2614
2615 err_alloc:
2616         free_link_table_buf(hr_dev, link_tbl);
2617         return ret;
2618 }
2619
2620 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev)
2621 {
2622         struct hns_roce_v2_priv *priv = hr_dev->priv;
2623
2624         free_link_table_buf(hr_dev, &priv->ext_llm);
2625 }
2626
2627 static void free_dip_list(struct hns_roce_dev *hr_dev)
2628 {
2629         struct hns_roce_dip *hr_dip;
2630         struct hns_roce_dip *tmp;
2631         unsigned long flags;
2632
2633         spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
2634
2635         list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) {
2636                 list_del(&hr_dip->node);
2637                 kfree(hr_dip);
2638         }
2639
2640         spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
2641 }
2642
2643 static void free_mr_exit(struct hns_roce_dev *hr_dev)
2644 {
2645         struct hns_roce_v2_priv *priv = hr_dev->priv;
2646         struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2647         int ret;
2648         int i;
2649
2650         for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2651                 if (free_mr->rsv_qp[i]) {
2652                         ret = ib_destroy_qp(free_mr->rsv_qp[i]);
2653                         if (ret)
2654                                 ibdev_err(&hr_dev->ib_dev,
2655                                           "failed to destroy qp in free mr.\n");
2656
2657                         free_mr->rsv_qp[i] = NULL;
2658                 }
2659         }
2660
2661         if (free_mr->rsv_cq) {
2662                 ib_destroy_cq(free_mr->rsv_cq);
2663                 free_mr->rsv_cq = NULL;
2664         }
2665
2666         if (free_mr->rsv_pd) {
2667                 ib_dealloc_pd(free_mr->rsv_pd);
2668                 free_mr->rsv_pd = NULL;
2669         }
2670 }
2671
2672 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev)
2673 {
2674         struct hns_roce_v2_priv *priv = hr_dev->priv;
2675         struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2676         struct ib_device *ibdev = &hr_dev->ib_dev;
2677         struct ib_cq_init_attr cq_init_attr = {};
2678         struct ib_qp_init_attr qp_init_attr = {};
2679         struct ib_pd *pd;
2680         struct ib_cq *cq;
2681         struct ib_qp *qp;
2682         int ret;
2683         int i;
2684
2685         pd = ib_alloc_pd(ibdev, 0);
2686         if (IS_ERR(pd)) {
2687                 ibdev_err(ibdev, "failed to create pd for free mr.\n");
2688                 return PTR_ERR(pd);
2689         }
2690         free_mr->rsv_pd = pd;
2691
2692         cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM;
2693         cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_init_attr);
2694         if (IS_ERR(cq)) {
2695                 ibdev_err(ibdev, "failed to create cq for free mr.\n");
2696                 ret = PTR_ERR(cq);
2697                 goto create_failed;
2698         }
2699         free_mr->rsv_cq = cq;
2700
2701         qp_init_attr.qp_type = IB_QPT_RC;
2702         qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
2703         qp_init_attr.send_cq = free_mr->rsv_cq;
2704         qp_init_attr.recv_cq = free_mr->rsv_cq;
2705         for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2706                 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM;
2707                 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM;
2708                 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM;
2709                 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM;
2710
2711                 qp = ib_create_qp(free_mr->rsv_pd, &qp_init_attr);
2712                 if (IS_ERR(qp)) {
2713                         ibdev_err(ibdev, "failed to create qp for free mr.\n");
2714                         ret = PTR_ERR(qp);
2715                         goto create_failed;
2716                 }
2717
2718                 free_mr->rsv_qp[i] = qp;
2719         }
2720
2721         return 0;
2722
2723 create_failed:
2724         free_mr_exit(hr_dev);
2725
2726         return ret;
2727 }
2728
2729 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev,
2730                                  struct ib_qp_attr *attr, int sl_num)
2731 {
2732         struct hns_roce_v2_priv *priv = hr_dev->priv;
2733         struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2734         struct ib_device *ibdev = &hr_dev->ib_dev;
2735         struct hns_roce_qp *hr_qp;
2736         int loopback;
2737         int mask;
2738         int ret;
2739
2740         hr_qp = to_hr_qp(free_mr->rsv_qp[sl_num]);
2741         hr_qp->free_mr_en = 1;
2742
2743         mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS;
2744         attr->qp_state = IB_QPS_INIT;
2745         attr->port_num = 1;
2746         attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE;
2747         ret = ib_modify_qp(&hr_qp->ibqp, attr, mask);
2748         if (ret) {
2749                 ibdev_err(ibdev, "failed to modify qp to init, ret = %d.\n",
2750                           ret);
2751                 return ret;
2752         }
2753
2754         loopback = hr_dev->loop_idc;
2755         /* Set qpc lbi = 1 incidate loopback IO */
2756         hr_dev->loop_idc = 1;
2757
2758         mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN |
2759                IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER;
2760         attr->qp_state = IB_QPS_RTR;
2761         attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2762         attr->path_mtu = IB_MTU_256;
2763         attr->dest_qp_num = hr_qp->qpn;
2764         attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2765
2766         rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num);
2767
2768         ret = ib_modify_qp(&hr_qp->ibqp, attr, mask);
2769         hr_dev->loop_idc = loopback;
2770         if (ret) {
2771                 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n",
2772                           ret);
2773                 return ret;
2774         }
2775
2776         mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT |
2777                IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC;
2778         attr->qp_state = IB_QPS_RTS;
2779         attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2780         attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT;
2781         attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT;
2782         ret = ib_modify_qp(&hr_qp->ibqp, attr, mask);
2783         if (ret)
2784                 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n",
2785                           ret);
2786
2787         return ret;
2788 }
2789
2790 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev)
2791 {
2792         struct hns_roce_v2_priv *priv = hr_dev->priv;
2793         struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2794         struct ib_qp_attr attr = {};
2795         int ret;
2796         int i;
2797
2798         rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
2799         rdma_ah_set_static_rate(&attr.ah_attr, 3);
2800         rdma_ah_set_port_num(&attr.ah_attr, 1);
2801
2802         for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2803                 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i);
2804                 if (ret)
2805                         return ret;
2806         }
2807
2808         return 0;
2809 }
2810
2811 static int free_mr_init(struct hns_roce_dev *hr_dev)
2812 {
2813         struct hns_roce_v2_priv *priv = hr_dev->priv;
2814         struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2815         int ret;
2816
2817         mutex_init(&free_mr->mutex);
2818
2819         ret = free_mr_alloc_res(hr_dev);
2820         if (ret)
2821                 return ret;
2822
2823         ret = free_mr_modify_qp(hr_dev);
2824         if (ret)
2825                 goto err_modify_qp;
2826
2827         return 0;
2828
2829 err_modify_qp:
2830         free_mr_exit(hr_dev);
2831
2832         return ret;
2833 }
2834
2835 static int get_hem_table(struct hns_roce_dev *hr_dev)
2836 {
2837         unsigned int qpc_count;
2838         unsigned int cqc_count;
2839         unsigned int gmv_count;
2840         int ret;
2841         int i;
2842
2843         /* Alloc memory for source address table buffer space chunk */
2844         for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num;
2845              gmv_count++) {
2846                 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count);
2847                 if (ret)
2848                         goto err_gmv_failed;
2849         }
2850
2851         if (hr_dev->is_vf)
2852                 return 0;
2853
2854         /* Alloc memory for QPC Timer buffer space chunk */
2855         for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
2856              qpc_count++) {
2857                 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
2858                                          qpc_count);
2859                 if (ret) {
2860                         dev_err(hr_dev->dev, "QPC Timer get failed\n");
2861                         goto err_qpc_timer_failed;
2862                 }
2863         }
2864
2865         /* Alloc memory for CQC Timer buffer space chunk */
2866         for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
2867              cqc_count++) {
2868                 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
2869                                          cqc_count);
2870                 if (ret) {
2871                         dev_err(hr_dev->dev, "CQC Timer get failed\n");
2872                         goto err_cqc_timer_failed;
2873                 }
2874         }
2875
2876         return 0;
2877
2878 err_cqc_timer_failed:
2879         for (i = 0; i < cqc_count; i++)
2880                 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2881
2882 err_qpc_timer_failed:
2883         for (i = 0; i < qpc_count; i++)
2884                 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2885
2886 err_gmv_failed:
2887         for (i = 0; i < gmv_count; i++)
2888                 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2889
2890         return ret;
2891 }
2892
2893 static void put_hem_table(struct hns_roce_dev *hr_dev)
2894 {
2895         int i;
2896
2897         for (i = 0; i < hr_dev->caps.gmv_entry_num; i++)
2898                 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2899
2900         if (hr_dev->is_vf)
2901                 return;
2902
2903         for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++)
2904                 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2905
2906         for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++)
2907                 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2908 }
2909
2910 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
2911 {
2912         int ret;
2913
2914         /* The hns ROCEE requires the extdb info to be cleared before using */
2915         ret = hns_roce_clear_extdb_list_info(hr_dev);
2916         if (ret)
2917                 return ret;
2918
2919         ret = get_hem_table(hr_dev);
2920         if (ret)
2921                 return ret;
2922
2923         if (hr_dev->is_vf)
2924                 return 0;
2925
2926         ret = hns_roce_init_link_table(hr_dev);
2927         if (ret) {
2928                 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret);
2929                 goto err_llm_init_failed;
2930         }
2931
2932         return 0;
2933
2934 err_llm_init_failed:
2935         put_hem_table(hr_dev);
2936
2937         return ret;
2938 }
2939
2940 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
2941 {
2942         hns_roce_function_clear(hr_dev);
2943
2944         if (!hr_dev->is_vf)
2945                 hns_roce_free_link_table(hr_dev);
2946
2947         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09)
2948                 free_dip_list(hr_dev);
2949 }
2950
2951 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev,
2952                               struct hns_roce_mbox_msg *mbox_msg)
2953 {
2954         struct hns_roce_cmq_desc desc;
2955         struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
2956
2957         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
2958
2959         mb->in_param_l = cpu_to_le32(mbox_msg->in_param);
2960         mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32);
2961         mb->out_param_l = cpu_to_le32(mbox_msg->out_param);
2962         mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32);
2963         mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd);
2964         mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 |
2965                                          mbox_msg->token);
2966
2967         return hns_roce_cmq_send(hr_dev, &desc, 1);
2968 }
2969
2970 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout,
2971                                  u8 *complete_status)
2972 {
2973         struct hns_roce_mbox_status *mb_st;
2974         struct hns_roce_cmq_desc desc;
2975         unsigned long end;
2976         int ret = -EBUSY;
2977         u32 status;
2978         bool busy;
2979
2980         mb_st = (struct hns_roce_mbox_status *)desc.data;
2981         end = msecs_to_jiffies(timeout) + jiffies;
2982         while (v2_chk_mbox_is_avail(hr_dev, &busy)) {
2983                 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
2984                         return -EIO;
2985
2986                 status = 0;
2987                 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST,
2988                                               true);
2989                 ret = __hns_roce_cmq_send(hr_dev, &desc, 1);
2990                 if (!ret) {
2991                         status = le32_to_cpu(mb_st->mb_status_hw_run);
2992                         /* No pending message exists in ROCEE mbox. */
2993                         if (!(status & MB_ST_HW_RUN_M))
2994                                 break;
2995                 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
2996                         break;
2997                 }
2998
2999                 if (time_after(jiffies, end)) {
3000                         dev_err_ratelimited(hr_dev->dev,
3001                                             "failed to wait mbox status 0x%x\n",
3002                                             status);
3003                         return -ETIMEDOUT;
3004                 }
3005
3006                 cond_resched();
3007                 ret = -EBUSY;
3008         }
3009
3010         if (!ret) {
3011                 *complete_status = (u8)(status & MB_ST_COMPLETE_M);
3012         } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
3013                 /* Ignore all errors if the mbox is unavailable. */
3014                 ret = 0;
3015                 *complete_status = MB_ST_COMPLETE_M;
3016         }
3017
3018         return ret;
3019 }
3020
3021 static int v2_post_mbox(struct hns_roce_dev *hr_dev,
3022                         struct hns_roce_mbox_msg *mbox_msg)
3023 {
3024         u8 status = 0;
3025         int ret;
3026
3027         /* Waiting for the mbox to be idle */
3028         ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS,
3029                                     &status);
3030         if (unlikely(ret)) {
3031                 dev_err_ratelimited(hr_dev->dev,
3032                                     "failed to check post mbox status = 0x%x, ret = %d.\n",
3033                                     status, ret);
3034                 return ret;
3035         }
3036
3037         /* Post new message to mbox */
3038         ret = hns_roce_mbox_post(hr_dev, mbox_msg);
3039         if (ret)
3040                 dev_err_ratelimited(hr_dev->dev,
3041                                     "failed to post mailbox, ret = %d.\n", ret);
3042
3043         return ret;
3044 }
3045
3046 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev)
3047 {
3048         u8 status = 0;
3049         int ret;
3050
3051         ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS,
3052                                     &status);
3053         if (!ret) {
3054                 if (status != MB_ST_COMPLETE_SUCC)
3055                         return -EBUSY;
3056         } else {
3057                 dev_err_ratelimited(hr_dev->dev,
3058                                     "failed to check mbox status = 0x%x, ret = %d.\n",
3059                                     status, ret);
3060         }
3061
3062         return ret;
3063 }
3064
3065 static void copy_gid(void *dest, const union ib_gid *gid)
3066 {
3067 #define GID_SIZE 4
3068         const union ib_gid *src = gid;
3069         __le32 (*p)[GID_SIZE] = dest;
3070         int i;
3071
3072         if (!gid)
3073                 src = &zgid;
3074
3075         for (i = 0; i < GID_SIZE; i++)
3076                 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]);
3077 }
3078
3079 static int config_sgid_table(struct hns_roce_dev *hr_dev,
3080                              int gid_index, const union ib_gid *gid,
3081                              enum hns_roce_sgid_type sgid_type)
3082 {
3083         struct hns_roce_cmq_desc desc;
3084         struct hns_roce_cfg_sgid_tb *sgid_tb =
3085                                     (struct hns_roce_cfg_sgid_tb *)desc.data;
3086
3087         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
3088
3089         hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index);
3090         hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type);
3091
3092         copy_gid(&sgid_tb->vf_sgid_l, gid);
3093
3094         return hns_roce_cmq_send(hr_dev, &desc, 1);
3095 }
3096
3097 static int config_gmv_table(struct hns_roce_dev *hr_dev,
3098                             int gid_index, const union ib_gid *gid,
3099                             enum hns_roce_sgid_type sgid_type,
3100                             const struct ib_gid_attr *attr)
3101 {
3102         struct hns_roce_cmq_desc desc[2];
3103         struct hns_roce_cfg_gmv_tb_a *tb_a =
3104                                 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data;
3105         struct hns_roce_cfg_gmv_tb_b *tb_b =
3106                                 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data;
3107
3108         u16 vlan_id = VLAN_CFI_MASK;
3109         u8 mac[ETH_ALEN] = {};
3110         int ret;
3111
3112         if (gid) {
3113                 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac);
3114                 if (ret)
3115                         return ret;
3116         }
3117
3118         hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3119         desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
3120
3121         hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3122
3123         copy_gid(&tb_a->vf_sgid_l, gid);
3124
3125         hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type);
3126         hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK);
3127         hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id);
3128
3129         tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac);
3130
3131         hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]);
3132         hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index);
3133
3134         return hns_roce_cmq_send(hr_dev, desc, 2);
3135 }
3136
3137 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index,
3138                                const union ib_gid *gid,
3139                                const struct ib_gid_attr *attr)
3140 {
3141         enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
3142         int ret;
3143
3144         if (gid) {
3145                 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
3146                         if (ipv6_addr_v4mapped((void *)gid))
3147                                 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
3148                         else
3149                                 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
3150                 } else if (attr->gid_type == IB_GID_TYPE_ROCE) {
3151                         sgid_type = GID_TYPE_FLAG_ROCE_V1;
3152                 }
3153         }
3154
3155         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
3156                 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr);
3157         else
3158                 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type);
3159
3160         if (ret)
3161                 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n",
3162                           ret);
3163
3164         return ret;
3165 }
3166
3167 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
3168                                const u8 *addr)
3169 {
3170         struct hns_roce_cmq_desc desc;
3171         struct hns_roce_cfg_smac_tb *smac_tb =
3172                                     (struct hns_roce_cfg_smac_tb *)desc.data;
3173         u16 reg_smac_h;
3174         u32 reg_smac_l;
3175
3176         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
3177
3178         reg_smac_l = *(u32 *)(&addr[0]);
3179         reg_smac_h = *(u16 *)(&addr[4]);
3180
3181         hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port);
3182         hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h);
3183         smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l);
3184
3185         return hns_roce_cmq_send(hr_dev, &desc, 1);
3186 }
3187
3188 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev,
3189                         struct hns_roce_v2_mpt_entry *mpt_entry,
3190                         struct hns_roce_mr *mr)
3191 {
3192         u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 };
3193         struct ib_device *ibdev = &hr_dev->ib_dev;
3194         dma_addr_t pbl_ba;
3195         int i, count;
3196
3197         count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
3198                                   ARRAY_SIZE(pages), &pbl_ba);
3199         if (count < 1) {
3200                 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n",
3201                           count);
3202                 return -ENOBUFS;
3203         }
3204
3205         /* Aligned to the hardware address access unit */
3206         for (i = 0; i < count; i++)
3207                 pages[i] >>= 6;
3208
3209         mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3210         mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3);
3211         hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));
3212
3213         mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
3214         hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0]));
3215
3216         mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
3217         hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1]));
3218         hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3219                      to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3220
3221         return 0;
3222 }
3223
3224 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev,
3225                                   void *mb_buf, struct hns_roce_mr *mr)
3226 {
3227         struct hns_roce_v2_mpt_entry *mpt_entry;
3228
3229         mpt_entry = mb_buf;
3230         memset(mpt_entry, 0, sizeof(*mpt_entry));
3231
3232         hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3233         hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3234
3235         hr_reg_write_bool(mpt_entry, MPT_BIND_EN,
3236                           mr->access & IB_ACCESS_MW_BIND);
3237         hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN,
3238                           mr->access & IB_ACCESS_REMOTE_ATOMIC);
3239         hr_reg_write_bool(mpt_entry, MPT_RR_EN,
3240                           mr->access & IB_ACCESS_REMOTE_READ);
3241         hr_reg_write_bool(mpt_entry, MPT_RW_EN,
3242                           mr->access & IB_ACCESS_REMOTE_WRITE);
3243         hr_reg_write_bool(mpt_entry, MPT_LW_EN,
3244                           mr->access & IB_ACCESS_LOCAL_WRITE);
3245
3246         mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3247         mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3248         mpt_entry->lkey = cpu_to_le32(mr->key);
3249         mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3250         mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3251
3252         if (mr->type != MR_TYPE_MR)
3253                 hr_reg_enable(mpt_entry, MPT_PA);
3254
3255         if (mr->type == MR_TYPE_DMA)
3256                 return 0;
3257
3258         if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0)
3259                 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num);
3260
3261         hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3262                      to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3263         hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD);
3264
3265         return set_mtpt_pbl(hr_dev, mpt_entry, mr);
3266 }
3267
3268 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
3269                                         struct hns_roce_mr *mr, int flags,
3270                                         void *mb_buf)
3271 {
3272         struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
3273         u32 mr_access_flags = mr->access;
3274         int ret = 0;
3275
3276         hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3277         hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3278
3279         if (flags & IB_MR_REREG_ACCESS) {
3280                 hr_reg_write(mpt_entry, MPT_BIND_EN,
3281                              (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
3282                 hr_reg_write(mpt_entry, MPT_ATOMIC_EN,
3283                              mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3284                 hr_reg_write(mpt_entry, MPT_RR_EN,
3285                              mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
3286                 hr_reg_write(mpt_entry, MPT_RW_EN,
3287                              mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
3288                 hr_reg_write(mpt_entry, MPT_LW_EN,
3289                              mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
3290         }
3291
3292         if (flags & IB_MR_REREG_TRANS) {
3293                 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3294                 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3295                 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3296                 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3297
3298                 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
3299         }
3300
3301         return ret;
3302 }
3303
3304 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev,
3305                                        void *mb_buf, struct hns_roce_mr *mr)
3306 {
3307         struct ib_device *ibdev = &hr_dev->ib_dev;
3308         struct hns_roce_v2_mpt_entry *mpt_entry;
3309         dma_addr_t pbl_ba = 0;
3310
3311         mpt_entry = mb_buf;
3312         memset(mpt_entry, 0, sizeof(*mpt_entry));
3313
3314         if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) {
3315                 ibdev_err(ibdev, "failed to find frmr mtr.\n");
3316                 return -ENOBUFS;
3317         }
3318
3319         hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3320         hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3321
3322         hr_reg_enable(mpt_entry, MPT_RA_EN);
3323         hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3324
3325         hr_reg_enable(mpt_entry, MPT_FRE);
3326         hr_reg_clear(mpt_entry, MPT_MR_MW);
3327         hr_reg_enable(mpt_entry, MPT_BPD);
3328         hr_reg_clear(mpt_entry, MPT_PA);
3329
3330         hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1);
3331         hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3332                      to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3333         hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3334                      to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3335
3336         mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3337
3338         mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3));
3339         hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));
3340
3341         return 0;
3342 }
3343
3344 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
3345 {
3346         struct hns_roce_v2_mpt_entry *mpt_entry;
3347
3348         mpt_entry = mb_buf;
3349         memset(mpt_entry, 0, sizeof(*mpt_entry));
3350
3351         hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3352         hr_reg_write(mpt_entry, MPT_PD, mw->pdn);
3353
3354         hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3355         hr_reg_enable(mpt_entry, MPT_LW_EN);
3356
3357         hr_reg_enable(mpt_entry, MPT_MR_MW);
3358         hr_reg_enable(mpt_entry, MPT_BPD);
3359         hr_reg_clear(mpt_entry, MPT_PA);
3360         hr_reg_write(mpt_entry, MPT_BQP,
3361                      mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
3362
3363         mpt_entry->lkey = cpu_to_le32(mw->rkey);
3364
3365         hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM,
3366                      mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
3367                                                              mw->pbl_hop_num);
3368         hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3369                      mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3370         hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3371                      mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
3372
3373         return 0;
3374 }
3375
3376 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp)
3377 {
3378         struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
3379         struct ib_device *ibdev = &hr_dev->ib_dev;
3380         const struct ib_send_wr *bad_wr;
3381         struct ib_rdma_wr rdma_wr = {};
3382         struct ib_send_wr *send_wr;
3383         int ret;
3384
3385         send_wr = &rdma_wr.wr;
3386         send_wr->opcode = IB_WR_RDMA_WRITE;
3387
3388         ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr);
3389         if (ret) {
3390                 ibdev_err(ibdev, "failed to post wqe for free mr, ret = %d.\n",
3391                           ret);
3392                 return ret;
3393         }
3394
3395         return 0;
3396 }
3397
3398 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3399                                struct ib_wc *wc);
3400
3401 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev)
3402 {
3403         struct hns_roce_v2_priv *priv = hr_dev->priv;
3404         struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
3405         struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)];
3406         struct ib_device *ibdev = &hr_dev->ib_dev;
3407         struct hns_roce_qp *hr_qp;
3408         unsigned long end;
3409         int cqe_cnt = 0;
3410         int npolled;
3411         int ret;
3412         int i;
3413
3414         /*
3415          * If the device initialization is not complete or in the uninstall
3416          * process, then there is no need to execute free mr.
3417          */
3418         if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
3419             priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT ||
3420             hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT)
3421                 return;
3422
3423         mutex_lock(&free_mr->mutex);
3424
3425         for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
3426                 hr_qp = to_hr_qp(free_mr->rsv_qp[i]);
3427
3428                 ret = free_mr_post_send_lp_wqe(hr_qp);
3429                 if (ret) {
3430                         ibdev_err(ibdev,
3431                                   "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n",
3432                                   hr_qp->qpn, ret);
3433                         break;
3434                 }
3435
3436                 cqe_cnt++;
3437         }
3438
3439         end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies;
3440         while (cqe_cnt) {
3441                 npolled = hns_roce_v2_poll_cq(free_mr->rsv_cq, cqe_cnt, wc);
3442                 if (npolled < 0) {
3443                         ibdev_err(ibdev,
3444                                   "failed to poll cqe for free mr, remain %d cqe.\n",
3445                                   cqe_cnt);
3446                         goto out;
3447                 }
3448
3449                 if (time_after(jiffies, end)) {
3450                         ibdev_err(ibdev,
3451                                   "failed to poll cqe for free mr and timeout, remain %d cqe.\n",
3452                                   cqe_cnt);
3453                         goto out;
3454                 }
3455                 cqe_cnt -= npolled;
3456         }
3457
3458 out:
3459         mutex_unlock(&free_mr->mutex);
3460 }
3461
3462 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev)
3463 {
3464         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
3465                 free_mr_send_cmd_to_hw(hr_dev);
3466 }
3467
3468 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
3469 {
3470         return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);
3471 }
3472
3473 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n)
3474 {
3475         struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
3476
3477         /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
3478         return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe :
3479                                                                          NULL;
3480 }
3481
3482 static inline void update_cq_db(struct hns_roce_dev *hr_dev,
3483                                 struct hns_roce_cq *hr_cq)
3484 {
3485         if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) {
3486                 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M;
3487         } else {
3488                 struct hns_roce_v2_db cq_db = {};
3489
3490                 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3491                 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB);
3492                 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3493                 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1);
3494
3495                 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3496         }
3497 }
3498
3499 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3500                                    struct hns_roce_srq *srq)
3501 {
3502         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3503         struct hns_roce_v2_cqe *cqe, *dest;
3504         u32 prod_index;
3505         int nfreed = 0;
3506         int wqe_index;
3507         u8 owner_bit;
3508
3509         for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
3510              ++prod_index) {
3511                 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe)
3512                         break;
3513         }
3514
3515         /*
3516          * Now backwards through the CQ, removing CQ entries
3517          * that match our QP by overwriting them with next entries.
3518          */
3519         while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
3520                 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
3521                 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) {
3522                         if (srq && hr_reg_read(cqe, CQE_S_R)) {
3523                                 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX);
3524                                 hns_roce_free_srq_wqe(srq, wqe_index);
3525                         }
3526                         ++nfreed;
3527                 } else if (nfreed) {
3528                         dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
3529                                           hr_cq->ib_cq.cqe);
3530                         owner_bit = hr_reg_read(dest, CQE_OWNER);
3531                         memcpy(dest, cqe, hr_cq->cqe_size);
3532                         hr_reg_write(dest, CQE_OWNER, owner_bit);
3533                 }
3534         }
3535
3536         if (nfreed) {
3537                 hr_cq->cons_index += nfreed;
3538                 update_cq_db(hr_dev, hr_cq);
3539         }
3540 }
3541
3542 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3543                                  struct hns_roce_srq *srq)
3544 {
3545         spin_lock_irq(&hr_cq->lock);
3546         __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
3547         spin_unlock_irq(&hr_cq->lock);
3548 }
3549
3550 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
3551                                   struct hns_roce_cq *hr_cq, void *mb_buf,
3552                                   u64 *mtts, dma_addr_t dma_handle)
3553 {
3554         struct hns_roce_v2_cq_context *cq_context;
3555
3556         cq_context = mb_buf;
3557         memset(cq_context, 0, sizeof(*cq_context));
3558
3559         hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID);
3560         hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED);
3561         hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth));
3562         hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector);
3563         hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn);
3564
3565         if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE)
3566                 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B);
3567
3568         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
3569                 hr_reg_enable(cq_context, CQC_STASH);
3570
3571         hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L,
3572                      to_hr_hw_page_addr(mtts[0]));
3573         hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H,
3574                      upper_32_bits(to_hr_hw_page_addr(mtts[0])));
3575         hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num ==
3576                      HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
3577         hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L,
3578                      to_hr_hw_page_addr(mtts[1]));
3579         hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H,
3580                      upper_32_bits(to_hr_hw_page_addr(mtts[1])));
3581         hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ,
3582                      to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift));
3583         hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ,
3584                      to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift));
3585         hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3);
3586         hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3)));
3587         hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN,
3588                           hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB);
3589         hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L,
3590                      ((u32)hr_cq->db.dma) >> 1);
3591         hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H,
3592                      hr_cq->db.dma >> 32);
3593         hr_reg_write(cq_context, CQC_CQ_MAX_CNT,
3594                      HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
3595         hr_reg_write(cq_context, CQC_CQ_PERIOD,
3596                      HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
3597 }
3598
3599 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
3600                                      enum ib_cq_notify_flags flags)
3601 {
3602         struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3603         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3604         struct hns_roce_v2_db cq_db = {};
3605         u32 notify_flag;
3606
3607         /*
3608          * flags = 0, then notify_flag : next
3609          * flags = 1, then notify flag : solocited
3610          */
3611         notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
3612                       V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
3613
3614         hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3615         hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY);
3616         hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3617         hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn);
3618         hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag);
3619
3620         hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3621
3622         return 0;
3623 }
3624
3625 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
3626                                         struct hns_roce_qp *qp,
3627                                         struct ib_wc *wc)
3628 {
3629         struct hns_roce_rinl_sge *sge_list;
3630         u32 wr_num, wr_cnt, sge_num;
3631         u32 sge_cnt, data_len, size;
3632         void *wqe_buf;
3633
3634         wr_num = hr_reg_read(cqe, CQE_WQE_IDX);
3635         wr_cnt = wr_num & (qp->rq.wqe_cnt - 1);
3636
3637         sge_list = qp->rq_inl_buf.wqe_list[wr_cnt].sg_list;
3638         sge_num = qp->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
3639         wqe_buf = hns_roce_get_recv_wqe(qp, wr_cnt);
3640         data_len = wc->byte_len;
3641
3642         for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
3643                 size = min(sge_list[sge_cnt].len, data_len);
3644                 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
3645
3646                 data_len -= size;
3647                 wqe_buf += size;
3648         }
3649
3650         if (unlikely(data_len)) {
3651                 wc->status = IB_WC_LOC_LEN_ERR;
3652                 return -EAGAIN;
3653         }
3654
3655         return 0;
3656 }
3657
3658 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq,
3659                    int num_entries, struct ib_wc *wc)
3660 {
3661         unsigned int left;
3662         int npolled = 0;
3663
3664         left = wq->head - wq->tail;
3665         if (left == 0)
3666                 return 0;
3667
3668         left = min_t(unsigned int, (unsigned int)num_entries, left);
3669         while (npolled < left) {
3670                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3671                 wc->status = IB_WC_WR_FLUSH_ERR;
3672                 wc->vendor_err = 0;
3673                 wc->qp = &hr_qp->ibqp;
3674
3675                 wq->tail++;
3676                 wc++;
3677                 npolled++;
3678         }
3679
3680         return npolled;
3681 }
3682
3683 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
3684                                   struct ib_wc *wc)
3685 {
3686         struct hns_roce_qp *hr_qp;
3687         int npolled = 0;
3688
3689         list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) {
3690                 npolled += sw_comp(hr_qp, &hr_qp->sq,
3691                                    num_entries - npolled, wc + npolled);
3692                 if (npolled >= num_entries)
3693                         goto out;
3694         }
3695
3696         list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) {
3697                 npolled += sw_comp(hr_qp, &hr_qp->rq,
3698                                    num_entries - npolled, wc + npolled);
3699                 if (npolled >= num_entries)
3700                         goto out;
3701         }
3702
3703 out:
3704         return npolled;
3705 }
3706
3707 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
3708                            struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe,
3709                            struct ib_wc *wc)
3710 {
3711         static const struct {
3712                 u32 cqe_status;
3713                 enum ib_wc_status wc_status;
3714         } map[] = {
3715                 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS },
3716                 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR },
3717                 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR },
3718                 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR },
3719                 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR },
3720                 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR },
3721                 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR },
3722                 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR },
3723                 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR },
3724                 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR },
3725                 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR },
3726                 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR,
3727                   IB_WC_RETRY_EXC_ERR },
3728                 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR },
3729                 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR },
3730                 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR}
3731         };
3732
3733         u32 cqe_status = hr_reg_read(cqe, CQE_STATUS);
3734         int i;
3735
3736         wc->status = IB_WC_GENERAL_ERR;
3737         for (i = 0; i < ARRAY_SIZE(map); i++)
3738                 if (cqe_status == map[i].cqe_status) {
3739                         wc->status = map[i].wc_status;
3740                         break;
3741                 }
3742
3743         if (likely(wc->status == IB_WC_SUCCESS ||
3744                    wc->status == IB_WC_WR_FLUSH_ERR))
3745                 return;
3746
3747         ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status);
3748         print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe,
3749                        cq->cqe_size, false);
3750         wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS);
3751
3752         /*
3753          * For hns ROCEE, GENERAL_ERR is an error type that is not defined in
3754          * the standard protocol, the driver must ignore it and needn't to set
3755          * the QP to an error state.
3756          */
3757         if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR)
3758                 return;
3759
3760         flush_cqe(hr_dev, qp);
3761 }
3762
3763 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe,
3764                       struct hns_roce_qp **cur_qp)
3765 {
3766         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3767         struct hns_roce_qp *hr_qp = *cur_qp;
3768         u32 qpn;
3769
3770         qpn = hr_reg_read(cqe, CQE_LCL_QPN);
3771
3772         if (!hr_qp || qpn != hr_qp->qpn) {
3773                 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
3774                 if (unlikely(!hr_qp)) {
3775                         ibdev_err(&hr_dev->ib_dev,
3776                                   "CQ %06lx with entry for unknown QPN %06x\n",
3777                                   hr_cq->cqn, qpn);
3778                         return -EINVAL;
3779                 }
3780                 *cur_qp = hr_qp;
3781         }
3782
3783         return 0;
3784 }
3785
3786 /*
3787  * mapped-value = 1 + real-value
3788  * The ib wc opcode's real value is start from 0, In order to distinguish
3789  * between initialized and uninitialized map values, we plus 1 to the actual
3790  * value when defining the mapping, so that the validity can be identified by
3791  * checking whether the mapped value is greater than 0.
3792  */
3793 #define HR_WC_OP_MAP(hr_key, ib_key) \
3794                 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key
3795
3796 static const u32 wc_send_op_map[] = {
3797         HR_WC_OP_MAP(SEND,                      SEND),
3798         HR_WC_OP_MAP(SEND_WITH_INV,             SEND),
3799         HR_WC_OP_MAP(SEND_WITH_IMM,             SEND),
3800         HR_WC_OP_MAP(RDMA_READ,                 RDMA_READ),
3801         HR_WC_OP_MAP(RDMA_WRITE,                RDMA_WRITE),
3802         HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM,       RDMA_WRITE),
3803         HR_WC_OP_MAP(ATOM_CMP_AND_SWAP,         COMP_SWAP),
3804         HR_WC_OP_MAP(ATOM_FETCH_AND_ADD,        FETCH_ADD),
3805         HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP,     MASKED_COMP_SWAP),
3806         HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD,    MASKED_FETCH_ADD),
3807         HR_WC_OP_MAP(FAST_REG_PMR,              REG_MR),
3808         HR_WC_OP_MAP(BIND_MW,                   REG_MR),
3809 };
3810
3811 static int to_ib_wc_send_op(u32 hr_opcode)
3812 {
3813         if (hr_opcode >= ARRAY_SIZE(wc_send_op_map))
3814                 return -EINVAL;
3815
3816         return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 :
3817                                            -EINVAL;
3818 }
3819
3820 static const u32 wc_recv_op_map[] = {
3821         HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM,               WITH_IMM),
3822         HR_WC_OP_MAP(SEND,                              RECV),
3823         HR_WC_OP_MAP(SEND_WITH_IMM,                     WITH_IMM),
3824         HR_WC_OP_MAP(SEND_WITH_INV,                     RECV),
3825 };
3826
3827 static int to_ib_wc_recv_op(u32 hr_opcode)
3828 {
3829         if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map))
3830                 return -EINVAL;
3831
3832         return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 :
3833                                            -EINVAL;
3834 }
3835
3836 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3837 {
3838         u32 hr_opcode;
3839         int ib_opcode;
3840
3841         wc->wc_flags = 0;
3842
3843         hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3844         switch (hr_opcode) {
3845         case HNS_ROCE_V2_WQE_OP_RDMA_READ:
3846                 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3847                 break;
3848         case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM:
3849         case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM:
3850                 wc->wc_flags |= IB_WC_WITH_IMM;
3851                 break;
3852         case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP:
3853         case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD:
3854         case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP:
3855         case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD:
3856                 wc->byte_len  = 8;
3857                 break;
3858         default:
3859                 break;
3860         }
3861
3862         ib_opcode = to_ib_wc_send_op(hr_opcode);
3863         if (ib_opcode < 0)
3864                 wc->status = IB_WC_GENERAL_ERR;
3865         else
3866                 wc->opcode = ib_opcode;
3867 }
3868
3869 static inline bool is_rq_inl_enabled(struct ib_wc *wc, u32 hr_opcode,
3870                                      struct hns_roce_v2_cqe *cqe)
3871 {
3872         return wc->qp->qp_type != IB_QPT_UD && wc->qp->qp_type != IB_QPT_GSI &&
3873                (hr_opcode == HNS_ROCE_V2_OPCODE_SEND ||
3874                 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
3875                 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
3876                hr_reg_read(cqe, CQE_RQ_INLINE);
3877 }
3878
3879 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3880 {
3881         struct hns_roce_qp *qp = to_hr_qp(wc->qp);
3882         u32 hr_opcode;
3883         int ib_opcode;
3884         int ret;
3885
3886         wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3887
3888         hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3889         switch (hr_opcode) {
3890         case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
3891         case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
3892                 wc->wc_flags = IB_WC_WITH_IMM;
3893                 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata));
3894                 break;
3895         case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
3896                 wc->wc_flags = IB_WC_WITH_INVALIDATE;
3897                 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
3898                 break;
3899         default:
3900                 wc->wc_flags = 0;
3901         }
3902
3903         ib_opcode = to_ib_wc_recv_op(hr_opcode);
3904         if (ib_opcode < 0)
3905                 wc->status = IB_WC_GENERAL_ERR;
3906         else
3907                 wc->opcode = ib_opcode;
3908
3909         if (is_rq_inl_enabled(wc, hr_opcode, cqe)) {
3910                 ret = hns_roce_handle_recv_inl_wqe(cqe, qp, wc);
3911                 if (unlikely(ret))
3912                         return ret;
3913         }
3914
3915         wc->sl = hr_reg_read(cqe, CQE_SL);
3916         wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN);
3917         wc->slid = 0;
3918         wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0;
3919         wc->port_num = hr_reg_read(cqe, CQE_PORTN);
3920         wc->pkey_index = 0;
3921
3922         if (hr_reg_read(cqe, CQE_VID_VLD)) {
3923                 wc->vlan_id = hr_reg_read(cqe, CQE_VID);
3924                 wc->wc_flags |= IB_WC_WITH_VLAN;
3925         } else {
3926                 wc->vlan_id = 0xffff;
3927         }
3928
3929         wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE);
3930
3931         return 0;
3932 }
3933
3934 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
3935                                 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
3936 {
3937         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3938         struct hns_roce_qp *qp = *cur_qp;
3939         struct hns_roce_srq *srq = NULL;
3940         struct hns_roce_v2_cqe *cqe;
3941         struct hns_roce_wq *wq;
3942         int is_send;
3943         u16 wqe_idx;
3944         int ret;
3945
3946         cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
3947         if (!cqe)
3948                 return -EAGAIN;
3949
3950         ++hr_cq->cons_index;
3951         /* Memory barrier */
3952         rmb();
3953
3954         ret = get_cur_qp(hr_cq, cqe, &qp);
3955         if (ret)
3956                 return ret;
3957
3958         wc->qp = &qp->ibqp;
3959         wc->vendor_err = 0;
3960
3961         wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX);
3962
3963         is_send = !hr_reg_read(cqe, CQE_S_R);
3964         if (is_send) {
3965                 wq = &qp->sq;
3966
3967                 /* If sg_signal_bit is set, tail pointer will be updated to
3968                  * the WQE corresponding to the current CQE.
3969                  */
3970                 if (qp->sq_signal_bits)
3971                         wq->tail += (wqe_idx - (u16)wq->tail) &
3972                                     (wq->wqe_cnt - 1);
3973
3974                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3975                 ++wq->tail;
3976
3977                 fill_send_wc(wc, cqe);
3978         } else {
3979                 if (qp->ibqp.srq) {
3980                         srq = to_hr_srq(qp->ibqp.srq);
3981                         wc->wr_id = srq->wrid[wqe_idx];
3982                         hns_roce_free_srq_wqe(srq, wqe_idx);
3983                 } else {
3984                         wq = &qp->rq;
3985                         wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3986                         ++wq->tail;
3987                 }
3988
3989                 ret = fill_recv_wc(wc, cqe);
3990         }
3991
3992         get_cqe_status(hr_dev, qp, hr_cq, cqe, wc);
3993         if (unlikely(wc->status != IB_WC_SUCCESS))
3994                 return 0;
3995
3996         return ret;
3997 }
3998
3999 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
4000                                struct ib_wc *wc)
4001 {
4002         struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
4003         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
4004         struct hns_roce_qp *cur_qp = NULL;
4005         unsigned long flags;
4006         int npolled;
4007
4008         spin_lock_irqsave(&hr_cq->lock, flags);
4009
4010         /*
4011          * When the device starts to reset, the state is RST_DOWN. At this time,
4012          * there may still be some valid CQEs in the hardware that are not
4013          * polled. Therefore, it is not allowed to switch to the software mode
4014          * immediately. When the state changes to UNINIT, CQE no longer exists
4015          * in the hardware, and then switch to software mode.
4016          */
4017         if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
4018                 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc);
4019                 goto out;
4020         }
4021
4022         for (npolled = 0; npolled < num_entries; ++npolled) {
4023                 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
4024                         break;
4025         }
4026
4027         if (npolled)
4028                 update_cq_db(hr_dev, hr_cq);
4029
4030 out:
4031         spin_unlock_irqrestore(&hr_cq->lock, flags);
4032
4033         return npolled;
4034 }
4035
4036 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
4037                               u32 step_idx, u8 *mbox_cmd)
4038 {
4039         u8 cmd;
4040
4041         switch (type) {
4042         case HEM_TYPE_QPC:
4043                 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0;
4044                 break;
4045         case HEM_TYPE_MTPT:
4046                 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0;
4047                 break;
4048         case HEM_TYPE_CQC:
4049                 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0;
4050                 break;
4051         case HEM_TYPE_SRQC:
4052                 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0;
4053                 break;
4054         case HEM_TYPE_SCCC:
4055                 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0;
4056                 break;
4057         case HEM_TYPE_QPC_TIMER:
4058                 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
4059                 break;
4060         case HEM_TYPE_CQC_TIMER:
4061                 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
4062                 break;
4063         default:
4064                 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type);
4065                 return -EINVAL;
4066         }
4067
4068         *mbox_cmd = cmd + step_idx;
4069
4070         return 0;
4071 }
4072
4073 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj,
4074                                dma_addr_t base_addr)
4075 {
4076         struct hns_roce_cmq_desc desc;
4077         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
4078         u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz);
4079         u64 addr = to_hr_hw_page_addr(base_addr);
4080
4081         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
4082
4083         hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr));
4084         hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr));
4085         hr_reg_write(req, CFG_GMV_BT_IDX, idx);
4086
4087         return hns_roce_cmq_send(hr_dev, &desc, 1);
4088 }
4089
4090 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj,
4091                          dma_addr_t base_addr, u32 hem_type, u32 step_idx)
4092 {
4093         int ret;
4094         u8 cmd;
4095
4096         if (unlikely(hem_type == HEM_TYPE_GMV))
4097                 return config_gmv_ba_to_hw(hr_dev, obj, base_addr);
4098
4099         if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx))
4100                 return 0;
4101
4102         ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd);
4103         if (ret < 0)
4104                 return ret;
4105
4106         return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj);
4107 }
4108
4109 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
4110                                struct hns_roce_hem_table *table, int obj,
4111                                u32 step_idx)
4112 {
4113         struct hns_roce_hem_iter iter;
4114         struct hns_roce_hem_mhop mhop;
4115         struct hns_roce_hem *hem;
4116         unsigned long mhop_obj = obj;
4117         int i, j, k;
4118         int ret = 0;
4119         u64 hem_idx = 0;
4120         u64 l1_idx = 0;
4121         u64 bt_ba = 0;
4122         u32 chunk_ba_num;
4123         u32 hop_num;
4124
4125         if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4126                 return 0;
4127
4128         hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
4129         i = mhop.l0_idx;
4130         j = mhop.l1_idx;
4131         k = mhop.l2_idx;
4132         hop_num = mhop.hop_num;
4133         chunk_ba_num = mhop.bt_chunk_size / 8;
4134
4135         if (hop_num == 2) {
4136                 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
4137                           k;
4138                 l1_idx = i * chunk_ba_num + j;
4139         } else if (hop_num == 1) {
4140                 hem_idx = i * chunk_ba_num + j;
4141         } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
4142                 hem_idx = i;
4143         }
4144
4145         if (table->type == HEM_TYPE_SCCC)
4146                 obj = mhop.l0_idx;
4147
4148         if (check_whether_last_step(hop_num, step_idx)) {
4149                 hem = table->hem[hem_idx];
4150                 for (hns_roce_hem_first(hem, &iter);
4151                      !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
4152                         bt_ba = hns_roce_hem_addr(&iter);
4153                         ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type,
4154                                             step_idx);
4155                 }
4156         } else {
4157                 if (step_idx == 0)
4158                         bt_ba = table->bt_l0_dma_addr[i];
4159                 else if (step_idx == 1 && hop_num == 2)
4160                         bt_ba = table->bt_l1_dma_addr[l1_idx];
4161
4162                 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx);
4163         }
4164
4165         return ret;
4166 }
4167
4168 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
4169                                  struct hns_roce_hem_table *table,
4170                                  int tag, u32 step_idx)
4171 {
4172         struct hns_roce_cmd_mailbox *mailbox;
4173         struct device *dev = hr_dev->dev;
4174         u8 cmd = 0xff;
4175         int ret;
4176
4177         if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4178                 return 0;
4179
4180         switch (table->type) {
4181         case HEM_TYPE_QPC:
4182                 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0;
4183                 break;
4184         case HEM_TYPE_MTPT:
4185                 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0;
4186                 break;
4187         case HEM_TYPE_CQC:
4188                 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0;
4189                 break;
4190         case HEM_TYPE_SRQC:
4191                 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
4192                 break;
4193         case HEM_TYPE_SCCC:
4194         case HEM_TYPE_QPC_TIMER:
4195         case HEM_TYPE_CQC_TIMER:
4196         case HEM_TYPE_GMV:
4197                 return 0;
4198         default:
4199                 dev_warn(dev, "table %u not to be destroyed by mailbox!\n",
4200                          table->type);
4201                 return 0;
4202         }
4203
4204         cmd += step_idx;
4205
4206         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4207         if (IS_ERR(mailbox))
4208                 return PTR_ERR(mailbox);
4209
4210         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag);
4211
4212         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4213         return ret;
4214 }
4215
4216 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
4217                                  struct hns_roce_v2_qp_context *context,
4218                                  struct hns_roce_v2_qp_context *qpc_mask,
4219                                  struct hns_roce_qp *hr_qp)
4220 {
4221         struct hns_roce_cmd_mailbox *mailbox;
4222         int qpc_size;
4223         int ret;
4224
4225         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4226         if (IS_ERR(mailbox))
4227                 return PTR_ERR(mailbox);
4228
4229         /* The qpc size of HIP08 is only 256B, which is half of HIP09 */
4230         qpc_size = hr_dev->caps.qpc_sz;
4231         memcpy(mailbox->buf, context, qpc_size);
4232         memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size);
4233
4234         ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
4235                                 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn);
4236
4237         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4238
4239         return ret;
4240 }
4241
4242 static void set_access_flags(struct hns_roce_qp *hr_qp,
4243                              struct hns_roce_v2_qp_context *context,
4244                              struct hns_roce_v2_qp_context *qpc_mask,
4245                              const struct ib_qp_attr *attr, int attr_mask)
4246 {
4247         u8 dest_rd_atomic;
4248         u32 access_flags;
4249
4250         dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
4251                          attr->max_dest_rd_atomic : hr_qp->resp_depth;
4252
4253         access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
4254                        attr->qp_access_flags : hr_qp->atomic_rd_en;
4255
4256         if (!dest_rd_atomic)
4257                 access_flags &= IB_ACCESS_REMOTE_WRITE;
4258
4259         hr_reg_write_bool(context, QPC_RRE,
4260                           access_flags & IB_ACCESS_REMOTE_READ);
4261         hr_reg_clear(qpc_mask, QPC_RRE);
4262
4263         hr_reg_write_bool(context, QPC_RWE,
4264                           access_flags & IB_ACCESS_REMOTE_WRITE);
4265         hr_reg_clear(qpc_mask, QPC_RWE);
4266
4267         hr_reg_write_bool(context, QPC_ATE,
4268                           access_flags & IB_ACCESS_REMOTE_ATOMIC);
4269         hr_reg_clear(qpc_mask, QPC_ATE);
4270         hr_reg_write_bool(context, QPC_EXT_ATE,
4271                           access_flags & IB_ACCESS_REMOTE_ATOMIC);
4272         hr_reg_clear(qpc_mask, QPC_EXT_ATE);
4273 }
4274
4275 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp,
4276                             struct hns_roce_v2_qp_context *context,
4277                             struct hns_roce_v2_qp_context *qpc_mask)
4278 {
4279         hr_reg_write(context, QPC_SGE_SHIFT,
4280                      to_hr_hem_entries_shift(hr_qp->sge.sge_cnt,
4281                                              hr_qp->sge.sge_shift));
4282
4283         hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt));
4284
4285         hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt));
4286 }
4287
4288 static inline int get_cqn(struct ib_cq *ib_cq)
4289 {
4290         return ib_cq ? to_hr_cq(ib_cq)->cqn : 0;
4291 }
4292
4293 static inline int get_pdn(struct ib_pd *ib_pd)
4294 {
4295         return ib_pd ? to_hr_pd(ib_pd)->pdn : 0;
4296 }
4297
4298 static void modify_qp_reset_to_init(struct ib_qp *ibqp,
4299                                     const struct ib_qp_attr *attr,
4300                                     struct hns_roce_v2_qp_context *context,
4301                                     struct hns_roce_v2_qp_context *qpc_mask)
4302 {
4303         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4304         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4305
4306         /*
4307          * In v2 engine, software pass context and context mask to hardware
4308          * when modifying qp. If software need modify some fields in context,
4309          * we should set all bits of the relevant fields in context mask to
4310          * 0 at the same time, else set them to 0x1.
4311          */
4312         hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4313
4314         hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4315
4316         hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs));
4317
4318         set_qpc_wqe_cnt(hr_qp, context, qpc_mask);
4319
4320         /* No VLAN need to set 0xFFF */
4321         hr_reg_write(context, QPC_VLAN_ID, 0xfff);
4322
4323         if (ibqp->qp_type == IB_QPT_XRC_TGT) {
4324                 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn);
4325
4326                 hr_reg_enable(context, QPC_XRC_QP_TYPE);
4327         }
4328
4329         if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
4330                 hr_reg_enable(context, QPC_RQ_RECORD_EN);
4331
4332         if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
4333                 hr_reg_enable(context, QPC_OWNER_MODE);
4334
4335         hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L,
4336                      lower_32_bits(hr_qp->rdb.dma) >> 1);
4337         hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H,
4338                      upper_32_bits(hr_qp->rdb.dma));
4339
4340         if (ibqp->qp_type != IB_QPT_UD && ibqp->qp_type != IB_QPT_GSI)
4341                 hr_reg_write_bool(context, QPC_RQIE,
4342                              hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE);
4343
4344         hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4345
4346         if (ibqp->srq) {
4347                 hr_reg_enable(context, QPC_SRQ_EN);
4348                 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4349         }
4350
4351         hr_reg_enable(context, QPC_FRE);
4352
4353         hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4354
4355         if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ)
4356                 return;
4357
4358         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
4359                 hr_reg_enable(&context->ext, QPCEX_STASH);
4360 }
4361
4362 static void modify_qp_init_to_init(struct ib_qp *ibqp,
4363                                    const struct ib_qp_attr *attr,
4364                                    struct hns_roce_v2_qp_context *context,
4365                                    struct hns_roce_v2_qp_context *qpc_mask)
4366 {
4367         /*
4368          * In v2 engine, software pass context and context mask to hardware
4369          * when modifying qp. If software need modify some fields in context,
4370          * we should set all bits of the relevant fields in context mask to
4371          * 0 at the same time, else set them to 0x1.
4372          */
4373         hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4374         hr_reg_clear(qpc_mask, QPC_TST);
4375
4376         hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4377         hr_reg_clear(qpc_mask, QPC_PD);
4378
4379         hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4380         hr_reg_clear(qpc_mask, QPC_RX_CQN);
4381
4382         hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4383         hr_reg_clear(qpc_mask, QPC_TX_CQN);
4384
4385         if (ibqp->srq) {
4386                 hr_reg_enable(context, QPC_SRQ_EN);
4387                 hr_reg_clear(qpc_mask, QPC_SRQ_EN);
4388                 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4389                 hr_reg_clear(qpc_mask, QPC_SRQN);
4390         }
4391 }
4392
4393 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev,
4394                             struct hns_roce_qp *hr_qp,
4395                             struct hns_roce_v2_qp_context *context,
4396                             struct hns_roce_v2_qp_context *qpc_mask)
4397 {
4398         u64 mtts[MTT_MIN_COUNT] = { 0 };
4399         u64 wqe_sge_ba;
4400         int count;
4401
4402         /* Search qp buf's mtts */
4403         count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts,
4404                                   MTT_MIN_COUNT, &wqe_sge_ba);
4405         if (hr_qp->rq.wqe_cnt && count < 1) {
4406                 ibdev_err(&hr_dev->ib_dev,
4407                           "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn);
4408                 return -EINVAL;
4409         }
4410
4411         context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3);
4412         qpc_mask->wqe_sge_ba = 0;
4413
4414         /*
4415          * In v2 engine, software pass context and context mask to hardware
4416          * when modifying qp. If software need modify some fields in context,
4417          * we should set all bits of the relevant fields in context mask to
4418          * 0 at the same time, else set them to 0x1.
4419          */
4420         hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3));
4421         hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H);
4422
4423         hr_reg_write(context, QPC_SQ_HOP_NUM,
4424                      to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num,
4425                                       hr_qp->sq.wqe_cnt));
4426         hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM);
4427
4428         hr_reg_write(context, QPC_SGE_HOP_NUM,
4429                      to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num,
4430                                       hr_qp->sge.sge_cnt));
4431         hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM);
4432
4433         hr_reg_write(context, QPC_RQ_HOP_NUM,
4434                      to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num,
4435                                       hr_qp->rq.wqe_cnt));
4436
4437         hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM);
4438
4439         hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ,
4440                      to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift));
4441         hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ);
4442
4443         hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ,
4444                      to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift));
4445         hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ);
4446
4447         context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
4448         qpc_mask->rq_cur_blk_addr = 0;
4449
4450         hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H,
4451                      upper_32_bits(to_hr_hw_page_addr(mtts[0])));
4452         hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H);
4453
4454         context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
4455         qpc_mask->rq_nxt_blk_addr = 0;
4456
4457         hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H,
4458                      upper_32_bits(to_hr_hw_page_addr(mtts[1])));
4459         hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H);
4460
4461         return 0;
4462 }
4463
4464 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev,
4465                             struct hns_roce_qp *hr_qp,
4466                             struct hns_roce_v2_qp_context *context,
4467                             struct hns_roce_v2_qp_context *qpc_mask)
4468 {
4469         struct ib_device *ibdev = &hr_dev->ib_dev;
4470         u64 sge_cur_blk = 0;
4471         u64 sq_cur_blk = 0;
4472         int count;
4473
4474         /* search qp buf's mtts */
4475         count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL);
4476         if (count < 1) {
4477                 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n",
4478                           hr_qp->qpn);
4479                 return -EINVAL;
4480         }
4481         if (hr_qp->sge.sge_cnt > 0) {
4482                 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
4483                                           hr_qp->sge.offset,
4484                                           &sge_cur_blk, 1, NULL);
4485                 if (count < 1) {
4486                         ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n",
4487                                   hr_qp->qpn);
4488                         return -EINVAL;
4489                 }
4490         }
4491
4492         /*
4493          * In v2 engine, software pass context and context mask to hardware
4494          * when modifying qp. If software need modify some fields in context,
4495          * we should set all bits of the relevant fields in context mask to
4496          * 0 at the same time, else set them to 0x1.
4497          */
4498         hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L,
4499                      lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4500         hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H,
4501                      upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4502         hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L);
4503         hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H);
4504
4505         hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L,
4506                      lower_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4507         hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H,
4508                      upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4509         hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L);
4510         hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H);
4511
4512         hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L,
4513                      lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4514         hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H,
4515                      upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4516         hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L);
4517         hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H);
4518
4519         return 0;
4520 }
4521
4522 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp,
4523                                   const struct ib_qp_attr *attr)
4524 {
4525         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
4526                 return IB_MTU_4096;
4527
4528         return attr->path_mtu;
4529 }
4530
4531 static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
4532                                  const struct ib_qp_attr *attr, int attr_mask,
4533                                  struct hns_roce_v2_qp_context *context,
4534                                  struct hns_roce_v2_qp_context *qpc_mask)
4535 {
4536         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4537         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4538         struct ib_device *ibdev = &hr_dev->ib_dev;
4539         dma_addr_t trrl_ba;
4540         dma_addr_t irrl_ba;
4541         enum ib_mtu ib_mtu;
4542         const u8 *smac;
4543         u8 lp_pktn_ini;
4544         u64 *mtts;
4545         u8 *dmac;
4546         u32 port;
4547         int mtu;
4548         int ret;
4549
4550         ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask);
4551         if (ret) {
4552                 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret);
4553                 return ret;
4554         }
4555
4556         /* Search IRRL's mtts */
4557         mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
4558                                    hr_qp->qpn, &irrl_ba);
4559         if (!mtts) {
4560                 ibdev_err(ibdev, "failed to find qp irrl_table.\n");
4561                 return -EINVAL;
4562         }
4563
4564         /* Search TRRL's mtts */
4565         mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
4566                                    hr_qp->qpn, &trrl_ba);
4567         if (!mtts) {
4568                 ibdev_err(ibdev, "failed to find qp trrl_table.\n");
4569                 return -EINVAL;
4570         }
4571
4572         if (attr_mask & IB_QP_ALT_PATH) {
4573                 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n",
4574                           attr_mask);
4575                 return -EINVAL;
4576         }
4577
4578         hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4);
4579         hr_reg_clear(qpc_mask, QPC_TRRL_BA_L);
4580         context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4));
4581         qpc_mask->trrl_ba = 0;
4582         hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4));
4583         hr_reg_clear(qpc_mask, QPC_TRRL_BA_H);
4584
4585         context->irrl_ba = cpu_to_le32(irrl_ba >> 6);
4586         qpc_mask->irrl_ba = 0;
4587         hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6));
4588         hr_reg_clear(qpc_mask, QPC_IRRL_BA_H);
4589
4590         hr_reg_enable(context, QPC_RMT_E2E);
4591         hr_reg_clear(qpc_mask, QPC_RMT_E2E);
4592
4593         hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits);
4594         hr_reg_clear(qpc_mask, QPC_SIG_TYPE);
4595
4596         port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
4597
4598         smac = (const u8 *)hr_dev->dev_addr[port];
4599         dmac = (u8 *)attr->ah_attr.roce.dmac;
4600         /* when dmac equals smac or loop_idc is 1, it should loopback */
4601         if (ether_addr_equal_unaligned(dmac, smac) ||
4602             hr_dev->loop_idc == 0x1) {
4603                 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc);
4604                 hr_reg_clear(qpc_mask, QPC_LBI);
4605         }
4606
4607         if (attr_mask & IB_QP_DEST_QPN) {
4608                 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num);
4609                 hr_reg_clear(qpc_mask, QPC_DQPN);
4610         }
4611
4612         memcpy(&context->dmac, dmac, sizeof(u32));
4613         hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4])));
4614         qpc_mask->dmac = 0;
4615         hr_reg_clear(qpc_mask, QPC_DMAC_H);
4616
4617         ib_mtu = get_mtu(ibqp, attr);
4618         hr_qp->path_mtu = ib_mtu;
4619
4620         mtu = ib_mtu_enum_to_int(ib_mtu);
4621         if (WARN_ON(mtu <= 0))
4622                 return -EINVAL;
4623 #define MAX_LP_MSG_LEN 16384
4624         /* MTU * (2 ^ LP_PKTN_INI) shouldn't be bigger than 16KB */
4625         lp_pktn_ini = ilog2(MAX_LP_MSG_LEN / mtu);
4626         if (WARN_ON(lp_pktn_ini >= 0xF))
4627                 return -EINVAL;
4628
4629         if (attr_mask & IB_QP_PATH_MTU) {
4630                 hr_reg_write(context, QPC_MTU, ib_mtu);
4631                 hr_reg_clear(qpc_mask, QPC_MTU);
4632         }
4633
4634         hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini);
4635         hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI);
4636
4637         /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */
4638         hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini);
4639         hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ);
4640
4641         hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR);
4642         hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN);
4643         hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE);
4644
4645         context->rq_rnr_timer = 0;
4646         qpc_mask->rq_rnr_timer = 0;
4647
4648         hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX);
4649         hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX);
4650
4651         /* rocee send 2^lp_sgen_ini segs every time */
4652         hr_reg_write(context, QPC_LP_SGEN_INI, 3);
4653         hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI);
4654
4655         return 0;
4656 }
4657
4658 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
4659                                 const struct ib_qp_attr *attr, int attr_mask,
4660                                 struct hns_roce_v2_qp_context *context,
4661                                 struct hns_roce_v2_qp_context *qpc_mask)
4662 {
4663         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4664         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4665         struct ib_device *ibdev = &hr_dev->ib_dev;
4666         int ret;
4667
4668         /* Not support alternate path and path migration */
4669         if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) {
4670                 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
4671                 return -EINVAL;
4672         }
4673
4674         ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask);
4675         if (ret) {
4676                 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret);
4677                 return ret;
4678         }
4679
4680         /*
4681          * Set some fields in context to zero, Because the default values
4682          * of all fields in context are zero, we need not set them to 0 again.
4683          * but we should set the relevant fields of context mask to 0.
4684          */
4685         hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX);
4686
4687         hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN);
4688
4689         hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE);
4690         hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD);
4691         hr_reg_clear(qpc_mask, QPC_IRRL_PSN);
4692
4693         hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL);
4694
4695         hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN);
4696
4697         hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG);
4698
4699         hr_reg_clear(qpc_mask, QPC_CHECK_FLG);
4700
4701         hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD);
4702
4703         return 0;
4704 }
4705
4706 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4707                            u32 *dip_idx)
4708 {
4709         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4710         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4711         u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx;
4712         u32 *head =  &hr_dev->qp_table.idx_table.head;
4713         u32 *tail =  &hr_dev->qp_table.idx_table.tail;
4714         struct hns_roce_dip *hr_dip;
4715         unsigned long flags;
4716         int ret = 0;
4717
4718         spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
4719
4720         spare_idx[*tail] = ibqp->qp_num;
4721         *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1);
4722
4723         list_for_each_entry(hr_dip, &hr_dev->dip_list, node) {
4724                 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) {
4725                         *dip_idx = hr_dip->dip_idx;
4726                         goto out;
4727                 }
4728         }
4729
4730         /* If no dgid is found, a new dip and a mapping between dgid and
4731          * dip_idx will be created.
4732          */
4733         hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC);
4734         if (!hr_dip) {
4735                 ret = -ENOMEM;
4736                 goto out;
4737         }
4738
4739         memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4740         hr_dip->dip_idx = *dip_idx = spare_idx[*head];
4741         *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1);
4742         list_add_tail(&hr_dip->node, &hr_dev->dip_list);
4743
4744 out:
4745         spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
4746         return ret;
4747 }
4748
4749 enum {
4750         CONG_DCQCN,
4751         CONG_WINDOW,
4752 };
4753
4754 enum {
4755         UNSUPPORT_CONG_LEVEL,
4756         SUPPORT_CONG_LEVEL,
4757 };
4758
4759 enum {
4760         CONG_LDCP,
4761         CONG_HC3,
4762 };
4763
4764 enum {
4765         DIP_INVALID,
4766         DIP_VALID,
4767 };
4768
4769 enum {
4770         WND_LIMIT,
4771         WND_UNLIMIT,
4772 };
4773
4774 static int check_cong_type(struct ib_qp *ibqp,
4775                            struct hns_roce_congestion_algorithm *cong_alg)
4776 {
4777         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4778
4779         /* different congestion types match different configurations */
4780         switch (hr_dev->caps.cong_type) {
4781         case CONG_TYPE_DCQCN:
4782                 cong_alg->alg_sel = CONG_DCQCN;
4783                 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4784                 cong_alg->dip_vld = DIP_INVALID;
4785                 cong_alg->wnd_mode_sel = WND_LIMIT;
4786                 break;
4787         case CONG_TYPE_LDCP:
4788                 cong_alg->alg_sel = CONG_WINDOW;
4789                 cong_alg->alg_sub_sel = CONG_LDCP;
4790                 cong_alg->dip_vld = DIP_INVALID;
4791                 cong_alg->wnd_mode_sel = WND_UNLIMIT;
4792                 break;
4793         case CONG_TYPE_HC3:
4794                 cong_alg->alg_sel = CONG_WINDOW;
4795                 cong_alg->alg_sub_sel = CONG_HC3;
4796                 cong_alg->dip_vld = DIP_INVALID;
4797                 cong_alg->wnd_mode_sel = WND_LIMIT;
4798                 break;
4799         case CONG_TYPE_DIP:
4800                 cong_alg->alg_sel = CONG_DCQCN;
4801                 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4802                 cong_alg->dip_vld = DIP_VALID;
4803                 cong_alg->wnd_mode_sel = WND_LIMIT;
4804                 break;
4805         default:
4806                 ibdev_err(&hr_dev->ib_dev,
4807                           "error type(%u) for congestion selection.\n",
4808                           hr_dev->caps.cong_type);
4809                 return -EINVAL;
4810         }
4811
4812         return 0;
4813 }
4814
4815 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4816                            struct hns_roce_v2_qp_context *context,
4817                            struct hns_roce_v2_qp_context *qpc_mask)
4818 {
4819         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4820         struct hns_roce_congestion_algorithm cong_field;
4821         struct ib_device *ibdev = ibqp->device;
4822         struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
4823         u32 dip_idx = 0;
4824         int ret;
4825
4826         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ||
4827             grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE)
4828                 return 0;
4829
4830         ret = check_cong_type(ibqp, &cong_field);
4831         if (ret)
4832                 return ret;
4833
4834         hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id +
4835                      hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE);
4836         hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID);
4837         hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel);
4838         hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL);
4839         hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL,
4840                      cong_field.alg_sub_sel);
4841         hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL);
4842         hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld);
4843         hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD);
4844         hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN,
4845                      cong_field.wnd_mode_sel);
4846         hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN);
4847
4848         /* if dip is disabled, there is no need to set dip idx */
4849         if (cong_field.dip_vld == 0)
4850                 return 0;
4851
4852         ret = get_dip_ctx_idx(ibqp, attr, &dip_idx);
4853         if (ret) {
4854                 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret);
4855                 return ret;
4856         }
4857
4858         hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx);
4859         hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0);
4860
4861         return 0;
4862 }
4863
4864 static int hns_roce_v2_set_path(struct ib_qp *ibqp,
4865                                 const struct ib_qp_attr *attr,
4866                                 int attr_mask,
4867                                 struct hns_roce_v2_qp_context *context,
4868                                 struct hns_roce_v2_qp_context *qpc_mask)
4869 {
4870         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4871         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4872         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4873         struct ib_device *ibdev = &hr_dev->ib_dev;
4874         const struct ib_gid_attr *gid_attr = NULL;
4875         int is_roce_protocol;
4876         u16 vlan_id = 0xffff;
4877         bool is_udp = false;
4878         u8 ib_port;
4879         u8 hr_port;
4880         int ret;
4881
4882         /*
4883          * If free_mr_en of qp is set, it means that this qp comes from
4884          * free mr. This qp will perform the loopback operation.
4885          * In the loopback scenario, only sl needs to be set.
4886          */
4887         if (hr_qp->free_mr_en) {
4888                 hr_reg_write(context, QPC_SL, rdma_ah_get_sl(&attr->ah_attr));
4889                 hr_reg_clear(qpc_mask, QPC_SL);
4890                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
4891                 return 0;
4892         }
4893
4894         ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
4895         hr_port = ib_port - 1;
4896         is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
4897                            rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
4898
4899         if (is_roce_protocol) {
4900                 gid_attr = attr->ah_attr.grh.sgid_attr;
4901                 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL);
4902                 if (ret)
4903                         return ret;
4904
4905                 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP);
4906         }
4907
4908         /* Only HIP08 needs to set the vlan_en bits in QPC */
4909         if (vlan_id < VLAN_N_VID &&
4910             hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
4911                 hr_reg_enable(context, QPC_RQ_VLAN_EN);
4912                 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN);
4913                 hr_reg_enable(context, QPC_SQ_VLAN_EN);
4914                 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN);
4915         }
4916
4917         hr_reg_write(context, QPC_VLAN_ID, vlan_id);
4918         hr_reg_clear(qpc_mask, QPC_VLAN_ID);
4919
4920         if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
4921                 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n",
4922                           grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]);
4923                 return -EINVAL;
4924         }
4925
4926         if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
4927                 ibdev_err(ibdev, "ah attr is not RDMA roce type\n");
4928                 return -EINVAL;
4929         }
4930
4931         hr_reg_write(context, QPC_UDPSPN,
4932                      is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num,
4933                                                  attr->dest_qp_num) :
4934                                     0);
4935
4936         hr_reg_clear(qpc_mask, QPC_UDPSPN);
4937
4938         hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index);
4939
4940         hr_reg_clear(qpc_mask, QPC_GMV_IDX);
4941
4942         hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit);
4943         hr_reg_clear(qpc_mask, QPC_HOPLIMIT);
4944
4945         ret = fill_cong_field(ibqp, attr, context, qpc_mask);
4946         if (ret)
4947                 return ret;
4948
4949         hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh));
4950         hr_reg_clear(qpc_mask, QPC_TC);
4951
4952         hr_reg_write(context, QPC_FL, grh->flow_label);
4953         hr_reg_clear(qpc_mask, QPC_FL);
4954         memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4955         memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
4956
4957         hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
4958         if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) {
4959                 ibdev_err(ibdev,
4960                           "failed to fill QPC, sl (%u) shouldn't be larger than %d.\n",
4961                           hr_qp->sl, MAX_SERVICE_LEVEL);
4962                 return -EINVAL;
4963         }
4964
4965         hr_reg_write(context, QPC_SL, hr_qp->sl);
4966         hr_reg_clear(qpc_mask, QPC_SL);
4967
4968         return 0;
4969 }
4970
4971 static bool check_qp_state(enum ib_qp_state cur_state,
4972                            enum ib_qp_state new_state)
4973 {
4974         static const bool sm[][IB_QPS_ERR + 1] = {
4975                 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
4976                                    [IB_QPS_INIT] = true },
4977                 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
4978                                   [IB_QPS_INIT] = true,
4979                                   [IB_QPS_RTR] = true,
4980                                   [IB_QPS_ERR] = true },
4981                 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
4982                                  [IB_QPS_RTS] = true,
4983                                  [IB_QPS_ERR] = true },
4984                 [IB_QPS_RTS] = { [IB_QPS_RESET] = true,
4985                                  [IB_QPS_RTS] = true,
4986                                  [IB_QPS_ERR] = true },
4987                 [IB_QPS_SQD] = {},
4988                 [IB_QPS_SQE] = {},
4989                 [IB_QPS_ERR] = { [IB_QPS_RESET] = true,
4990                                  [IB_QPS_ERR] = true }
4991         };
4992
4993         return sm[cur_state][new_state];
4994 }
4995
4996 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
4997                                       const struct ib_qp_attr *attr,
4998                                       int attr_mask,
4999                                       enum ib_qp_state cur_state,
5000                                       enum ib_qp_state new_state,
5001                                       struct hns_roce_v2_qp_context *context,
5002                                       struct hns_roce_v2_qp_context *qpc_mask)
5003 {
5004         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5005         int ret = 0;
5006
5007         if (!check_qp_state(cur_state, new_state)) {
5008                 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n");
5009                 return -EINVAL;
5010         }
5011
5012         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
5013                 memset(qpc_mask, 0, hr_dev->caps.qpc_sz);
5014                 modify_qp_reset_to_init(ibqp, attr, context, qpc_mask);
5015         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
5016                 modify_qp_init_to_init(ibqp, attr, context, qpc_mask);
5017         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
5018                 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
5019                                             qpc_mask);
5020         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
5021                 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
5022                                            qpc_mask);
5023         }
5024
5025         return ret;
5026 }
5027
5028 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout)
5029 {
5030 #define QP_ACK_TIMEOUT_MAX_HIP08 20
5031 #define QP_ACK_TIMEOUT_OFFSET 10
5032 #define QP_ACK_TIMEOUT_MAX 31
5033
5034         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5035                 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) {
5036                         ibdev_warn(&hr_dev->ib_dev,
5037                                    "local ACK timeout shall be 0 to 20.\n");
5038                         return false;
5039                 }
5040                 *timeout += QP_ACK_TIMEOUT_OFFSET;
5041         } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) {
5042                 if (*timeout > QP_ACK_TIMEOUT_MAX) {
5043                         ibdev_warn(&hr_dev->ib_dev,
5044                                    "local ACK timeout shall be 0 to 31.\n");
5045                         return false;
5046                 }
5047         }
5048
5049         return true;
5050 }
5051
5052 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp,
5053                                       const struct ib_qp_attr *attr,
5054                                       int attr_mask,
5055                                       struct hns_roce_v2_qp_context *context,
5056                                       struct hns_roce_v2_qp_context *qpc_mask)
5057 {
5058         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5059         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5060         int ret = 0;
5061         u8 timeout;
5062
5063         if (attr_mask & IB_QP_AV) {
5064                 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context,
5065                                            qpc_mask);
5066                 if (ret)
5067                         return ret;
5068         }
5069
5070         if (attr_mask & IB_QP_TIMEOUT) {
5071                 timeout = attr->timeout;
5072                 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) {
5073                         hr_reg_write(context, QPC_AT, timeout);
5074                         hr_reg_clear(qpc_mask, QPC_AT);
5075                 }
5076         }
5077
5078         if (attr_mask & IB_QP_RETRY_CNT) {
5079                 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt);
5080                 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT);
5081
5082                 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt);
5083                 hr_reg_clear(qpc_mask, QPC_RETRY_CNT);
5084         }
5085
5086         if (attr_mask & IB_QP_RNR_RETRY) {
5087                 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry);
5088                 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT);
5089
5090                 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry);
5091                 hr_reg_clear(qpc_mask, QPC_RNR_CNT);
5092         }
5093
5094         if (attr_mask & IB_QP_SQ_PSN) {
5095                 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn);
5096                 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN);
5097
5098                 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn);
5099                 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN);
5100
5101                 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn);
5102                 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L);
5103
5104                 hr_reg_write(context, QPC_RETRY_MSG_PSN_H,
5105                              attr->sq_psn >> RETRY_MSG_PSN_SHIFT);
5106                 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H);
5107
5108                 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn);
5109                 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN);
5110
5111                 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn);
5112                 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN);
5113         }
5114
5115         if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
5116              attr->max_dest_rd_atomic) {
5117                 hr_reg_write(context, QPC_RR_MAX,
5118                              fls(attr->max_dest_rd_atomic - 1));
5119                 hr_reg_clear(qpc_mask, QPC_RR_MAX);
5120         }
5121
5122         if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
5123                 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1));
5124                 hr_reg_clear(qpc_mask, QPC_SR_MAX);
5125         }
5126
5127         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
5128                 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
5129
5130         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
5131                 hr_reg_write(context, QPC_MIN_RNR_TIME,
5132                             hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ?
5133                             HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer);
5134                 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME);
5135         }
5136
5137         if (attr_mask & IB_QP_RQ_PSN) {
5138                 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn);
5139                 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN);
5140
5141                 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1);
5142                 hr_reg_clear(qpc_mask, QPC_RAQ_PSN);
5143         }
5144
5145         if (attr_mask & IB_QP_QKEY) {
5146                 context->qkey_xrcd = cpu_to_le32(attr->qkey);
5147                 qpc_mask->qkey_xrcd = 0;
5148                 hr_qp->qkey = attr->qkey;
5149         }
5150
5151         return ret;
5152 }
5153
5154 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp,
5155                                           const struct ib_qp_attr *attr,
5156                                           int attr_mask)
5157 {
5158         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5159         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5160
5161         if (attr_mask & IB_QP_ACCESS_FLAGS)
5162                 hr_qp->atomic_rd_en = attr->qp_access_flags;
5163
5164         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
5165                 hr_qp->resp_depth = attr->max_dest_rd_atomic;
5166         if (attr_mask & IB_QP_PORT) {
5167                 hr_qp->port = attr->port_num - 1;
5168                 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
5169         }
5170 }
5171
5172 static void clear_qp(struct hns_roce_qp *hr_qp)
5173 {
5174         struct ib_qp *ibqp = &hr_qp->ibqp;
5175
5176         if (ibqp->send_cq)
5177                 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
5178                                      hr_qp->qpn, NULL);
5179
5180         if (ibqp->recv_cq  && ibqp->recv_cq != ibqp->send_cq)
5181                 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq),
5182                                      hr_qp->qpn, ibqp->srq ?
5183                                      to_hr_srq(ibqp->srq) : NULL);
5184
5185         if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
5186                 *hr_qp->rdb.db_record = 0;
5187
5188         hr_qp->rq.head = 0;
5189         hr_qp->rq.tail = 0;
5190         hr_qp->sq.head = 0;
5191         hr_qp->sq.tail = 0;
5192         hr_qp->next_sge = 0;
5193 }
5194
5195 static void v2_set_flushed_fields(struct ib_qp *ibqp,
5196                                   struct hns_roce_v2_qp_context *context,
5197                                   struct hns_roce_v2_qp_context *qpc_mask)
5198 {
5199         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5200         unsigned long sq_flag = 0;
5201         unsigned long rq_flag = 0;
5202
5203         if (ibqp->qp_type == IB_QPT_XRC_TGT)
5204                 return;
5205
5206         spin_lock_irqsave(&hr_qp->sq.lock, sq_flag);
5207         hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head);
5208         hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX);
5209         hr_qp->state = IB_QPS_ERR;
5210         spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag);
5211
5212         if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */
5213                 return;
5214
5215         spin_lock_irqsave(&hr_qp->rq.lock, rq_flag);
5216         hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head);
5217         hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX);
5218         spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag);
5219 }
5220
5221 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
5222                                  const struct ib_qp_attr *attr,
5223                                  int attr_mask, enum ib_qp_state cur_state,
5224                                  enum ib_qp_state new_state)
5225 {
5226         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5227         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5228         struct hns_roce_v2_qp_context ctx[2];
5229         struct hns_roce_v2_qp_context *context = ctx;
5230         struct hns_roce_v2_qp_context *qpc_mask = ctx + 1;
5231         struct ib_device *ibdev = &hr_dev->ib_dev;
5232         int ret;
5233
5234         if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
5235                 return -EOPNOTSUPP;
5236
5237         /*
5238          * In v2 engine, software pass context and context mask to hardware
5239          * when modifying qp. If software need modify some fields in context,
5240          * we should set all bits of the relevant fields in context mask to
5241          * 0 at the same time, else set them to 0x1.
5242          */
5243         memset(context, 0, hr_dev->caps.qpc_sz);
5244         memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz);
5245
5246         ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
5247                                          new_state, context, qpc_mask);
5248         if (ret)
5249                 goto out;
5250
5251         /* When QP state is err, SQ and RQ WQE should be flushed */
5252         if (new_state == IB_QPS_ERR)
5253                 v2_set_flushed_fields(ibqp, context, qpc_mask);
5254
5255         /* Configure the optional fields */
5256         ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context,
5257                                          qpc_mask);
5258         if (ret)
5259                 goto out;
5260
5261         hr_reg_write_bool(context, QPC_INV_CREDIT,
5262                           to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC ||
5263                           ibqp->srq);
5264         hr_reg_clear(qpc_mask, QPC_INV_CREDIT);
5265
5266         /* Every status migrate must change state */
5267         hr_reg_write(context, QPC_QP_ST, new_state);
5268         hr_reg_clear(qpc_mask, QPC_QP_ST);
5269
5270         /* SW pass context to HW */
5271         ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp);
5272         if (ret) {
5273                 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret);
5274                 goto out;
5275         }
5276
5277         hr_qp->state = new_state;
5278
5279         hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask);
5280
5281         if (new_state == IB_QPS_RESET && !ibqp->uobject)
5282                 clear_qp(hr_qp);
5283
5284 out:
5285         return ret;
5286 }
5287
5288 static int to_ib_qp_st(enum hns_roce_v2_qp_state state)
5289 {
5290         static const enum ib_qp_state map[] = {
5291                 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET,
5292                 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT,
5293                 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR,
5294                 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS,
5295                 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD,
5296                 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE,
5297                 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR,
5298                 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD
5299         };
5300
5301         return (state < ARRAY_SIZE(map)) ? map[state] : -1;
5302 }
5303
5304 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn,
5305                                  void *buffer)
5306 {
5307         struct hns_roce_cmd_mailbox *mailbox;
5308         int ret;
5309
5310         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5311         if (IS_ERR(mailbox))
5312                 return PTR_ERR(mailbox);
5313
5314         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC,
5315                                 qpn);
5316         if (ret)
5317                 goto out;
5318
5319         memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz);
5320
5321 out:
5322         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5323         return ret;
5324 }
5325
5326 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5327                                 int qp_attr_mask,
5328                                 struct ib_qp_init_attr *qp_init_attr)
5329 {
5330         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5331         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5332         struct hns_roce_v2_qp_context context = {};
5333         struct ib_device *ibdev = &hr_dev->ib_dev;
5334         int tmp_qp_state;
5335         int state;
5336         int ret;
5337
5338         memset(qp_attr, 0, sizeof(*qp_attr));
5339         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5340
5341         mutex_lock(&hr_qp->mutex);
5342
5343         if (hr_qp->state == IB_QPS_RESET) {
5344                 qp_attr->qp_state = IB_QPS_RESET;
5345                 ret = 0;
5346                 goto done;
5347         }
5348
5349         ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context);
5350         if (ret) {
5351                 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret);
5352                 ret = -EINVAL;
5353                 goto out;
5354         }
5355
5356         state = hr_reg_read(&context, QPC_QP_ST);
5357         tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
5358         if (tmp_qp_state == -1) {
5359                 ibdev_err(ibdev, "Illegal ib_qp_state\n");
5360                 ret = -EINVAL;
5361                 goto out;
5362         }
5363         hr_qp->state = (u8)tmp_qp_state;
5364         qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
5365         qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU);
5366         qp_attr->path_mig_state = IB_MIG_ARMED;
5367         qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
5368         if (hr_qp->ibqp.qp_type == IB_QPT_UD)
5369                 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd);
5370
5371         qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN);
5372         qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN);
5373         qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN);
5374         qp_attr->qp_access_flags =
5375                 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) |
5376                 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) |
5377                 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S);
5378
5379         if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
5380             hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5381             hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) {
5382                 struct ib_global_route *grh =
5383                         rdma_ah_retrieve_grh(&qp_attr->ah_attr);
5384
5385                 rdma_ah_set_sl(&qp_attr->ah_attr,
5386                                hr_reg_read(&context, QPC_SL));
5387                 grh->flow_label = hr_reg_read(&context, QPC_FL);
5388                 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX);
5389                 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT);
5390                 grh->traffic_class = hr_reg_read(&context, QPC_TC);
5391
5392                 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw));
5393         }
5394
5395         qp_attr->port_num = hr_qp->port + 1;
5396         qp_attr->sq_draining = 0;
5397         qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX);
5398         qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX);
5399
5400         qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME);
5401         qp_attr->timeout = (u8)hr_reg_read(&context, QPC_AT);
5402         qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT);
5403         qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT);
5404
5405 done:
5406         qp_attr->cur_qp_state = qp_attr->qp_state;
5407         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
5408         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
5409         qp_attr->cap.max_inline_data = hr_qp->max_inline_data;
5410
5411         qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
5412         qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
5413
5414         qp_init_attr->qp_context = ibqp->qp_context;
5415         qp_init_attr->qp_type = ibqp->qp_type;
5416         qp_init_attr->recv_cq = ibqp->recv_cq;
5417         qp_init_attr->send_cq = ibqp->send_cq;
5418         qp_init_attr->srq = ibqp->srq;
5419         qp_init_attr->cap = qp_attr->cap;
5420         qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits;
5421
5422 out:
5423         mutex_unlock(&hr_qp->mutex);
5424         return ret;
5425 }
5426
5427 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp)
5428 {
5429         return ((hr_qp->ibqp.qp_type == IB_QPT_RC ||
5430                  hr_qp->ibqp.qp_type == IB_QPT_UD ||
5431                  hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5432                  hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
5433                 hr_qp->state != IB_QPS_RESET);
5434 }
5435
5436 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
5437                                          struct hns_roce_qp *hr_qp,
5438                                          struct ib_udata *udata)
5439 {
5440         struct ib_device *ibdev = &hr_dev->ib_dev;
5441         struct hns_roce_cq *send_cq, *recv_cq;
5442         unsigned long flags;
5443         int ret = 0;
5444
5445         if (modify_qp_is_ok(hr_qp)) {
5446                 /* Modify qp to reset before destroying qp */
5447                 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
5448                                             hr_qp->state, IB_QPS_RESET);
5449                 if (ret)
5450                         ibdev_err(ibdev,
5451                                   "failed to modify QP to RST, ret = %d.\n",
5452                                   ret);
5453         }
5454
5455         send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
5456         recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
5457
5458         spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
5459         hns_roce_lock_cqs(send_cq, recv_cq);
5460
5461         if (!udata) {
5462                 if (recv_cq)
5463                         __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn,
5464                                                (hr_qp->ibqp.srq ?
5465                                                 to_hr_srq(hr_qp->ibqp.srq) :
5466                                                 NULL));
5467
5468                 if (send_cq && send_cq != recv_cq)
5469                         __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
5470         }
5471
5472         hns_roce_qp_remove(hr_dev, hr_qp);
5473
5474         hns_roce_unlock_cqs(send_cq, recv_cq);
5475         spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
5476
5477         return ret;
5478 }
5479
5480 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
5481 {
5482         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5483         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5484         int ret;
5485
5486         ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
5487         if (ret)
5488                 ibdev_err(&hr_dev->ib_dev,
5489                           "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n",
5490                           hr_qp->qpn, ret);
5491
5492         hns_roce_qp_destroy(hr_dev, hr_qp, udata);
5493
5494         return 0;
5495 }
5496
5497 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
5498                                             struct hns_roce_qp *hr_qp)
5499 {
5500         struct ib_device *ibdev = &hr_dev->ib_dev;
5501         struct hns_roce_sccc_clr_done *resp;
5502         struct hns_roce_sccc_clr *clr;
5503         struct hns_roce_cmq_desc desc;
5504         int ret, i;
5505
5506         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
5507                 return 0;
5508
5509         mutex_lock(&hr_dev->qp_table.scc_mutex);
5510
5511         /* set scc ctx clear done flag */
5512         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
5513         ret =  hns_roce_cmq_send(hr_dev, &desc, 1);
5514         if (ret) {
5515                 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret);
5516                 goto out;
5517         }
5518
5519         /* clear scc context */
5520         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
5521         clr = (struct hns_roce_sccc_clr *)desc.data;
5522         clr->qpn = cpu_to_le32(hr_qp->qpn);
5523         ret =  hns_roce_cmq_send(hr_dev, &desc, 1);
5524         if (ret) {
5525                 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret);
5526                 goto out;
5527         }
5528
5529         /* query scc context clear is done or not */
5530         resp = (struct hns_roce_sccc_clr_done *)desc.data;
5531         for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
5532                 hns_roce_cmq_setup_basic_desc(&desc,
5533                                               HNS_ROCE_OPC_QUERY_SCCC, true);
5534                 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5535                 if (ret) {
5536                         ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
5537                                   ret);
5538                         goto out;
5539                 }
5540
5541                 if (resp->clr_done)
5542                         goto out;
5543
5544                 msleep(20);
5545         }
5546
5547         ibdev_err(ibdev, "query SCC clr done flag overtime.\n");
5548         ret = -ETIMEDOUT;
5549
5550 out:
5551         mutex_unlock(&hr_dev->qp_table.scc_mutex);
5552         return ret;
5553 }
5554
5555 #define DMA_IDX_SHIFT 3
5556 #define DMA_WQE_SHIFT 3
5557
5558 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq,
5559                                               struct hns_roce_srq_context *ctx)
5560 {
5561         struct hns_roce_idx_que *idx_que = &srq->idx_que;
5562         struct ib_device *ibdev = srq->ibsrq.device;
5563         struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5564         u64 mtts_idx[MTT_MIN_COUNT] = {};
5565         dma_addr_t dma_handle_idx = 0;
5566         int ret;
5567
5568         /* Get physical address of idx que buf */
5569         ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx,
5570                                 ARRAY_SIZE(mtts_idx), &dma_handle_idx);
5571         if (ret < 1) {
5572                 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n",
5573                           ret);
5574                 return -ENOBUFS;
5575         }
5576
5577         hr_reg_write(ctx, SRQC_IDX_HOP_NUM,
5578                      to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt));
5579
5580         hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT);
5581         hr_reg_write(ctx, SRQC_IDX_BT_BA_H,
5582                      upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT));
5583
5584         hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ,
5585                      to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift));
5586         hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ,
5587                      to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift));
5588
5589         hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L,
5590                      to_hr_hw_page_addr(mtts_idx[0]));
5591         hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H,
5592                      upper_32_bits(to_hr_hw_page_addr(mtts_idx[0])));
5593
5594         hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L,
5595                      to_hr_hw_page_addr(mtts_idx[1]));
5596         hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H,
5597                      upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
5598
5599         return 0;
5600 }
5601
5602 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf)
5603 {
5604         struct ib_device *ibdev = srq->ibsrq.device;
5605         struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5606         struct hns_roce_srq_context *ctx = mb_buf;
5607         u64 mtts_wqe[MTT_MIN_COUNT] = {};
5608         dma_addr_t dma_handle_wqe = 0;
5609         int ret;
5610
5611         memset(ctx, 0, sizeof(*ctx));
5612
5613         /* Get the physical address of srq buf */
5614         ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe,
5615                                 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe);
5616         if (ret < 1) {
5617                 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n",
5618                           ret);
5619                 return -ENOBUFS;
5620         }
5621
5622         hr_reg_write(ctx, SRQC_SRQ_ST, 1);
5623         hr_reg_write_bool(ctx, SRQC_SRQ_TYPE,
5624                           srq->ibsrq.srq_type == IB_SRQT_XRC);
5625         hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn);
5626         hr_reg_write(ctx, SRQC_SRQN, srq->srqn);
5627         hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn);
5628         hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn);
5629         hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt));
5630         hr_reg_write(ctx, SRQC_RQWS,
5631                      srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1));
5632
5633         hr_reg_write(ctx, SRQC_WQE_HOP_NUM,
5634                      to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num,
5635                                       srq->wqe_cnt));
5636
5637         hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT);
5638         hr_reg_write(ctx, SRQC_WQE_BT_BA_H,
5639                      upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT));
5640
5641         hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ,
5642                      to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift));
5643         hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ,
5644                      to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift));
5645
5646         return hns_roce_v2_write_srqc_index_queue(srq, ctx);
5647 }
5648
5649 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5650                                   struct ib_srq_attr *srq_attr,
5651                                   enum ib_srq_attr_mask srq_attr_mask,
5652                                   struct ib_udata *udata)
5653 {
5654         struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5655         struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5656         struct hns_roce_srq_context *srq_context;
5657         struct hns_roce_srq_context *srqc_mask;
5658         struct hns_roce_cmd_mailbox *mailbox;
5659         int ret;
5660
5661         /* Resizing SRQs is not supported yet */
5662         if (srq_attr_mask & IB_SRQ_MAX_WR)
5663                 return -EINVAL;
5664
5665         if (srq_attr_mask & IB_SRQ_LIMIT) {
5666                 if (srq_attr->srq_limit > srq->wqe_cnt)
5667                         return -EINVAL;
5668
5669                 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5670                 if (IS_ERR(mailbox))
5671                         return PTR_ERR(mailbox);
5672
5673                 srq_context = mailbox->buf;
5674                 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5675
5676                 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5677
5678                 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit);
5679                 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL);
5680
5681                 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5682                                         HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn);
5683                 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5684                 if (ret) {
5685                         ibdev_err(&hr_dev->ib_dev,
5686                                   "failed to handle cmd of modifying SRQ, ret = %d.\n",
5687                                   ret);
5688                         return ret;
5689                 }
5690         }
5691
5692         return 0;
5693 }
5694
5695 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
5696 {
5697         struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5698         struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5699         struct hns_roce_srq_context *srq_context;
5700         struct hns_roce_cmd_mailbox *mailbox;
5701         int ret;
5702
5703         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5704         if (IS_ERR(mailbox))
5705                 return PTR_ERR(mailbox);
5706
5707         srq_context = mailbox->buf;
5708         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5709                                 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn);
5710         if (ret) {
5711                 ibdev_err(&hr_dev->ib_dev,
5712                           "failed to process cmd of querying SRQ, ret = %d.\n",
5713                           ret);
5714                 goto out;
5715         }
5716
5717         attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL);
5718         attr->max_wr = srq->wqe_cnt;
5719         attr->max_sge = srq->max_gs - srq->rsv_sge;
5720
5721 out:
5722         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5723         return ret;
5724 }
5725
5726 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
5727 {
5728         struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
5729         struct hns_roce_v2_cq_context *cq_context;
5730         struct hns_roce_cq *hr_cq = to_hr_cq(cq);
5731         struct hns_roce_v2_cq_context *cqc_mask;
5732         struct hns_roce_cmd_mailbox *mailbox;
5733         int ret;
5734
5735         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5736         if (IS_ERR(mailbox))
5737                 return PTR_ERR(mailbox);
5738
5739         cq_context = mailbox->buf;
5740         cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
5741
5742         memset(cqc_mask, 0xff, sizeof(*cqc_mask));
5743
5744         hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count);
5745         hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT);
5746
5747         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5748                 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
5749                         dev_info(hr_dev->dev,
5750                                  "cq_period(%u) reached the upper limit, adjusted to 65.\n",
5751                                  cq_period);
5752                         cq_period = HNS_ROCE_MAX_CQ_PERIOD;
5753                 }
5754                 cq_period *= HNS_ROCE_CLOCK_ADJUST;
5755         }
5756         hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period);
5757         hr_reg_clear(cqc_mask, CQC_CQ_PERIOD);
5758
5759         ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5760                                 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn);
5761         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5762         if (ret)
5763                 ibdev_err(&hr_dev->ib_dev,
5764                           "failed to process cmd when modifying CQ, ret = %d.\n",
5765                           ret);
5766
5767         return ret;
5768 }
5769
5770 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn,
5771                                  void *buffer)
5772 {
5773         struct hns_roce_v2_cq_context *context;
5774         struct hns_roce_cmd_mailbox *mailbox;
5775         int ret;
5776
5777         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5778         if (IS_ERR(mailbox))
5779                 return PTR_ERR(mailbox);
5780
5781         context = mailbox->buf;
5782         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5783                                 HNS_ROCE_CMD_QUERY_CQC, cqn);
5784         if (ret) {
5785                 ibdev_err(&hr_dev->ib_dev,
5786                           "failed to process cmd when querying CQ, ret = %d.\n",
5787                           ret);
5788                 goto err_mailbox;
5789         }
5790
5791         memcpy(buffer, context, sizeof(*context));
5792
5793 err_mailbox:
5794         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5795
5796         return ret;
5797 }
5798
5799 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key,
5800                                  void *buffer)
5801 {
5802         struct hns_roce_v2_mpt_entry *context;
5803         struct hns_roce_cmd_mailbox *mailbox;
5804         int ret;
5805
5806         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5807         if (IS_ERR(mailbox))
5808                 return PTR_ERR(mailbox);
5809
5810         context = mailbox->buf;
5811         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT,
5812                                 key_to_hw_index(key));
5813         if (ret) {
5814                 ibdev_err(&hr_dev->ib_dev,
5815                           "failed to process cmd when querying MPT, ret = %d.\n",
5816                           ret);
5817                 goto err_mailbox;
5818         }
5819
5820         memcpy(buffer, context, sizeof(*context));
5821
5822 err_mailbox:
5823         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5824
5825         return ret;
5826 }
5827
5828 static void hns_roce_irq_work_handle(struct work_struct *work)
5829 {
5830         struct hns_roce_work *irq_work =
5831                                 container_of(work, struct hns_roce_work, work);
5832         struct ib_device *ibdev = &irq_work->hr_dev->ib_dev;
5833
5834         switch (irq_work->event_type) {
5835         case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5836                 ibdev_info(ibdev, "path migrated succeeded.\n");
5837                 break;
5838         case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5839                 ibdev_warn(ibdev, "path migration failed.\n");
5840                 break;
5841         case HNS_ROCE_EVENT_TYPE_COMM_EST:
5842                 break;
5843         case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5844                 ibdev_warn(ibdev, "send queue drained.\n");
5845                 break;
5846         case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5847                 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n",
5848                           irq_work->queue_num, irq_work->sub_type);
5849                 break;
5850         case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5851                 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n",
5852                           irq_work->queue_num);
5853                 break;
5854         case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5855                 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n",
5856                           irq_work->queue_num, irq_work->sub_type);
5857                 break;
5858         case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5859                 ibdev_warn(ibdev, "SRQ limit reach.\n");
5860                 break;
5861         case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5862                 ibdev_warn(ibdev, "SRQ last wqe reach.\n");
5863                 break;
5864         case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5865                 ibdev_err(ibdev, "SRQ catas error.\n");
5866                 break;
5867         case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5868                 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num);
5869                 break;
5870         case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5871                 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num);
5872                 break;
5873         case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5874                 ibdev_warn(ibdev, "DB overflow.\n");
5875                 break;
5876         case HNS_ROCE_EVENT_TYPE_FLR:
5877                 ibdev_warn(ibdev, "function level reset.\n");
5878                 break;
5879         case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5880                 ibdev_err(ibdev, "xrc domain violation error.\n");
5881                 break;
5882         case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5883                 ibdev_err(ibdev, "invalid xrceth error.\n");
5884                 break;
5885         default:
5886                 break;
5887         }
5888
5889         kfree(irq_work);
5890 }
5891
5892 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
5893                                       struct hns_roce_eq *eq, u32 queue_num)
5894 {
5895         struct hns_roce_work *irq_work;
5896
5897         irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
5898         if (!irq_work)
5899                 return;
5900
5901         INIT_WORK(&irq_work->work, hns_roce_irq_work_handle);
5902         irq_work->hr_dev = hr_dev;
5903         irq_work->event_type = eq->event_type;
5904         irq_work->sub_type = eq->sub_type;
5905         irq_work->queue_num = queue_num;
5906         queue_work(hr_dev->irq_workq, &irq_work->work);
5907 }
5908
5909 static void update_eq_db(struct hns_roce_eq *eq)
5910 {
5911         struct hns_roce_dev *hr_dev = eq->hr_dev;
5912         struct hns_roce_v2_db eq_db = {};
5913
5914         if (eq->type_flag == HNS_ROCE_AEQ) {
5915                 hr_reg_write(&eq_db, EQ_DB_CMD,
5916                              eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5917                              HNS_ROCE_EQ_DB_CMD_AEQ :
5918                              HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
5919         } else {
5920                 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn);
5921
5922                 hr_reg_write(&eq_db, EQ_DB_CMD,
5923                              eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5924                              HNS_ROCE_EQ_DB_CMD_CEQ :
5925                              HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
5926         }
5927
5928         hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index);
5929
5930         hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg);
5931 }
5932
5933 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
5934 {
5935         struct hns_roce_aeqe *aeqe;
5936
5937         aeqe = hns_roce_buf_offset(eq->mtr.kmem,
5938                                    (eq->cons_index & (eq->entries - 1)) *
5939                                    eq->eqe_size);
5940
5941         return (hr_reg_read(aeqe, AEQE_OWNER) ^
5942                 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
5943 }
5944
5945 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
5946                                        struct hns_roce_eq *eq)
5947 {
5948         struct device *dev = hr_dev->dev;
5949         struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);
5950         irqreturn_t aeqe_found = IRQ_NONE;
5951         int event_type;
5952         u32 queue_num;
5953         int sub_type;
5954
5955         while (aeqe) {
5956                 /* Make sure we read AEQ entry after we have checked the
5957                  * ownership bit
5958                  */
5959                 dma_rmb();
5960
5961                 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE);
5962                 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE);
5963                 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM);
5964
5965                 switch (event_type) {
5966                 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5967                 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5968                 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5969                 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5970                 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5971                 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5972                 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5973                 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5974                 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5975                 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5976                         hns_roce_qp_event(hr_dev, queue_num, event_type);
5977                         break;
5978                 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5979                 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5980                         hns_roce_srq_event(hr_dev, queue_num, event_type);
5981                         break;
5982                 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5983                 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5984                         hns_roce_cq_event(hr_dev, queue_num, event_type);
5985                         break;
5986                 case HNS_ROCE_EVENT_TYPE_MB:
5987                         hns_roce_cmd_event(hr_dev,
5988                                         le16_to_cpu(aeqe->event.cmd.token),
5989                                         aeqe->event.cmd.status,
5990                                         le64_to_cpu(aeqe->event.cmd.out_param));
5991                         break;
5992                 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5993                 case HNS_ROCE_EVENT_TYPE_FLR:
5994                         break;
5995                 default:
5996                         dev_err(dev, "unhandled event %d on EQ %d at idx %u.\n",
5997                                 event_type, eq->eqn, eq->cons_index);
5998                         break;
5999                 }
6000
6001                 eq->event_type = event_type;
6002                 eq->sub_type = sub_type;
6003                 ++eq->cons_index;
6004                 aeqe_found = IRQ_HANDLED;
6005
6006                 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num);
6007
6008                 aeqe = next_aeqe_sw_v2(eq);
6009         }
6010
6011         update_eq_db(eq);
6012
6013         return IRQ_RETVAL(aeqe_found);
6014 }
6015
6016 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
6017 {
6018         struct hns_roce_ceqe *ceqe;
6019
6020         ceqe = hns_roce_buf_offset(eq->mtr.kmem,
6021                                    (eq->cons_index & (eq->entries - 1)) *
6022                                    eq->eqe_size);
6023
6024         return (hr_reg_read(ceqe, CEQE_OWNER) ^
6025                 !!(eq->cons_index & eq->entries)) ? ceqe : NULL;
6026 }
6027
6028 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
6029                                        struct hns_roce_eq *eq)
6030 {
6031         struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
6032         irqreturn_t ceqe_found = IRQ_NONE;
6033         u32 cqn;
6034
6035         while (ceqe) {
6036                 /* Make sure we read CEQ entry after we have checked the
6037                  * ownership bit
6038                  */
6039                 dma_rmb();
6040
6041                 cqn = hr_reg_read(ceqe, CEQE_CQN);
6042
6043                 hns_roce_cq_completion(hr_dev, cqn);
6044
6045                 ++eq->cons_index;
6046                 ceqe_found = IRQ_HANDLED;
6047
6048                 ceqe = next_ceqe_sw_v2(eq);
6049         }
6050
6051         update_eq_db(eq);
6052
6053         return IRQ_RETVAL(ceqe_found);
6054 }
6055
6056 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
6057 {
6058         struct hns_roce_eq *eq = eq_ptr;
6059         struct hns_roce_dev *hr_dev = eq->hr_dev;
6060         irqreturn_t int_work;
6061
6062         if (eq->type_flag == HNS_ROCE_CEQ)
6063                 /* Completion event interrupt */
6064                 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
6065         else
6066                 /* Asynchronous event interrupt */
6067                 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
6068
6069         return IRQ_RETVAL(int_work);
6070 }
6071
6072 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev,
6073                                             u32 int_st)
6074 {
6075         struct pci_dev *pdev = hr_dev->pci_dev;
6076         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
6077         const struct hnae3_ae_ops *ops = ae_dev->ops;
6078         irqreturn_t int_work = IRQ_NONE;
6079         u32 int_en;
6080
6081         int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
6082
6083         if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
6084                 dev_err(hr_dev->dev, "AEQ overflow!\n");
6085
6086                 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG,
6087                            1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S);
6088
6089                 /* Set reset level for reset_event() */
6090                 if (ops->set_default_reset_request)
6091                         ops->set_default_reset_request(ae_dev,
6092                                                        HNAE3_FUNC_RESET);
6093                 if (ops->reset_event)
6094                         ops->reset_event(pdev, NULL);
6095
6096                 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
6097                 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
6098
6099                 int_work = IRQ_HANDLED;
6100         } else {
6101                 dev_err(hr_dev->dev, "there is no basic abn irq found.\n");
6102         }
6103
6104         return IRQ_RETVAL(int_work);
6105 }
6106
6107 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev,
6108                                struct fmea_ram_ecc *ecc_info)
6109 {
6110         struct hns_roce_cmq_desc desc;
6111         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6112         int ret;
6113
6114         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true);
6115         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6116         if (ret)
6117                 return ret;
6118
6119         ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR);
6120         ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE);
6121         ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG);
6122
6123         return 0;
6124 }
6125
6126 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx)
6127 {
6128         struct hns_roce_cmq_desc desc;
6129         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6130         u32 addr_upper;
6131         u32 addr_low;
6132         int ret;
6133
6134         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true);
6135         hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6136
6137         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6138         if (ret) {
6139                 dev_err(hr_dev->dev,
6140                         "failed to execute cmd to read gmv, ret = %d.\n", ret);
6141                 return ret;
6142         }
6143
6144         addr_low =  hr_reg_read(req, CFG_GMV_BT_BA_L);
6145         addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H);
6146
6147         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
6148         hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low);
6149         hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper);
6150         hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6151
6152         return hns_roce_cmq_send(hr_dev, &desc, 1);
6153 }
6154
6155 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data)
6156 {
6157         if (res_type == ECC_RESOURCE_QPC_TIMER ||
6158             res_type == ECC_RESOURCE_CQC_TIMER ||
6159             res_type == ECC_RESOURCE_SCCC)
6160                 return le64_to_cpu(*data);
6161
6162         return le64_to_cpu(*data) << PAGE_SHIFT;
6163 }
6164
6165 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type,
6166                                u32 index)
6167 {
6168         u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op;
6169         u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op;
6170         struct hns_roce_cmd_mailbox *mailbox;
6171         u64 addr;
6172         int ret;
6173
6174         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6175         if (IS_ERR(mailbox))
6176                 return PTR_ERR(mailbox);
6177
6178         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index);
6179         if (ret) {
6180                 dev_err(hr_dev->dev,
6181                         "failed to execute cmd to read fmea ram, ret = %d.\n",
6182                         ret);
6183                 goto out;
6184         }
6185
6186         addr = fmea_get_ram_res_addr(res_type, mailbox->buf);
6187
6188         ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index);
6189         if (ret)
6190                 dev_err(hr_dev->dev,
6191                         "failed to execute cmd to write fmea ram, ret = %d.\n",
6192                         ret);
6193
6194 out:
6195         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6196         return ret;
6197 }
6198
6199 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev,
6200                                  struct fmea_ram_ecc *ecc_info)
6201 {
6202         u32 res_type = ecc_info->res_type;
6203         u32 index = ecc_info->index;
6204         int ret;
6205
6206         BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT);
6207
6208         if (res_type >= ECC_RESOURCE_COUNT) {
6209                 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n",
6210                         res_type);
6211                 return;
6212         }
6213
6214         if (res_type == ECC_RESOURCE_GMV)
6215                 ret = fmea_recover_gmv(hr_dev, index);
6216         else
6217                 ret = fmea_recover_others(hr_dev, res_type, index);
6218         if (ret)
6219                 dev_err(hr_dev->dev,
6220                         "failed to recover %s, index = %u, ret = %d.\n",
6221                         fmea_ram_res[res_type].name, index, ret);
6222 }
6223
6224 static void fmea_ram_ecc_work(struct work_struct *ecc_work)
6225 {
6226         struct hns_roce_dev *hr_dev =
6227                 container_of(ecc_work, struct hns_roce_dev, ecc_work);
6228         struct fmea_ram_ecc ecc_info = {};
6229
6230         if (fmea_ram_ecc_query(hr_dev, &ecc_info)) {
6231                 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n");
6232                 return;
6233         }
6234
6235         if (!ecc_info.is_ecc_err) {
6236                 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n");
6237                 return;
6238         }
6239
6240         fmea_ram_ecc_recover(hr_dev, &ecc_info);
6241 }
6242
6243 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
6244 {
6245         struct hns_roce_dev *hr_dev = dev_id;
6246         irqreturn_t int_work = IRQ_NONE;
6247         u32 int_st;
6248
6249         int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
6250
6251         if (int_st) {
6252                 int_work = abnormal_interrupt_basic(hr_dev, int_st);
6253         } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
6254                 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work);
6255                 int_work = IRQ_HANDLED;
6256         } else {
6257                 dev_err(hr_dev->dev, "there is no abnormal irq found.\n");
6258         }
6259
6260         return IRQ_RETVAL(int_work);
6261 }
6262
6263 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
6264                                         int eq_num, u32 enable_flag)
6265 {
6266         int i;
6267
6268         for (i = 0; i < eq_num; i++)
6269                 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
6270                            i * EQ_REG_OFFSET, enable_flag);
6271
6272         roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag);
6273         roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag);
6274 }
6275
6276 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn)
6277 {
6278         struct device *dev = hr_dev->dev;
6279         int ret;
6280         u8 cmd;
6281
6282         if (eqn < hr_dev->caps.num_comp_vectors)
6283                 cmd = HNS_ROCE_CMD_DESTROY_CEQC;
6284         else
6285                 cmd = HNS_ROCE_CMD_DESTROY_AEQC;
6286
6287         ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M);
6288         if (ret)
6289                 dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn);
6290 }
6291
6292 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6293 {
6294         hns_roce_mtr_destroy(hr_dev, &eq->mtr);
6295 }
6296
6297 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6298 {
6299         eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
6300         eq->cons_index = 0;
6301         eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
6302         eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
6303         eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
6304         eq->shift = ilog2((unsigned int)eq->entries);
6305 }
6306
6307 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
6308                       void *mb_buf)
6309 {
6310         u64 eqe_ba[MTT_MIN_COUNT] = { 0 };
6311         struct hns_roce_eq_context *eqc;
6312         u64 bt_ba = 0;
6313         int count;
6314
6315         eqc = mb_buf;
6316         memset(eqc, 0, sizeof(struct hns_roce_eq_context));
6317
6318         init_eq_config(hr_dev, eq);
6319
6320         /* if not multi-hop, eqe buffer only use one trunk */
6321         count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT,
6322                                   &bt_ba);
6323         if (count < 1) {
6324                 dev_err(hr_dev->dev, "failed to find EQE mtr\n");
6325                 return -ENOBUFS;
6326         }
6327
6328         hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID);
6329         hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num);
6330         hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore);
6331         hr_reg_write(eqc, EQC_COALESCE, eq->coalesce);
6332         hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st);
6333         hr_reg_write(eqc, EQC_EQN, eq->eqn);
6334         hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT);
6335         hr_reg_write(eqc, EQC_EQE_BA_PG_SZ,
6336                      to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
6337         hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ,
6338                      to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
6339         hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX);
6340         hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt);
6341
6342         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6343                 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
6344                         dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n",
6345                                  eq->eq_period);
6346                         eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD;
6347                 }
6348                 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST;
6349         }
6350
6351         hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period);
6352         hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER);
6353         hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3);
6354         hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35);
6355         hr_reg_write(eqc, EQC_SHIFT, eq->shift);
6356         hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX);
6357         hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12);
6358         hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28);
6359         hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60);
6360         hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX);
6361         hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12);
6362         hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44);
6363         hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE);
6364
6365         return 0;
6366 }
6367
6368 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6369 {
6370         struct hns_roce_buf_attr buf_attr = {};
6371         int err;
6372
6373         if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0)
6374                 eq->hop_num = 0;
6375         else
6376                 eq->hop_num = hr_dev->caps.eqe_hop_num;
6377
6378         buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT;
6379         buf_attr.region[0].size = eq->entries * eq->eqe_size;
6380         buf_attr.region[0].hopnum = eq->hop_num;
6381         buf_attr.region_count = 1;
6382
6383         err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr,
6384                                   hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL,
6385                                   0);
6386         if (err)
6387                 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err);
6388
6389         return err;
6390 }
6391
6392 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
6393                                  struct hns_roce_eq *eq, u8 eq_cmd)
6394 {
6395         struct hns_roce_cmd_mailbox *mailbox;
6396         int ret;
6397
6398         /* Allocate mailbox memory */
6399         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6400         if (IS_ERR(mailbox))
6401                 return PTR_ERR(mailbox);
6402
6403         ret = alloc_eq_buf(hr_dev, eq);
6404         if (ret)
6405                 goto free_cmd_mbox;
6406
6407         ret = config_eqc(hr_dev, eq, mailbox->buf);
6408         if (ret)
6409                 goto err_cmd_mbox;
6410
6411         ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn);
6412         if (ret) {
6413                 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
6414                 goto err_cmd_mbox;
6415         }
6416
6417         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6418
6419         return 0;
6420
6421 err_cmd_mbox:
6422         free_eq_buf(hr_dev, eq);
6423
6424 free_cmd_mbox:
6425         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6426
6427         return ret;
6428 }
6429
6430 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
6431                                   int comp_num, int aeq_num, int other_num)
6432 {
6433         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6434         int i, j;
6435         int ret;
6436
6437         for (i = 0; i < irq_num; i++) {
6438                 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
6439                                                GFP_KERNEL);
6440                 if (!hr_dev->irq_names[i]) {
6441                         ret = -ENOMEM;
6442                         goto err_kzalloc_failed;
6443                 }
6444         }
6445
6446         /* irq contains: abnormal + AEQ + CEQ */
6447         for (j = 0; j < other_num; j++)
6448                 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6449                          "hns-abn-%d", j);
6450
6451         for (j = other_num; j < (other_num + aeq_num); j++)
6452                 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6453                          "hns-aeq-%d", j - other_num);
6454
6455         for (j = (other_num + aeq_num); j < irq_num; j++)
6456                 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6457                          "hns-ceq-%d", j - other_num - aeq_num);
6458
6459         for (j = 0; j < irq_num; j++) {
6460                 if (j < other_num)
6461                         ret = request_irq(hr_dev->irq[j],
6462                                           hns_roce_v2_msix_interrupt_abn,
6463                                           0, hr_dev->irq_names[j], hr_dev);
6464
6465                 else if (j < (other_num + comp_num))
6466                         ret = request_irq(eq_table->eq[j - other_num].irq,
6467                                           hns_roce_v2_msix_interrupt_eq,
6468                                           0, hr_dev->irq_names[j + aeq_num],
6469                                           &eq_table->eq[j - other_num]);
6470                 else
6471                         ret = request_irq(eq_table->eq[j - other_num].irq,
6472                                           hns_roce_v2_msix_interrupt_eq,
6473                                           0, hr_dev->irq_names[j - comp_num],
6474                                           &eq_table->eq[j - other_num]);
6475                 if (ret) {
6476                         dev_err(hr_dev->dev, "request irq error!\n");
6477                         goto err_request_failed;
6478                 }
6479         }
6480
6481         return 0;
6482
6483 err_request_failed:
6484         for (j -= 1; j >= 0; j--)
6485                 if (j < other_num)
6486                         free_irq(hr_dev->irq[j], hr_dev);
6487                 else
6488                         free_irq(eq_table->eq[j - other_num].irq,
6489                                  &eq_table->eq[j - other_num]);
6490
6491 err_kzalloc_failed:
6492         for (i -= 1; i >= 0; i--)
6493                 kfree(hr_dev->irq_names[i]);
6494
6495         return ret;
6496 }
6497
6498 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev)
6499 {
6500         int irq_num;
6501         int eq_num;
6502         int i;
6503
6504         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6505         irq_num = eq_num + hr_dev->caps.num_other_vectors;
6506
6507         for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
6508                 free_irq(hr_dev->irq[i], hr_dev);
6509
6510         for (i = 0; i < eq_num; i++)
6511                 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
6512
6513         for (i = 0; i < irq_num; i++)
6514                 kfree(hr_dev->irq_names[i]);
6515 }
6516
6517 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
6518 {
6519         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6520         struct device *dev = hr_dev->dev;
6521         struct hns_roce_eq *eq;
6522         int other_num;
6523         int comp_num;
6524         int aeq_num;
6525         int irq_num;
6526         int eq_num;
6527         u8 eq_cmd;
6528         int ret;
6529         int i;
6530
6531         other_num = hr_dev->caps.num_other_vectors;
6532         comp_num = hr_dev->caps.num_comp_vectors;
6533         aeq_num = hr_dev->caps.num_aeq_vectors;
6534
6535         eq_num = comp_num + aeq_num;
6536         irq_num = eq_num + other_num;
6537
6538         eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
6539         if (!eq_table->eq)
6540                 return -ENOMEM;
6541
6542         /* create eq */
6543         for (i = 0; i < eq_num; i++) {
6544                 eq = &eq_table->eq[i];
6545                 eq->hr_dev = hr_dev;
6546                 eq->eqn = i;
6547                 if (i < comp_num) {
6548                         /* CEQ */
6549                         eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
6550                         eq->type_flag = HNS_ROCE_CEQ;
6551                         eq->entries = hr_dev->caps.ceqe_depth;
6552                         eq->eqe_size = hr_dev->caps.ceqe_size;
6553                         eq->irq = hr_dev->irq[i + other_num + aeq_num];
6554                         eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
6555                         eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
6556                 } else {
6557                         /* AEQ */
6558                         eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
6559                         eq->type_flag = HNS_ROCE_AEQ;
6560                         eq->entries = hr_dev->caps.aeqe_depth;
6561                         eq->eqe_size = hr_dev->caps.aeqe_size;
6562                         eq->irq = hr_dev->irq[i - comp_num + other_num];
6563                         eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
6564                         eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
6565                 }
6566
6567                 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
6568                 if (ret) {
6569                         dev_err(dev, "failed to create eq.\n");
6570                         goto err_create_eq_fail;
6571                 }
6572         }
6573
6574         INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work);
6575
6576         hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0);
6577         if (!hr_dev->irq_workq) {
6578                 dev_err(dev, "failed to create irq workqueue.\n");
6579                 ret = -ENOMEM;
6580                 goto err_create_eq_fail;
6581         }
6582
6583         ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num,
6584                                      other_num);
6585         if (ret) {
6586                 dev_err(dev, "failed to request irq.\n");
6587                 goto err_request_irq_fail;
6588         }
6589
6590         /* enable irq */
6591         hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
6592
6593         return 0;
6594
6595 err_request_irq_fail:
6596         destroy_workqueue(hr_dev->irq_workq);
6597
6598 err_create_eq_fail:
6599         for (i -= 1; i >= 0; i--)
6600                 free_eq_buf(hr_dev, &eq_table->eq[i]);
6601         kfree(eq_table->eq);
6602
6603         return ret;
6604 }
6605
6606 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
6607 {
6608         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6609         int eq_num;
6610         int i;
6611
6612         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6613
6614         /* Disable irq */
6615         hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
6616
6617         __hns_roce_free_irq(hr_dev);
6618         destroy_workqueue(hr_dev->irq_workq);
6619
6620         for (i = 0; i < eq_num; i++) {
6621                 hns_roce_v2_destroy_eqc(hr_dev, i);
6622
6623                 free_eq_buf(hr_dev, &eq_table->eq[i]);
6624         }
6625
6626         kfree(eq_table->eq);
6627 }
6628
6629 static const struct ib_device_ops hns_roce_v2_dev_ops = {
6630         .destroy_qp = hns_roce_v2_destroy_qp,
6631         .modify_cq = hns_roce_v2_modify_cq,
6632         .poll_cq = hns_roce_v2_poll_cq,
6633         .post_recv = hns_roce_v2_post_recv,
6634         .post_send = hns_roce_v2_post_send,
6635         .query_qp = hns_roce_v2_query_qp,
6636         .req_notify_cq = hns_roce_v2_req_notify_cq,
6637 };
6638
6639 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
6640         .modify_srq = hns_roce_v2_modify_srq,
6641         .post_srq_recv = hns_roce_v2_post_srq_recv,
6642         .query_srq = hns_roce_v2_query_srq,
6643 };
6644
6645 static const struct hns_roce_hw hns_roce_hw_v2 = {
6646         .cmq_init = hns_roce_v2_cmq_init,
6647         .cmq_exit = hns_roce_v2_cmq_exit,
6648         .hw_profile = hns_roce_v2_profile,
6649         .hw_init = hns_roce_v2_init,
6650         .hw_exit = hns_roce_v2_exit,
6651         .post_mbox = v2_post_mbox,
6652         .poll_mbox_done = v2_poll_mbox_done,
6653         .chk_mbox_avail = v2_chk_mbox_is_avail,
6654         .set_gid = hns_roce_v2_set_gid,
6655         .set_mac = hns_roce_v2_set_mac,
6656         .write_mtpt = hns_roce_v2_write_mtpt,
6657         .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
6658         .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
6659         .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
6660         .write_cqc = hns_roce_v2_write_cqc,
6661         .set_hem = hns_roce_v2_set_hem,
6662         .clear_hem = hns_roce_v2_clear_hem,
6663         .modify_qp = hns_roce_v2_modify_qp,
6664         .dereg_mr = hns_roce_v2_dereg_mr,
6665         .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
6666         .init_eq = hns_roce_v2_init_eq_table,
6667         .cleanup_eq = hns_roce_v2_cleanup_eq_table,
6668         .write_srqc = hns_roce_v2_write_srqc,
6669         .query_cqc = hns_roce_v2_query_cqc,
6670         .query_qpc = hns_roce_v2_query_qpc,
6671         .query_mpt = hns_roce_v2_query_mpt,
6672         .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
6673         .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
6674 };
6675
6676 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
6677         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
6678         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
6679         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
6680         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
6681         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
6682         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
6683         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
6684          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
6685         /* required last entry */
6686         {0, }
6687 };
6688
6689 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
6690
6691 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
6692                                   struct hnae3_handle *handle)
6693 {
6694         struct hns_roce_v2_priv *priv = hr_dev->priv;
6695         const struct pci_device_id *id;
6696         int i;
6697
6698         hr_dev->pci_dev = handle->pdev;
6699         id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
6700         hr_dev->is_vf = id->driver_data;
6701         hr_dev->dev = &handle->pdev->dev;
6702         hr_dev->hw = &hns_roce_hw_v2;
6703         hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
6704         hr_dev->odb_offset = hr_dev->sdb_offset;
6705
6706         /* Get info from NIC driver. */
6707         hr_dev->reg_base = handle->rinfo.roce_io_base;
6708         hr_dev->mem_base = handle->rinfo.roce_mem_base;
6709         hr_dev->caps.num_ports = 1;
6710         hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
6711         hr_dev->iboe.phy_port[0] = 0;
6712
6713         addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
6714                             hr_dev->iboe.netdevs[0]->dev_addr);
6715
6716         for (i = 0; i < handle->rinfo.num_vectors; i++)
6717                 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
6718                                                 i + handle->rinfo.base_vector);
6719
6720         /* cmd issue mode: 0 is poll, 1 is event */
6721         hr_dev->cmd_mod = 1;
6722         hr_dev->loop_idc = 0;
6723
6724         hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
6725         priv->handle = handle;
6726 }
6727
6728 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6729 {
6730         struct hns_roce_dev *hr_dev;
6731         int ret;
6732
6733         hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
6734         if (!hr_dev)
6735                 return -ENOMEM;
6736
6737         hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
6738         if (!hr_dev->priv) {
6739                 ret = -ENOMEM;
6740                 goto error_failed_kzalloc;
6741         }
6742
6743         hns_roce_hw_v2_get_cfg(hr_dev, handle);
6744
6745         ret = hns_roce_init(hr_dev);
6746         if (ret) {
6747                 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6748                 goto error_failed_cfg;
6749         }
6750
6751         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6752                 ret = free_mr_init(hr_dev);
6753                 if (ret) {
6754                         dev_err(hr_dev->dev, "failed to init free mr!\n");
6755                         goto error_failed_roce_init;
6756                 }
6757         }
6758
6759         handle->priv = hr_dev;
6760
6761         return 0;
6762
6763 error_failed_roce_init:
6764         hns_roce_exit(hr_dev);
6765
6766 error_failed_cfg:
6767         kfree(hr_dev->priv);
6768
6769 error_failed_kzalloc:
6770         ib_dealloc_device(&hr_dev->ib_dev);
6771
6772         return ret;
6773 }
6774
6775 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6776                                            bool reset)
6777 {
6778         struct hns_roce_dev *hr_dev = handle->priv;
6779
6780         if (!hr_dev)
6781                 return;
6782
6783         handle->priv = NULL;
6784
6785         hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
6786         hns_roce_handle_device_err(hr_dev);
6787
6788         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
6789                 free_mr_exit(hr_dev);
6790
6791         hns_roce_exit(hr_dev);
6792         kfree(hr_dev->priv);
6793         ib_dealloc_device(&hr_dev->ib_dev);
6794 }
6795
6796 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6797 {
6798         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
6799         const struct pci_device_id *id;
6800         struct device *dev = &handle->pdev->dev;
6801         int ret;
6802
6803         handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
6804
6805         if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
6806                 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6807                 goto reset_chk_err;
6808         }
6809
6810         id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
6811         if (!id)
6812                 return 0;
6813
6814         if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08)
6815                 return 0;
6816
6817         ret = __hns_roce_hw_v2_init_instance(handle);
6818         if (ret) {
6819                 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6820                 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
6821                 if (ops->ae_dev_resetting(handle) ||
6822                     ops->get_hw_reset_stat(handle))
6823                         goto reset_chk_err;
6824                 else
6825                         return ret;
6826         }
6827
6828         handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
6829
6830         return 0;
6831
6832 reset_chk_err:
6833         dev_err(dev, "Device is busy in resetting state.\n"
6834                      "please retry later.\n");
6835
6836         return -EBUSY;
6837 }
6838
6839 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6840                                            bool reset)
6841 {
6842         if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
6843                 return;
6844
6845         handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
6846
6847         __hns_roce_hw_v2_uninit_instance(handle, reset);
6848
6849         handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6850 }
6851 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
6852 {
6853         struct hns_roce_dev *hr_dev;
6854
6855         if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
6856                 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6857                 return 0;
6858         }
6859
6860         handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
6861         clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6862
6863         hr_dev = handle->priv;
6864         if (!hr_dev)
6865                 return 0;
6866
6867         hr_dev->active = false;
6868         hr_dev->dis_db = true;
6869         hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN;
6870
6871         return 0;
6872 }
6873
6874 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
6875 {
6876         struct device *dev = &handle->pdev->dev;
6877         int ret;
6878
6879         if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
6880                                &handle->rinfo.state)) {
6881                 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6882                 return 0;
6883         }
6884
6885         handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
6886
6887         dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
6888         ret = __hns_roce_hw_v2_init_instance(handle);
6889         if (ret) {
6890                 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
6891                  * callback function, RoCE Engine reinitialize. If RoCE reinit
6892                  * failed, we should inform NIC driver.
6893                  */
6894                 handle->priv = NULL;
6895                 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
6896         } else {
6897                 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6898                 dev_info(dev, "reset done, RoCE client reinit finished.\n");
6899         }
6900
6901         return ret;
6902 }
6903
6904 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
6905 {
6906         if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
6907                 return 0;
6908
6909         handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
6910         dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
6911         msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
6912         __hns_roce_hw_v2_uninit_instance(handle, false);
6913
6914         return 0;
6915 }
6916
6917 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
6918                                        enum hnae3_reset_notify_type type)
6919 {
6920         int ret = 0;
6921
6922         switch (type) {
6923         case HNAE3_DOWN_CLIENT:
6924                 ret = hns_roce_hw_v2_reset_notify_down(handle);
6925                 break;
6926         case HNAE3_INIT_CLIENT:
6927                 ret = hns_roce_hw_v2_reset_notify_init(handle);
6928                 break;
6929         case HNAE3_UNINIT_CLIENT:
6930                 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
6931                 break;
6932         default:
6933                 break;
6934         }
6935
6936         return ret;
6937 }
6938
6939 static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
6940         .init_instance = hns_roce_hw_v2_init_instance,
6941         .uninit_instance = hns_roce_hw_v2_uninit_instance,
6942         .reset_notify = hns_roce_hw_v2_reset_notify,
6943 };
6944
6945 static struct hnae3_client hns_roce_hw_v2_client = {
6946         .name = "hns_roce_hw_v2",
6947         .type = HNAE3_CLIENT_ROCE,
6948         .ops = &hns_roce_hw_v2_ops,
6949 };
6950
6951 static int __init hns_roce_hw_v2_init(void)
6952 {
6953         return hnae3_register_client(&hns_roce_hw_v2_client);
6954 }
6955
6956 static void __exit hns_roce_hw_v2_exit(void)
6957 {
6958         hnae3_unregister_client(&hns_roce_hw_v2_client);
6959 }
6960
6961 module_init(hns_roce_hw_v2_init);
6962 module_exit(hns_roce_hw_v2_exit);
6963
6964 MODULE_LICENSE("Dual BSD/GPL");
6965 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
6966 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
6967 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
6968 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");