2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
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7 * General Public License (GPL) Version 2, available from the file
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34 #ifndef _HNS_ROCE_HEM_H
35 #define _HNS_ROCE_HEM_H
37 #define HW_SYNC_TIMEOUT_MSECS 500
38 #define HW_SYNC_SLEEP_TIME_INTERVAL 20
39 #define BT_CMD_SYNC_SHIFT 31
42 /* MAP HEM(Hardware Entry Memory) */
55 #define HNS_ROCE_HEM_CHUNK_LEN \
56 ((256 - sizeof(struct list_head) - 2 * sizeof(int)) / \
57 (sizeof(struct scatterlist)))
59 #define check_whether_bt_num_3(type, hop_num) \
60 (type < HEM_TYPE_MTT && hop_num == 2)
62 #define check_whether_bt_num_2(type, hop_num) \
63 ((type < HEM_TYPE_MTT && hop_num == 1) || \
64 (type >= HEM_TYPE_MTT && hop_num == 2))
66 #define check_whether_bt_num_1(type, hop_num) \
67 ((type < HEM_TYPE_MTT && hop_num == HNS_ROCE_HOP_NUM_0) || \
68 (type >= HEM_TYPE_MTT && hop_num == 1) || \
69 (type >= HEM_TYPE_MTT && hop_num == HNS_ROCE_HOP_NUM_0))
72 HNS_ROCE_HEM_PAGE_SHIFT = 12,
73 HNS_ROCE_HEM_PAGE_SIZE = 1 << HNS_ROCE_HEM_PAGE_SHIFT,
76 struct hns_roce_hem_chunk {
77 struct list_head list;
80 struct scatterlist mem[HNS_ROCE_HEM_CHUNK_LEN];
84 struct list_head chunk_list;
88 struct hns_roce_hem_iter {
89 struct hns_roce_hem *hem;
90 struct hns_roce_hem_chunk *chunk;
94 struct hns_roce_hem_mhop {
99 u32 l0_idx;/* level 0 base address table index */
100 u32 l1_idx;/* level 1 base address table index */
101 u32 l2_idx;/* level 2 base address table index */
104 void hns_roce_free_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem *hem);
105 int hns_roce_table_get(struct hns_roce_dev *hr_dev,
106 struct hns_roce_hem_table *table, unsigned long obj);
107 void hns_roce_table_put(struct hns_roce_dev *hr_dev,
108 struct hns_roce_hem_table *table, unsigned long obj);
109 void *hns_roce_table_find(struct hns_roce_dev *hr_dev,
110 struct hns_roce_hem_table *table, unsigned long obj,
111 dma_addr_t *dma_handle);
112 int hns_roce_table_get_range(struct hns_roce_dev *hr_dev,
113 struct hns_roce_hem_table *table,
114 unsigned long start, unsigned long end);
115 void hns_roce_table_put_range(struct hns_roce_dev *hr_dev,
116 struct hns_roce_hem_table *table,
117 unsigned long start, unsigned long end);
118 int hns_roce_init_hem_table(struct hns_roce_dev *hr_dev,
119 struct hns_roce_hem_table *table, u32 type,
120 unsigned long obj_size, unsigned long nobj,
122 void hns_roce_cleanup_hem_table(struct hns_roce_dev *hr_dev,
123 struct hns_roce_hem_table *table);
124 void hns_roce_cleanup_hem(struct hns_roce_dev *hr_dev);
125 int hns_roce_calc_hem_mhop(struct hns_roce_dev *hr_dev,
126 struct hns_roce_hem_table *table, unsigned long *obj,
127 struct hns_roce_hem_mhop *mhop);
128 bool hns_roce_check_whether_mhop(struct hns_roce_dev *hr_dev, u32 type);
130 static inline void hns_roce_hem_first(struct hns_roce_hem *hem,
131 struct hns_roce_hem_iter *iter)
134 iter->chunk = list_empty(&hem->chunk_list) ? NULL :
135 list_entry(hem->chunk_list.next,
136 struct hns_roce_hem_chunk, list);
140 static inline int hns_roce_hem_last(struct hns_roce_hem_iter *iter)
145 static inline void hns_roce_hem_next(struct hns_roce_hem_iter *iter)
147 if (++iter->page_idx >= iter->chunk->nsg) {
148 if (iter->chunk->list.next == &iter->hem->chunk_list) {
153 iter->chunk = list_entry(iter->chunk->list.next,
154 struct hns_roce_hem_chunk, list);
159 static inline dma_addr_t hns_roce_hem_addr(struct hns_roce_hem_iter *iter)
161 return sg_dma_address(&iter->chunk->mem[iter->page_idx]);
164 #endif /*_HNS_ROCE_HEM_H*/