4 * Copyright(c) 2015-2018 Intel Corporation.
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
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15 * This program is distributed in the hope that it will be useful, but
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50 #include <linux/interrupt.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/mutex.h>
54 #include <linux/list.h>
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/idr.h>
60 #include <linux/completion.h>
61 #include <linux/kref.h>
62 #include <linux/sched.h>
63 #include <linux/cdev.h>
64 #include <linux/delay.h>
65 #include <linux/kthread.h>
66 #include <linux/i2c.h>
67 #include <linux/i2c-algo-bit.h>
68 #include <rdma/ib_hdrs.h>
69 #include <rdma/opa_addr.h>
70 #include <linux/rhashtable.h>
71 #include <linux/netdevice.h>
72 #include <rdma/rdma_vt.h>
74 #include "chip_registers.h"
84 /* bumped 1 from s/w major version of TrueScale */
85 #define HFI1_CHIP_VERS_MAJ 3U
87 /* don't care about this except printing */
88 #define HFI1_CHIP_VERS_MIN 0U
90 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
91 #define HFI1_OUI 0x001175
92 #define HFI1_OUI_LSB 40
94 #define DROP_PACKET_OFF 0
95 #define DROP_PACKET_ON 1
97 #define NEIGHBOR_TYPE_HFI 0
98 #define NEIGHBOR_TYPE_SWITCH 1
100 extern unsigned long hfi1_cap_mask;
101 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
102 #define HFI1_CAP_UGET_MASK(mask, cap) \
103 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap)
104 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap))
105 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap))
106 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap))
107 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap))
108 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \
110 /* Offline Disabled Reason is 4-bits */
111 #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON)
114 * Control context is always 0 and handles the error packets.
115 * It also handles the VL15 and multicast packets.
117 #define HFI1_CTRL_CTXT 0
120 * Driver context will store software counters for each of the events
121 * associated with these status registers
123 #define NUM_CCE_ERR_STATUS_COUNTERS 41
124 #define NUM_RCV_ERR_STATUS_COUNTERS 64
125 #define NUM_MISC_ERR_STATUS_COUNTERS 13
126 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36
127 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4
128 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64
129 #define NUM_SEND_ERR_STATUS_COUNTERS 3
130 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5
131 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24
134 * per driver stats, either not device nor port-specific, or
135 * summed over all of the devices and ports.
136 * They are described by name via ipathfs filesystem, so layout
137 * and number of elements can change without breaking compatibility.
138 * If members are added or deleted hfi1_statnames[] in debugfs.c must
141 struct hfi1_ib_stats {
142 __u64 sps_ints; /* number of interrupts handled */
143 __u64 sps_errints; /* number of error interrupts */
144 __u64 sps_txerrs; /* tx-related packet errors */
145 __u64 sps_rcverrs; /* non-crc rcv packet errors */
146 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
147 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
148 __u64 sps_ctxts; /* number of contexts currently open */
149 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
154 extern struct hfi1_ib_stats hfi1_stats;
155 extern const struct pci_error_handlers hfi1_pci_err_handler;
158 * First-cut criterion for "device is active" is
159 * two thousand dwords combined Tx, Rx traffic per
160 * 5-second interval. SMA packets are 64 dwords,
161 * and occur "a few per second", presumably each way.
163 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000)
166 * Below contains all data related to a single context (formerly called port).
169 struct hfi1_opcode_stats_perctx;
171 struct ctxt_eager_bufs {
172 struct eager_buffer {
181 u32 size; /* total size of eager buffers */
182 u32 rcvtid_size; /* size of each eager rcv tid */
183 u16 count; /* size of buffers array */
184 u16 numbufs; /* number of buffers allocated */
185 u16 alloced; /* number of rcvarray entries used */
186 u16 threshold; /* head update threshold */
190 struct list_head list;
194 typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet);
195 struct hfi1_ctxtdata {
196 /* rcvhdrq base, needs mmap before useful */
198 /* kernel virtual address where hdrqtail is updated */
199 volatile __le64 *rcvhdrtail_kvaddr;
200 /* so functions that need physical port can get it easily */
201 struct hfi1_pportdata *ppd;
202 /* so file ops can get at unit */
203 struct hfi1_devdata *dd;
204 /* this receive context's assigned PIO ACK send context */
205 struct send_context *sc;
206 /* per context recv functions */
207 const rhf_rcv_function_ptr *rhf_rcv_function_map;
209 * The interrupt handler for a particular receive context can vary
210 * throughout it's lifetime. This is not a lock protected data member so
211 * it must be updated atomically and the prev and new value must always
212 * be valid. Worst case is we process an extra interrupt and up to 64
213 * packets with the wrong interrupt handler.
215 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded);
216 /* verbs rx_stats per rcd */
217 struct hfi1_opcode_stats_perctx *opstats;
218 /* clear interrupt mask */
220 /* ctxt rcvhdrq head offset */
222 /* number of rcvhdrq entries */
224 u8 ireg; /* clear interrupt register */
225 /* receive packet sequence counter */
227 /* size of each of the rcvhdrq entries */
229 /* offset of RHF within receive header entry */
231 /* dynamic receive available interrupt timeout */
233 /* Indicates that this is vnic context */
235 /* vnic queue index this context is mapped to */
237 /* Is ASPM interrupt supported for this context */
238 bool aspm_intr_supported;
239 /* ASPM state (enabled/disabled) for this context */
241 /* Is ASPM processing enabled for this context (in intr context) */
242 bool aspm_intr_enable;
243 struct ctxt_eager_bufs egrbufs;
244 /* QPs waiting for context processing */
245 struct list_head qp_wait_list;
246 /* tid allocation lists */
247 struct exp_tid_set tid_group_list;
248 struct exp_tid_set tid_used_list;
249 struct exp_tid_set tid_full_list;
251 /* Timer for re-enabling ASPM if interrupt activity quiets down */
252 struct timer_list aspm_timer;
253 /* per-context configuration flags */
255 /* array of tid_groups */
256 struct tid_group *groups;
257 /* mmap of hdrq, must fit in 44 bits */
258 dma_addr_t rcvhdrq_dma;
259 dma_addr_t rcvhdrqtailaddr_dma;
260 /* Last interrupt timestamp */
261 ktime_t aspm_ts_last_intr;
262 /* Last timestamp at which we scheduled a timer for this context */
263 ktime_t aspm_ts_timer_sched;
264 /* Lock to serialize between intr, timer intr and user threads */
265 spinlock_t aspm_lock;
266 /* Reference count the base context usage */
268 /* numa node of this context */
270 /* associated msix interrupt. */
274 /* number of RcvArray groups for this context. */
275 u16 rcv_array_groups;
276 /* index of first eager TID entry. */
278 /* number of expected TID entries */
280 /* index of first expected TID entry. */
282 /* Device context index */
285 /* PSM Specific fields */
286 /* lock protecting all Expected TID data */
287 struct mutex exp_mutex;
288 /* when waiting for rcv or pioavail */
289 wait_queue_head_t wait;
292 /* same size as task_struct .comm[], command that opened context */
293 char comm[TASK_COMM_LEN];
294 /* Bitmask of in use context(s) */
295 DECLARE_BITMAP(in_use_ctxts, HFI1_MAX_SHARED_CTXTS);
296 /* per-context event flags for fileops/intr communication */
297 unsigned long event_flags;
298 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
299 void *subctxt_uregbase;
300 /* An array of pages for the eager receive buffers * N */
301 void *subctxt_rcvegrbuf;
302 /* An array of pages for the eager header queue entries * N */
303 void *subctxt_rcvhdr_base;
304 /* total number of polled urgent packets */
306 /* saved total number of polled urgent packets for poll edge trigger */
308 /* Type of packets or conditions we want to poll for */
310 /* non-zero if ctxt is being shared. */
312 /* The version of the library which opened this ctxt */
315 * non-zero if ctxt can be shared, and defines the maximum number of
316 * sub-contexts for this device context.
323 * rcvhdrq_size - return total size in bytes for header queue
324 * @rcd: the receive context
326 * rcvhdrqentsize is in DWs, so we have to convert to bytes
329 static inline u32 rcvhdrq_size(struct hfi1_ctxtdata *rcd)
331 return PAGE_ALIGN(rcd->rcvhdrq_cnt *
332 rcd->rcvhdrqentsize * sizeof(u32));
336 * Represents a single packet at a high level. Put commonly computed things in
337 * here so we do not have to keep doing them over and over. The rule of thumb is
338 * if something is used one time to derive some value, store that something in
339 * here. If it is used multiple times, then store the result of that derivation
346 struct hfi1_ctxtdata *rcd;
349 struct ib_other_headers *ohdr;
351 struct opa_16b_mgmt *mgmt;
374 #define HFI1_PKT_TYPE_9B 0
375 #define HFI1_PKT_TYPE_16B 1
380 #define OPA_16B_L4_MASK 0xFFull
381 #define OPA_16B_SC_MASK 0x1F00000ull
382 #define OPA_16B_SC_SHIFT 20
383 #define OPA_16B_LID_MASK 0xFFFFFull
384 #define OPA_16B_DLID_MASK 0xF000ull
385 #define OPA_16B_DLID_SHIFT 20
386 #define OPA_16B_DLID_HIGH_SHIFT 12
387 #define OPA_16B_SLID_MASK 0xF00ull
388 #define OPA_16B_SLID_SHIFT 20
389 #define OPA_16B_SLID_HIGH_SHIFT 8
390 #define OPA_16B_BECN_MASK 0x80000000ull
391 #define OPA_16B_BECN_SHIFT 31
392 #define OPA_16B_FECN_MASK 0x10000000ull
393 #define OPA_16B_FECN_SHIFT 28
394 #define OPA_16B_L2_MASK 0x60000000ull
395 #define OPA_16B_L2_SHIFT 29
396 #define OPA_16B_PKEY_MASK 0xFFFF0000ull
397 #define OPA_16B_PKEY_SHIFT 16
398 #define OPA_16B_LEN_MASK 0x7FF00000ull
399 #define OPA_16B_LEN_SHIFT 20
400 #define OPA_16B_RC_MASK 0xE000000ull
401 #define OPA_16B_RC_SHIFT 25
402 #define OPA_16B_AGE_MASK 0xFF0000ull
403 #define OPA_16B_AGE_SHIFT 16
404 #define OPA_16B_ENTROPY_MASK 0xFFFFull
407 * OPA 16B L2/L4 Encodings
409 #define OPA_16B_L4_9B 0x00
410 #define OPA_16B_L2_TYPE 0x02
411 #define OPA_16B_L4_FM 0x08
412 #define OPA_16B_L4_IB_LOCAL 0x09
413 #define OPA_16B_L4_IB_GLOBAL 0x0A
414 #define OPA_16B_L4_ETHR OPA_VNIC_L4_ETHR
419 #define OPA_16B_L4_FM_PAD 3 /* fixed 3B pad */
420 #define OPA_16B_L4_FM_HLEN 24 /* 16B(16) + L4_FM(8) */
422 static inline u8 hfi1_16B_get_l4(struct hfi1_16b_header *hdr)
424 return (u8)(hdr->lrh[2] & OPA_16B_L4_MASK);
427 static inline u8 hfi1_16B_get_sc(struct hfi1_16b_header *hdr)
429 return (u8)((hdr->lrh[1] & OPA_16B_SC_MASK) >> OPA_16B_SC_SHIFT);
432 static inline u32 hfi1_16B_get_dlid(struct hfi1_16b_header *hdr)
434 return (u32)((hdr->lrh[1] & OPA_16B_LID_MASK) |
435 (((hdr->lrh[2] & OPA_16B_DLID_MASK) >>
436 OPA_16B_DLID_HIGH_SHIFT) << OPA_16B_DLID_SHIFT));
439 static inline u32 hfi1_16B_get_slid(struct hfi1_16b_header *hdr)
441 return (u32)((hdr->lrh[0] & OPA_16B_LID_MASK) |
442 (((hdr->lrh[2] & OPA_16B_SLID_MASK) >>
443 OPA_16B_SLID_HIGH_SHIFT) << OPA_16B_SLID_SHIFT));
446 static inline u8 hfi1_16B_get_becn(struct hfi1_16b_header *hdr)
448 return (u8)((hdr->lrh[0] & OPA_16B_BECN_MASK) >> OPA_16B_BECN_SHIFT);
451 static inline u8 hfi1_16B_get_fecn(struct hfi1_16b_header *hdr)
453 return (u8)((hdr->lrh[1] & OPA_16B_FECN_MASK) >> OPA_16B_FECN_SHIFT);
456 static inline u8 hfi1_16B_get_l2(struct hfi1_16b_header *hdr)
458 return (u8)((hdr->lrh[1] & OPA_16B_L2_MASK) >> OPA_16B_L2_SHIFT);
461 static inline u16 hfi1_16B_get_pkey(struct hfi1_16b_header *hdr)
463 return (u16)((hdr->lrh[2] & OPA_16B_PKEY_MASK) >> OPA_16B_PKEY_SHIFT);
466 static inline u8 hfi1_16B_get_rc(struct hfi1_16b_header *hdr)
468 return (u8)((hdr->lrh[1] & OPA_16B_RC_MASK) >> OPA_16B_RC_SHIFT);
471 static inline u8 hfi1_16B_get_age(struct hfi1_16b_header *hdr)
473 return (u8)((hdr->lrh[3] & OPA_16B_AGE_MASK) >> OPA_16B_AGE_SHIFT);
476 static inline u16 hfi1_16B_get_len(struct hfi1_16b_header *hdr)
478 return (u16)((hdr->lrh[0] & OPA_16B_LEN_MASK) >> OPA_16B_LEN_SHIFT);
481 static inline u16 hfi1_16B_get_entropy(struct hfi1_16b_header *hdr)
483 return (u16)(hdr->lrh[3] & OPA_16B_ENTROPY_MASK);
486 #define OPA_16B_MAKE_QW(low_dw, high_dw) (((u64)(high_dw) << 32) | (low_dw))
491 #define OPA_16B_BTH_PAD_MASK 7
492 static inline u8 hfi1_16B_bth_get_pad(struct ib_other_headers *ohdr)
494 return (u8)((be32_to_cpu(ohdr->bth[0]) >> IB_BTH_PAD_SHIFT) &
495 OPA_16B_BTH_PAD_MASK);
501 #define OPA_16B_MGMT_QPN_MASK 0xFFFFFF
502 static inline u32 hfi1_16B_get_dest_qpn(struct opa_16b_mgmt *mgmt)
504 return be32_to_cpu(mgmt->dest_qpn) & OPA_16B_MGMT_QPN_MASK;
507 static inline u32 hfi1_16B_get_src_qpn(struct opa_16b_mgmt *mgmt)
509 return be32_to_cpu(mgmt->src_qpn) & OPA_16B_MGMT_QPN_MASK;
512 static inline void hfi1_16B_set_qpn(struct opa_16b_mgmt *mgmt,
513 u32 dest_qp, u32 src_qp)
515 mgmt->dest_qpn = cpu_to_be32(dest_qp & OPA_16B_MGMT_QPN_MASK);
516 mgmt->src_qpn = cpu_to_be32(src_qp & OPA_16B_MGMT_QPN_MASK);
519 struct rvt_sge_state;
522 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
523 * Mostly for MADs that set or query link parameters, also ipath
526 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
527 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */
528 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */
529 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */
530 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
531 #define HFI1_IB_CFG_SPD 5 /* current Link spd */
532 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
533 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
534 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
535 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
536 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */
537 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
538 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
539 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
540 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
541 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
542 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */
543 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */
544 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19
545 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
546 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */
549 * HFI or Host Link States
551 * These describe the states the driver thinks the logical and physical
552 * states are in. Used as an argument to set_link_state(). Implemented
553 * as bits for easy multi-state checking. The actual state can only be
556 #define __HLS_UP_INIT_BP 0
557 #define __HLS_UP_ARMED_BP 1
558 #define __HLS_UP_ACTIVE_BP 2
559 #define __HLS_DN_DOWNDEF_BP 3 /* link down default */
560 #define __HLS_DN_POLL_BP 4
561 #define __HLS_DN_DISABLE_BP 5
562 #define __HLS_DN_OFFLINE_BP 6
563 #define __HLS_VERIFY_CAP_BP 7
564 #define __HLS_GOING_UP_BP 8
565 #define __HLS_GOING_OFFLINE_BP 9
566 #define __HLS_LINK_COOLDOWN_BP 10
568 #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP)
569 #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP)
570 #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP)
571 #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */
572 #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP)
573 #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP)
574 #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP)
575 #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP)
576 #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP)
577 #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP)
578 #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP)
580 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
581 #define HLS_DOWN ~(HLS_UP)
583 #define HLS_DEFAULT HLS_DN_POLL
585 /* use this MTU size if none other is given */
586 #define HFI1_DEFAULT_ACTIVE_MTU 10240
587 /* use this MTU size as the default maximum */
588 #define HFI1_DEFAULT_MAX_MTU 10240
589 /* default partition key */
590 #define DEFAULT_PKEY 0xffff
593 * Possible fabric manager config parameters for fm_{get,set}_table()
595 #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */
596 #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */
597 #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */
598 #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */
599 #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */
600 #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */
603 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
604 * these are bits so they can be combined, e.g.
605 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB
607 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01
608 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02
609 #define HFI1_RCVCTRL_CTXT_ENB 0x04
610 #define HFI1_RCVCTRL_CTXT_DIS 0x08
611 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10
612 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20
613 #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
614 #define HFI1_RCVCTRL_PKEY_DIS 0x80
615 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400
616 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800
617 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000
618 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000
619 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000
620 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000
621 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000
622 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000
624 /* partition enforcement flags */
625 #define HFI1_PART_ENFORCE_IN 0x1
626 #define HFI1_PART_ENFORCE_OUT 0x2
628 /* how often we check for synthetic counter wrap around */
629 #define SYNTH_CNT_TIME 3
632 #define CNTR_NORMAL 0x0 /* Normal counters, just read register */
633 #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */
634 #define CNTR_DISABLED 0x2 /* Disable this counter */
635 #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */
636 #define CNTR_VL 0x8 /* Per VL counter */
637 #define CNTR_SDMA 0x10
638 #define CNTR_INVALID_VL -1 /* Specifies invalid VL */
639 #define CNTR_MODE_W 0x0
640 #define CNTR_MODE_R 0x1
642 /* VLs Supported/Operational */
643 #define HFI1_MIN_VLS_SUPPORTED 1
644 #define HFI1_MAX_VLS_SUPPORTED 8
646 #define HFI1_GUIDS_PER_PORT 5
647 #define HFI1_PORT_GUID_INDEX 0
649 static inline void incr_cntr64(u64 *cntr)
651 if (*cntr < (u64)-1LL)
655 static inline void incr_cntr32(u32 *cntr)
657 if (*cntr < (u32)-1LL)
661 #define MAX_NAME_SIZE 64
662 struct hfi1_msix_entry {
667 struct irq_affinity_notify notify;
670 /* per-SL CCA information */
672 struct hrtimer hrtimer;
673 struct hfi1_pportdata *ppd; /* read-only */
674 int sl; /* read-only */
675 u16 ccti; /* read/write - current value of CCTI */
678 struct link_down_reason {
680 * SMA-facing value. Should be set from .latest when
681 * HLS_UP_* -> HLS_DN_* transition actually occurs.
693 struct vl_arb_cache {
694 /* protect vl arb cache */
696 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE];
700 * The structure below encapsulates data relevant to a physical IB Port.
701 * Current chips support only one such port, but the separation
702 * clarifies things a bit. Note that to conform to IB conventions,
703 * port-numbers are one-based. The first or only port is port1.
705 struct hfi1_pportdata {
706 struct hfi1_ibport ibport_data;
708 struct hfi1_devdata *dd;
709 struct kobject pport_cc_kobj;
710 struct kobject sc2vl_kobj;
711 struct kobject sl2sc_kobj;
712 struct kobject vl2mtu_kobj;
715 struct qsfp_data qsfp_info;
716 /* Values for SI tuning of SerDes */
726 /* did we read platform config from scratch registers? */
727 bool config_from_scratch;
729 /* GUIDs for this interface, in host order, guids[0] is a port guid */
730 u64 guids[HFI1_GUIDS_PER_PORT];
732 /* GUID for peer interface, in host order */
735 /* up or down physical link state */
739 * this address is mapped read-only into user processes so they can
740 * get status cheaply, whenever they want. One qword of status per port
744 /* SendDMA related entries */
746 struct workqueue_struct *hfi1_wq;
747 struct workqueue_struct *link_wq;
749 /* move out of interrupt context */
750 struct work_struct link_vc_work;
751 struct work_struct link_up_work;
752 struct work_struct link_down_work;
753 struct work_struct sma_message_work;
754 struct work_struct freeze_work;
755 struct work_struct link_downgrade_work;
756 struct work_struct link_bounce_work;
757 struct delayed_work start_link_work;
758 /* host link state variables */
759 struct mutex hls_lock;
762 /* these are the "32 bit" regs */
764 u32 ibmtu; /* The MTU programmed for this unit */
766 * Current max size IB packet (in bytes) including IB headers, that
767 * we can send. Changes when ibmtu changes.
770 u32 current_egress_rate; /* units [10^6 bits/sec] */
771 /* LID programmed for this instance */
773 /* list of pkeys programmed; 0 if not set */
774 u16 pkeys[MAX_PKEY_VALUES];
775 u16 link_width_supported;
776 u16 link_width_downgrade_supported;
777 u16 link_speed_supported;
778 u16 link_width_enabled;
779 u16 link_width_downgrade_enabled;
780 u16 link_speed_enabled;
781 u16 link_width_active;
782 u16 link_width_downgrade_tx_active;
783 u16 link_width_downgrade_rx_active;
784 u16 link_speed_active;
787 u8 actual_vls_operational;
788 /* LID mask control */
790 /* Rx Polarity inversion (compensate for ~tx on partner) */
793 u8 hw_pidx; /* physical port index */
794 u8 port; /* IB port number and index into dd->pports - 1 */
795 /* type of neighbor node */
798 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */
799 u8 neighbor_port_number;
800 u8 is_sm_config_started;
801 u8 offline_disabled_reason;
802 u8 is_active_optimize_enabled;
803 u8 driver_link_ready; /* driver ready for active link */
804 u8 link_enabled; /* link enabled? */
806 u8 local_tx_rate; /* rate given to 8051 firmware */
809 /* placeholders for IB MAD packet settings */
810 u8 overrun_threshold;
811 u8 phy_error_threshold;
812 unsigned int is_link_down_queued;
814 /* Used to override LED behavior for things like maintenance beaconing*/
816 * Alternates per phase of blink
817 * [0] holds LED off duration, [1] holds LED on duration
819 unsigned long led_override_vals[2];
820 u8 led_override_phase; /* LSB picks from vals[] */
821 atomic_t led_override_timer_active;
822 /* Used to flash LEDs in override mode */
823 struct timer_list led_override_timer;
829 * cca_timer_lock protects access to the per-SL cca_timer
830 * structures (specifically the ccti member).
832 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp;
833 struct cca_timer cca_timer[OPA_MAX_SLS];
835 /* List of congestion control table entries */
836 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX];
838 /* congestion entries, each entry corresponding to a SL */
839 struct opa_congestion_setting_entry_shadow
840 congestion_entries[OPA_MAX_SLS];
843 * cc_state_lock protects (write) access to the per-port
846 spinlock_t cc_state_lock ____cacheline_aligned_in_smp;
848 struct cc_state __rcu *cc_state;
850 /* Total number of congestion control table entries */
853 /* Bit map identifying service level */
854 u32 cc_sl_control_map;
856 /* CA's max number of 64 entry units in the congestion control table */
857 u8 cc_max_table_entries;
860 * begin congestion log related entries
861 * cc_log_lock protects all congestion log related data
863 spinlock_t cc_log_lock ____cacheline_aligned_in_smp;
864 u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
865 u16 threshold_event_counter;
866 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS];
867 int cc_log_idx; /* index for logging events */
868 int cc_mad_idx; /* index for reporting events */
869 /* end congestion log related entries */
871 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE];
873 /* port relative counter buffer */
875 /* port relative synthetic counter buffer */
877 /* port_xmit_discards are synthesized from different egress errors */
878 u64 port_xmit_discards;
879 u64 port_xmit_discards_vl[C_VL_COUNT];
880 u64 port_xmit_constraint_errors;
881 u64 port_rcv_constraint_errors;
882 /* count of 'link_err' interrupts from DC */
884 /* number of times link retrained successfully */
886 /* number of times a link unknown frame was reported */
887 u64 unknown_frame_count;
888 /* port_ltp_crc_mode is returned in 'portinfo' MADs */
889 u16 port_ltp_crc_mode;
890 /* port_crc_mode_enabled is the crc we support */
891 u8 port_crc_mode_enabled;
892 /* mgmt_allowed is also returned in 'portinfo' MADs */
894 u8 part_enforce; /* partition enforcement flags */
895 struct link_down_reason local_link_down_reason;
896 struct link_down_reason neigh_link_down_reason;
897 /* Value to be sent to link peer on LinkDown .*/
898 u8 remote_link_down_reason;
899 /* Error events that will cause a port bounce. */
900 u32 port_error_action;
901 struct work_struct linkstate_active_work;
902 /* Does this port need to prescan for FECNs */
905 * Sample sendWaitCnt & sendWaitVlCnt during link transition
906 * and counter request.
908 u64 port_vl_xmit_wait_last[C_VL_COUNT + 1];
910 u64 vl_xmit_flit_cnt[C_VL_COUNT + 1];
913 typedef void (*opcode_handler)(struct hfi1_packet *packet);
914 typedef void (*hfi1_make_req)(struct rvt_qp *qp,
915 struct hfi1_pkt_state *ps,
916 struct rvt_swqe *wqe);
917 extern const rhf_rcv_function_ptr normal_rhf_rcv_functions[];
920 /* return values for the RHF receive functions */
921 #define RHF_RCV_CONTINUE 0 /* keep going */
922 #define RHF_RCV_DONE 1 /* stop, this packet processed */
923 #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */
925 struct rcv_array_data {
933 struct send_context *sc;
936 /* 16 to directly index */
937 #define PER_VL_SEND_CONTEXTS 16
939 struct err_info_rcvport {
945 struct err_info_constraint {
952 unsigned int curr; /* current temperature */
953 unsigned int lo_lim; /* low temperature limit */
954 unsigned int hi_lim; /* high temperature limit */
955 unsigned int crit_lim; /* critical temperature limit */
956 u8 triggers; /* temperature triggers */
959 struct hfi1_i2c_bus {
960 struct hfi1_devdata *controlling_dd; /* current controlling device */
961 struct i2c_adapter adapter; /* bus details */
962 struct i2c_algo_bit_data algo; /* bus algorithm details */
963 int num; /* bus number, 0 or 1 */
966 /* common data between shared ASIC HFIs */
967 struct hfi1_asic_data {
968 struct hfi1_devdata *dds[2]; /* back pointers */
969 struct mutex asic_resource_mutex;
970 struct hfi1_i2c_bus *i2c_bus0;
971 struct hfi1_i2c_bus *i2c_bus1;
974 /* sizes for both the QP and RSM map tables */
975 #define NUM_MAP_ENTRIES 256
976 #define NUM_MAP_REGS 32
979 * Number of VNIC contexts used. Ensure it is less than or equal to
980 * max queues supported by VNIC (HFI1_VNIC_MAX_QUEUE).
982 #define HFI1_NUM_VNIC_CTXT 8
984 /* Number of VNIC RSM entries */
985 #define NUM_VNIC_MAP_ENTRIES 8
987 /* Virtual NIC information */
988 struct hfi1_vnic_data {
989 struct hfi1_ctxtdata *ctxt[HFI1_NUM_VNIC_CTXT];
990 struct kmem_cache *txreq_cache;
998 struct hfi1_vnic_vport_info;
1000 /* device data struct now contains only "general per-device" info.
1001 * fields related to a physical IB port are in a hfi1_pportdata struct.
1006 #define BOARD_VERS_MAX 96 /* how long the version string can be */
1007 #define SERIAL_MAX 16 /* length of the serial number */
1009 typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64);
1010 struct hfi1_devdata {
1011 struct hfi1_ibdev verbs_dev; /* must be first */
1012 struct list_head list;
1013 /* pointers to related structs for this device */
1014 /* pci access data structure */
1015 struct pci_dev *pcidev;
1016 struct cdev user_cdev;
1017 struct cdev diag_cdev;
1018 struct cdev ui_cdev;
1019 struct device *user_device;
1020 struct device *diag_device;
1021 struct device *ui_device;
1023 /* first mapping up to RcvArray */
1024 u8 __iomem *kregbase1;
1025 resource_size_t physaddr;
1027 /* second uncached mapping from RcvArray to pio send buffers */
1028 u8 __iomem *kregbase2;
1029 /* for detecting offset above kregbase2 address */
1032 /* Per VL data. Enough for all VLs but not all elements are set/used. */
1033 struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
1034 /* send context data */
1035 struct send_context_info *send_contexts;
1036 /* map hardware send contexts to software index */
1038 /* spinlock for allocating and releasing send context resources */
1040 /* lock for pio_map */
1041 spinlock_t pio_map_lock;
1042 /* Send Context initialization lock. */
1043 spinlock_t sc_init_lock;
1044 /* lock for sdma_map */
1045 spinlock_t sde_map_lock;
1046 /* array of kernel send contexts */
1047 struct send_context **kernel_send_context;
1048 /* array of vl maps */
1049 struct pio_vl_map __rcu *pio_map;
1050 /* default flags to last descriptor */
1053 /* fields common to all SDMA engines */
1055 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */
1056 dma_addr_t sdma_heads_phys;
1057 void *sdma_pad_dma; /* DMA'ed by chip */
1058 dma_addr_t sdma_pad_phys;
1059 /* for deallocation */
1060 size_t sdma_heads_size;
1063 /* array of engines sized by num_sdma */
1064 struct sdma_engine *per_sdma;
1065 /* array of vl maps */
1066 struct sdma_vl_map __rcu *sdma_map;
1067 /* SPC freeze waitqueue and variable */
1068 wait_queue_head_t sdma_unfreeze_wq;
1069 atomic_t sdma_unfreeze_count;
1071 u32 lcb_access_count; /* count of LCB users */
1073 /* common data between shared ASIC HFIs in this OS */
1074 struct hfi1_asic_data *asic_data;
1076 /* mem-mapped pointer to base of PIO buffers */
1077 void __iomem *piobase;
1079 * write-combining mem-mapped pointer to base of RcvArray
1082 void __iomem *rcvarray_wc;
1084 * credit return base - a per-NUMA range of DMA address that
1085 * the chip will use to update the per-context free counter
1087 struct credit_return_base *cr_base;
1089 /* send context numbers and sizes for each type */
1090 struct sc_config_sizes sc_sizes[SC_MAX];
1092 char *boardname; /* human readable board info */
1097 u64 z_send_schedule;
1099 u64 __percpu *send_schedule;
1100 /* number of reserved contexts for VNIC usage */
1101 u16 num_vnic_contexts;
1102 /* number of receive contexts in use by the driver */
1103 u32 num_rcv_contexts;
1104 /* number of pio send contexts in use by the driver */
1105 u32 num_send_contexts;
1107 * number of ctxts available for PSM open
1110 /* total number of available user/PSM contexts */
1111 u32 num_user_contexts;
1112 /* base receive interrupt timeout, in CSR units */
1113 u32 rcv_intr_timeout_csr;
1115 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */
1116 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */
1117 spinlock_t uctxt_lock; /* protect rcd changes */
1118 struct mutex dc8051_lock; /* exclusive access to 8051 */
1119 struct workqueue_struct *update_cntr_wq;
1120 struct work_struct update_cntr_work;
1121 /* exclusive access to 8051 memory */
1122 spinlock_t dc8051_memlock;
1123 int dc8051_timed_out; /* remember if the 8051 timed out */
1125 * A page that will hold event notification bitmaps for all
1126 * contexts. This page will be mapped into all processes.
1128 unsigned long *events;
1130 * per unit status, see also portdata statusp
1131 * mapped read-only into user processes so they can get unit and
1132 * IB link status cheaply
1134 struct hfi1_status *status;
1136 /* revision register shadow */
1138 /* Base GUID for device (network order) */
1141 /* both sides of the PCIe link are gen3 capable */
1142 u8 link_gen3_capable;
1144 /* localbus width (1, 2,4,8,16,32) from config space */
1146 /* localbus speed in MHz */
1148 int unit; /* unit # of this chip */
1149 int node; /* home node of this chip */
1151 /* save these PCI fields to restore after a reset */
1163 * ASCII serial number, from flash, large enough for original
1164 * all digit strings, and longer serial number format
1166 u8 serial[SERIAL_MAX];
1167 /* human readable board version */
1168 u8 boardversion[BOARD_VERS_MAX];
1169 u8 lbus_info[32]; /* human readable localbus info */
1170 /* chip major rev, from CceRevision */
1172 /* chip minor rev, from CceRevision */
1176 /* implementation code */
1178 /* vAU of this device */
1180 /* vCU of this device */
1182 /* link credits of this device */
1184 /* initial vl15 credits to use */
1188 * Cached value for vl15buf, read during verify cap interrupt. VL15
1189 * credits are to be kept at 0 and set when handling the link-up
1190 * interrupt. This removes the possibility of receiving VL15 MAD
1191 * packets before this HFI is ready.
1195 /* Misc small ints */
1199 u16 irev; /* implementation revision */
1200 u32 dc8051_ver; /* 8051 firmware version */
1202 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */
1203 struct platform_config platform_config;
1204 struct platform_config_cache pcfg_cache;
1206 struct diag_client *diag_client;
1208 /* MSI-X information */
1209 struct hfi1_msix_entry *msix_entries;
1210 u32 num_msix_entries;
1211 u32 first_dyn_msix_idx;
1213 /* INTx information */
1214 u32 requested_intx_irq; /* did we request one? */
1216 /* general interrupt: mask of handled interrupts */
1217 u64 gi_mask[CCE_NUM_INT_CSRS];
1219 struct rcv_array_data rcv_entries;
1221 /* cycle length of PS* counters in HW (in picoseconds) */
1222 u16 psxmitwait_check_rate;
1225 * 64 bit synthetic counters
1227 struct timer_list synth_stats_timer;
1233 size_t cntrnameslen;
1239 * remembered values for synthetic counters
1248 char *portcntrnames;
1249 size_t portcntrnameslen;
1251 struct err_info_rcvport err_info_rcvport;
1252 struct err_info_constraint err_info_rcv_constraint;
1253 struct err_info_constraint err_info_xmit_constraint;
1255 atomic_t drop_packet;
1257 u8 err_info_uncorrectable;
1258 u8 err_info_fmconfig;
1261 * Software counters for the status bits defined by the
1262 * associated error status registers
1264 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS];
1265 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS];
1266 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS];
1267 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS];
1268 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS];
1269 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS];
1270 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS];
1272 /* Software counter that spans all contexts */
1273 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS];
1274 /* Software counter that spans all DMA engines */
1275 u64 sw_send_dma_eng_err_status_cnt[
1276 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS];
1277 /* Software counter that aggregates all cce_err_status errors */
1278 u64 sw_cce_err_status_aggregate;
1279 /* Software counter that aggregates all bypass packet rcv errors */
1280 u64 sw_rcv_bypass_packet_errors;
1282 /* Save the enabled LCB error bits */
1284 struct cpu_mask_set *comp_vect;
1285 int *comp_vect_mappings;
1286 u32 comp_vect_possible_cpus;
1289 * Capability to have different send engines simply by changing a
1292 send_routine process_pio_send ____cacheline_aligned_in_smp;
1293 send_routine process_dma_send;
1294 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1295 u64 pbc, const void *from, size_t count);
1296 int (*process_vnic_dma_send)(struct hfi1_devdata *dd, u8 q_idx,
1297 struct hfi1_vnic_vport_info *vinfo,
1298 struct sk_buff *skb, u64 pbc, u8 plen);
1299 /* hfi1_pportdata, points to array of (physical) port-specific
1300 * data structs, indexed by pidx (0..n-1)
1302 struct hfi1_pportdata *pport;
1303 /* receive context data */
1304 struct hfi1_ctxtdata **rcd;
1305 u64 __percpu *int_counter;
1306 /* verbs tx opcode stats */
1307 struct hfi1_opcode_stats_perctx __percpu *tx_opstats;
1308 /* device (not port) flags, basically device capabilities */
1310 /* Number of physical ports available */
1312 /* Lowest context number which can be used by user processes or VNIC */
1313 u8 first_dyn_alloc_ctxt;
1314 /* adding a new field here would make it part of this cacheline */
1316 /* seqlock for sc2vl */
1317 seqlock_t sc2vl_lock ____cacheline_aligned_in_smp;
1319 u64 __percpu *rcv_limit;
1320 /* adding a new field here would make it part of this cacheline */
1322 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */
1327 /* Timer and counter used to detect RcvBufOvflCnt changes */
1328 struct timer_list rcverr_timer;
1330 wait_queue_head_t event_queue;
1332 /* receive context tail dummy address */
1333 __le64 *rcvhdrtail_dummy_kvaddr;
1334 dma_addr_t rcvhdrtail_dummy_dma;
1337 /* Serialize ASPM enable/disable between multiple verbs contexts */
1338 spinlock_t aspm_lock;
1339 /* Number of verbs contexts which have disabled ASPM */
1340 atomic_t aspm_disabled_cnt;
1341 /* Keeps track of user space clients */
1342 atomic_t user_refcount;
1343 /* Used to wait for outstanding user space clients before dev removal */
1344 struct completion user_comp;
1346 bool eprom_available; /* true if EPROM is available for this device */
1347 bool aspm_supported; /* Does HW support ASPM */
1348 bool aspm_enabled; /* ASPM state: enabled/disabled */
1349 struct rhashtable *sdma_rht;
1351 struct kobject kobj;
1354 struct hfi1_vnic_data vnic;
1357 static inline bool hfi1_vnic_is_rsm_full(struct hfi1_devdata *dd, int spare)
1359 return (dd->vnic.rmt_start + spare) > NUM_MAP_ENTRIES;
1362 /* 8051 firmware version helper */
1363 #define dc8051_ver(a, b, c) ((a) << 16 | (b) << 8 | (c))
1364 #define dc8051_ver_maj(a) (((a) & 0xff0000) >> 16)
1365 #define dc8051_ver_min(a) (((a) & 0x00ff00) >> 8)
1366 #define dc8051_ver_patch(a) ((a) & 0x0000ff)
1368 /* f_put_tid types */
1369 #define PT_EXPECTED 0
1371 #define PT_INVALID_FLUSH 2
1372 #define PT_INVALID 3
1376 struct mmu_rb_handler;
1378 /* Private data for file operations */
1379 struct hfi1_filedata {
1380 struct hfi1_devdata *dd;
1381 struct hfi1_ctxtdata *uctxt;
1382 struct hfi1_user_sdma_comp_q *cq;
1383 struct hfi1_user_sdma_pkt_q *pq;
1385 /* for cpu affinity; -1 if none */
1388 struct mmu_rb_handler *handler;
1389 struct tid_rb_node **entry_to_rb;
1390 spinlock_t tid_lock; /* protect tid_[limit,used] counters */
1394 u32 invalid_tid_idx;
1395 /* protect invalid_tids array and invalid_tid_idx */
1396 spinlock_t invalid_lock;
1397 struct mm_struct *mm;
1400 extern struct list_head hfi1_dev_list;
1401 extern spinlock_t hfi1_devs_lock;
1402 struct hfi1_devdata *hfi1_lookup(int unit);
1404 static inline unsigned long uctxt_offset(struct hfi1_ctxtdata *uctxt)
1406 return (uctxt->ctxt - uctxt->dd->first_dyn_alloc_ctxt) *
1407 HFI1_MAX_SHARED_CTXTS;
1410 int hfi1_init(struct hfi1_devdata *dd, int reinit);
1411 int hfi1_count_active_units(void);
1413 int hfi1_diag_add(struct hfi1_devdata *dd);
1414 void hfi1_diag_remove(struct hfi1_devdata *dd);
1415 void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup);
1417 void handle_user_interrupt(struct hfi1_ctxtdata *rcd);
1419 int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1420 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd);
1421 int hfi1_create_kctxts(struct hfi1_devdata *dd);
1422 int hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, int numa,
1423 struct hfi1_ctxtdata **rcd);
1424 void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd);
1425 void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
1426 struct hfi1_devdata *dd, u8 hw_pidx, u8 port);
1427 void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1428 int hfi1_rcd_put(struct hfi1_ctxtdata *rcd);
1429 void hfi1_rcd_get(struct hfi1_ctxtdata *rcd);
1430 struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd,
1432 struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt);
1433 int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread);
1434 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1435 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1436 void set_all_slowpath(struct hfi1_devdata *dd);
1437 void hfi1_vnic_synchronize_irq(struct hfi1_devdata *dd);
1438 void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata *rcd);
1439 void hfi1_reset_vnic_msix_info(struct hfi1_ctxtdata *rcd);
1441 extern const struct pci_device_id hfi1_pci_tbl[];
1442 void hfi1_make_ud_req_9B(struct rvt_qp *qp,
1443 struct hfi1_pkt_state *ps,
1444 struct rvt_swqe *wqe);
1446 void hfi1_make_ud_req_16B(struct rvt_qp *qp,
1447 struct hfi1_pkt_state *ps,
1448 struct rvt_swqe *wqe);
1450 /* receive packet handler dispositions */
1451 #define RCV_PKT_OK 0x0 /* keep going */
1452 #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */
1453 #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */
1455 /* calculate the current RHF address */
1456 static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd)
1458 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->rhf_offset;
1461 int hfi1_reset_device(int);
1463 void receive_interrupt_work(struct work_struct *work);
1465 /* extract service channel from header and rhf */
1466 static inline int hfi1_9B_get_sc5(struct ib_header *hdr, u64 rhf)
1468 return ib_get_sc(hdr) | ((!!(rhf_dc_info(rhf))) << 4);
1471 #define HFI1_JKEY_WIDTH 16
1472 #define HFI1_JKEY_MASK (BIT(16) - 1)
1473 #define HFI1_ADMIN_JKEY_RANGE 32
1476 * J_KEYs are split and allocated in the following groups:
1477 * 0 - 31 - users with administrator privileges
1478 * 32 - 63 - kernel protocols using KDETH packets
1479 * 64 - 65535 - all other users using KDETH packets
1481 static inline u16 generate_jkey(kuid_t uid)
1483 u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK;
1485 if (capable(CAP_SYS_ADMIN))
1486 jkey &= HFI1_ADMIN_JKEY_RANGE - 1;
1488 jkey |= BIT(HFI1_JKEY_WIDTH - 1);
1494 * active_egress_rate
1496 * returns the active egress rate in units of [10^6 bits/sec]
1498 static inline u32 active_egress_rate(struct hfi1_pportdata *ppd)
1500 u16 link_speed = ppd->link_speed_active;
1501 u16 link_width = ppd->link_width_active;
1504 if (link_speed == OPA_LINK_SPEED_25G)
1505 egress_rate = 25000;
1506 else /* assume OPA_LINK_SPEED_12_5G */
1507 egress_rate = 12500;
1509 switch (link_width) {
1510 case OPA_LINK_WIDTH_4X:
1513 case OPA_LINK_WIDTH_3X:
1516 case OPA_LINK_WIDTH_2X:
1520 /* assume IB_WIDTH_1X */
1530 * Returns the number of 'fabric clock cycles' to egress a packet
1531 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock
1532 * rate is (approximately) 805 MHz, the units of the returned value
1535 static inline u32 egress_cycles(u32 len, u32 rate)
1542 * (length) [bits] / (rate) [bits/sec]
1543 * ---------------------------------------------------
1544 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec]
1547 cycles = len * 8; /* bits */
1554 void set_link_ipg(struct hfi1_pportdata *ppd);
1555 void process_becn(struct hfi1_pportdata *ppd, u8 sl, u32 rlid, u32 lqpn,
1556 u32 rqpn, u8 svc_type);
1557 void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn,
1558 u16 pkey, u32 slid, u32 dlid, u8 sc5,
1559 const struct ib_grh *old_grh);
1560 void return_cnp_16B(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1561 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
1562 u8 sc5, const struct ib_grh *old_grh);
1563 typedef void (*hfi1_handle_cnp)(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1564 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
1565 u8 sc5, const struct ib_grh *old_grh);
1567 #define PKEY_CHECK_INVALID -1
1568 int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey,
1569 u8 sc5, int8_t s_pkey_index);
1571 #define PACKET_EGRESS_TIMEOUT 350
1572 static inline void pause_for_credit_return(struct hfi1_devdata *dd)
1574 /* Pause at least 1us, to ensure chip returns all credits */
1575 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000;
1577 udelay(usec ? usec : 1);
1581 * sc_to_vlt() reverse lookup sc to vl
1585 static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5)
1590 if (sc5 >= OPA_MAX_SCS)
1594 seq = read_seqbegin(&dd->sc2vl_lock);
1595 rval = *(((u8 *)dd->sc2vl) + sc5);
1596 } while (read_seqretry(&dd->sc2vl_lock, seq));
1601 #define PKEY_MEMBER_MASK 0x8000
1602 #define PKEY_LOW_15_MASK 0x7fff
1605 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1606 * being an entry from the ingress partition key table), return 0
1607 * otherwise. Use the matching criteria for ingress partition keys
1608 * specified in the OPAv1 spec., section 9.10.14.
1610 static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent)
1612 u16 mkey = pkey & PKEY_LOW_15_MASK;
1613 u16 ment = ent & PKEY_LOW_15_MASK;
1617 * If pkey[15] is clear (limited partition member),
1618 * is bit 15 in the corresponding table element
1619 * clear (limited member)?
1621 if (!(pkey & PKEY_MEMBER_MASK))
1622 return !!(ent & PKEY_MEMBER_MASK);
1629 * ingress_pkey_table_search - search the entire pkey table for
1630 * an entry which matches 'pkey'. return 0 if a match is found,
1633 static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey)
1637 for (i = 0; i < MAX_PKEY_VALUES; i++) {
1638 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1645 * ingress_pkey_table_fail - record a failure of ingress pkey validation,
1646 * i.e., increment port_rcv_constraint_errors for the port, and record
1647 * the 'error info' for this failure.
1649 static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey,
1652 struct hfi1_devdata *dd = ppd->dd;
1654 incr_cntr64(&ppd->port_rcv_constraint_errors);
1655 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) {
1656 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK;
1657 dd->err_info_rcv_constraint.slid = slid;
1658 dd->err_info_rcv_constraint.pkey = pkey;
1663 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1
1664 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx
1665 * is a hint as to the best place in the partition key table to begin
1666 * searching. This function should not be called on the data path because
1667 * of performance reasons. On datapath pkey check is expected to be done
1668 * by HW and rcv_pkey_check function should be called instead.
1670 static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1671 u8 sc5, u8 idx, u32 slid, bool force)
1673 if (!(force) && !(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1676 /* If SC15, pkey[0:14] must be 0x7fff */
1677 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1680 /* Is the pkey = 0x0, or 0x8000? */
1681 if ((pkey & PKEY_LOW_15_MASK) == 0)
1684 /* The most likely matching pkey has index 'idx' */
1685 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx]))
1688 /* no match - try the whole table */
1689 if (!ingress_pkey_table_search(ppd, pkey))
1693 ingress_pkey_table_fail(ppd, pkey, slid);
1698 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1
1699 * otherwise. It only ensures pkey is vlid for QP0. This function
1700 * should be called on the data path instead of ingress_pkey_check
1701 * as on data path, pkey check is done by HW (except for QP0).
1703 static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1706 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1709 /* If SC15, pkey[0:14] must be 0x7fff */
1710 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1715 ingress_pkey_table_fail(ppd, pkey, slid);
1721 /* MTU enumeration, 256-4k match IB */
1723 #define OPA_MTU_256 1
1724 #define OPA_MTU_512 2
1725 #define OPA_MTU_1024 3
1726 #define OPA_MTU_2048 4
1727 #define OPA_MTU_4096 5
1729 u32 lrh_max_header_bytes(struct hfi1_devdata *dd);
1730 int mtu_to_enum(u32 mtu, int default_if_bad);
1731 u16 enum_to_mtu(int mtu);
1732 static inline int valid_ib_mtu(unsigned int mtu)
1734 return mtu == 256 || mtu == 512 ||
1735 mtu == 1024 || mtu == 2048 ||
1739 static inline int valid_opa_max_mtu(unsigned int mtu)
1741 return mtu >= 2048 &&
1742 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240);
1745 int set_mtu(struct hfi1_pportdata *ppd);
1747 int hfi1_set_lid(struct hfi1_pportdata *ppd, u32 lid, u8 lmc);
1748 void hfi1_disable_after_error(struct hfi1_devdata *dd);
1749 int hfi1_set_uevent_bits(struct hfi1_pportdata *ppd, const int evtbit);
1750 int hfi1_rcvbuf_validate(u32 size, u8 type, u16 *encode);
1752 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t);
1753 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t);
1755 void set_up_vau(struct hfi1_devdata *dd, u8 vau);
1756 void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf);
1757 void reset_link_credits(struct hfi1_devdata *dd);
1758 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);
1760 int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc);
1762 static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd)
1767 static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev)
1769 return container_of(dev, struct hfi1_devdata, verbs_dev);
1772 static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev)
1774 return dd_from_dev(to_idev(ibdev));
1777 static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp)
1779 return container_of(ibp, struct hfi1_pportdata, ibport_data);
1782 static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi)
1784 return container_of(rdi, struct hfi1_ibdev, rdi);
1787 static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port)
1789 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1790 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1792 WARN_ON(pidx >= dd->num_pports);
1793 return &dd->pport[pidx].ibport_data;
1796 static inline struct hfi1_ibport *rcd_to_iport(struct hfi1_ctxtdata *rcd)
1798 return &rcd->ppd->ibport_data;
1801 void hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt,
1803 static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt,
1809 if (pkt->etype == RHF_RCV_TYPE_BYPASS) {
1810 fecn = hfi1_16B_get_fecn(pkt->hdr);
1811 becn = hfi1_16B_get_becn(pkt->hdr);
1813 fecn = ib_bth_get_fecn(pkt->ohdr);
1814 becn = ib_bth_get_becn(pkt->ohdr);
1816 if (unlikely(fecn || becn)) {
1817 hfi1_process_ecn_slowpath(qp, pkt, do_cnp);
1824 * Return the indexed PKEY from the port PKEY table.
1826 static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index)
1828 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1831 if (index >= ARRAY_SIZE(ppd->pkeys))
1834 ret = ppd->pkeys[index];
1840 * Return the indexed GUID from the port GUIDs table.
1842 static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index)
1844 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1846 WARN_ON(index >= HFI1_GUIDS_PER_PORT);
1847 return cpu_to_be64(ppd->guids[index]);
1851 * Called by readers of cc_state only, must call under rcu_read_lock().
1853 static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd)
1855 return rcu_dereference(ppd->cc_state);
1859 * Called by writers of cc_state only, must call under cc_state_lock.
1862 struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd)
1864 return rcu_dereference_protected(ppd->cc_state,
1865 lockdep_is_held(&ppd->cc_state_lock));
1869 * values for dd->flags (_device_ related flags)
1871 #define HFI1_INITTED 0x1 /* chip and driver up and initted */
1872 #define HFI1_PRESENT 0x2 /* chip accesses can be done */
1873 #define HFI1_FROZEN 0x4 /* chip in SPC freeze */
1874 #define HFI1_HAS_SDMA_TIMEOUT 0x8
1875 #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */
1876 #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */
1877 #define HFI1_SHUTDOWN 0x100 /* device is shutting down */
1879 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1880 #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1)
1882 /* ctxt_flag bit offsets */
1883 /* base context has not finished initializing */
1884 #define HFI1_CTXT_BASE_UNINIT 1
1885 /* base context initaliation failed */
1886 #define HFI1_CTXT_BASE_FAILED 2
1887 /* waiting for a packet to arrive */
1888 #define HFI1_CTXT_WAITING_RCV 3
1889 /* waiting for an urgent packet to arrive */
1890 #define HFI1_CTXT_WAITING_URG 4
1892 /* free up any allocated data at closes */
1893 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
1894 const struct pci_device_id *ent);
1895 void hfi1_free_devdata(struct hfi1_devdata *dd);
1896 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra);
1898 /* LED beaconing functions */
1899 void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon,
1900 unsigned int timeoff);
1901 void shutdown_led_override(struct hfi1_pportdata *ppd);
1903 #define HFI1_CREDIT_RETURN_RATE (100)
1906 * The number of words for the KDETH protocol field. If this is
1907 * larger then the actual field used, then part of the payload
1908 * will be in the header.
1910 * Optimally, we want this sized so that a typical case will
1911 * use full cache lines. The typical local KDETH header would
1922 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS
1924 #define DEFAULT_RCVHDRSIZE 9
1927 * Maximal header byte count:
1938 * We also want to maintain a cache line alignment to assist DMA'ing
1939 * of the header bytes. Round up to a good size.
1941 #define DEFAULT_RCVHDR_ENTSIZE 32
1943 bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm,
1944 u32 nlocked, u32 npages);
1945 int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr,
1946 size_t npages, bool writable, struct page **pages);
1947 void hfi1_release_user_pages(struct mm_struct *mm, struct page **p,
1948 size_t npages, bool dirty);
1950 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1952 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL;
1955 static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1958 * volatile because it's a DMA target from the chip, routine is
1959 * inlined, and don't want register caching or reordering.
1961 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr);
1968 extern const char ib_hfi1_version[];
1970 int hfi1_device_create(struct hfi1_devdata *dd);
1971 void hfi1_device_remove(struct hfi1_devdata *dd);
1973 int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
1974 struct kobject *kobj);
1975 int hfi1_verbs_register_sysfs(struct hfi1_devdata *dd);
1976 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *dd);
1977 /* Hook for sysfs read of QSFP */
1978 int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len);
1980 int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent);
1981 void hfi1_clean_up_interrupts(struct hfi1_devdata *dd);
1982 void hfi1_pcie_cleanup(struct pci_dev *pdev);
1983 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev);
1984 void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
1985 int pcie_speeds(struct hfi1_devdata *dd);
1986 int request_msix(struct hfi1_devdata *dd, u32 msireq);
1987 int restore_pci_variables(struct hfi1_devdata *dd);
1988 int save_pci_variables(struct hfi1_devdata *dd);
1989 int do_pcie_gen3_transition(struct hfi1_devdata *dd);
1990 int parse_platform_config(struct hfi1_devdata *dd);
1991 int get_platform_config_field(struct hfi1_devdata *dd,
1992 enum platform_config_table_type_encoding
1993 table_type, int table_index, int field_index,
1994 u32 *data, u32 len);
1996 struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi);
1999 * Flush write combining store buffers (if present) and perform a write
2002 static inline void flush_wc(void)
2004 asm volatile("sfence" : : : "memory");
2007 void handle_eflags(struct hfi1_packet *packet);
2008 void seqfile_dump_rcd(struct seq_file *s, struct hfi1_ctxtdata *rcd);
2010 /* global module parameter variables */
2011 extern unsigned int hfi1_max_mtu;
2012 extern unsigned int hfi1_cu;
2013 extern unsigned int user_credit_return_threshold;
2014 extern int num_user_contexts;
2015 extern unsigned long n_krcvqs;
2016 extern uint krcvqs[];
2017 extern int krcvqsset;
2018 extern uint kdeth_qp;
2019 extern uint loopback;
2020 extern uint quick_linkup;
2021 extern uint rcv_intr_timeout;
2022 extern uint rcv_intr_count;
2023 extern uint rcv_intr_dynamic;
2024 extern ushort link_crc_mask;
2026 extern struct mutex hfi1_mutex;
2028 /* Number of seconds before our card status check... */
2029 #define STATUS_TIMEOUT 60
2031 #define DRIVER_NAME "hfi1"
2032 #define HFI1_USER_MINOR_BASE 0
2033 #define HFI1_TRACE_MINOR 127
2034 #define HFI1_NMINORS 255
2036 #define PCI_VENDOR_ID_INTEL 0x8086
2037 #define PCI_DEVICE_ID_INTEL0 0x24f0
2038 #define PCI_DEVICE_ID_INTEL1 0x24f1
2040 #define HFI1_PKT_USER_SC_INTEGRITY \
2041 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \
2042 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \
2043 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \
2044 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK)
2046 #define HFI1_PKT_KERNEL_SC_INTEGRITY \
2047 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK)
2049 static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,
2052 u64 base_sc_integrity;
2054 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
2055 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2059 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2060 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
2061 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2062 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2063 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2064 #ifndef CONFIG_FAULT_INJECTION
2065 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK
2067 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2068 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2069 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2070 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK
2071 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2072 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2073 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
2074 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
2075 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
2076 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2078 if (ctxt_type == SC_USER)
2079 base_sc_integrity |=
2080 #ifndef CONFIG_FAULT_INJECTION
2081 SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK |
2083 HFI1_PKT_USER_SC_INTEGRITY;
2085 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY;
2087 /* turn on send-side job key checks if !A0 */
2089 base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2091 return base_sc_integrity;
2094 static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)
2096 u64 base_sdma_integrity;
2098 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
2099 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2102 base_sdma_integrity =
2103 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2104 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2105 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2106 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2107 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2108 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2109 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2110 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK
2111 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2112 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2113 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
2114 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
2115 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
2116 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2118 if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
2119 base_sdma_integrity |=
2120 SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK;
2122 /* turn on send-side job key checks if !A0 */
2124 base_sdma_integrity |=
2125 SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2127 return base_sdma_integrity;
2131 * hfi1_early_err is used (only!) to print early errors before devdata is
2132 * allocated, or when dd->pcidev may not be valid, and at the tail end of
2133 * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is
2134 * the same as dd_dev_err, but is used when the message really needs
2135 * the IB port# to be definitive as to what's happening..
2137 #define hfi1_early_err(dev, fmt, ...) \
2138 dev_err(dev, fmt, ##__VA_ARGS__)
2140 #define hfi1_early_info(dev, fmt, ...) \
2141 dev_info(dev, fmt, ##__VA_ARGS__)
2143 #define dd_dev_emerg(dd, fmt, ...) \
2144 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \
2145 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2147 #define dd_dev_err(dd, fmt, ...) \
2148 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
2149 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2151 #define dd_dev_err_ratelimited(dd, fmt, ...) \
2152 dev_err_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2153 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2156 #define dd_dev_warn(dd, fmt, ...) \
2157 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
2158 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2160 #define dd_dev_warn_ratelimited(dd, fmt, ...) \
2161 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2162 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2165 #define dd_dev_info(dd, fmt, ...) \
2166 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \
2167 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2169 #define dd_dev_info_ratelimited(dd, fmt, ...) \
2170 dev_info_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2171 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2174 #define dd_dev_dbg(dd, fmt, ...) \
2175 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \
2176 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2178 #define hfi1_dev_porterr(dd, port, fmt, ...) \
2179 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \
2180 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), (port), ##__VA_ARGS__)
2183 * this is used for formatting hw error messages...
2185 struct hfi1_hwerror_msgs {
2192 void hfi1_format_hwerrors(u64 hwerrs,
2193 const struct hfi1_hwerror_msgs *hwerrmsgs,
2194 size_t nhwerrmsgs, char *msg, size_t lmsg);
2196 #define USER_OPCODE_CHECK_VAL 0xC0
2197 #define USER_OPCODE_CHECK_MASK 0xC0
2198 #define OPCODE_CHECK_VAL_DISABLED 0x0
2199 #define OPCODE_CHECK_MASK_DISABLED 0x0
2201 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd)
2203 struct hfi1_pportdata *ppd;
2206 dd->z_int_counter = get_all_cpu_total(dd->int_counter);
2207 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit);
2208 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule);
2210 ppd = (struct hfi1_pportdata *)(dd + 1);
2211 for (i = 0; i < dd->num_pports; i++, ppd++) {
2212 ppd->ibport_data.rvp.z_rc_acks =
2213 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks);
2214 ppd->ibport_data.rvp.z_rc_qacks =
2215 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks);
2219 /* Control LED state */
2220 static inline void setextled(struct hfi1_devdata *dd, u32 on)
2223 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
2225 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
2228 /* return the i2c resource given the target */
2229 static inline u32 i2c_target(u32 target)
2231 return target ? CR_I2C2 : CR_I2C1;
2234 /* return the i2c chain chip resource that this HFI uses for QSFP */
2235 static inline u32 qsfp_resource(struct hfi1_devdata *dd)
2237 return i2c_target(dd->hfi1_id);
2240 /* Is this device integrated or discrete? */
2241 static inline bool is_integrated(struct hfi1_devdata *dd)
2243 return dd->pcidev->device == PCI_DEVICE_ID_INTEL1;
2246 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp);
2248 #define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev))
2249 #define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev))
2251 static inline void hfi1_update_ah_attr(struct ib_device *ibdev,
2252 struct rdma_ah_attr *attr)
2254 struct hfi1_pportdata *ppd;
2255 struct hfi1_ibport *ibp;
2256 u32 dlid = rdma_ah_get_dlid(attr);
2259 * Kernel clients may not have setup GRH information
2262 ibp = to_iport(ibdev, rdma_ah_get_port_num(attr));
2263 ppd = ppd_from_ibp(ibp);
2264 if ((((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ||
2265 (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE))) &&
2266 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)) &&
2267 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2268 (!(rdma_ah_get_ah_flags(attr) & IB_AH_GRH))) ||
2269 (rdma_ah_get_make_grd(attr))) {
2270 rdma_ah_set_ah_flags(attr, IB_AH_GRH);
2271 rdma_ah_set_interface_id(attr, OPA_MAKE_ID(dlid));
2272 rdma_ah_set_subnet_prefix(attr, ibp->rvp.gid_prefix);
2277 * hfi1_check_mcast- Check if the given lid is
2278 * in the OPA multicast range.
2280 * The LID might either reside in ah.dlid or might be
2281 * in the GRH of the address handle as DGID if extended
2282 * addresses are in use.
2284 static inline bool hfi1_check_mcast(u32 lid)
2286 return ((lid >= opa_get_mcast_base(OPA_MCAST_NR)) &&
2287 (lid != be32_to_cpu(OPA_LID_PERMISSIVE)));
2290 #define opa_get_lid(lid, format) \
2291 __opa_get_lid(lid, OPA_PORT_PACKET_FORMAT_##format)
2293 /* Convert a lid to a specific lid space */
2294 static inline u32 __opa_get_lid(u32 lid, u8 format)
2296 bool is_mcast = hfi1_check_mcast(lid);
2299 case OPA_PORT_PACKET_FORMAT_8B:
2300 case OPA_PORT_PACKET_FORMAT_10B:
2302 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2304 return lid & 0xFFFFF;
2305 case OPA_PORT_PACKET_FORMAT_16B:
2307 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2309 return lid & 0xFFFFFF;
2310 case OPA_PORT_PACKET_FORMAT_9B:
2313 opa_get_mcast_base(OPA_MCAST_NR) +
2314 be16_to_cpu(IB_MULTICAST_LID_BASE));
2316 return lid & 0xFFFF;
2322 /* Return true if the given lid is the OPA 16B multicast range */
2323 static inline bool hfi1_is_16B_mcast(u32 lid)
2326 opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 16B)) &&
2327 (lid != opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B)));
2330 static inline void hfi1_make_opa_lid(struct rdma_ah_attr *attr)
2332 const struct ib_global_route *grh = rdma_ah_read_grh(attr);
2333 u32 dlid = rdma_ah_get_dlid(attr);
2335 /* Modify ah_attr.dlid to be in the 32 bit LID space.
2336 * This is how the address will be laid out:
2337 * Assuming MCAST_NR to be 4,
2338 * 32 bit permissive LID = 0xFFFFFFFF
2339 * Multicast LID range = 0xFFFFFFFE to 0xF0000000
2340 * Unicast LID range = 0xEFFFFFFF to 1
2343 if (ib_is_opa_gid(&grh->dgid))
2344 dlid = opa_get_lid_from_gid(&grh->dgid);
2345 else if ((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) &&
2346 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2347 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)))
2348 dlid = dlid - be16_to_cpu(IB_MULTICAST_LID_BASE) +
2349 opa_get_mcast_base(OPA_MCAST_NR);
2350 else if (dlid == be16_to_cpu(IB_LID_PERMISSIVE))
2351 dlid = be32_to_cpu(OPA_LID_PERMISSIVE);
2353 rdma_ah_set_dlid(attr, dlid);
2356 static inline u8 hfi1_get_packet_type(u32 lid)
2358 /* 9B if lid > 0xF0000000 */
2359 if (lid >= opa_get_mcast_base(OPA_MCAST_NR))
2360 return HFI1_PKT_TYPE_9B;
2362 /* 16B if lid > 0xC000 */
2363 if (lid >= opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 9B))
2364 return HFI1_PKT_TYPE_16B;
2366 return HFI1_PKT_TYPE_9B;
2369 static inline bool hfi1_get_hdr_type(u32 lid, struct rdma_ah_attr *attr)
2372 * If there was an incoming 16B packet with permissive
2373 * LIDs, OPA GIDs would have been programmed when those
2374 * packets were received. A 16B packet will have to
2375 * be sent in response to that packet. Return a 16B
2376 * header type if that's the case.
2378 if (rdma_ah_get_dlid(attr) == be32_to_cpu(OPA_LID_PERMISSIVE))
2379 return (ib_is_opa_gid(&rdma_ah_read_grh(attr)->dgid)) ?
2380 HFI1_PKT_TYPE_16B : HFI1_PKT_TYPE_9B;
2383 * Return a 16B header type if either the the destination
2384 * or source lid is extended.
2386 if (hfi1_get_packet_type(rdma_ah_get_dlid(attr)) == HFI1_PKT_TYPE_16B)
2387 return HFI1_PKT_TYPE_16B;
2389 return hfi1_get_packet_type(lid);
2392 static inline void hfi1_make_ext_grh(struct hfi1_packet *packet,
2393 struct ib_grh *grh, u32 slid,
2396 struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
2397 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2403 grh->sgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2404 if (slid == opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B))
2405 grh->sgid.global.interface_id =
2406 OPA_MAKE_ID(be32_to_cpu(OPA_LID_PERMISSIVE));
2408 grh->sgid.global.interface_id = OPA_MAKE_ID(slid);
2411 * Upper layers (like mad) may compare the dgid in the
2412 * wc that is obtained here with the sgid_index in
2413 * the wr. Since sgid_index in wr is always 0 for
2414 * extended lids, set the dgid here to the default
2417 grh->dgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2418 grh->dgid.global.interface_id =
2419 cpu_to_be64(ppd->guids[HFI1_PORT_GUID_INDEX]);
2422 static inline int hfi1_get_16b_padding(u32 hdr_size, u32 payload)
2424 return -(hdr_size + payload + (SIZE_OF_CRC << 2) +
2428 static inline void hfi1_make_ib_hdr(struct ib_header *hdr,
2432 hdr->lrh[0] = cpu_to_be16(lrh0);
2433 hdr->lrh[1] = cpu_to_be16(dlid);
2434 hdr->lrh[2] = cpu_to_be16(len);
2435 hdr->lrh[3] = cpu_to_be16(slid);
2438 static inline void hfi1_make_16b_hdr(struct hfi1_16b_header *hdr,
2441 bool becn, bool fecn, u8 l4,
2445 u32 lrh1 = 0x40000000;
2449 lrh0 = (lrh0 & ~OPA_16B_BECN_MASK) | (becn << OPA_16B_BECN_SHIFT);
2450 lrh0 = (lrh0 & ~OPA_16B_LEN_MASK) | (len << OPA_16B_LEN_SHIFT);
2451 lrh0 = (lrh0 & ~OPA_16B_LID_MASK) | (slid & OPA_16B_LID_MASK);
2452 lrh1 = (lrh1 & ~OPA_16B_FECN_MASK) | (fecn << OPA_16B_FECN_SHIFT);
2453 lrh1 = (lrh1 & ~OPA_16B_SC_MASK) | (sc << OPA_16B_SC_SHIFT);
2454 lrh1 = (lrh1 & ~OPA_16B_LID_MASK) | (dlid & OPA_16B_LID_MASK);
2455 lrh2 = (lrh2 & ~OPA_16B_SLID_MASK) |
2456 ((slid >> OPA_16B_SLID_SHIFT) << OPA_16B_SLID_HIGH_SHIFT);
2457 lrh2 = (lrh2 & ~OPA_16B_DLID_MASK) |
2458 ((dlid >> OPA_16B_DLID_SHIFT) << OPA_16B_DLID_HIGH_SHIFT);
2459 lrh2 = (lrh2 & ~OPA_16B_PKEY_MASK) | ((u32)pkey << OPA_16B_PKEY_SHIFT);
2460 lrh2 = (lrh2 & ~OPA_16B_L4_MASK) | l4;
2467 #endif /* _HFI1_KERNEL_H */