drivers/infiniband/hw/hfi1/chip.c

   1 /*
   2  * Copyright(c) 2015, 2016 Intel Corporation.
   3  *
   4  * This file is provided under a dual BSD/GPLv2 license.  When using or
   5  * redistributing this file, you may do so under either license.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * BSD LICENSE
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  *
  24  *  - Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  *  - Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in
  28  *    the documentation and/or other materials provided with the
  29  *    distribution.
  30  *  - Neither the name of Intel Corporation nor the names of its
  31  *    contributors may be used to endorse or promote products derived
  32  *    from this software without specific prior written permission.
  33  *
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45  *
  46  */
  47
  48 /*
  49  * This file contains all of the code that is specific to the HFI chip
  50  */
  51
  52 #include <linux/pci.h>
  53 #include <linux/delay.h>
  54 #include <linux/interrupt.h>
  55 #include <linux/module.h>
  56
  57 #include "hfi.h"
  58 #include "trace.h"
  59 #include "mad.h"
  60 #include "pio.h"
  61 #include "sdma.h"
  62 #include "eprom.h"
  63 #include "efivar.h"
  64 #include "platform.h"
  65 #include "aspm.h"
  66 #include "affinity.h"
  67
  68 #define NUM_IB_PORTS 1
  69
  70 uint kdeth_qp;
  71 module_param_named(kdeth_qp, kdeth_qp, uint, S_IRUGO);
  72 MODULE_PARM_DESC(kdeth_qp, "Set the KDETH queue pair prefix");
  73
  74 uint num_vls = HFI1_MAX_VLS_SUPPORTED;
  75 module_param(num_vls, uint, S_IRUGO);
  76 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
  77
  78 /*
  79  * Default time to aggregate two 10K packets from the idle state
  80  * (timer not running). The timer starts at the end of the first packet,
  81  * so only the time for one 10K packet and header plus a bit extra is needed.
  82  * 10 * 1024 + 64 header byte = 10304 byte
  83  * 10304 byte / 12.5 GB/s = 824.32ns
  84  */
  85 uint rcv_intr_timeout = (824 + 16); /* 16 is for coalescing interrupt */
  86 module_param(rcv_intr_timeout, uint, S_IRUGO);
  87 MODULE_PARM_DESC(rcv_intr_timeout, "Receive interrupt mitigation timeout in ns");
  88
  89 uint rcv_intr_count = 16; /* same as qib */
  90 module_param(rcv_intr_count, uint, S_IRUGO);
  91 MODULE_PARM_DESC(rcv_intr_count, "Receive interrupt mitigation count");
  92
  93 ushort link_crc_mask = SUPPORTED_CRCS;
  94 module_param(link_crc_mask, ushort, S_IRUGO);
  95 MODULE_PARM_DESC(link_crc_mask, "CRCs to use on the link");
  96
  97 uint loopback;
  98 module_param_named(loopback, loopback, uint, S_IRUGO);
  99 MODULE_PARM_DESC(loopback, "Put into loopback mode (1 = serdes, 3 = external cable");
 100
 101 /* Other driver tunables */
 102 uint rcv_intr_dynamic = 1; /* enable dynamic mode for rcv int mitigation*/
 103 static ushort crc_14b_sideband = 1;
 104 static uint use_flr = 1;
 105 uint quick_linkup; /* skip LNI */
 106
 107 struct flag_table {
 108         u64 flag;       /* the flag */
 109         char *str;      /* description string */
 110         u16 extra;      /* extra information */
 111         u16 unused0;
 112         u32 unused1;
 113 };
 114
 115 /* str must be a string constant */
 116 #define FLAG_ENTRY(str, extra, flag) {flag, str, extra}
 117 #define FLAG_ENTRY0(str, flag) {flag, str, 0}
 118
 119 /* Send Error Consequences */
 120 #define SEC_WRITE_DROPPED       0x1
 121 #define SEC_PACKET_DROPPED      0x2
 122 #define SEC_SC_HALTED           0x4     /* per-context only */
 123 #define SEC_SPC_FREEZE          0x8     /* per-HFI only */
 124
 125 #define DEFAULT_KRCVQS            2
 126 #define MIN_KERNEL_KCTXTS         2
 127 #define FIRST_KERNEL_KCTXT        1
 128 /* sizes for both the QP and RSM map tables */
 129 #define NUM_MAP_ENTRIES         256
 130 #define NUM_MAP_REGS             32
 131
 132 /* Bit offset into the GUID which carries HFI id information */
 133 #define GUID_HFI_INDEX_SHIFT     39
 134
 135 /* extract the emulation revision */
 136 #define emulator_rev(dd) ((dd)->irev >> 8)
 137 /* parallel and serial emulation versions are 3 and 4 respectively */
 138 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3)
 139 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4)
 140
 141 /* RSM fields */
 142
 143 /* packet type */
 144 #define IB_PACKET_TYPE         2ull
 145 #define QW_SHIFT               6ull
 146 /* QPN[7..1] */
 147 #define QPN_WIDTH              7ull
 148
 149 /* LRH.BTH: QW 0, OFFSET 48 - for match */
 150 #define LRH_BTH_QW             0ull
 151 #define LRH_BTH_BIT_OFFSET     48ull
 152 #define LRH_BTH_OFFSET(off)    ((LRH_BTH_QW << QW_SHIFT) | (off))
 153 #define LRH_BTH_MATCH_OFFSET   LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET)
 154 #define LRH_BTH_SELECT
 155 #define LRH_BTH_MASK           3ull
 156 #define LRH_BTH_VALUE          2ull
 157
 158 /* LRH.SC[3..0] QW 0, OFFSET 56 - for match */
 159 #define LRH_SC_QW              0ull
 160 #define LRH_SC_BIT_OFFSET      56ull
 161 #define LRH_SC_OFFSET(off)     ((LRH_SC_QW << QW_SHIFT) | (off))
 162 #define LRH_SC_MATCH_OFFSET    LRH_SC_OFFSET(LRH_SC_BIT_OFFSET)
 163 #define LRH_SC_MASK            128ull
 164 #define LRH_SC_VALUE           0ull
 165
 166 /* SC[n..0] QW 0, OFFSET 60 - for select */
 167 #define LRH_SC_SELECT_OFFSET  ((LRH_SC_QW << QW_SHIFT) | (60ull))
 168
 169 /* QPN[m+n:1] QW 1, OFFSET 1 */
 170 #define QPN_SELECT_OFFSET      ((1ull << QW_SHIFT) | (1ull))
 171
 172 /* defines to build power on SC2VL table */
 173 #define SC2VL_VAL( \
 174         num, \
 175         sc0, sc0val, \
 176         sc1, sc1val, \
 177         sc2, sc2val, \
 178         sc3, sc3val, \
 179         sc4, sc4val, \
 180         sc5, sc5val, \
 181         sc6, sc6val, \
 182         sc7, sc7val) \
 183 ( \
 184         ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \
 185         ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \
 186         ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \
 187         ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \
 188         ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \
 189         ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \
 190         ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \
 191         ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT)   \
 192 )
 193
 194 #define DC_SC_VL_VAL( \
 195         range, \
 196         e0, e0val, \
 197         e1, e1val, \
 198         e2, e2val, \
 199         e3, e3val, \
 200         e4, e4val, \
 201         e5, e5val, \
 202         e6, e6val, \
 203         e7, e7val, \
 204         e8, e8val, \
 205         e9, e9val, \
 206         e10, e10val, \
 207         e11, e11val, \
 208         e12, e12val, \
 209         e13, e13val, \
 210         e14, e14val, \
 211         e15, e15val) \
 212 ( \
 213         ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \
 214         ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \
 215         ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \
 216         ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \
 217         ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \
 218         ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \
 219         ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \
 220         ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \
 221         ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \
 222         ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \
 223         ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \
 224         ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \
 225         ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \
 226         ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \
 227         ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \
 228         ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \
 229 )
 230
 231 /* all CceStatus sub-block freeze bits */
 232 #define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \
 233                         | CCE_STATUS_RXE_FROZE_SMASK \
 234                         | CCE_STATUS_TXE_FROZE_SMASK \
 235                         | CCE_STATUS_TXE_PIO_FROZE_SMASK)
 236 /* all CceStatus sub-block TXE pause bits */
 237 #define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \
 238                         | CCE_STATUS_TXE_PAUSED_SMASK \
 239                         | CCE_STATUS_SDMA_PAUSED_SMASK)
 240 /* all CceStatus sub-block RXE pause bits */
 241 #define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK
 242
 243 #define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL
 244 #define CNTR_32BIT_MAX 0x00000000FFFFFFFF
 245
 246 /*
 247  * CCE Error flags.
 248  */
 249 static struct flag_table cce_err_status_flags[] = {
 250 /* 0*/  FLAG_ENTRY0("CceCsrParityErr",
 251                 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK),
 252 /* 1*/  FLAG_ENTRY0("CceCsrReadBadAddrErr",
 253                 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK),
 254 /* 2*/  FLAG_ENTRY0("CceCsrWriteBadAddrErr",
 255                 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK),
 256 /* 3*/  FLAG_ENTRY0("CceTrgtAsyncFifoParityErr",
 257                 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK),
 258 /* 4*/  FLAG_ENTRY0("CceTrgtAccessErr",
 259                 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK),
 260 /* 5*/  FLAG_ENTRY0("CceRspdDataParityErr",
 261                 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK),
 262 /* 6*/  FLAG_ENTRY0("CceCli0AsyncFifoParityErr",
 263                 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK),
 264 /* 7*/  FLAG_ENTRY0("CceCsrCfgBusParityErr",
 265                 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK),
 266 /* 8*/  FLAG_ENTRY0("CceCli2AsyncFifoParityErr",
 267                 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK),
 268 /* 9*/  FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
 269             CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK),
 270 /*10*/  FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
 271             CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK),
 272 /*11*/  FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError",
 273             CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK),
 274 /*12*/  FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError",
 275                 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK),
 276 /*13*/  FLAG_ENTRY0("PcicRetryMemCorErr",
 277                 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK),
 278 /*14*/  FLAG_ENTRY0("PcicRetryMemCorErr",
 279                 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK),
 280 /*15*/  FLAG_ENTRY0("PcicPostHdQCorErr",
 281                 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK),
 282 /*16*/  FLAG_ENTRY0("PcicPostHdQCorErr",
 283                 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK),
 284 /*17*/  FLAG_ENTRY0("PcicPostHdQCorErr",
 285                 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK),
 286 /*18*/  FLAG_ENTRY0("PcicCplDatQCorErr",
 287                 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK),
 288 /*19*/  FLAG_ENTRY0("PcicNPostHQParityErr",
 289                 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK),
 290 /*20*/  FLAG_ENTRY0("PcicNPostDatQParityErr",
 291                 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK),
 292 /*21*/  FLAG_ENTRY0("PcicRetryMemUncErr",
 293                 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK),
 294 /*22*/  FLAG_ENTRY0("PcicRetrySotMemUncErr",
 295                 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK),
 296 /*23*/  FLAG_ENTRY0("PcicPostHdQUncErr",
 297                 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK),
 298 /*24*/  FLAG_ENTRY0("PcicPostDatQUncErr",
 299                 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK),
 300 /*25*/  FLAG_ENTRY0("PcicCplHdQUncErr",
 301                 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK),
 302 /*26*/  FLAG_ENTRY0("PcicCplDatQUncErr",
 303                 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK),
 304 /*27*/  FLAG_ENTRY0("PcicTransmitFrontParityErr",
 305                 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK),
 306 /*28*/  FLAG_ENTRY0("PcicTransmitBackParityErr",
 307                 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK),
 308 /*29*/  FLAG_ENTRY0("PcicReceiveParityErr",
 309                 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK),
 310 /*30*/  FLAG_ENTRY0("CceTrgtCplTimeoutErr",
 311                 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK),
 312 /*31*/  FLAG_ENTRY0("LATriggered",
 313                 CCE_ERR_STATUS_LA_TRIGGERED_SMASK),
 314 /*32*/  FLAG_ENTRY0("CceSegReadBadAddrErr",
 315                 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK),
 316 /*33*/  FLAG_ENTRY0("CceSegWriteBadAddrErr",
 317                 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK),
 318 /*34*/  FLAG_ENTRY0("CceRcplAsyncFifoParityErr",
 319                 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK),
 320 /*35*/  FLAG_ENTRY0("CceRxdmaConvFifoParityErr",
 321                 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK),
 322 /*36*/  FLAG_ENTRY0("CceMsixTableCorErr",
 323                 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK),
 324 /*37*/  FLAG_ENTRY0("CceMsixTableUncErr",
 325                 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK),
 326 /*38*/  FLAG_ENTRY0("CceIntMapCorErr",
 327                 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK),
 328 /*39*/  FLAG_ENTRY0("CceIntMapUncErr",
 329                 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK),
 330 /*40*/  FLAG_ENTRY0("CceMsixCsrParityErr",
 331                 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK),
 332 /*41-63 reserved*/
 333 };
 334
 335 /*
 336  * Misc Error flags
 337  */
 338 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
 339 static struct flag_table misc_err_status_flags[] = {
 340 /* 0*/  FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)),
 341 /* 1*/  FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)),
 342 /* 2*/  FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)),
 343 /* 3*/  FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)),
 344 /* 4*/  FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)),
 345 /* 5*/  FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)),
 346 /* 6*/  FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)),
 347 /* 7*/  FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)),
 348 /* 8*/  FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)),
 349 /* 9*/  FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY)),
 350 /*10*/  FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD)),
 351 /*11*/  FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL)),
 352 /*12*/  FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL))
 353 };
 354
 355 /*
 356  * TXE PIO Error flags and consequences
 357  */
 358 static struct flag_table pio_err_status_flags[] = {
 359 /* 0*/  FLAG_ENTRY("PioWriteBadCtxt",
 360         SEC_WRITE_DROPPED,
 361         SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK),
 362 /* 1*/  FLAG_ENTRY("PioWriteAddrParity",
 363         SEC_SPC_FREEZE,
 364         SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK),
 365 /* 2*/  FLAG_ENTRY("PioCsrParity",
 366         SEC_SPC_FREEZE,
 367         SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK),
 368 /* 3*/  FLAG_ENTRY("PioSbMemFifo0",
 369         SEC_SPC_FREEZE,
 370         SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK),
 371 /* 4*/  FLAG_ENTRY("PioSbMemFifo1",
 372         SEC_SPC_FREEZE,
 373         SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK),
 374 /* 5*/  FLAG_ENTRY("PioPccFifoParity",
 375         SEC_SPC_FREEZE,
 376         SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK),
 377 /* 6*/  FLAG_ENTRY("PioPecFifoParity",
 378         SEC_SPC_FREEZE,
 379         SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK),
 380 /* 7*/  FLAG_ENTRY("PioSbrdctlCrrelParity",
 381         SEC_SPC_FREEZE,
 382         SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK),
 383 /* 8*/  FLAG_ENTRY("PioSbrdctrlCrrelFifoParity",
 384         SEC_SPC_FREEZE,
 385         SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK),
 386 /* 9*/  FLAG_ENTRY("PioPktEvictFifoParityErr",
 387         SEC_SPC_FREEZE,
 388         SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK),
 389 /*10*/  FLAG_ENTRY("PioSmPktResetParity",
 390         SEC_SPC_FREEZE,
 391         SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK),
 392 /*11*/  FLAG_ENTRY("PioVlLenMemBank0Unc",
 393         SEC_SPC_FREEZE,
 394         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK),
 395 /*12*/  FLAG_ENTRY("PioVlLenMemBank1Unc",
 396         SEC_SPC_FREEZE,
 397         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK),
 398 /*13*/  FLAG_ENTRY("PioVlLenMemBank0Cor",
 399         0,
 400         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK),
 401 /*14*/  FLAG_ENTRY("PioVlLenMemBank1Cor",
 402         0,
 403         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK),
 404 /*15*/  FLAG_ENTRY("PioCreditRetFifoParity",
 405         SEC_SPC_FREEZE,
 406         SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK),
 407 /*16*/  FLAG_ENTRY("PioPpmcPblFifo",
 408         SEC_SPC_FREEZE,
 409         SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK),
 410 /*17*/  FLAG_ENTRY("PioInitSmIn",
 411         0,
 412         SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK),
 413 /*18*/  FLAG_ENTRY("PioPktEvictSmOrArbSm",
 414         SEC_SPC_FREEZE,
 415         SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK),
 416 /*19*/  FLAG_ENTRY("PioHostAddrMemUnc",
 417         SEC_SPC_FREEZE,
 418         SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK),
 419 /*20*/  FLAG_ENTRY("PioHostAddrMemCor",
 420         0,
 421         SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK),
 422 /*21*/  FLAG_ENTRY("PioWriteDataParity",
 423         SEC_SPC_FREEZE,
 424         SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK),
 425 /*22*/  FLAG_ENTRY("PioStateMachine",
 426         SEC_SPC_FREEZE,
 427         SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK),
 428 /*23*/  FLAG_ENTRY("PioWriteQwValidParity",
 429         SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
 430         SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK),
 431 /*24*/  FLAG_ENTRY("PioBlockQwCountParity",
 432         SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
 433         SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK),
 434 /*25*/  FLAG_ENTRY("PioVlfVlLenParity",
 435         SEC_SPC_FREEZE,
 436         SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK),
 437 /*26*/  FLAG_ENTRY("PioVlfSopParity",
 438         SEC_SPC_FREEZE,
 439         SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK),
 440 /*27*/  FLAG_ENTRY("PioVlFifoParity",
 441         SEC_SPC_FREEZE,
 442         SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK),
 443 /*28*/  FLAG_ENTRY("PioPpmcBqcMemParity",
 444         SEC_SPC_FREEZE,
 445         SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK),
 446 /*29*/  FLAG_ENTRY("PioPpmcSopLen",
 447         SEC_SPC_FREEZE,
 448         SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK),
 449 /*30-31 reserved*/
 450 /*32*/  FLAG_ENTRY("PioCurrentFreeCntParity",
 451         SEC_SPC_FREEZE,
 452         SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK),
 453 /*33*/  FLAG_ENTRY("PioLastReturnedCntParity",
 454         SEC_SPC_FREEZE,
 455         SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK),
 456 /*34*/  FLAG_ENTRY("PioPccSopHeadParity",
 457         SEC_SPC_FREEZE,
 458         SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK),
 459 /*35*/  FLAG_ENTRY("PioPecSopHeadParityErr",
 460         SEC_SPC_FREEZE,
 461         SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK),
 462 /*36-63 reserved*/
 463 };
 464
 465 /* TXE PIO errors that cause an SPC freeze */
 466 #define ALL_PIO_FREEZE_ERR \
 467         (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \
 468         | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \
 469         | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \
 470         | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \
 471         | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \
 472         | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \
 473         | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \
 474         | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
 475         | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \
 476         | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \
 477         | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \
 478         | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \
 479         | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \
 480         | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \
 481         | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \
 482         | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \
 483         | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \
 484         | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \
 485         | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \
 486         | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
 487         | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \
 488         | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \
 489         | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \
 490         | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \
 491         | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \
 492         | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
 493         | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
 494         | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
 495         | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK)
 496
 497 /*
 498  * TXE SDMA Error flags
 499  */
 500 static struct flag_table sdma_err_status_flags[] = {
 501 /* 0*/  FLAG_ENTRY0("SDmaRpyTagErr",
 502                 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK),
 503 /* 1*/  FLAG_ENTRY0("SDmaCsrParityErr",
 504                 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK),
 505 /* 2*/  FLAG_ENTRY0("SDmaPcieReqTrackingUncErr",
 506                 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK),
 507 /* 3*/  FLAG_ENTRY0("SDmaPcieReqTrackingCorErr",
 508                 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK),
 509 /*04-63 reserved*/
 510 };
 511
 512 /* TXE SDMA errors that cause an SPC freeze */
 513 #define ALL_SDMA_FREEZE_ERR  \
 514                 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \
 515                 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \
 516                 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK)
 517
 518 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
 519 #define PORT_DISCARD_EGRESS_ERRS \
 520         (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \
 521         | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \
 522         | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK)
 523
 524 /*
 525  * TXE Egress Error flags
 526  */
 527 #define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
 528 static struct flag_table egress_err_status_flags[] = {
 529 /* 0*/  FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)),
 530 /* 1*/  FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)),
 531 /* 2 reserved */
 532 /* 3*/  FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr",
 533                 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY)),
 534 /* 4*/  FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN)),
 535 /* 5*/  FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE)),
 536 /* 6 reserved */
 537 /* 7*/  FLAG_ENTRY0("TxPioLaunchIntfParityErr",
 538                 SEES(TX_PIO_LAUNCH_INTF_PARITY)),
 539 /* 8*/  FLAG_ENTRY0("TxSdmaLaunchIntfParityErr",
 540                 SEES(TX_SDMA_LAUNCH_INTF_PARITY)),
 541 /* 9-10 reserved */
 542 /*11*/  FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr",
 543                 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY)),
 544 /*12*/  FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL)),
 545 /*13*/  FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY)),
 546 /*14*/  FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY)),
 547 /*15*/  FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY)),
 548 /*16*/  FLAG_ENTRY0("TxSdma0DisallowedPacketErr",
 549                 SEES(TX_SDMA0_DISALLOWED_PACKET)),
 550 /*17*/  FLAG_ENTRY0("TxSdma1DisallowedPacketErr",
 551                 SEES(TX_SDMA1_DISALLOWED_PACKET)),
 552 /*18*/  FLAG_ENTRY0("TxSdma2DisallowedPacketErr",
 553                 SEES(TX_SDMA2_DISALLOWED_PACKET)),
 554 /*19*/  FLAG_ENTRY0("TxSdma3DisallowedPacketErr",
 555                 SEES(TX_SDMA3_DISALLOWED_PACKET)),
 556 /*20*/  FLAG_ENTRY0("TxSdma4DisallowedPacketErr",
 557                 SEES(TX_SDMA4_DISALLOWED_PACKET)),
 558 /*21*/  FLAG_ENTRY0("TxSdma5DisallowedPacketErr",
 559                 SEES(TX_SDMA5_DISALLOWED_PACKET)),
 560 /*22*/  FLAG_ENTRY0("TxSdma6DisallowedPacketErr",
 561                 SEES(TX_SDMA6_DISALLOWED_PACKET)),
 562 /*23*/  FLAG_ENTRY0("TxSdma7DisallowedPacketErr",
 563                 SEES(TX_SDMA7_DISALLOWED_PACKET)),
 564 /*24*/  FLAG_ENTRY0("TxSdma8DisallowedPacketErr",
 565                 SEES(TX_SDMA8_DISALLOWED_PACKET)),
 566 /*25*/  FLAG_ENTRY0("TxSdma9DisallowedPacketErr",
 567                 SEES(TX_SDMA9_DISALLOWED_PACKET)),
 568 /*26*/  FLAG_ENTRY0("TxSdma10DisallowedPacketErr",
 569                 SEES(TX_SDMA10_DISALLOWED_PACKET)),
 570 /*27*/  FLAG_ENTRY0("TxSdma11DisallowedPacketErr",
 571                 SEES(TX_SDMA11_DISALLOWED_PACKET)),
 572 /*28*/  FLAG_ENTRY0("TxSdma12DisallowedPacketErr",
 573                 SEES(TX_SDMA12_DISALLOWED_PACKET)),
 574 /*29*/  FLAG_ENTRY0("TxSdma13DisallowedPacketErr",
 575                 SEES(TX_SDMA13_DISALLOWED_PACKET)),
 576 /*30*/  FLAG_ENTRY0("TxSdma14DisallowedPacketErr",
 577                 SEES(TX_SDMA14_DISALLOWED_PACKET)),
 578 /*31*/  FLAG_ENTRY0("TxSdma15DisallowedPacketErr",
 579                 SEES(TX_SDMA15_DISALLOWED_PACKET)),
 580 /*32*/  FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr",
 581                 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY)),
 582 /*33*/  FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr",
 583                 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY)),
 584 /*34*/  FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr",
 585                 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY)),
 586 /*35*/  FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr",
 587                 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY)),
 588 /*36*/  FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr",
 589                 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY)),
 590 /*37*/  FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr",
 591                 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY)),
 592 /*38*/  FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr",
 593                 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY)),
 594 /*39*/  FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr",
 595                 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY)),
 596 /*40*/  FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr",
 597                 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY)),
 598 /*41*/  FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY)),
 599 /*42*/  FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC)),
 600 /*43*/  FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC)),
 601 /*44*/  FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC)),
 602 /*45*/  FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC)),
 603 /*46*/  FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION)),
 604 /*47*/  FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL)),
 605 /*48*/  FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR)),
 606 /*49*/  FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR)),
 607 /*50*/  FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR)),
 608 /*51*/  FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR)),
 609 /*52*/  FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR)),
 610 /*53*/  FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR)),
 611 /*54*/  FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR)),
 612 /*55*/  FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR)),
 613 /*56*/  FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR)),
 614 /*57*/  FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN)),
 615 /*58*/  FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR)),
 616 /*59*/  FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR)),
 617 /*60*/  FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR)),
 618 /*61*/  FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR)),
 619 /*62*/  FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr",
 620                 SEES(TX_READ_SDMA_MEMORY_CSR_UNC)),
 621 /*63*/  FLAG_ENTRY0("TxReadPioMemoryCsrUncErr",
 622                 SEES(TX_READ_PIO_MEMORY_CSR_UNC)),
 623 };
 624
 625 /*
 626  * TXE Egress Error Info flags
 627  */
 628 #define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
 629 static struct flag_table egress_err_info_flags[] = {
 630 /* 0*/  FLAG_ENTRY0("Reserved", 0ull),
 631 /* 1*/  FLAG_ENTRY0("VLErr", SEEI(VL)),
 632 /* 2*/  FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
 633 /* 3*/  FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
 634 /* 4*/  FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY)),
 635 /* 5*/  FLAG_ENTRY0("SLIDErr", SEEI(SLID)),
 636 /* 6*/  FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE)),
 637 /* 7*/  FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING)),
 638 /* 8*/  FLAG_ENTRY0("RawErr", SEEI(RAW)),
 639 /* 9*/  FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6)),
 640 /*10*/  FLAG_ENTRY0("GRHErr", SEEI(GRH)),
 641 /*11*/  FLAG_ENTRY0("BypassErr", SEEI(BYPASS)),
 642 /*12*/  FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS)),
 643 /*13*/  FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS)),
 644 /*14*/  FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS)),
 645 /*15*/  FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS)),
 646 /*16*/  FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST)),
 647 /*17*/  FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN)),
 648 /*18*/  FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET)),
 649 /*19*/  FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS)),
 650 /*20*/  FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL)),
 651 /*21*/  FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN)),
 652 };
 653
 654 /* TXE Egress errors that cause an SPC freeze */
 655 #define ALL_TXE_EGRESS_FREEZE_ERR \
 656         (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \
 657         | SEES(TX_PIO_LAUNCH_INTF_PARITY) \
 658         | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \
 659         | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \
 660         | SEES(TX_LAUNCH_CSR_PARITY) \
 661         | SEES(TX_SBRD_CTL_CSR_PARITY) \
 662         | SEES(TX_CONFIG_PARITY) \
 663         | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \
 664         | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \
 665         | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \
 666         | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \
 667         | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \
 668         | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \
 669         | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \
 670         | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \
 671         | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \
 672         | SEES(TX_CREDIT_RETURN_PARITY))
 673
 674 /*
 675  * TXE Send error flags
 676  */
 677 #define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
 678 static struct flag_table send_err_status_flags[] = {
 679 /* 0*/  FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)),
 680 /* 1*/  FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)),
 681 /* 2*/  FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR))
 682 };
 683
 684 /*
 685  * TXE Send Context Error flags and consequences
 686  */
 687 static struct flag_table sc_err_status_flags[] = {
 688 /* 0*/  FLAG_ENTRY("InconsistentSop",
 689                 SEC_PACKET_DROPPED | SEC_SC_HALTED,
 690                 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK),
 691 /* 1*/  FLAG_ENTRY("DisallowedPacket",
 692                 SEC_PACKET_DROPPED | SEC_SC_HALTED,
 693                 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK),
 694 /* 2*/  FLAG_ENTRY("WriteCrossesBoundary",
 695                 SEC_WRITE_DROPPED | SEC_SC_HALTED,
 696                 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK),
 697 /* 3*/  FLAG_ENTRY("WriteOverflow",
 698                 SEC_WRITE_DROPPED | SEC_SC_HALTED,
 699                 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK),
 700 /* 4*/  FLAG_ENTRY("WriteOutOfBounds",
 701                 SEC_WRITE_DROPPED | SEC_SC_HALTED,
 702                 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK),
 703 /* 5-63 reserved*/
 704 };
 705
 706 /*
 707  * RXE Receive Error flags
 708  */
 709 #define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
 710 static struct flag_table rxe_err_status_flags[] = {
 711 /* 0*/  FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)),
 712 /* 1*/  FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)),
 713 /* 2*/  FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)),
 714 /* 3*/  FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR)),
 715 /* 4*/  FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC)),
 716 /* 5*/  FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR)),
 717 /* 6*/  FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC)),
 718 /* 7*/  FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR)),
 719 /* 8*/  FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY)),
 720 /* 9*/  FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY)),
 721 /*10*/  FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC)),
 722 /*11*/  FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR)),
 723 /*12*/  FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING)),
 724 /*13*/  FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC)),
 725 /*14*/  FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR)),
 726 /*15*/  FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC)),
 727 /*16*/  FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr",
 728                 RXES(RBUF_LOOKUP_DES_REG_UNC_COR)),
 729 /*17*/  FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC)),
 730 /*18*/  FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR)),
 731 /*19*/  FLAG_ENTRY0("RxRbufBlockListReadUncErr",
 732                 RXES(RBUF_BLOCK_LIST_READ_UNC)),
 733 /*20*/  FLAG_ENTRY0("RxRbufBlockListReadCorErr",
 734                 RXES(RBUF_BLOCK_LIST_READ_COR)),
 735 /*21*/  FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr",
 736                 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY)),
 737 /*22*/  FLAG_ENTRY0("RxRbufCsrQEntCntParityErr",
 738                 RXES(RBUF_CSR_QENT_CNT_PARITY)),
 739 /*23*/  FLAG_ENTRY0("RxRbufCsrQNextBufParityErr",
 740                 RXES(RBUF_CSR_QNEXT_BUF_PARITY)),
 741 /*24*/  FLAG_ENTRY0("RxRbufCsrQVldBitParityErr",
 742                 RXES(RBUF_CSR_QVLD_BIT_PARITY)),
 743 /*25*/  FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY)),
 744 /*26*/  FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY)),
 745 /*27*/  FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr",
 746                 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY)),
 747 /*28*/  FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY)),
 748 /*29*/  FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY)),
 749 /*30*/  FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP)),
 750 /*31*/  FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL)),
 751 /*32*/  FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY)),
 752 /*33*/  FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY)),
 753 /*34*/  FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY)),
 754 /*35*/  FLAG_ENTRY0("RxRbufFlInitdoneParityErr",
 755                 RXES(RBUF_FL_INITDONE_PARITY)),
 756 /*36*/  FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr",
 757                 RXES(RBUF_FL_INIT_WR_ADDR_PARITY)),
 758 /*37*/  FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC)),
 759 /*38*/  FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR)),
 760 /*39*/  FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC)),
 761 /*40*/  FLAG_ENTRY0("RxLookupDesPart1UncCorErr",
 762                 RXES(LOOKUP_DES_PART1_UNC_COR)),
 763 /*41*/  FLAG_ENTRY0("RxLookupDesPart2ParityErr",
 764                 RXES(LOOKUP_DES_PART2_PARITY)),
 765 /*42*/  FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC)),
 766 /*43*/  FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR)),
 767 /*44*/  FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY)),
 768 /*45*/  FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY)),
 769 /*46*/  FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM)),
 770 /*47*/  FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC)),
 771 /*48*/  FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR)),
 772 /*49*/  FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC)),
 773 /*50*/  FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR)),
 774 /*51*/  FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC)),
 775 /*52*/  FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR)),
 776 /*53*/  FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC)),
 777 /*54*/  FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR)),
 778 /*55*/  FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC)),
 779 /*56*/  FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR)),
 780 /*57*/  FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY)),
 781 /*58*/  FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING)),
 782 /*59*/  FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING)),
 783 /*60*/  FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC)),
 784 /*61*/  FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR)),
 785 /*62*/  FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR)),
 786 /*63*/  FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY))
 787 };
 788
 789 /* RXE errors that will trigger an SPC freeze */
 790 #define ALL_RXE_FREEZE_ERR  \
 791         (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \
 792         | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \
 793         | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \
 794         | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \
 795         | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \
 796         | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \
 797         | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \
 798         | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \
 799         | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \
 800         | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
 801         | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \
 802         | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \
 803         | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \
 804         | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \
 805         | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \
 806         | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
 807         | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \
 808         | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \
 809         | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \
 810         | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \
 811         | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \
 812         | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \
 813         | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \
 814         | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \
 815         | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
 816         | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \
 817         | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \
 818         | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
 819         | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
 820         | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \
 821         | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \
 822         | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \
 823         | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \
 824         | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \
 825         | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \
 826         | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \
 827         | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \
 828         | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
 829         | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \
 830         | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \
 831         | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
 832         | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
 833         | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \
 834         | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK)
 835
 836 #define RXE_FREEZE_ABORT_MASK \
 837         (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \
 838         RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \
 839         RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK)
 840
 841 /*
 842  * DCC Error Flags
 843  */
 844 #define DCCE(name) DCC_ERR_FLG_##name##_SMASK
 845 static struct flag_table dcc_err_flags[] = {
 846         FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)),
 847         FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)),
 848         FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)),
 849         FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR)),
 850         FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR)),
 851         FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR)),
 852         FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR)),
 853         FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR)),
 854         FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR)),
 855         FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR)),
 856         FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR)),
 857         FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE)),
 858         FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR)),
 859         FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR)),
 860         FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR)),
 861         FLAG_ENTRY0("link_err", DCCE(LINK_ERR)),
 862         FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR)),
 863         FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR)),
 864         FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR)),
 865         FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR)),
 866         FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR)),
 867         FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR)),
 868         FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR)),
 869         FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR)),
 870         FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR)),
 871         FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR)),
 872         FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR)),
 873         FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR)),
 874         FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR)),
 875         FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR)),
 876         FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR)),
 877         FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR)),
 878         FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR)),
 879         FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR)),
 880         FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST)),
 881         FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC)),
 882         FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR)),
 883         FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR)),
 884         FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR)),
 885         FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR)),
 886         FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR)),
 887         FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR)),
 888         FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR)),
 889         FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR)),
 890         FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR)),
 891         FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR)),
 892 };
 893
 894 /*
 895  * LCB error flags
 896  */
 897 #define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
 898 static struct flag_table lcb_err_flags[] = {
 899 /* 0*/  FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)),
 900 /* 1*/  FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)),
 901 /* 2*/  FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)),
 902 /* 3*/  FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST",
 903                 LCBE(ALL_LNS_FAILED_REINIT_TEST)),
 904 /* 4*/  FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS)),
 905 /* 5*/  FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS)),
 906 /* 6*/  FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS)),
 907 /* 7*/  FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR)),
 908 /* 8*/  FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER)),
 909 /* 9*/  FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE)),
 910 /*10*/  FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT)),
 911 /*11*/  FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED)),
 912 /*12*/  FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER)),
 913 /*13*/  FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER",
 914                 LCBE(UNEXPECTED_ROUND_TRIP_MARKER)),
 915 /*14*/  FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP)),
 916 /*15*/  FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING)),
 917 /*16*/  FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW)),
 918 /*17*/  FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW)),
 919 /*18*/  FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR)),
 920 /*19*/  FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE",
 921                 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE)),
 922 /*20*/  FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE)),
 923 /*21*/  FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE)),
 924 /*22*/  FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE)),
 925 /*23*/  FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE)),
 926 /*24*/  FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE)),
 927 /*25*/  FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT)),
 928 /*26*/  FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP",
 929                 LCBE(RST_FOR_INCOMPLT_RND_TRIP)),
 930 /*27*/  FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT)),
 931 /*28*/  FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE",
 932                 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE)),
 933 /*29*/  FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR",
 934                 LCBE(REDUNDANT_FLIT_PARITY_ERR))
 935 };
 936
 937 /*
 938  * DC8051 Error Flags
 939  */
 940 #define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
 941 static struct flag_table dc8051_err_flags[] = {
 942         FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)),
 943         FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)),
 944         FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)),
 945         FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE)),
 946         FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE)),
 947         FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE)),
 948         FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE)),
 949         FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE)),
 950         FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES",
 951                     D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES)),
 952         FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR)),
 953 };
 954
 955 /*
 956  * DC8051 Information Error flags
 957  *
 958  * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
 959  */
 960 static struct flag_table dc8051_info_err_flags[] = {
 961         FLAG_ENTRY0("Spico ROM check failed",  SPICO_ROM_FAILED),
 962         FLAG_ENTRY0("Unknown frame received",  UNKNOWN_FRAME),
 963         FLAG_ENTRY0("Target BER not met",      TARGET_BER_NOT_MET),
 964         FLAG_ENTRY0("Serdes internal loopback failure",
 965                     FAILED_SERDES_INTERNAL_LOOPBACK),
 966         FLAG_ENTRY0("Failed SerDes init",      FAILED_SERDES_INIT),
 967         FLAG_ENTRY0("Failed LNI(Polling)",     FAILED_LNI_POLLING),
 968         FLAG_ENTRY0("Failed LNI(Debounce)",    FAILED_LNI_DEBOUNCE),
 969         FLAG_ENTRY0("Failed LNI(EstbComm)",    FAILED_LNI_ESTBCOMM),
 970         FLAG_ENTRY0("Failed LNI(OptEq)",       FAILED_LNI_OPTEQ),
 971         FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1),
 972         FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2),
 973         FLAG_ENTRY0("Failed LNI(ConfigLT)",    FAILED_LNI_CONFIGLT),
 974         FLAG_ENTRY0("Host Handshake Timeout",  HOST_HANDSHAKE_TIMEOUT)
 975 };
 976
 977 /*
 978  * DC8051 Information Host Information flags
 979  *
 980  * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
 981  */
 982 static struct flag_table dc8051_info_host_msg_flags[] = {
 983         FLAG_ENTRY0("Host request done", 0x0001),
 984         FLAG_ENTRY0("BC SMA message", 0x0002),
 985         FLAG_ENTRY0("BC PWR_MGM message", 0x0004),
 986         FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008),
 987         FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010),
 988         FLAG_ENTRY0("External device config request", 0x0020),
 989         FLAG_ENTRY0("VerifyCap all frames received", 0x0040),
 990         FLAG_ENTRY0("LinkUp achieved", 0x0080),
 991         FLAG_ENTRY0("Link going down", 0x0100),
 992 };
 993
 994 static u32 encoded_size(u32 size);
 995 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate);
 996 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state);
 997 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
 998                                u8 *continuous);
 999 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
1000                                   u8 *vcu, u16 *vl15buf, u8 *crc_sizes);
1001 static void read_vc_remote_link_width(struct hfi1_devdata *dd,
1002                                       u8 *remote_tx_rate, u16 *link_widths);
1003 static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
1004                                      u8 *flag_bits, u16 *link_widths);
1005 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
1006                                   u8 *device_rev);
1007 static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed);
1008 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx);
1009 static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx,
1010                             u8 *tx_polarity_inversion,
1011                             u8 *rx_polarity_inversion, u8 *max_rate);
1012 static void handle_sdma_eng_err(struct hfi1_devdata *dd,
1013                                 unsigned int context, u64 err_status);
1014 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg);
1015 static void handle_dcc_err(struct hfi1_devdata *dd,
1016                            unsigned int context, u64 err_status);
1017 static void handle_lcb_err(struct hfi1_devdata *dd,
1018                            unsigned int context, u64 err_status);
1019 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg);
1020 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1021 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1022 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1023 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1024 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1025 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1026 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1027 static void set_partition_keys(struct hfi1_pportdata *);
1028 static const char *link_state_name(u32 state);
1029 static const char *link_state_reason_name(struct hfi1_pportdata *ppd,
1030                                           u32 state);
1031 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data,
1032                            u64 *out_data);
1033 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data);
1034 static int thermal_init(struct hfi1_devdata *dd);
1035
1036 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
1037                                   int msecs);
1038 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc);
1039 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr);
1040 static void handle_temp_err(struct hfi1_devdata *);
1041 static void dc_shutdown(struct hfi1_devdata *);
1042 static void dc_start(struct hfi1_devdata *);
1043 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp,
1044                            unsigned int *np);
1045 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd);
1046
1047 /*
1048  * Error interrupt table entry.  This is used as input to the interrupt
1049  * "clear down" routine used for all second tier error interrupt register.
1050  * Second tier interrupt registers have a single bit representing them
1051  * in the top-level CceIntStatus.
1052  */
1053 struct err_reg_info {
1054         u32 status;             /* status CSR offset */
1055         u32 clear;              /* clear CSR offset */
1056         u32 mask;               /* mask CSR offset */
1057         void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg);
1058         const char *desc;
1059 };
1060
1061 #define NUM_MISC_ERRS (IS_GENERAL_ERR_END - IS_GENERAL_ERR_START)
1062 #define NUM_DC_ERRS (IS_DC_END - IS_DC_START)
1063 #define NUM_VARIOUS (IS_VARIOUS_END - IS_VARIOUS_START)
1064
1065 /*
1066  * Helpers for building HFI and DC error interrupt table entries.  Different
1067  * helpers are needed because of inconsistent register names.
1068  */
1069 #define EE(reg, handler, desc) \
1070         { reg##_STATUS, reg##_CLEAR, reg##_MASK, \
1071                 handler, desc }
1072 #define DC_EE1(reg, handler, desc) \
1073         { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc }
1074 #define DC_EE2(reg, handler, desc) \
1075         { reg##_FLG, reg##_CLR, reg##_EN, handler, desc }
1076
1077 /*
1078  * Table of the "misc" grouping of error interrupts.  Each entry refers to
1079  * another register containing more information.
1080  */
1081 static const struct err_reg_info misc_errs[NUM_MISC_ERRS] = {
1082 /* 0*/  EE(CCE_ERR,             handle_cce_err,    "CceErr"),
1083 /* 1*/  EE(RCV_ERR,             handle_rxe_err,    "RxeErr"),
1084 /* 2*/  EE(MISC_ERR,    handle_misc_err,   "MiscErr"),
1085 /* 3*/  { 0, 0, 0, NULL }, /* reserved */
1086 /* 4*/  EE(SEND_PIO_ERR,    handle_pio_err,    "PioErr"),
1087 /* 5*/  EE(SEND_DMA_ERR,    handle_sdma_err,   "SDmaErr"),
1088 /* 6*/  EE(SEND_EGRESS_ERR, handle_egress_err, "EgressErr"),
1089 /* 7*/  EE(SEND_ERR,    handle_txe_err,    "TxeErr")
1090         /* the rest are reserved */
1091 };
1092
1093 /*
1094  * Index into the Various section of the interrupt sources
1095  * corresponding to the Critical Temperature interrupt.
1096  */
1097 #define TCRIT_INT_SOURCE 4
1098
1099 /*
1100  * SDMA error interrupt entry - refers to another register containing more
1101  * information.
1102  */
1103 static const struct err_reg_info sdma_eng_err =
1104         EE(SEND_DMA_ENG_ERR, handle_sdma_eng_err, "SDmaEngErr");
1105
1106 static const struct err_reg_info various_err[NUM_VARIOUS] = {
1107 /* 0*/  { 0, 0, 0, NULL }, /* PbcInt */
1108 /* 1*/  { 0, 0, 0, NULL }, /* GpioAssertInt */
1109 /* 2*/  EE(ASIC_QSFP1,  handle_qsfp_int,        "QSFP1"),
1110 /* 3*/  EE(ASIC_QSFP2,  handle_qsfp_int,        "QSFP2"),
1111 /* 4*/  { 0, 0, 0, NULL }, /* TCritInt */
1112         /* rest are reserved */
1113 };
1114
1115 /*
1116  * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG
1117  * register can not be derived from the MTU value because 10K is not
1118  * a power of 2. Therefore, we need a constant. Everything else can
1119  * be calculated.
1120  */
1121 #define DCC_CFG_PORT_MTU_CAP_10240 7
1122
1123 /*
1124  * Table of the DC grouping of error interrupts.  Each entry refers to
1125  * another register containing more information.
1126  */
1127 static const struct err_reg_info dc_errs[NUM_DC_ERRS] = {
1128 /* 0*/  DC_EE1(DCC_ERR,         handle_dcc_err,        "DCC Err"),
1129 /* 1*/  DC_EE2(DC_LCB_ERR,      handle_lcb_err,        "LCB Err"),
1130 /* 2*/  DC_EE2(DC_DC8051_ERR,   handle_8051_interrupt, "DC8051 Interrupt"),
1131 /* 3*/  /* dc_lbm_int - special, see is_dc_int() */
1132         /* the rest are reserved */
1133 };
1134
1135 struct cntr_entry {
1136         /*
1137          * counter name
1138          */
1139         char *name;
1140
1141         /*
1142          * csr to read for name (if applicable)
1143          */
1144         u64 csr;
1145
1146         /*
1147          * offset into dd or ppd to store the counter's value
1148          */
1149         int offset;
1150
1151         /*
1152          * flags
1153          */
1154         u8 flags;
1155
1156         /*
1157          * accessor for stat element, context either dd or ppd
1158          */
1159         u64 (*rw_cntr)(const struct cntr_entry *, void *context, int vl,
1160                        int mode, u64 data);
1161 };
1162
1163 #define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0
1164 #define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159
1165
1166 #define CNTR_ELEM(name, csr, offset, flags, accessor) \
1167 { \
1168         name, \
1169         csr, \
1170         offset, \
1171         flags, \
1172         accessor \
1173 }
1174
1175 /* 32bit RXE */
1176 #define RXE32_PORT_CNTR_ELEM(name, counter, flags) \
1177 CNTR_ELEM(#name, \
1178           (counter * 8 + RCV_COUNTER_ARRAY32), \
1179           0, flags | CNTR_32BIT, \
1180           port_access_u32_csr)
1181
1182 #define RXE32_DEV_CNTR_ELEM(name, counter, flags) \
1183 CNTR_ELEM(#name, \
1184           (counter * 8 + RCV_COUNTER_ARRAY32), \
1185           0, flags | CNTR_32BIT, \
1186           dev_access_u32_csr)
1187
1188 /* 64bit RXE */
1189 #define RXE64_PORT_CNTR_ELEM(name, counter, flags) \
1190 CNTR_ELEM(#name, \
1191           (counter * 8 + RCV_COUNTER_ARRAY64), \
1192           0, flags, \
1193           port_access_u64_csr)
1194
1195 #define RXE64_DEV_CNTR_ELEM(name, counter, flags) \
1196 CNTR_ELEM(#name, \
1197           (counter * 8 + RCV_COUNTER_ARRAY64), \
1198           0, flags, \
1199           dev_access_u64_csr)
1200
1201 #define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx
1202 #define OVR_ELM(ctx) \
1203 CNTR_ELEM("RcvHdrOvr" #ctx, \
1204           (RCV_HDR_OVFL_CNT + ctx * 0x100), \
1205           0, CNTR_NORMAL, port_access_u64_csr)
1206
1207 /* 32bit TXE */
1208 #define TXE32_PORT_CNTR_ELEM(name, counter, flags) \
1209 CNTR_ELEM(#name, \
1210           (counter * 8 + SEND_COUNTER_ARRAY32), \
1211           0, flags | CNTR_32BIT, \
1212           port_access_u32_csr)
1213
1214 /* 64bit TXE */
1215 #define TXE64_PORT_CNTR_ELEM(name, counter, flags) \
1216 CNTR_ELEM(#name, \
1217           (counter * 8 + SEND_COUNTER_ARRAY64), \
1218           0, flags, \
1219           port_access_u64_csr)
1220
1221 # define TX64_DEV_CNTR_ELEM(name, counter, flags) \
1222 CNTR_ELEM(#name,\
1223           counter * 8 + SEND_COUNTER_ARRAY64, \
1224           0, \
1225           flags, \
1226           dev_access_u64_csr)
1227
1228 /* CCE */
1229 #define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \
1230 CNTR_ELEM(#name, \
1231           (counter * 8 + CCE_COUNTER_ARRAY32), \
1232           0, flags | CNTR_32BIT, \
1233           dev_access_u32_csr)
1234
1235 #define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \
1236 CNTR_ELEM(#name, \
1237           (counter * 8 + CCE_INT_COUNTER_ARRAY32), \
1238           0, flags | CNTR_32BIT, \
1239           dev_access_u32_csr)
1240
1241 /* DC */
1242 #define DC_PERF_CNTR(name, counter, flags) \
1243 CNTR_ELEM(#name, \
1244           counter, \
1245           0, \
1246           flags, \
1247           dev_access_u64_csr)
1248
1249 #define DC_PERF_CNTR_LCB(name, counter, flags) \
1250 CNTR_ELEM(#name, \
1251           counter, \
1252           0, \
1253           flags, \
1254           dc_access_lcb_cntr)
1255
1256 /* ibp counters */
1257 #define SW_IBP_CNTR(name, cntr) \
1258 CNTR_ELEM(#name, \
1259           0, \
1260           0, \
1261           CNTR_SYNTH, \
1262           access_ibp_##cntr)
1263
1264 u64 read_csr(const struct hfi1_devdata *dd, u32 offset)
1265 {
1266         if (dd->flags & HFI1_PRESENT) {
1267                 return readq((void __iomem *)dd->kregbase + offset);
1268         }
1269         return -1;
1270 }
1271
1272 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value)
1273 {
1274         if (dd->flags & HFI1_PRESENT)
1275                 writeq(value, (void __iomem *)dd->kregbase + offset);
1276 }
1277
1278 void __iomem *get_csr_addr(
1279         struct hfi1_devdata *dd,
1280         u32 offset)
1281 {
1282         return (void __iomem *)dd->kregbase + offset;
1283 }
1284
1285 static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr,
1286                                  int mode, u64 value)
1287 {
1288         u64 ret;
1289
1290         if (mode == CNTR_MODE_R) {
1291                 ret = read_csr(dd, csr);
1292         } else if (mode == CNTR_MODE_W) {
1293                 write_csr(dd, csr, value);
1294                 ret = value;
1295         } else {
1296                 dd_dev_err(dd, "Invalid cntr register access mode");
1297                 return 0;
1298         }
1299
1300         hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);
1301         return ret;
1302 }
1303
1304 /* Dev Access */
1305 static u64 dev_access_u32_csr(const struct cntr_entry *entry,
1306                               void *context, int vl, int mode, u64 data)
1307 {
1308         struct hfi1_devdata *dd = context;
1309         u64 csr = entry->csr;
1310
1311         if (entry->flags & CNTR_SDMA) {
1312                 if (vl == CNTR_INVALID_VL)
1313                         return 0;
1314                 csr += 0x100 * vl;
1315         } else {
1316                 if (vl != CNTR_INVALID_VL)
1317                         return 0;
1318         }
1319         return read_write_csr(dd, csr, mode, data);
1320 }
1321
1322 static u64 access_sde_err_cnt(const struct cntr_entry *entry,
1323                               void *context, int idx, int mode, u64 data)
1324 {
1325         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1326
1327         if (dd->per_sdma && idx < dd->num_sdma)
1328                 return dd->per_sdma[idx].err_cnt;
1329         return 0;
1330 }
1331
1332 static u64 access_sde_int_cnt(const struct cntr_entry *entry,
1333                               void *context, int idx, int mode, u64 data)
1334 {
1335         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1336
1337         if (dd->per_sdma && idx < dd->num_sdma)
1338                 return dd->per_sdma[idx].sdma_int_cnt;
1339         return 0;
1340 }
1341
1342 static u64 access_sde_idle_int_cnt(const struct cntr_entry *entry,
1343                                    void *context, int idx, int mode, u64 data)
1344 {
1345         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1346
1347         if (dd->per_sdma && idx < dd->num_sdma)
1348                 return dd->per_sdma[idx].idle_int_cnt;
1349         return 0;
1350 }
1351
1352 static u64 access_sde_progress_int_cnt(const struct cntr_entry *entry,
1353                                        void *context, int idx, int mode,
1354                                        u64 data)
1355 {
1356         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1357
1358         if (dd->per_sdma && idx < dd->num_sdma)
1359                 return dd->per_sdma[idx].progress_int_cnt;
1360         return 0;
1361 }
1362
1363 static u64 dev_access_u64_csr(const struct cntr_entry *entry, void *context,
1364                               int vl, int mode, u64 data)
1365 {
1366         struct hfi1_devdata *dd = context;
1367
1368         u64 val = 0;
1369         u64 csr = entry->csr;
1370
1371         if (entry->flags & CNTR_VL) {
1372                 if (vl == CNTR_INVALID_VL)
1373                         return 0;
1374                 csr += 8 * vl;
1375         } else {
1376                 if (vl != CNTR_INVALID_VL)
1377                         return 0;
1378         }
1379
1380         val = read_write_csr(dd, csr, mode, data);
1381         return val;
1382 }
1383
1384 static u64 dc_access_lcb_cntr(const struct cntr_entry *entry, void *context,
1385                               int vl, int mode, u64 data)
1386 {
1387         struct hfi1_devdata *dd = context;
1388         u32 csr = entry->csr;
1389         int ret = 0;
1390
1391         if (vl != CNTR_INVALID_VL)
1392                 return 0;
1393         if (mode == CNTR_MODE_R)
1394                 ret = read_lcb_csr(dd, csr, &data);
1395         else if (mode == CNTR_MODE_W)
1396                 ret = write_lcb_csr(dd, csr, data);
1397
1398         if (ret) {
1399                 dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr);
1400                 return 0;
1401         }
1402
1403         hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);
1404         return data;
1405 }
1406
1407 /* Port Access */
1408 static u64 port_access_u32_csr(const struct cntr_entry *entry, void *context,
1409                                int vl, int mode, u64 data)
1410 {
1411         struct hfi1_pportdata *ppd = context;
1412
1413         if (vl != CNTR_INVALID_VL)
1414                 return 0;
1415         return read_write_csr(ppd->dd, entry->csr, mode, data);
1416 }
1417
1418 static u64 port_access_u64_csr(const struct cntr_entry *entry,
1419                                void *context, int vl, int mode, u64 data)
1420 {
1421         struct hfi1_pportdata *ppd = context;
1422         u64 val;
1423         u64 csr = entry->csr;
1424
1425         if (entry->flags & CNTR_VL) {
1426                 if (vl == CNTR_INVALID_VL)
1427                         return 0;
1428                 csr += 8 * vl;
1429         } else {
1430                 if (vl != CNTR_INVALID_VL)
1431                         return 0;
1432         }
1433         val = read_write_csr(ppd->dd, csr, mode, data);
1434         return val;
1435 }
1436
1437 /* Software defined */
1438 static inline u64 read_write_sw(struct hfi1_devdata *dd, u64 *cntr, int mode,
1439                                 u64 data)
1440 {
1441         u64 ret;
1442
1443         if (mode == CNTR_MODE_R) {
1444                 ret = *cntr;
1445         } else if (mode == CNTR_MODE_W) {
1446                 *cntr = data;
1447                 ret = data;
1448         } else {
1449                 dd_dev_err(dd, "Invalid cntr sw access mode");
1450                 return 0;
1451         }
1452
1453         hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode);
1454
1455         return ret;
1456 }
1457
1458 static u64 access_sw_link_dn_cnt(const struct cntr_entry *entry, void *context,
1459                                  int vl, int mode, u64 data)
1460 {
1461         struct hfi1_pportdata *ppd = context;
1462
1463         if (vl != CNTR_INVALID_VL)
1464                 return 0;
1465         return read_write_sw(ppd->dd, &ppd->link_downed, mode, data);
1466 }
1467
1468 static u64 access_sw_link_up_cnt(const struct cntr_entry *entry, void *context,
1469                                  int vl, int mode, u64 data)
1470 {
1471         struct hfi1_pportdata *ppd = context;
1472
1473         if (vl != CNTR_INVALID_VL)
1474                 return 0;
1475         return read_write_sw(ppd->dd, &ppd->link_up, mode, data);
1476 }
1477
1478 static u64 access_sw_unknown_frame_cnt(const struct cntr_entry *entry,
1479                                        void *context, int vl, int mode,
1480                                        u64 data)
1481 {
1482         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1483
1484         if (vl != CNTR_INVALID_VL)
1485                 return 0;
1486         return read_write_sw(ppd->dd, &ppd->unknown_frame_count, mode, data);
1487 }
1488
1489 static u64 access_sw_xmit_discards(const struct cntr_entry *entry,
1490                                    void *context, int vl, int mode, u64 data)
1491 {
1492         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1493         u64 zero = 0;
1494         u64 *counter;
1495
1496         if (vl == CNTR_INVALID_VL)
1497                 counter = &ppd->port_xmit_discards;
1498         else if (vl >= 0 && vl < C_VL_COUNT)
1499                 counter = &ppd->port_xmit_discards_vl[vl];
1500         else
1501                 counter = &zero;
1502
1503         return read_write_sw(ppd->dd, counter, mode, data);
1504 }
1505
1506 static u64 access_xmit_constraint_errs(const struct cntr_entry *entry,
1507                                        void *context, int vl, int mode,
1508                                        u64 data)
1509 {
1510         struct hfi1_pportdata *ppd = context;
1511
1512         if (vl != CNTR_INVALID_VL)
1513                 return 0;
1514
1515         return read_write_sw(ppd->dd, &ppd->port_xmit_constraint_errors,
1516                              mode, data);
1517 }
1518
1519 static u64 access_rcv_constraint_errs(const struct cntr_entry *entry,
1520                                       void *context, int vl, int mode, u64 data)
1521 {
1522         struct hfi1_pportdata *ppd = context;
1523
1524         if (vl != CNTR_INVALID_VL)
1525                 return 0;
1526
1527         return read_write_sw(ppd->dd, &ppd->port_rcv_constraint_errors,
1528                              mode, data);
1529 }
1530
1531 u64 get_all_cpu_total(u64 __percpu *cntr)
1532 {
1533         int cpu;
1534         u64 counter = 0;
1535
1536         for_each_possible_cpu(cpu)
1537                 counter += *per_cpu_ptr(cntr, cpu);
1538         return counter;
1539 }
1540
1541 static u64 read_write_cpu(struct hfi1_devdata *dd, u64 *z_val,
1542                           u64 __percpu *cntr,
1543                           int vl, int mode, u64 data)
1544 {
1545         u64 ret = 0;
1546
1547         if (vl != CNTR_INVALID_VL)
1548                 return 0;
1549
1550         if (mode == CNTR_MODE_R) {
1551                 ret = get_all_cpu_total(cntr) - *z_val;
1552         } else if (mode == CNTR_MODE_W) {
1553                 /* A write can only zero the counter */
1554                 if (data == 0)
1555                         *z_val = get_all_cpu_total(cntr);
1556                 else
1557                         dd_dev_err(dd, "Per CPU cntrs can only be zeroed");
1558         } else {
1559                 dd_dev_err(dd, "Invalid cntr sw cpu access mode");
1560                 return 0;
1561         }
1562
1563         return ret;
1564 }
1565
1566 static u64 access_sw_cpu_intr(const struct cntr_entry *entry,
1567                               void *context, int vl, int mode, u64 data)
1568 {
1569         struct hfi1_devdata *dd = context;
1570
1571         return read_write_cpu(dd, &dd->z_int_counter, dd->int_counter, vl,
1572                               mode, data);
1573 }
1574
1575 static u64 access_sw_cpu_rcv_limit(const struct cntr_entry *entry,
1576                                    void *context, int vl, int mode, u64 data)
1577 {
1578         struct hfi1_devdata *dd = context;
1579
1580         return read_write_cpu(dd, &dd->z_rcv_limit, dd->rcv_limit, vl,
1581                               mode, data);
1582 }
1583
1584 static u64 access_sw_pio_wait(const struct cntr_entry *entry,
1585                               void *context, int vl, int mode, u64 data)
1586 {
1587         struct hfi1_devdata *dd = context;
1588
1589         return dd->verbs_dev.n_piowait;
1590 }
1591
1592 static u64 access_sw_pio_drain(const struct cntr_entry *entry,
1593                                void *context, int vl, int mode, u64 data)
1594 {
1595         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1596
1597         return dd->verbs_dev.n_piodrain;
1598 }
1599
1600 static u64 access_sw_vtx_wait(const struct cntr_entry *entry,
1601                               void *context, int vl, int mode, u64 data)
1602 {
1603         struct hfi1_devdata *dd = context;
1604
1605         return dd->verbs_dev.n_txwait;
1606 }
1607
1608 static u64 access_sw_kmem_wait(const struct cntr_entry *entry,
1609                                void *context, int vl, int mode, u64 data)
1610 {
1611         struct hfi1_devdata *dd = context;
1612
1613         return dd->verbs_dev.n_kmem_wait;
1614 }
1615
1616 static u64 access_sw_send_schedule(const struct cntr_entry *entry,
1617                                    void *context, int vl, int mode, u64 data)
1618 {
1619         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1620
1621         return read_write_cpu(dd, &dd->z_send_schedule, dd->send_schedule, vl,
1622                               mode, data);
1623 }
1624
1625 /* Software counters for the error status bits within MISC_ERR_STATUS */
1626 static u64 access_misc_pll_lock_fail_err_cnt(const struct cntr_entry *entry,
1627                                              void *context, int vl, int mode,
1628                                              u64 data)
1629 {
1630         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1631
1632         return dd->misc_err_status_cnt[12];
1633 }
1634
1635 static u64 access_misc_mbist_fail_err_cnt(const struct cntr_entry *entry,
1636                                           void *context, int vl, int mode,
1637                                           u64 data)
1638 {
1639         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1640
1641         return dd->misc_err_status_cnt[11];
1642 }
1643
1644 static u64 access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry *entry,
1645                                                void *context, int vl, int mode,
1646                                                u64 data)
1647 {
1648         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1649
1650         return dd->misc_err_status_cnt[10];
1651 }
1652
1653 static u64 access_misc_efuse_done_parity_err_cnt(const struct cntr_entry *entry,
1654                                                  void *context, int vl,
1655                                                  int mode, u64 data)
1656 {
1657         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1658
1659         return dd->misc_err_status_cnt[9];
1660 }
1661
1662 static u64 access_misc_efuse_write_err_cnt(const struct cntr_entry *entry,
1663                                            void *context, int vl, int mode,
1664                                            u64 data)
1665 {
1666         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1667
1668         return dd->misc_err_status_cnt[8];
1669 }
1670
1671 static u64 access_misc_efuse_read_bad_addr_err_cnt(
1672                                 const struct cntr_entry *entry,
1673                                 void *context, int vl, int mode, u64 data)
1674 {
1675         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1676
1677         return dd->misc_err_status_cnt[7];
1678 }
1679
1680 static u64 access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry *entry,
1681                                                 void *context, int vl,
1682                                                 int mode, u64 data)
1683 {
1684         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1685
1686         return dd->misc_err_status_cnt[6];
1687 }
1688
1689 static u64 access_misc_fw_auth_failed_err_cnt(const struct cntr_entry *entry,
1690                                               void *context, int vl, int mode,
1691                                               u64 data)
1692 {
1693         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1694
1695         return dd->misc_err_status_cnt[5];
1696 }
1697
1698 static u64 access_misc_key_mismatch_err_cnt(const struct cntr_entry *entry,
1699                                             void *context, int vl, int mode,
1700                                             u64 data)
1701 {
1702         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1703
1704         return dd->misc_err_status_cnt[4];
1705 }
1706
1707 static u64 access_misc_sbus_write_failed_err_cnt(const struct cntr_entry *entry,
1708                                                  void *context, int vl,
1709                                                  int mode, u64 data)
1710 {
1711         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1712
1713         return dd->misc_err_status_cnt[3];
1714 }
1715
1716 static u64 access_misc_csr_write_bad_addr_err_cnt(
1717                                 const struct cntr_entry *entry,
1718                                 void *context, int vl, int mode, u64 data)
1719 {
1720         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1721
1722         return dd->misc_err_status_cnt[2];
1723 }
1724
1725 static u64 access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1726                                                  void *context, int vl,
1727                                                  int mode, u64 data)
1728 {
1729         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1730
1731         return dd->misc_err_status_cnt[1];
1732 }
1733
1734 static u64 access_misc_csr_parity_err_cnt(const struct cntr_entry *entry,
1735                                           void *context, int vl, int mode,
1736                                           u64 data)
1737 {
1738         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1739
1740         return dd->misc_err_status_cnt[0];
1741 }
1742
1743 /*
1744  * Software counter for the aggregate of
1745  * individual CceErrStatus counters
1746  */
1747 static u64 access_sw_cce_err_status_aggregated_cnt(
1748                                 const struct cntr_entry *entry,
1749                                 void *context, int vl, int mode, u64 data)
1750 {
1751         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1752
1753         return dd->sw_cce_err_status_aggregate;
1754 }
1755
1756 /*
1757  * Software counters corresponding to each of the
1758  * error status bits within CceErrStatus
1759  */
1760 static u64 access_cce_msix_csr_parity_err_cnt(const struct cntr_entry *entry,
1761                                               void *context, int vl, int mode,
1762                                               u64 data)
1763 {
1764         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1765
1766         return dd->cce_err_status_cnt[40];
1767 }
1768
1769 static u64 access_cce_int_map_unc_err_cnt(const struct cntr_entry *entry,
1770                                           void *context, int vl, int mode,
1771                                           u64 data)
1772 {
1773         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1774
1775         return dd->cce_err_status_cnt[39];
1776 }
1777
1778 static u64 access_cce_int_map_cor_err_cnt(const struct cntr_entry *entry,
1779                                           void *context, int vl, int mode,
1780                                           u64 data)
1781 {
1782         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1783
1784         return dd->cce_err_status_cnt[38];
1785 }
1786
1787 static u64 access_cce_msix_table_unc_err_cnt(const struct cntr_entry *entry,
1788                                              void *context, int vl, int mode,
1789                                              u64 data)
1790 {
1791         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1792
1793         return dd->cce_err_status_cnt[37];
1794 }
1795
1796 static u64 access_cce_msix_table_cor_err_cnt(const struct cntr_entry *entry,
1797                                              void *context, int vl, int mode,
1798                                              u64 data)
1799 {
1800         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1801
1802         return dd->cce_err_status_cnt[36];
1803 }
1804
1805 static u64 access_cce_rxdma_conv_fifo_parity_err_cnt(
1806                                 const struct cntr_entry *entry,
1807                                 void *context, int vl, int mode, u64 data)
1808 {
1809         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1810
1811         return dd->cce_err_status_cnt[35];
1812 }
1813
1814 static u64 access_cce_rcpl_async_fifo_parity_err_cnt(
1815                                 const struct cntr_entry *entry,
1816                                 void *context, int vl, int mode, u64 data)
1817 {
1818         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1819
1820         return dd->cce_err_status_cnt[34];
1821 }
1822
1823 static u64 access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry *entry,
1824                                                  void *context, int vl,
1825                                                  int mode, u64 data)
1826 {
1827         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1828
1829         return dd->cce_err_status_cnt[33];
1830 }
1831
1832 static u64 access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1833                                                 void *context, int vl, int mode,
1834                                                 u64 data)
1835 {
1836         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1837
1838         return dd->cce_err_status_cnt[32];
1839 }
1840
1841 static u64 access_la_triggered_cnt(const struct cntr_entry *entry,
1842                                    void *context, int vl, int mode, u64 data)
1843 {
1844         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1845
1846         return dd->cce_err_status_cnt[31];
1847 }
1848
1849 static u64 access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry *entry,
1850                                                void *context, int vl, int mode,
1851                                                u64 data)
1852 {
1853         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1854
1855         return dd->cce_err_status_cnt[30];
1856 }
1857
1858 static u64 access_pcic_receive_parity_err_cnt(const struct cntr_entry *entry,
1859                                               void *context, int vl, int mode,
1860                                               u64 data)
1861 {
1862         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1863
1864         return dd->cce_err_status_cnt[29];
1865 }
1866
1867 static u64 access_pcic_transmit_back_parity_err_cnt(
1868                                 const struct cntr_entry *entry,
1869                                 void *context, int vl, int mode, u64 data)
1870 {
1871         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1872
1873         return dd->cce_err_status_cnt[28];
1874 }
1875
1876 static u64 access_pcic_transmit_front_parity_err_cnt(
1877                                 const struct cntr_entry *entry,
1878                                 void *context, int vl, int mode, u64 data)
1879 {
1880         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1881
1882         return dd->cce_err_status_cnt[27];
1883 }
1884
1885 static u64 access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1886                                              void *context, int vl, int mode,
1887                                              u64 data)
1888 {
1889         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1890
1891         return dd->cce_err_status_cnt[26];
1892 }
1893
1894 static u64 access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1895                                             void *context, int vl, int mode,
1896                                             u64 data)
1897 {
1898         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1899
1900         return dd->cce_err_status_cnt[25];
1901 }
1902
1903 static u64 access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1904                                               void *context, int vl, int mode,
1905                                               u64 data)
1906 {
1907         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1908
1909         return dd->cce_err_status_cnt[24];
1910 }
1911
1912 static u64 access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1913                                              void *context, int vl, int mode,
1914                                              u64 data)
1915 {
1916         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1917
1918         return dd->cce_err_status_cnt[23];
1919 }
1920
1921 static u64 access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry *entry,
1922                                                  void *context, int vl,
1923                                                  int mode, u64 data)
1924 {
1925         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1926
1927         return dd->cce_err_status_cnt[22];
1928 }
1929
1930 static u64 access_pcic_retry_mem_unc_err(const struct cntr_entry *entry,
1931                                          void *context, int vl, int mode,
1932                                          u64 data)
1933 {
1934         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1935
1936         return dd->cce_err_status_cnt[21];
1937 }
1938
1939 static u64 access_pcic_n_post_dat_q_parity_err_cnt(
1940                                 const struct cntr_entry *entry,
1941                                 void *context, int vl, int mode, u64 data)
1942 {
1943         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1944
1945         return dd->cce_err_status_cnt[20];
1946 }
1947
1948 static u64 access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry *entry,
1949                                                  void *context, int vl,
1950                                                  int mode, u64 data)
1951 {
1952         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1953
1954         return dd->cce_err_status_cnt[19];
1955 }
1956
1957 static u64 access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry *entry,
1958                                              void *context, int vl, int mode,
1959                                              u64 data)
1960 {
1961         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1962
1963         return dd->cce_err_status_cnt[18];
1964 }
1965
1966 static u64 access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry *entry,
1967                                             void *context, int vl, int mode,
1968                                             u64 data)
1969 {
1970         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1971
1972         return dd->cce_err_status_cnt[17];
1973 }
1974
1975 static u64 access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry *entry,
1976                                               void *context, int vl, int mode,
1977                                               u64 data)
1978 {
1979         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1980
1981         return dd->cce_err_status_cnt[16];
1982 }
1983
1984 static u64 access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry *entry,
1985                                              void *context, int vl, int mode,
1986                                              u64 data)
1987 {
1988         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1989
1990         return dd->cce_err_status_cnt[15];
1991 }
1992
1993 static u64 access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry *entry,
1994                                                  void *context, int vl,
1995                                                  int mode, u64 data)
1996 {
1997         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1998
1999         return dd->cce_err_status_cnt[14];
2000 }
2001
2002 static u64 access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry *entry,
2003                                              void *context, int vl, int mode,
2004                                              u64 data)
2005 {
2006         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2007
2008         return dd->cce_err_status_cnt[13];
2009 }
2010
2011 static u64 access_cce_cli1_async_fifo_dbg_parity_err_cnt(
2012                                 const struct cntr_entry *entry,
2013                                 void *context, int vl, int mode, u64 data)
2014 {
2015         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2016
2017         return dd->cce_err_status_cnt[12];
2018 }
2019
2020 static u64 access_cce_cli1_async_fifo_rxdma_parity_err_cnt(
2021                                 const struct cntr_entry *entry,
2022                                 void *context, int vl, int mode, u64 data)
2023 {
2024         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2025
2026         return dd->cce_err_status_cnt[11];
2027 }
2028
2029 static u64 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt(
2030                                 const struct cntr_entry *entry,
2031                                 void *context, int vl, int mode, u64 data)
2032 {
2033         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2034
2035         return dd->cce_err_status_cnt[10];
2036 }
2037
2038 static u64 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt(
2039                                 const struct cntr_entry *entry,
2040                                 void *context, int vl, int mode, u64 data)
2041 {
2042         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2043
2044         return dd->cce_err_status_cnt[9];
2045 }
2046
2047 static u64 access_cce_cli2_async_fifo_parity_err_cnt(
2048                                 const struct cntr_entry *entry,
2049                                 void *context, int vl, int mode, u64 data)
2050 {
2051         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2052
2053         return dd->cce_err_status_cnt[8];
2054 }
2055
2056 static u64 access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry *entry,
2057                                                  void *context, int vl,
2058                                                  int mode, u64 data)
2059 {
2060         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2061
2062         return dd->cce_err_status_cnt[7];
2063 }
2064
2065 static u64 access_cce_cli0_async_fifo_parity_err_cnt(
2066                                 const struct cntr_entry *entry,
2067                                 void *context, int vl, int mode, u64 data)
2068 {
2069         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2070
2071         return dd->cce_err_status_cnt[6];
2072 }
2073
2074 static u64 access_cce_rspd_data_parity_err_cnt(const struct cntr_entry *entry,
2075                                                void *context, int vl, int mode,
2076                                                u64 data)
2077 {
2078         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2079
2080         return dd->cce_err_status_cnt[5];
2081 }
2082
2083 static u64 access_cce_trgt_access_err_cnt(const struct cntr_entry *entry,
2084                                           void *context, int vl, int mode,
2085                                           u64 data)
2086 {
2087         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2088
2089         return dd->cce_err_status_cnt[4];
2090 }
2091
2092 static u64 access_cce_trgt_async_fifo_parity_err_cnt(
2093                                 const struct cntr_entry *entry,
2094                                 void *context, int vl, int mode, u64 data)
2095 {
2096         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2097
2098         return dd->cce_err_status_cnt[3];
2099 }
2100
2101 static u64 access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2102                                                  void *context, int vl,
2103                                                  int mode, u64 data)
2104 {
2105         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2106
2107         return dd->cce_err_status_cnt[2];
2108 }
2109
2110 static u64 access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2111                                                 void *context, int vl,
2112                                                 int mode, u64 data)
2113 {
2114         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2115
2116         return dd->cce_err_status_cnt[1];
2117 }
2118
2119 static u64 access_ccs_csr_parity_err_cnt(const struct cntr_entry *entry,
2120                                          void *context, int vl, int mode,
2121                                          u64 data)
2122 {
2123         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2124
2125         return dd->cce_err_status_cnt[0];
2126 }
2127
2128 /*
2129  * Software counters corresponding to each of the
2130  * error status bits within RcvErrStatus
2131  */
2132 static u64 access_rx_csr_parity_err_cnt(const struct cntr_entry *entry,
2133                                         void *context, int vl, int mode,
2134                                         u64 data)
2135 {
2136         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2137
2138         return dd->rcv_err_status_cnt[63];
2139 }
2140
2141 static u64 access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2142                                                 void *context, int vl,
2143                                                 int mode, u64 data)
2144 {
2145         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2146
2147         return dd->rcv_err_status_cnt[62];
2148 }
2149
2150 static u64 access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2151                                                void *context, int vl, int mode,
2152                                                u64 data)
2153 {
2154         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2155
2156         return dd->rcv_err_status_cnt[61];
2157 }
2158
2159 static u64 access_rx_dma_csr_unc_err_cnt(const struct cntr_entry *entry,
2160                                          void *context, int vl, int mode,
2161                                          u64 data)
2162 {
2163         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2164
2165         return dd->rcv_err_status_cnt[60];
2166 }
2167
2168 static u64 access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2169                                                  void *context, int vl,
2170                                                  int mode, u64 data)
2171 {
2172         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2173
2174         return dd->rcv_err_status_cnt[59];
2175 }
2176
2177 static u64 access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2178                                                  void *context, int vl,
2179                                                  int mode, u64 data)
2180 {
2181         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2182
2183         return dd->rcv_err_status_cnt[58];
2184 }
2185
2186 static u64 access_rx_dma_csr_parity_err_cnt(const struct cntr_entry *entry,
2187                                             void *context, int vl, int mode,
2188                                             u64 data)
2189 {
2190         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2191
2192         return dd->rcv_err_status_cnt[57];
2193 }
2194
2195 static u64 access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry *entry,
2196                                            void *context, int vl, int mode,
2197                                            u64 data)
2198 {
2199         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2200
2201         return dd->rcv_err_status_cnt[56];
2202 }
2203
2204 static u64 access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry *entry,
2205                                            void *context, int vl, int mode,
2206                                            u64 data)
2207 {
2208         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2209
2210         return dd->rcv_err_status_cnt[55];
2211 }
2212
2213 static u64 access_rx_dma_data_fifo_rd_cor_err_cnt(
2214                                 const struct cntr_entry *entry,
2215                                 void *context, int vl, int mode, u64 data)
2216 {
2217         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2218
2219         return dd->rcv_err_status_cnt[54];
2220 }
2221
2222 static u64 access_rx_dma_data_fifo_rd_unc_err_cnt(
2223                                 const struct cntr_entry *entry,
2224                                 void *context, int vl, int mode, u64 data)
2225 {
2226         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2227
2228         return dd->rcv_err_status_cnt[53];
2229 }
2230
2231 static u64 access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry *entry,
2232                                                  void *context, int vl,
2233                                                  int mode, u64 data)
2234 {
2235         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2236
2237         return dd->rcv_err_status_cnt[52];
2238 }
2239
2240 static u64 access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry *entry,
2241                                                  void *context, int vl,
2242                                                  int mode, u64 data)
2243 {
2244         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2245
2246         return dd->rcv_err_status_cnt[51];
2247 }
2248
2249 static u64 access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry *entry,
2250                                                  void *context, int vl,
2251                                                  int mode, u64 data)
2252 {
2253         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2254
2255         return dd->rcv_err_status_cnt[50];
2256 }
2257
2258 static u64 access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry *entry,
2259                                                  void *context, int vl,
2260                                                  int mode, u64 data)
2261 {
2262         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2263
2264         return dd->rcv_err_status_cnt[49];
2265 }
2266
2267 static u64 access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry *entry,
2268                                                  void *context, int vl,
2269                                                  int mode, u64 data)
2270 {
2271         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2272
2273         return dd->rcv_err_status_cnt[48];
2274 }
2275
2276 static u64 access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry *entry,
2277                                                  void *context, int vl,
2278                                                  int mode, u64 data)
2279 {
2280         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2281
2282         return dd->rcv_err_status_cnt[47];
2283 }
2284
2285 static u64 access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry *entry,
2286                                          void *context, int vl, int mode,
2287                                          u64 data)
2288 {
2289         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2290
2291         return dd->rcv_err_status_cnt[46];
2292 }
2293
2294 static u64 access_rx_hq_intr_csr_parity_err_cnt(
2295                                 const struct cntr_entry *entry,
2296                                 void *context, int vl, int mode, u64 data)
2297 {
2298         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2299
2300         return dd->rcv_err_status_cnt[45];
2301 }
2302
2303 static u64 access_rx_lookup_csr_parity_err_cnt(
2304                                 const struct cntr_entry *entry,
2305                                 void *context, int vl, int mode, u64 data)
2306 {
2307         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2308
2309         return dd->rcv_err_status_cnt[44];
2310 }
2311
2312 static u64 access_rx_lookup_rcv_array_cor_err_cnt(
2313                                 const struct cntr_entry *entry,
2314                                 void *context, int vl, int mode, u64 data)
2315 {
2316         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2317
2318         return dd->rcv_err_status_cnt[43];
2319 }
2320
2321 static u64 access_rx_lookup_rcv_array_unc_err_cnt(
2322                                 const struct cntr_entry *entry,
2323                                 void *context, int vl, int mode, u64 data)
2324 {
2325         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2326
2327         return dd->rcv_err_status_cnt[42];
2328 }
2329
2330 static u64 access_rx_lookup_des_part2_parity_err_cnt(
2331                                 const struct cntr_entry *entry,
2332                                 void *context, int vl, int mode, u64 data)
2333 {
2334         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2335
2336         return dd->rcv_err_status_cnt[41];
2337 }
2338
2339 static u64 access_rx_lookup_des_part1_unc_cor_err_cnt(
2340                                 const struct cntr_entry *entry,
2341                                 void *context, int vl, int mode, u64 data)
2342 {
2343         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2344
2345         return dd->rcv_err_status_cnt[40];
2346 }
2347
2348 static u64 access_rx_lookup_des_part1_unc_err_cnt(
2349                                 const struct cntr_entry *entry,
2350                                 void *context, int vl, int mode, u64 data)
2351 {
2352         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2353
2354         return dd->rcv_err_status_cnt[39];
2355 }
2356
2357 static u64 access_rx_rbuf_next_free_buf_cor_err_cnt(
2358                                 const struct cntr_entry *entry,
2359                                 void *context, int vl, int mode, u64 data)
2360 {
2361         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2362
2363         return dd->rcv_err_status_cnt[38];
2364 }
2365
2366 static u64 access_rx_rbuf_next_free_buf_unc_err_cnt(
2367                                 const struct cntr_entry *entry,
2368                                 void *context, int vl, int mode, u64 data)
2369 {
2370         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2371
2372         return dd->rcv_err_status_cnt[37];
2373 }
2374
2375 static u64 access_rbuf_fl_init_wr_addr_parity_err_cnt(
2376                                 const struct cntr_entry *entry,
2377                                 void *context, int vl, int mode, u64 data)
2378 {
2379         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2380
2381         return dd->rcv_err_status_cnt[36];
2382 }
2383
2384 static u64 access_rx_rbuf_fl_initdone_parity_err_cnt(
2385                                 const struct cntr_entry *entry,
2386                                 void *context, int vl, int mode, u64 data)
2387 {
2388         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2389
2390         return dd->rcv_err_status_cnt[35];
2391 }
2392
2393 static u64 access_rx_rbuf_fl_write_addr_parity_err_cnt(
2394                                 const struct cntr_entry *entry,
2395                                 void *context, int vl, int mode, u64 data)
2396 {
2397         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2398
2399         return dd->rcv_err_status_cnt[34];
2400 }
2401
2402 static u64 access_rx_rbuf_fl_rd_addr_parity_err_cnt(
2403                                 const struct cntr_entry *entry,
2404                                 void *context, int vl, int mode, u64 data)
2405 {
2406         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2407
2408         return dd->rcv_err_status_cnt[33];
2409 }
2410
2411 static u64 access_rx_rbuf_empty_err_cnt(const struct cntr_entry *entry,
2412                                         void *context, int vl, int mode,
2413                                         u64 data)
2414 {
2415         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2416
2417         return dd->rcv_err_status_cnt[32];
2418 }
2419
2420 static u64 access_rx_rbuf_full_err_cnt(const struct cntr_entry *entry,
2421                                        void *context, int vl, int mode,
2422                                        u64 data)
2423 {
2424         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2425
2426         return dd->rcv_err_status_cnt[31];
2427 }
2428
2429 static u64 access_rbuf_bad_lookup_err_cnt(const struct cntr_entry *entry,
2430                                           void *context, int vl, int mode,
2431                                           u64 data)
2432 {
2433         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2434
2435         return dd->rcv_err_status_cnt[30];
2436 }
2437
2438 static u64 access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry *entry,
2439                                              void *context, int vl, int mode,
2440                                              u64 data)
2441 {
2442         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2443
2444         return dd->rcv_err_status_cnt[29];
2445 }
2446
2447 static u64 access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry *entry,
2448                                                  void *context, int vl,
2449                                                  int mode, u64 data)
2450 {
2451         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2452
2453         return dd->rcv_err_status_cnt[28];
2454 }
2455
2456 static u64 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt(
2457                                 const struct cntr_entry *entry,
2458                                 void *context, int vl, int mode, u64 data)
2459 {
2460         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2461
2462         return dd->rcv_err_status_cnt[27];
2463 }
2464
2465 static u64 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt(
2466                                 const struct cntr_entry *entry,
2467                                 void *context, int vl, int mode, u64 data)
2468 {
2469         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2470
2471         return dd->rcv_err_status_cnt[26];
2472 }
2473
2474 static u64 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt(
2475                                 const struct cntr_entry *entry,
2476                                 void *context, int vl, int mode, u64 data)
2477 {
2478         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2479
2480         return dd->rcv_err_status_cnt[25];
2481 }
2482
2483 static u64 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt(
2484                                 const struct cntr_entry *entry,
2485                                 void *context, int vl, int mode, u64 data)
2486 {
2487         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2488
2489         return dd->rcv_err_status_cnt[24];
2490 }
2491
2492 static u64 access_rx_rbuf_csr_q_next_buf_parity_err_cnt(
2493                                 const struct cntr_entry *entry,
2494                                 void *context, int vl, int mode, u64 data)
2495 {
2496         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2497
2498         return dd->rcv_err_status_cnt[23];
2499 }
2500
2501 static u64 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt(
2502                                 const struct cntr_entry *entry,
2503                                 void *context, int vl, int mode, u64 data)
2504 {
2505         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2506
2507         return dd->rcv_err_status_cnt[22];
2508 }
2509
2510 static u64 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt(
2511                                 const struct cntr_entry *entry,
2512                                 void *context, int vl, int mode, u64 data)
2513 {
2514         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2515
2516         return dd->rcv_err_status_cnt[21];
2517 }
2518
2519 static u64 access_rx_rbuf_block_list_read_cor_err_cnt(
2520                                 const struct cntr_entry *entry,
2521                                 void *context, int vl, int mode, u64 data)
2522 {
2523         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2524
2525         return dd->rcv_err_status_cnt[20];
2526 }
2527
2528 static u64 access_rx_rbuf_block_list_read_unc_err_cnt(
2529                                 const struct cntr_entry *entry,
2530                                 void *context, int vl, int mode, u64 data)
2531 {
2532         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2533
2534         return dd->rcv_err_status_cnt[19];
2535 }
2536
2537 static u64 access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry *entry,
2538                                                  void *context, int vl,
2539                                                  int mode, u64 data)
2540 {
2541         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2542
2543         return dd->rcv_err_status_cnt[18];
2544 }
2545
2546 static u64 access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry *entry,
2547                                                  void *context, int vl,
2548                                                  int mode, u64 data)
2549 {
2550         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2551
2552         return dd->rcv_err_status_cnt[17];
2553 }
2554
2555 static u64 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt(
2556                                 const struct cntr_entry *entry,
2557                                 void *context, int vl, int mode, u64 data)
2558 {
2559         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2560
2561         return dd->rcv_err_status_cnt[16];
2562 }
2563
2564 static u64 access_rx_rbuf_lookup_des_reg_unc_err_cnt(
2565                                 const struct cntr_entry *entry,
2566                                 void *context, int vl, int mode, u64 data)
2567 {
2568         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2569
2570         return dd->rcv_err_status_cnt[15];
2571 }
2572
2573 static u64 access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry *entry,
2574                                                 void *context, int vl,
2575                                                 int mode, u64 data)
2576 {
2577         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2578
2579         return dd->rcv_err_status_cnt[14];
2580 }
2581
2582 static u64 access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry *entry,
2583                                                 void *context, int vl,
2584                                                 int mode, u64 data)
2585 {
2586         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2587
2588         return dd->rcv_err_status_cnt[13];
2589 }
2590
2591 static u64 access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2592                                               void *context, int vl, int mode,
2593                                               u64 data)
2594 {
2595         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2596
2597         return dd->rcv_err_status_cnt[12];
2598 }
2599
2600 static u64 access_rx_dma_flag_cor_err_cnt(const struct cntr_entry *entry,
2601                                           void *context, int vl, int mode,
2602                                           u64 data)
2603 {
2604         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2605
2606         return dd->rcv_err_status_cnt[11];
2607 }
2608
2609 static u64 access_rx_dma_flag_unc_err_cnt(const struct cntr_entry *entry,
2610                                           void *context, int vl, int mode,
2611                                           u64 data)
2612 {
2613         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2614
2615         return dd->rcv_err_status_cnt[10];
2616 }
2617
2618 static u64 access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry *entry,
2619                                                void *context, int vl, int mode,
2620                                                u64 data)
2621 {
2622         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2623
2624         return dd->rcv_err_status_cnt[9];
2625 }
2626
2627 static u64 access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry *entry,
2628                                             void *context, int vl, int mode,
2629                                             u64 data)
2630 {
2631         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2632
2633         return dd->rcv_err_status_cnt[8];
2634 }
2635
2636 static u64 access_rx_rcv_qp_map_table_cor_err_cnt(
2637                                 const struct cntr_entry *entry,
2638                                 void *context, int vl, int mode, u64 data)
2639 {
2640         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2641
2642         return dd->rcv_err_status_cnt[7];
2643 }
2644
2645 static u64 access_rx_rcv_qp_map_table_unc_err_cnt(
2646                                 const struct cntr_entry *entry,
2647                                 void *context, int vl, int mode, u64 data)
2648 {
2649         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2650
2651         return dd->rcv_err_status_cnt[6];
2652 }
2653
2654 static u64 access_rx_rcv_data_cor_err_cnt(const struct cntr_entry *entry,
2655                                           void *context, int vl, int mode,
2656                                           u64 data)
2657 {
2658         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2659
2660         return dd->rcv_err_status_cnt[5];
2661 }
2662
2663 static u64 access_rx_rcv_data_unc_err_cnt(const struct cntr_entry *entry,
2664                                           void *context, int vl, int mode,
2665                                           u64 data)
2666 {
2667         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2668
2669         return dd->rcv_err_status_cnt[4];
2670 }
2671
2672 static u64 access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry *entry,
2673                                          void *context, int vl, int mode,
2674                                          u64 data)
2675 {
2676         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2677
2678         return dd->rcv_err_status_cnt[3];
2679 }
2680
2681 static u64 access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry *entry,
2682                                          void *context, int vl, int mode,
2683                                          u64 data)
2684 {
2685         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2686
2687         return dd->rcv_err_status_cnt[2];
2688 }
2689
2690 static u64 access_rx_dc_intf_parity_err_cnt(const struct cntr_entry *entry,
2691                                             void *context, int vl, int mode,
2692                                             u64 data)
2693 {
2694         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2695
2696         return dd->rcv_err_status_cnt[1];
2697 }
2698
2699 static u64 access_rx_dma_csr_cor_err_cnt(const struct cntr_entry *entry,
2700                                          void *context, int vl, int mode,
2701                                          u64 data)
2702 {
2703         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2704
2705         return dd->rcv_err_status_cnt[0];
2706 }
2707
2708 /*
2709  * Software counters corresponding to each of the
2710  * error status bits within SendPioErrStatus
2711  */
2712 static u64 access_pio_pec_sop_head_parity_err_cnt(
2713                                 const struct cntr_entry *entry,
2714                                 void *context, int vl, int mode, u64 data)
2715 {
2716         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2717
2718         return dd->send_pio_err_status_cnt[35];
2719 }
2720
2721 static u64 access_pio_pcc_sop_head_parity_err_cnt(
2722                                 const struct cntr_entry *entry,
2723                                 void *context, int vl, int mode, u64 data)
2724 {
2725         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2726
2727         return dd->send_pio_err_status_cnt[34];
2728 }
2729
2730 static u64 access_pio_last_returned_cnt_parity_err_cnt(
2731                                 const struct cntr_entry *entry,
2732                                 void *context, int vl, int mode, u64 data)
2733 {
2734         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2735
2736         return dd->send_pio_err_status_cnt[33];
2737 }
2738
2739 static u64 access_pio_current_free_cnt_parity_err_cnt(
2740                                 const struct cntr_entry *entry,
2741                                 void *context, int vl, int mode, u64 data)
2742 {
2743         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2744
2745         return dd->send_pio_err_status_cnt[32];
2746 }
2747
2748 static u64 access_pio_reserved_31_err_cnt(const struct cntr_entry *entry,
2749                                           void *context, int vl, int mode,
2750                                           u64 data)
2751 {
2752         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2753
2754         return dd->send_pio_err_status_cnt[31];
2755 }
2756
2757 static u64 access_pio_reserved_30_err_cnt(const struct cntr_entry *entry,
2758                                           void *context, int vl, int mode,
2759                                           u64 data)
2760 {
2761         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2762
2763         return dd->send_pio_err_status_cnt[30];
2764 }
2765
2766 static u64 access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry *entry,
2767                                            void *context, int vl, int mode,
2768                                            u64 data)
2769 {
2770         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2771
2772         return dd->send_pio_err_status_cnt[29];
2773 }
2774
2775 static u64 access_pio_ppmc_bqc_mem_parity_err_cnt(
2776                                 const struct cntr_entry *entry,
2777                                 void *context, int vl, int mode, u64 data)
2778 {
2779         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2780
2781         return dd->send_pio_err_status_cnt[28];
2782 }
2783
2784 static u64 access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry *entry,
2785                                              void *context, int vl, int mode,
2786                                              u64 data)
2787 {
2788         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2789
2790         return dd->send_pio_err_status_cnt[27];
2791 }
2792
2793 static u64 access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry *entry,
2794                                              void *context, int vl, int mode,
2795                                              u64 data)
2796 {
2797         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2798
2799         return dd->send_pio_err_status_cnt[26];
2800 }
2801
2802 static u64 access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry *entry,
2803                                                 void *context, int vl,
2804                                                 int mode, u64 data)
2805 {
2806         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2807
2808         return dd->send_pio_err_status_cnt[25];
2809 }
2810
2811 static u64 access_pio_block_qw_count_parity_err_cnt(
2812                                 const struct cntr_entry *entry,
2813                                 void *context, int vl, int mode, u64 data)
2814 {
2815         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2816
2817         return dd->send_pio_err_status_cnt[24];
2818 }
2819
2820 static u64 access_pio_write_qw_valid_parity_err_cnt(
2821                                 const struct cntr_entry *entry,
2822                                 void *context, int vl, int mode, u64 data)
2823 {
2824         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2825
2826         return dd->send_pio_err_status_cnt[23];
2827 }
2828
2829 static u64 access_pio_state_machine_err_cnt(const struct cntr_entry *entry,
2830                                             void *context, int vl, int mode,
2831                                             u64 data)
2832 {
2833         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2834
2835         return dd->send_pio_err_status_cnt[22];
2836 }
2837
2838 static u64 access_pio_write_data_parity_err_cnt(const struct cntr_entry *entry,
2839                                                 void *context, int vl,
2840                                                 int mode, u64 data)
2841 {
2842         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2843
2844         return dd->send_pio_err_status_cnt[21];
2845 }
2846
2847 static u64 access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry *entry,
2848                                                 void *context, int vl,
2849                                                 int mode, u64 data)
2850 {
2851         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2852
2853         return dd->send_pio_err_status_cnt[20];
2854 }
2855
2856 static u64 access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry *entry,
2857                                                 void *context, int vl,
2858                                                 int mode, u64 data)
2859 {
2860         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2861
2862         return dd->send_pio_err_status_cnt[19];
2863 }
2864
2865 static u64 access_pio_pkt_evict_sm_or_arb_sm_err_cnt(
2866                                 const struct cntr_entry *entry,
2867                                 void *context, int vl, int mode, u64 data)
2868 {
2869         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2870
2871         return dd->send_pio_err_status_cnt[18];
2872 }
2873
2874 static u64 access_pio_init_sm_in_err_cnt(const struct cntr_entry *entry,
2875                                          void *context, int vl, int mode,
2876                                          u64 data)
2877 {
2878         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2879
2880         return dd->send_pio_err_status_cnt[17];
2881 }
2882
2883 static u64 access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry *entry,
2884                                             void *context, int vl, int mode,
2885                                             u64 data)
2886 {
2887         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2888
2889         return dd->send_pio_err_status_cnt[16];
2890 }
2891
2892 static u64 access_pio_credit_ret_fifo_parity_err_cnt(
2893                                 const struct cntr_entry *entry,
2894                                 void *context, int vl, int mode, u64 data)
2895 {
2896         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2897
2898         return dd->send_pio_err_status_cnt[15];
2899 }
2900
2901 static u64 access_pio_v1_len_mem_bank1_cor_err_cnt(
2902                                 const struct cntr_entry *entry,
2903                                 void *context, int vl, int mode, u64 data)
2904 {
2905         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2906
2907         return dd->send_pio_err_status_cnt[14];
2908 }
2909
2910 static u64 access_pio_v1_len_mem_bank0_cor_err_cnt(
2911                                 const struct cntr_entry *entry,
2912                                 void *context, int vl, int mode, u64 data)
2913 {
2914         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2915
2916         return dd->send_pio_err_status_cnt[13];
2917 }
2918
2919 static u64 access_pio_v1_len_mem_bank1_unc_err_cnt(
2920                                 const struct cntr_entry *entry,
2921                                 void *context, int vl, int mode, u64 data)
2922 {
2923         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2924
2925         return dd->send_pio_err_status_cnt[12];
2926 }
2927
2928 static u64 access_pio_v1_len_mem_bank0_unc_err_cnt(
2929                                 const struct cntr_entry *entry,
2930                                 void *context, int vl, int mode, u64 data)
2931 {
2932         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2933
2934         return dd->send_pio_err_status_cnt[11];
2935 }
2936
2937 static u64 access_pio_sm_pkt_reset_parity_err_cnt(
2938                                 const struct cntr_entry *entry,
2939                                 void *context, int vl, int mode, u64 data)
2940 {
2941         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2942
2943         return dd->send_pio_err_status_cnt[10];
2944 }
2945
2946 static u64 access_pio_pkt_evict_fifo_parity_err_cnt(
2947                                 const struct cntr_entry *entry,
2948                                 void *context, int vl, int mode, u64 data)
2949 {
2950         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2951
2952         return dd->send_pio_err_status_cnt[9];
2953 }
2954
2955 static u64 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt(
2956                                 const struct cntr_entry *entry,
2957                                 void *context, int vl, int mode, u64 data)
2958 {
2959         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2960
2961         return dd->send_pio_err_status_cnt[8];
2962 }
2963
2964 static u64 access_pio_sbrdctl_crrel_parity_err_cnt(
2965                                 const struct cntr_entry *entry,
2966                                 void *context, int vl, int mode, u64 data)
2967 {
2968         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2969
2970         return dd->send_pio_err_status_cnt[7];
2971 }
2972
2973 static u64 access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry *entry,
2974                                               void *context, int vl, int mode,
2975                                               u64 data)
2976 {
2977         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2978
2979         return dd->send_pio_err_status_cnt[6];
2980 }
2981
2982 static u64 access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry *entry,
2983                                               void *context, int vl, int mode,
2984                                               u64 data)
2985 {
2986         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2987
2988         return dd->send_pio_err_status_cnt[5];
2989 }
2990
2991 static u64 access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry *entry,
2992                                            void *context, int vl, int mode,
2993                                            u64 data)
2994 {
2995         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2996
2997         return dd->send_pio_err_status_cnt[4];
2998 }
2999
3000 static u64 access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry *entry,
3001                                            void *context, int vl, int mode,
3002                                            u64 data)
3003 {
3004         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3005
3006         return dd->send_pio_err_status_cnt[3];
3007 }
3008
3009 static u64 access_pio_csr_parity_err_cnt(const struct cntr_entry *entry,
3010                                          void *context, int vl, int mode,
3011                                          u64 data)
3012 {
3013         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3014
3015         return dd->send_pio_err_status_cnt[2];
3016 }
3017
3018 static u64 access_pio_write_addr_parity_err_cnt(const struct cntr_entry *entry,
3019                                                 void *context, int vl,
3020                                                 int mode, u64 data)
3021 {
3022         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3023
3024         return dd->send_pio_err_status_cnt[1];
3025 }
3026
3027 static u64 access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry *entry,
3028                                              void *context, int vl, int mode,
3029                                              u64 data)
3030 {
3031         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3032
3033         return dd->send_pio_err_status_cnt[0];
3034 }
3035
3036 /*
3037  * Software counters corresponding to each of the
3038  * error status bits within SendDmaErrStatus
3039  */
3040 static u64 access_sdma_pcie_req_tracking_cor_err_cnt(
3041                                 const struct cntr_entry *entry,
3042                                 void *context, int vl, int mode, u64 data)
3043 {
3044         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3045
3046         return dd->send_dma_err_status_cnt[3];
3047 }
3048
3049 static u64 access_sdma_pcie_req_tracking_unc_err_cnt(
3050                                 const struct cntr_entry *entry,
3051                                 void *context, int vl, int mode, u64 data)
3052 {
3053         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3054
3055         return dd->send_dma_err_status_cnt[2];
3056 }
3057
3058 static u64 access_sdma_csr_parity_err_cnt(const struct cntr_entry *entry,
3059                                           void *context, int vl, int mode,
3060                                           u64 data)
3061 {
3062         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3063
3064         return dd->send_dma_err_status_cnt[1];
3065 }
3066
3067 static u64 access_sdma_rpy_tag_err_cnt(const struct cntr_entry *entry,
3068                                        void *context, int vl, int mode,
3069                                        u64 data)
3070 {
3071         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3072
3073         return dd->send_dma_err_status_cnt[0];
3074 }
3075
3076 /*
3077  * Software counters corresponding to each of the
3078  * error status bits within SendEgressErrStatus
3079  */
3080 static u64 access_tx_read_pio_memory_csr_unc_err_cnt(
3081                                 const struct cntr_entry *entry,
3082                                 void *context, int vl, int mode, u64 data)
3083 {
3084         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3085
3086         return dd->send_egress_err_status_cnt[63];
3087 }
3088
3089 static u64 access_tx_read_sdma_memory_csr_err_cnt(
3090                                 const struct cntr_entry *entry,
3091                                 void *context, int vl, int mode, u64 data)
3092 {
3093         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3094
3095         return dd->send_egress_err_status_cnt[62];
3096 }
3097
3098 static u64 access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry *entry,
3099                                              void *context, int vl, int mode,
3100                                              u64 data)
3101 {
3102         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3103
3104         return dd->send_egress_err_status_cnt[61];
3105 }
3106
3107 static u64 access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry *entry,
3108                                                  void *context, int vl,
3109                                                  int mode, u64 data)
3110 {
3111         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3112
3113         return dd->send_egress_err_status_cnt[60];
3114 }
3115
3116 static u64 access_tx_read_sdma_memory_cor_err_cnt(
3117                                 const struct cntr_entry *entry,
3118                                 void *context, int vl, int mode, u64 data)
3119 {
3120         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3121
3122         return dd->send_egress_err_status_cnt[59];
3123 }
3124
3125 static u64 access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry *entry,
3126                                         void *context, int vl, int mode,
3127                                         u64 data)
3128 {
3129         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3130
3131         return dd->send_egress_err_status_cnt[58];
3132 }
3133
3134 static u64 access_tx_credit_overrun_err_cnt(const struct cntr_entry *entry,
3135                                             void *context, int vl, int mode,
3136                                             u64 data)
3137 {
3138         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3139
3140         return dd->send_egress_err_status_cnt[57];
3141 }
3142
3143 static u64 access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry *entry,
3144                                               void *context, int vl, int mode,
3145                                               u64 data)
3146 {
3147         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3148
3149         return dd->send_egress_err_status_cnt[56];
3150 }
3151
3152 static u64 access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry *entry,
3153                                               void *context, int vl, int mode,
3154                                               u64 data)
3155 {
3156         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3157
3158         return dd->send_egress_err_status_cnt[55];
3159 }
3160
3161 static u64 access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry *entry,
3162                                               void *context, int vl, int mode,
3163                                               u64 data)
3164 {
3165         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3166
3167         return dd->send_egress_err_status_cnt[54];
3168 }
3169
3170 static u64 access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry *entry,
3171                                               void *context, int vl, int mode,
3172                                               u64 data)
3173 {
3174         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3175
3176         return dd->send_egress_err_status_cnt[53];
3177 }
3178
3179 static u64 access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry *entry,
3180                                               void *context, int vl, int mode,
3181                                               u64 data)
3182 {
3183         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3184
3185         return dd->send_egress_err_status_cnt[52];
3186 }
3187
3188 static u64 access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry *entry,
3189                                               void *context, int vl, int mode,
3190                                               u64 data)
3191 {
3192         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3193
3194         return dd->send_egress_err_status_cnt[51];
3195 }
3196
3197 static u64 access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry *entry,
3198                                               void *context, int vl, int mode,
3199                                               u64 data)
3200 {
3201         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3202
3203         return dd->send_egress_err_status_cnt[50];
3204 }
3205
3206 static u64 access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry *entry,
3207                                               void *context, int vl, int mode,
3208                                               u64 data)
3209 {
3210         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3211
3212         return dd->send_egress_err_status_cnt[49];
3213 }
3214
3215 static u64 access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry *entry,
3216                                               void *context, int vl, int mode,
3217                                               u64 data)
3218 {
3219         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3220
3221         return dd->send_egress_err_status_cnt[48];
3222 }
3223
3224 static u64 access_tx_credit_return_vl_err_cnt(const struct cntr_entry *entry,
3225                                               void *context, int vl, int mode,
3226                                               u64 data)
3227 {
3228         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3229
3230         return dd->send_egress_err_status_cnt[47];
3231 }
3232
3233 static u64 access_tx_hcrc_insertion_err_cnt(const struct cntr_entry *entry,
3234                                             void *context, int vl, int mode,
3235                                             u64 data)
3236 {
3237         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3238
3239         return dd->send_egress_err_status_cnt[46];
3240 }
3241
3242 static u64 access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry *entry,
3243                                              void *context, int vl, int mode,
3244                                              u64 data)
3245 {
3246         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3247
3248         return dd->send_egress_err_status_cnt[45];
3249 }
3250
3251 static u64 access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry *entry,
3252                                                  void *context, int vl,
3253                                                  int mode, u64 data)
3254 {
3255         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3256
3257         return dd->send_egress_err_status_cnt[44];
3258 }
3259
3260 static u64 access_tx_read_sdma_memory_unc_err_cnt(
3261                                 const struct cntr_entry *entry,
3262                                 void *context, int vl, int mode, u64 data)
3263 {
3264         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3265
3266         return dd->send_egress_err_status_cnt[43];
3267 }
3268
3269 static u64 access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry *entry,
3270                                         void *context, int vl, int mode,
3271                                         u64 data)
3272 {
3273         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3274
3275         return dd->send_egress_err_status_cnt[42];
3276 }
3277
3278 static u64 access_tx_credit_return_partiy_err_cnt(
3279                                 const struct cntr_entry *entry,
3280                                 void *context, int vl, int mode, u64 data)
3281 {
3282         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3283
3284         return dd->send_egress_err_status_cnt[41];
3285 }
3286
3287 static u64 access_tx_launch_fifo8_unc_or_parity_err_cnt(
3288                                 const struct cntr_entry *entry,
3289                                 void *context, int vl, int mode, u64 data)
3290 {
3291         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3292
3293         return dd->send_egress_err_status_cnt[40];
3294 }
3295
3296 static u64 access_tx_launch_fifo7_unc_or_parity_err_cnt(
3297                                 const struct cntr_entry *entry,
3298                                 void *context, int vl, int mode, u64 data)
3299 {
3300         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3301
3302         return dd->send_egress_err_status_cnt[39];
3303 }
3304
3305 static u64 access_tx_launch_fifo6_unc_or_parity_err_cnt(
3306                                 const struct cntr_entry *entry,
3307                                 void *context, int vl, int mode, u64 data)
3308 {
3309         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3310
3311         return dd->send_egress_err_status_cnt[38];
3312 }
3313
3314 static u64 access_tx_launch_fifo5_unc_or_parity_err_cnt(
3315                                 const struct cntr_entry *entry,
3316                                 void *context, int vl, int mode, u64 data)
3317 {
3318         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3319
3320         return dd->send_egress_err_status_cnt[37];
3321 }
3322
3323 static u64 access_tx_launch_fifo4_unc_or_parity_err_cnt(
3324                                 const struct cntr_entry *entry,
3325                                 void *context, int vl, int mode, u64 data)
3326 {
3327         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3328
3329         return dd->send_egress_err_status_cnt[36];
3330 }
3331
3332 static u64 access_tx_launch_fifo3_unc_or_parity_err_cnt(
3333                                 const struct cntr_entry *entry,
3334                                 void *context, int vl, int mode, u64 data)
3335 {
3336         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3337
3338         return dd->send_egress_err_status_cnt[35];
3339 }
3340
3341 static u64 access_tx_launch_fifo2_unc_or_parity_err_cnt(
3342                                 const struct cntr_entry *entry,
3343                                 void *context, int vl, int mode, u64 data)
3344 {
3345         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3346
3347         return dd->send_egress_err_status_cnt[34];
3348 }
3349
3350 static u64 access_tx_launch_fifo1_unc_or_parity_err_cnt(
3351                                 const struct cntr_entry *entry,
3352                                 void *context, int vl, int mode, u64 data)
3353 {
3354         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3355
3356         return dd->send_egress_err_status_cnt[33];
3357 }
3358
3359 static u64 access_tx_launch_fifo0_unc_or_parity_err_cnt(
3360                                 const struct cntr_entry *entry,
3361                                 void *context, int vl, int mode, u64 data)
3362 {
3363         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3364
3365         return dd->send_egress_err_status_cnt[32];
3366 }
3367
3368 static u64 access_tx_sdma15_disallowed_packet_err_cnt(
3369                                 const struct cntr_entry *entry,
3370                                 void *context, int vl, int mode, u64 data)
3371 {
3372         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3373
3374         return dd->send_egress_err_status_cnt[31];
3375 }
3376
3377 static u64 access_tx_sdma14_disallowed_packet_err_cnt(
3378                                 const struct cntr_entry *entry,
3379                                 void *context, int vl, int mode, u64 data)
3380 {
3381         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3382
3383         return dd->send_egress_err_status_cnt[30];
3384 }
3385
3386 static u64 access_tx_sdma13_disallowed_packet_err_cnt(
3387                                 const struct cntr_entry *entry,
3388                                 void *context, int vl, int mode, u64 data)
3389 {
3390         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3391
3392         return dd->send_egress_err_status_cnt[29];
3393 }
3394
3395 static u64 access_tx_sdma12_disallowed_packet_err_cnt(
3396                                 const struct cntr_entry *entry,
3397                                 void *context, int vl, int mode, u64 data)
3398 {
3399         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3400
3401         return dd->send_egress_err_status_cnt[28];
3402 }
3403
3404 static u64 access_tx_sdma11_disallowed_packet_err_cnt(
3405                                 const struct cntr_entry *entry,
3406                                 void *context, int vl, int mode, u64 data)
3407 {
3408         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3409
3410         return dd->send_egress_err_status_cnt[27];
3411 }
3412
3413 static u64 access_tx_sdma10_disallowed_packet_err_cnt(
3414                                 const struct cntr_entry *entry,
3415                                 void *context, int vl, int mode, u64 data)
3416 {
3417         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3418
3419         return dd->send_egress_err_status_cnt[26];
3420 }
3421
3422 static u64 access_tx_sdma9_disallowed_packet_err_cnt(
3423                                 const struct cntr_entry *entry,
3424                                 void *context, int vl, int mode, u64 data)
3425 {
3426         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3427
3428         return dd->send_egress_err_status_cnt[25];
3429 }
3430
3431 static u64 access_tx_sdma8_disallowed_packet_err_cnt(
3432                                 const struct cntr_entry *entry,
3433                                 void *context, int vl, int mode, u64 data)
3434 {
3435         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3436
3437         return dd->send_egress_err_status_cnt[24];
3438 }
3439
3440 static u64 access_tx_sdma7_disallowed_packet_err_cnt(
3441                                 const struct cntr_entry *entry,
3442                                 void *context, int vl, int mode, u64 data)
3443 {
3444         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3445
3446         return dd->send_egress_err_status_cnt[23];
3447 }
3448
3449 static u64 access_tx_sdma6_disallowed_packet_err_cnt(
3450                                 const struct cntr_entry *entry,
3451                                 void *context, int vl, int mode, u64 data)
3452 {
3453         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3454
3455         return dd->send_egress_err_status_cnt[22];
3456 }
3457
3458 static u64 access_tx_sdma5_disallowed_packet_err_cnt(
3459                                 const struct cntr_entry *entry,
3460                                 void *context, int vl, int mode, u64 data)
3461 {
3462         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3463
3464         return dd->send_egress_err_status_cnt[21];
3465 }
3466
3467 static u64 access_tx_sdma4_disallowed_packet_err_cnt(
3468                                 const struct cntr_entry *entry,
3469                                 void *context, int vl, int mode, u64 data)
3470 {
3471         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3472
3473         return dd->send_egress_err_status_cnt[20];
3474 }
3475
3476 static u64 access_tx_sdma3_disallowed_packet_err_cnt(
3477                                 const struct cntr_entry *entry,
3478                                 void *context, int vl, int mode, u64 data)
3479 {
3480         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3481
3482         return dd->send_egress_err_status_cnt[19];
3483 }
3484
3485 static u64 access_tx_sdma2_disallowed_packet_err_cnt(
3486                                 const struct cntr_entry *entry,
3487                                 void *context, int vl, int mode, u64 data)
3488 {
3489         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3490
3491         return dd->send_egress_err_status_cnt[18];
3492 }
3493
3494 static u64 access_tx_sdma1_disallowed_packet_err_cnt(
3495                                 const struct cntr_entry *entry,
3496                                 void *context, int vl, int mode, u64 data)
3497 {
3498         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3499
3500         return dd->send_egress_err_status_cnt[17];
3501 }
3502
3503 static u64 access_tx_sdma0_disallowed_packet_err_cnt(
3504                                 const struct cntr_entry *entry,
3505                                 void *context, int vl, int mode, u64 data)
3506 {
3507         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3508
3509         return dd->send_egress_err_status_cnt[16];
3510 }
3511
3512 static u64 access_tx_config_parity_err_cnt(const struct cntr_entry *entry,
3513                                            void *context, int vl, int mode,
3514                                            u64 data)
3515 {
3516         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3517
3518         return dd->send_egress_err_status_cnt[15];
3519 }
3520
3521 static u64 access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry *entry,
3522                                                  void *context, int vl,
3523                                                  int mode, u64 data)
3524 {
3525         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3526
3527         return dd->send_egress_err_status_cnt[14];
3528 }
3529
3530 static u64 access_tx_launch_csr_parity_err_cnt(const struct cntr_entry *entry,
3531                                                void *context, int vl, int mode,
3532                                                u64 data)
3533 {
3534         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3535
3536         return dd->send_egress_err_status_cnt[13];
3537 }
3538
3539 static u64 access_tx_illegal_vl_err_cnt(const struct cntr_entry *entry,
3540                                         void *context, int vl, int mode,
3541                                         u64 data)
3542 {
3543         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3544
3545         return dd->send_egress_err_status_cnt[12];
3546 }
3547
3548 static u64 access_tx_sbrd_ctl_state_machine_parity_err_cnt(
3549                                 const struct cntr_entry *entry,
3550                                 void *context, int vl, int mode, u64 data)
3551 {
3552         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3553
3554         return dd->send_egress_err_status_cnt[11];
3555 }
3556
3557 static u64 access_egress_reserved_10_err_cnt(const struct cntr_entry *entry,
3558                                              void *context, int vl, int mode,
3559                                              u64 data)
3560 {
3561         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3562
3563         return dd->send_egress_err_status_cnt[10];
3564 }
3565
3566 static u64 access_egress_reserved_9_err_cnt(const struct cntr_entry *entry,
3567                                             void *context, int vl, int mode,
3568                                             u64 data)
3569 {
3570         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3571
3572         return dd->send_egress_err_status_cnt[9];
3573 }
3574
3575 static u64 access_tx_sdma_launch_intf_parity_err_cnt(
3576                                 const struct cntr_entry *entry,
3577                                 void *context, int vl, int mode, u64 data)
3578 {
3579         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3580
3581         return dd->send_egress_err_status_cnt[8];
3582 }
3583
3584 static u64 access_tx_pio_launch_intf_parity_err_cnt(
3585                                 const struct cntr_entry *entry,
3586                                 void *context, int vl, int mode, u64 data)
3587 {
3588         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3589
3590         return dd->send_egress_err_status_cnt[7];
3591 }
3592
3593 static u64 access_egress_reserved_6_err_cnt(const struct cntr_entry *entry,
3594                                             void *context, int vl, int mode,
3595                                             u64 data)
3596 {
3597         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3598
3599         return dd->send_egress_err_status_cnt[6];
3600 }
3601
3602 static u64 access_tx_incorrect_link_state_err_cnt(
3603                                 const struct cntr_entry *entry,
3604                                 void *context, int vl, int mode, u64 data)
3605 {
3606         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3607
3608         return dd->send_egress_err_status_cnt[5];
3609 }
3610
3611 static u64 access_tx_linkdown_err_cnt(const struct cntr_entry *entry,
3612                                       void *context, int vl, int mode,
3613                                       u64 data)
3614 {
3615         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3616
3617         return dd->send_egress_err_status_cnt[4];
3618 }
3619
3620 static u64 access_tx_egress_fifi_underrun_or_parity_err_cnt(
3621                                 const struct cntr_entry *entry,
3622                                 void *context, int vl, int mode, u64 data)
3623 {
3624         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3625
3626         return dd->send_egress_err_status_cnt[3];
3627 }
3628
3629 static u64 access_egress_reserved_2_err_cnt(const struct cntr_entry *entry,
3630                                             void *context, int vl, int mode,
3631                                             u64 data)
3632 {
3633         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3634
3635         return dd->send_egress_err_status_cnt[2];
3636 }
3637
3638 static u64 access_tx_pkt_integrity_mem_unc_err_cnt(
3639                                 const struct cntr_entry *entry,
3640                                 void *context, int vl, int mode, u64 data)
3641 {
3642         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3643
3644         return dd->send_egress_err_status_cnt[1];
3645 }
3646
3647 static u64 access_tx_pkt_integrity_mem_cor_err_cnt(
3648                                 const struct cntr_entry *entry,
3649                                 void *context, int vl, int mode, u64 data)
3650 {
3651         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3652
3653         return dd->send_egress_err_status_cnt[0];
3654 }
3655
3656 /*
3657  * Software counters corresponding to each of the
3658  * error status bits within SendErrStatus
3659  */
3660 static u64 access_send_csr_write_bad_addr_err_cnt(
3661                                 const struct cntr_entry *entry,
3662                                 void *context, int vl, int mode, u64 data)
3663 {
3664         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3665
3666         return dd->send_err_status_cnt[2];
3667 }
3668
3669 static u64 access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
3670                                                  void *context, int vl,
3671                                                  int mode, u64 data)
3672 {
3673         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3674
3675         return dd->send_err_status_cnt[1];
3676 }
3677
3678 static u64 access_send_csr_parity_cnt(const struct cntr_entry *entry,
3679                                       void *context, int vl, int mode,
3680                                       u64 data)
3681 {
3682         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3683
3684         return dd->send_err_status_cnt[0];
3685 }
3686
3687 /*
3688  * Software counters corresponding to each of the
3689  * error status bits within SendCtxtErrStatus
3690  */
3691 static u64 access_pio_write_out_of_bounds_err_cnt(
3692                                 const struct cntr_entry *entry,
3693                                 void *context, int vl, int mode, u64 data)
3694 {
3695         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3696
3697         return dd->sw_ctxt_err_status_cnt[4];
3698 }
3699
3700 static u64 access_pio_write_overflow_err_cnt(const struct cntr_entry *entry,
3701                                              void *context, int vl, int mode,
3702                                              u64 data)
3703 {
3704         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3705
3706         return dd->sw_ctxt_err_status_cnt[3];
3707 }
3708
3709 static u64 access_pio_write_crosses_boundary_err_cnt(
3710                                 const struct cntr_entry *entry,
3711                                 void *context, int vl, int mode, u64 data)
3712 {
3713         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3714
3715         return dd->sw_ctxt_err_status_cnt[2];
3716 }
3717
3718 static u64 access_pio_disallowed_packet_err_cnt(const struct cntr_entry *entry,
3719                                                 void *context, int vl,
3720                                                 int mode, u64 data)
3721 {
3722         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3723
3724         return dd->sw_ctxt_err_status_cnt[1];
3725 }
3726
3727 static u64 access_pio_inconsistent_sop_err_cnt(const struct cntr_entry *entry,
3728                                                void *context, int vl, int mode,
3729                                                u64 data)
3730 {
3731         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3732
3733         return dd->sw_ctxt_err_status_cnt[0];
3734 }
3735
3736 /*
3737  * Software counters corresponding to each of the
3738  * error status bits within SendDmaEngErrStatus
3739  */
3740 static u64 access_sdma_header_request_fifo_cor_err_cnt(
3741                                 const struct cntr_entry *entry,
3742                                 void *context, int vl, int mode, u64 data)
3743 {
3744         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3745
3746         return dd->sw_send_dma_eng_err_status_cnt[23];
3747 }
3748
3749 static u64 access_sdma_header_storage_cor_err_cnt(
3750                                 const struct cntr_entry *entry,
3751                                 void *context, int vl, int mode, u64 data)
3752 {
3753         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3754
3755         return dd->sw_send_dma_eng_err_status_cnt[22];
3756 }
3757
3758 static u64 access_sdma_packet_tracking_cor_err_cnt(
3759                                 const struct cntr_entry *entry,
3760                                 void *context, int vl, int mode, u64 data)
3761 {
3762         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3763
3764         return dd->sw_send_dma_eng_err_status_cnt[21];
3765 }
3766
3767 static u64 access_sdma_assembly_cor_err_cnt(const struct cntr_entry *entry,
3768                                             void *context, int vl, int mode,
3769                                             u64 data)
3770 {
3771         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3772
3773         return dd->sw_send_dma_eng_err_status_cnt[20];
3774 }
3775
3776 static u64 access_sdma_desc_table_cor_err_cnt(const struct cntr_entry *entry,
3777                                               void *context, int vl, int mode,
3778                                               u64 data)
3779 {
3780         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3781
3782         return dd->sw_send_dma_eng_err_status_cnt[19];
3783 }
3784
3785 static u64 access_sdma_header_request_fifo_unc_err_cnt(
3786                                 const struct cntr_entry *entry,
3787                                 void *context, int vl, int mode, u64 data)
3788 {
3789         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3790
3791         return dd->sw_send_dma_eng_err_status_cnt[18];
3792 }
3793
3794 static u64 access_sdma_header_storage_unc_err_cnt(
3795                                 const struct cntr_entry *entry,
3796                                 void *context, int vl, int mode, u64 data)
3797 {
3798         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3799
3800         return dd->sw_send_dma_eng_err_status_cnt[17];
3801 }
3802
3803 static u64 access_sdma_packet_tracking_unc_err_cnt(
3804                                 const struct cntr_entry *entry,
3805                                 void *context, int vl, int mode, u64 data)
3806 {
3807         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3808
3809         return dd->sw_send_dma_eng_err_status_cnt[16];
3810 }
3811
3812 static u64 access_sdma_assembly_unc_err_cnt(const struct cntr_entry *entry,
3813                                             void *context, int vl, int mode,
3814                                             u64 data)
3815 {
3816         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3817
3818         return dd->sw_send_dma_eng_err_status_cnt[15];
3819 }
3820
3821 static u64 access_sdma_desc_table_unc_err_cnt(const struct cntr_entry *entry,
3822                                               void *context, int vl, int mode,
3823                                               u64 data)
3824 {
3825         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3826
3827         return dd->sw_send_dma_eng_err_status_cnt[14];
3828 }
3829
3830 static u64 access_sdma_timeout_err_cnt(const struct cntr_entry *entry,
3831                                        void *context, int vl, int mode,
3832                                        u64 data)
3833 {
3834         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3835
3836         return dd->sw_send_dma_eng_err_status_cnt[13];
3837 }
3838
3839 static u64 access_sdma_header_length_err_cnt(const struct cntr_entry *entry,
3840                                              void *context, int vl, int mode,
3841                                              u64 data)
3842 {
3843         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3844
3845         return dd->sw_send_dma_eng_err_status_cnt[12];
3846 }
3847
3848 static u64 access_sdma_header_address_err_cnt(const struct cntr_entry *entry,
3849                                               void *context, int vl, int mode,
3850                                               u64 data)
3851 {
3852         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3853
3854         return dd->sw_send_dma_eng_err_status_cnt[11];
3855 }
3856
3857 static u64 access_sdma_header_select_err_cnt(const struct cntr_entry *entry,
3858                                              void *context, int vl, int mode,
3859                                              u64 data)
3860 {
3861         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3862
3863         return dd->sw_send_dma_eng_err_status_cnt[10];
3864 }
3865
3866 static u64 access_sdma_reserved_9_err_cnt(const struct cntr_entry *entry,
3867                                           void *context, int vl, int mode,
3868                                           u64 data)
3869 {
3870         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3871
3872         return dd->sw_send_dma_eng_err_status_cnt[9];
3873 }
3874
3875 static u64 access_sdma_packet_desc_overflow_err_cnt(
3876                                 const struct cntr_entry *entry,
3877                                 void *context, int vl, int mode, u64 data)
3878 {
3879         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3880
3881         return dd->sw_send_dma_eng_err_status_cnt[8];
3882 }
3883
3884 static u64 access_sdma_length_mismatch_err_cnt(const struct cntr_entry *entry,
3885                                                void *context, int vl,
3886                                                int mode, u64 data)
3887 {
3888         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3889
3890         return dd->sw_send_dma_eng_err_status_cnt[7];
3891 }
3892
3893 static u64 access_sdma_halt_err_cnt(const struct cntr_entry *entry,
3894                                     void *context, int vl, int mode, u64 data)
3895 {
3896         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3897
3898         return dd->sw_send_dma_eng_err_status_cnt[6];
3899 }
3900
3901 static u64 access_sdma_mem_read_err_cnt(const struct cntr_entry *entry,
3902                                         void *context, int vl, int mode,
3903                                         u64 data)
3904 {
3905         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3906
3907         return dd->sw_send_dma_eng_err_status_cnt[5];
3908 }
3909
3910 static u64 access_sdma_first_desc_err_cnt(const struct cntr_entry *entry,
3911                                           void *context, int vl, int mode,
3912                                           u64 data)
3913 {
3914         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3915
3916         return dd->sw_send_dma_eng_err_status_cnt[4];
3917 }
3918
3919 static u64 access_sdma_tail_out_of_bounds_err_cnt(
3920                                 const struct cntr_entry *entry,
3921                                 void *context, int vl, int mode, u64 data)
3922 {
3923         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3924
3925         return dd->sw_send_dma_eng_err_status_cnt[3];
3926 }
3927
3928 static u64 access_sdma_too_long_err_cnt(const struct cntr_entry *entry,
3929                                         void *context, int vl, int mode,
3930                                         u64 data)
3931 {
3932         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3933
3934         return dd->sw_send_dma_eng_err_status_cnt[2];
3935 }
3936
3937 static u64 access_sdma_gen_mismatch_err_cnt(const struct cntr_entry *entry,
3938                                             void *context, int vl, int mode,
3939                                             u64 data)
3940 {
3941         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3942
3943         return dd->sw_send_dma_eng_err_status_cnt[1];
3944 }
3945
3946 static u64 access_sdma_wrong_dw_err_cnt(const struct cntr_entry *entry,
3947                                         void *context, int vl, int mode,
3948                                         u64 data)
3949 {
3950         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3951
3952         return dd->sw_send_dma_eng_err_status_cnt[0];
3953 }
3954
3955 static u64 access_dc_rcv_err_cnt(const struct cntr_entry *entry,
3956                                  void *context, int vl, int mode,
3957                                  u64 data)
3958 {
3959         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3960
3961         u64 val = 0;
3962         u64 csr = entry->csr;
3963
3964         val = read_write_csr(dd, csr, mode, data);
3965         if (mode == CNTR_MODE_R) {
3966                 val = val > CNTR_MAX - dd->sw_rcv_bypass_packet_errors ?
3967                         CNTR_MAX : val + dd->sw_rcv_bypass_packet_errors;
3968         } else if (mode == CNTR_MODE_W) {
3969                 dd->sw_rcv_bypass_packet_errors = 0;
3970         } else {
3971                 dd_dev_err(dd, "Invalid cntr register access mode");
3972                 return 0;
3973         }
3974         return val;
3975 }
3976
3977 #define def_access_sw_cpu(cntr) \
3978 static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry,               \
3979                               void *context, int vl, int mode, u64 data)      \
3980 {                                                                             \
3981         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;        \
3982         return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr,       \
3983                               ppd->ibport_data.rvp.cntr, vl,                  \
3984                               mode, data);                                    \
3985 }
3986
3987 def_access_sw_cpu(rc_acks);
3988 def_access_sw_cpu(rc_qacks);
3989 def_access_sw_cpu(rc_delayed_comp);
3990
3991 #define def_access_ibp_counter(cntr) \
3992 static u64 access_ibp_##cntr(const struct cntr_entry *entry,                  \
3993                                 void *context, int vl, int mode, u64 data)    \
3994 {                                                                             \
3995         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;        \
3996                                                                               \
3997         if (vl != CNTR_INVALID_VL)                                            \
3998                 return 0;                                                     \
3999                                                                               \
4000         return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr,        \
4001                              mode, data);                                     \
4002 }
4003
4004 def_access_ibp_counter(loop_pkts);
4005 def_access_ibp_counter(rc_resends);
4006 def_access_ibp_counter(rnr_naks);
4007 def_access_ibp_counter(other_naks);
4008 def_access_ibp_counter(rc_timeouts);
4009 def_access_ibp_counter(pkt_drops);
4010 def_access_ibp_counter(dmawait);
4011 def_access_ibp_counter(rc_seqnak);
4012 def_access_ibp_counter(rc_dupreq);
4013 def_access_ibp_counter(rdma_seq);
4014 def_access_ibp_counter(unaligned);
4015 def_access_ibp_counter(seq_naks);
4016
4017 static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = {
4018 [C_RCV_OVF] = RXE32_DEV_CNTR_ELEM(RcvOverflow, RCV_BUF_OVFL_CNT, CNTR_SYNTH),
4019 [C_RX_TID_FULL] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr, RCV_TID_FULL_ERR_CNT,
4020                         CNTR_NORMAL),
4021 [C_RX_TID_INVALID] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid, RCV_TID_VALID_ERR_CNT,
4022                         CNTR_NORMAL),
4023 [C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs,
4024                         RCV_TID_FLOW_GEN_MISMATCH_CNT,
4025                         CNTR_NORMAL),
4026 [C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL,
4027                         CNTR_NORMAL),
4028 [C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs,
4029                         RCV_TID_FLOW_SEQ_MISMATCH_CNT, CNTR_NORMAL),
4030 [C_CCE_PCI_CR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt,
4031                         CCE_PCIE_POSTED_CRDT_STALL_CNT, CNTR_NORMAL),
4032 [C_CCE_PCI_TR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt, CCE_PCIE_TRGT_STALL_CNT,
4033                         CNTR_NORMAL),
4034 [C_CCE_PIO_WR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt, CCE_PIO_WR_STALL_CNT,
4035                         CNTR_NORMAL),
4036 [C_CCE_ERR_INT] = CCE_INT_DEV_CNTR_ELEM(CceErrInt, CCE_ERR_INT_CNT,
4037                         CNTR_NORMAL),
4038 [C_CCE_SDMA_INT] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt, CCE_SDMA_INT_CNT,
4039                         CNTR_NORMAL),
4040 [C_CCE_MISC_INT] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt, CCE_MISC_INT_CNT,
4041                         CNTR_NORMAL),
4042 [C_CCE_RCV_AV_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt, CCE_RCV_AVAIL_INT_CNT,
4043                         CNTR_NORMAL),
4044 [C_CCE_RCV_URG_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt,
4045                         CCE_RCV_URGENT_INT_CNT, CNTR_NORMAL),
4046 [C_CCE_SEND_CR_INT] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt,
4047                         CCE_SEND_CREDIT_INT_CNT, CNTR_NORMAL),
4048 [C_DC_UNC_ERR] = DC_PERF_CNTR(DcUnctblErr, DCC_ERR_UNCORRECTABLE_CNT,
4049                               CNTR_SYNTH),
4050 [C_DC_RCV_ERR] = CNTR_ELEM("DcRecvErr", DCC_ERR_PORTRCV_ERR_CNT, 0, CNTR_SYNTH,
4051                             access_dc_rcv_err_cnt),
4052 [C_DC_FM_CFG_ERR] = DC_PERF_CNTR(DcFmCfgErr, DCC_ERR_FMCONFIG_ERR_CNT,
4053                                  CNTR_SYNTH),
4054 [C_DC_RMT_PHY_ERR] = DC_PERF_CNTR(DcRmtPhyErr, DCC_ERR_RCVREMOTE_PHY_ERR_CNT,
4055                                   CNTR_SYNTH),
4056 [C_DC_DROPPED_PKT] = DC_PERF_CNTR(DcDroppedPkt, DCC_ERR_DROPPED_PKT_CNT,
4057                                   CNTR_SYNTH),
4058 [C_DC_MC_XMIT_PKTS] = DC_PERF_CNTR(DcMcXmitPkts,
4059                                    DCC_PRF_PORT_XMIT_MULTICAST_CNT, CNTR_SYNTH),
4060 [C_DC_MC_RCV_PKTS] = DC_PERF_CNTR(DcMcRcvPkts,
4061                                   DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT,
4062                                   CNTR_SYNTH),
4063 [C_DC_XMIT_CERR] = DC_PERF_CNTR(DcXmitCorr,
4064                                 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT, CNTR_SYNTH),
4065 [C_DC_RCV_CERR] = DC_PERF_CNTR(DcRcvCorrCnt, DCC_PRF_PORT_RCV_CORRECTABLE_CNT,
4066                                CNTR_SYNTH),
4067 [C_DC_RCV_FCC] = DC_PERF_CNTR(DcRxFCntl, DCC_PRF_RX_FLOW_CRTL_CNT,
4068                               CNTR_SYNTH),
4069 [C_DC_XMIT_FCC] = DC_PERF_CNTR(DcXmitFCntl, DCC_PRF_TX_FLOW_CRTL_CNT,
4070                                CNTR_SYNTH),
4071 [C_DC_XMIT_FLITS] = DC_PERF_CNTR(DcXmitFlits, DCC_PRF_PORT_XMIT_DATA_CNT,
4072                                  CNTR_SYNTH),
4073 [C_DC_RCV_FLITS] = DC_PERF_CNTR(DcRcvFlits, DCC_PRF_PORT_RCV_DATA_CNT,
4074                                 CNTR_SYNTH),
4075 [C_DC_XMIT_PKTS] = DC_PERF_CNTR(DcXmitPkts, DCC_PRF_PORT_XMIT_PKTS_CNT,
4076                                 CNTR_SYNTH),
4077 [C_DC_RCV_PKTS] = DC_PERF_CNTR(DcRcvPkts, DCC_PRF_PORT_RCV_PKTS_CNT,
4078                                CNTR_SYNTH),
4079 [C_DC_RX_FLIT_VL] = DC_PERF_CNTR(DcRxFlitVl, DCC_PRF_PORT_VL_RCV_DATA_CNT,
4080                                  CNTR_SYNTH | CNTR_VL),
4081 [C_DC_RX_PKT_VL] = DC_PERF_CNTR(DcRxPktVl, DCC_PRF_PORT_VL_RCV_PKTS_CNT,
4082                                 CNTR_SYNTH | CNTR_VL),
4083 [C_DC_RCV_FCN] = DC_PERF_CNTR(DcRcvFcn, DCC_PRF_PORT_RCV_FECN_CNT, CNTR_SYNTH),
4084 [C_DC_RCV_FCN_VL] = DC_PERF_CNTR(DcRcvFcnVl, DCC_PRF_PORT_VL_RCV_FECN_CNT,
4085                                  CNTR_SYNTH | CNTR_VL),
4086 [C_DC_RCV_BCN] = DC_PERF_CNTR(DcRcvBcn, DCC_PRF_PORT_RCV_BECN_CNT, CNTR_SYNTH),
4087 [C_DC_RCV_BCN_VL] = DC_PERF_CNTR(DcRcvBcnVl, DCC_PRF_PORT_VL_RCV_BECN_CNT,
4088                                  CNTR_SYNTH | CNTR_VL),
4089 [C_DC_RCV_BBL] = DC_PERF_CNTR(DcRcvBbl, DCC_PRF_PORT_RCV_BUBBLE_CNT,
4090                               CNTR_SYNTH),
4091 [C_DC_RCV_BBL_VL] = DC_PERF_CNTR(DcRcvBblVl, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT,
4092                                  CNTR_SYNTH | CNTR_VL),
4093 [C_DC_MARK_FECN] = DC_PERF_CNTR(DcMarkFcn, DCC_PRF_PORT_MARK_FECN_CNT,
4094                                 CNTR_SYNTH),
4095 [C_DC_MARK_FECN_VL] = DC_PERF_CNTR(DcMarkFcnVl, DCC_PRF_PORT_VL_MARK_FECN_CNT,
4096                                    CNTR_SYNTH | CNTR_VL),
4097 [C_DC_TOTAL_CRC] =
4098         DC_PERF_CNTR_LCB(DcTotCrc, DC_LCB_ERR_INFO_TOTAL_CRC_ERR,
4099                          CNTR_SYNTH),
4100 [C_DC_CRC_LN0] = DC_PERF_CNTR_LCB(DcCrcLn0, DC_LCB_ERR_INFO_CRC_ERR_LN0,
4101                                   CNTR_SYNTH),
4102 [C_DC_CRC_LN1] = DC_PERF_CNTR_LCB(DcCrcLn1, DC_LCB_ERR_INFO_CRC_ERR_LN1,
4103                                   CNTR_SYNTH),
4104 [C_DC_CRC_LN2] = DC_PERF_CNTR_LCB(DcCrcLn2, DC_LCB_ERR_INFO_CRC_ERR_LN2,
4105                                   CNTR_SYNTH),
4106 [C_DC_CRC_LN3] = DC_PERF_CNTR_LCB(DcCrcLn3, DC_LCB_ERR_INFO_CRC_ERR_LN3,
4107                                   CNTR_SYNTH),
4108 [C_DC_CRC_MULT_LN] =
4109         DC_PERF_CNTR_LCB(DcMultLn, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN,
4110                          CNTR_SYNTH),
4111 [C_DC_TX_REPLAY] = DC_PERF_CNTR_LCB(DcTxReplay, DC_LCB_ERR_INFO_TX_REPLAY_CNT,
4112                                     CNTR_SYNTH),
4113 [C_DC_RX_REPLAY] = DC_PERF_CNTR_LCB(DcRxReplay, DC_LCB_ERR_INFO_RX_REPLAY_CNT,
4114                                     CNTR_SYNTH),
4115 [C_DC_SEQ_CRC_CNT] =
4116         DC_PERF_CNTR_LCB(DcLinkSeqCrc, DC_LCB_ERR_INFO_SEQ_CRC_CNT,
4117                          CNTR_SYNTH),
4118 [C_DC_ESC0_ONLY_CNT] =
4119         DC_PERF_CNTR_LCB(DcEsc0, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT,
4120                          CNTR_SYNTH),
4121 [C_DC_ESC0_PLUS1_CNT] =
4122         DC_PERF_CNTR_LCB(DcEsc1, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT,
4123                          CNTR_SYNTH),
4124 [C_DC_ESC0_PLUS2_CNT] =
4125         DC_PERF_CNTR_LCB(DcEsc0Plus2, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT,
4126                          CNTR_SYNTH),
4127 [C_DC_REINIT_FROM_PEER_CNT] =
4128         DC_PERF_CNTR_LCB(DcReinitPeer, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT,
4129                          CNTR_SYNTH),
4130 [C_DC_SBE_CNT] = DC_PERF_CNTR_LCB(DcSbe, DC_LCB_ERR_INFO_SBE_CNT,
4131                                   CNTR_SYNTH),
4132 [C_DC_MISC_FLG_CNT] =
4133         DC_PERF_CNTR_LCB(DcMiscFlg, DC_LCB_ERR_INFO_MISC_FLG_CNT,
4134                          CNTR_SYNTH),
4135 [C_DC_PRF_GOOD_LTP_CNT] =
4136         DC_PERF_CNTR_LCB(DcGoodLTP, DC_LCB_PRF_GOOD_LTP_CNT, CNTR_SYNTH),
4137 [C_DC_PRF_ACCEPTED_LTP_CNT] =
4138         DC_PERF_CNTR_LCB(DcAccLTP, DC_LCB_PRF_ACCEPTED_LTP_CNT,
4139                          CNTR_SYNTH),
4140 [C_DC_PRF_RX_FLIT_CNT] =
4141         DC_PERF_CNTR_LCB(DcPrfRxFlit, DC_LCB_PRF_RX_FLIT_CNT, CNTR_SYNTH),
4142 [C_DC_PRF_TX_FLIT_CNT] =
4143         DC_PERF_CNTR_LCB(DcPrfTxFlit, DC_LCB_PRF_TX_FLIT_CNT, CNTR_SYNTH),
4144 [C_DC_PRF_CLK_CNTR] =
4145         DC_PERF_CNTR_LCB(DcPrfClk, DC_LCB_PRF_CLK_CNTR, CNTR_SYNTH),
4146 [C_DC_PG_DBG_FLIT_CRDTS_CNT] =
4147         DC_PERF_CNTR_LCB(DcFltCrdts, DC_LCB_PG_DBG_FLIT_CRDTS_CNT, CNTR_SYNTH),
4148 [C_DC_PG_STS_PAUSE_COMPLETE_CNT] =
4149         DC_PERF_CNTR_LCB(DcPauseComp, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT,
4150                          CNTR_SYNTH),
4151 [C_DC_PG_STS_TX_SBE_CNT] =
4152         DC_PERF_CNTR_LCB(DcStsTxSbe, DC_LCB_PG_STS_TX_SBE_CNT, CNTR_SYNTH),
4153 [C_DC_PG_STS_TX_MBE_CNT] =
4154         DC_PERF_CNTR_LCB(DcStsTxMbe, DC_LCB_PG_STS_TX_MBE_CNT,
4155                          CNTR_SYNTH),
4156 [C_SW_CPU_INTR] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL,
4157                             access_sw_cpu_intr),
4158 [C_SW_CPU_RCV_LIM] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL,
4159                             access_sw_cpu_rcv_limit),
4160 [C_SW_VTX_WAIT] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL,
4161                             access_sw_vtx_wait),
4162 [C_SW_PIO_WAIT] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL,
4163                             access_sw_pio_wait),
4164 [C_SW_PIO_DRAIN] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL,
4165                             access_sw_pio_drain),
4166 [C_SW_KMEM_WAIT] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL,
4167                             access_sw_kmem_wait),
4168 [C_SW_SEND_SCHED] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL,
4169                             access_sw_send_schedule),
4170 [C_SDMA_DESC_FETCHED_CNT] = CNTR_ELEM("SDEDscFdCn",
4171                                       SEND_DMA_DESC_FETCHED_CNT, 0,
4172                                       CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4173                                       dev_access_u32_csr),
4174 [C_SDMA_INT_CNT] = CNTR_ELEM("SDMAInt", 0, 0,
4175                              CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4176                              access_sde_int_cnt),
4177 [C_SDMA_ERR_CNT] = CNTR_ELEM("SDMAErrCt", 0, 0,
4178                              CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4179                              access_sde_err_cnt),
4180 [C_SDMA_IDLE_INT_CNT] = CNTR_ELEM("SDMAIdInt", 0, 0,
4181                                   CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4182                                   access_sde_idle_int_cnt),
4183 [C_SDMA_PROGRESS_INT_CNT] = CNTR_ELEM("SDMAPrIntCn", 0, 0,
4184                                       CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4185                                       access_sde_progress_int_cnt),
4186 /* MISC_ERR_STATUS */
4187 [C_MISC_PLL_LOCK_FAIL_ERR] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0,
4188                                 CNTR_NORMAL,
4189                                 access_misc_pll_lock_fail_err_cnt),
4190 [C_MISC_MBIST_FAIL_ERR] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0,
4191                                 CNTR_NORMAL,
4192                                 access_misc_mbist_fail_err_cnt),
4193 [C_MISC_INVALID_EEP_CMD_ERR] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0,
4194                                 CNTR_NORMAL,
4195                                 access_misc_invalid_eep_cmd_err_cnt),
4196 [C_MISC_EFUSE_DONE_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0,
4197                                 CNTR_NORMAL,
4198                                 access_misc_efuse_done_parity_err_cnt),
4199 [C_MISC_EFUSE_WRITE_ERR] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0,
4200                                 CNTR_NORMAL,
4201                                 access_misc_efuse_write_err_cnt),
4202 [C_MISC_EFUSE_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0,
4203                                 0, CNTR_NORMAL,
4204                                 access_misc_efuse_read_bad_addr_err_cnt),
4205 [C_MISC_EFUSE_CSR_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0,
4206                                 CNTR_NORMAL,
4207                                 access_misc_efuse_csr_parity_err_cnt),
4208 [C_MISC_FW_AUTH_FAILED_ERR] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0,
4209                                 CNTR_NORMAL,
4210                                 access_misc_fw_auth_failed_err_cnt),
4211 [C_MISC_KEY_MISMATCH_ERR] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0,
4212                                 CNTR_NORMAL,
4213                                 access_misc_key_mismatch_err_cnt),
4214 [C_MISC_SBUS_WRITE_FAILED_ERR] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0,
4215                                 CNTR_NORMAL,
4216                                 access_misc_sbus_write_failed_err_cnt),
4217 [C_MISC_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0,
4218                                 CNTR_NORMAL,
4219                                 access_misc_csr_write_bad_addr_err_cnt),
4220 [C_MISC_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0,
4221                                 CNTR_NORMAL,
4222                                 access_misc_csr_read_bad_addr_err_cnt),
4223 [C_MISC_CSR_PARITY_ERR] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0,
4224                                 CNTR_NORMAL,
4225                                 access_misc_csr_parity_err_cnt),
4226 /* CceErrStatus */
4227 [C_CCE_ERR_STATUS_AGGREGATED_CNT] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0,
4228                                 CNTR_NORMAL,
4229                                 access_sw_cce_err_status_aggregated_cnt),
4230 [C_CCE_MSIX_CSR_PARITY_ERR] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0,
4231                                 CNTR_NORMAL,
4232                                 access_cce_msix_csr_parity_err_cnt),
4233 [C_CCE_INT_MAP_UNC_ERR] = CNTR_ELEM("CceIntMapUncErr", 0, 0,
4234                                 CNTR_NORMAL,
4235                                 access_cce_int_map_unc_err_cnt),
4236 [C_CCE_INT_MAP_COR_ERR] = CNTR_ELEM("CceIntMapCorErr", 0, 0,
4237                                 CNTR_NORMAL,
4238                                 access_cce_int_map_cor_err_cnt),
4239 [C_CCE_MSIX_TABLE_UNC_ERR] = CNTR_ELEM("CceMsixTableUncErr", 0, 0,
4240                                 CNTR_NORMAL,
4241                                 access_cce_msix_table_unc_err_cnt),
4242 [C_CCE_MSIX_TABLE_COR_ERR] = CNTR_ELEM("CceMsixTableCorErr", 0, 0,
4243                                 CNTR_NORMAL,
4244                                 access_cce_msix_table_cor_err_cnt),
4245 [C_CCE_RXDMA_CONV_FIFO_PARITY_ERR] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0,
4246                                 0, CNTR_NORMAL,
4247                                 access_cce_rxdma_conv_fifo_parity_err_cnt),
4248 [C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0,
4249                                 0, CNTR_NORMAL,
4250                                 access_cce_rcpl_async_fifo_parity_err_cnt),
4251 [C_CCE_SEG_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0,
4252                                 CNTR_NORMAL,
4253                                 access_cce_seg_write_bad_addr_err_cnt),
4254 [C_CCE_SEG_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0,
4255                                 CNTR_NORMAL,
4256                                 access_cce_seg_read_bad_addr_err_cnt),
4257 [C_LA_TRIGGERED] = CNTR_ELEM("Cce LATriggered", 0, 0,
4258                                 CNTR_NORMAL,
4259                                 access_la_triggered_cnt),
4260 [C_CCE_TRGT_CPL_TIMEOUT_ERR] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0,
4261                                 CNTR_NORMAL,
4262                                 access_cce_trgt_cpl_timeout_err_cnt),
4263 [C_PCIC_RECEIVE_PARITY_ERR] = CNTR_ELEM("PcicReceiveParityErr", 0, 0,
4264                                 CNTR_NORMAL,
4265                                 access_pcic_receive_parity_err_cnt),
4266 [C_PCIC_TRANSMIT_BACK_PARITY_ERR] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0,
4267                                 CNTR_NORMAL,
4268                                 access_pcic_transmit_back_parity_err_cnt),
4269 [C_PCIC_TRANSMIT_FRONT_PARITY_ERR] = CNTR_ELEM("PcicTransmitFrontParityErr", 0,
4270                                 0, CNTR_NORMAL,
4271                                 access_pcic_transmit_front_parity_err_cnt),
4272 [C_PCIC_CPL_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0,
4273                                 CNTR_NORMAL,
4274                                 access_pcic_cpl_dat_q_unc_err_cnt),
4275 [C_PCIC_CPL_HD_Q_UNC_ERR] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0,
4276                                 CNTR_NORMAL,
4277                                 access_pcic_cpl_hd_q_unc_err_cnt),
4278 [C_PCIC_POST_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0,
4279                                 CNTR_NORMAL,
4280                                 access_pcic_post_dat_q_unc_err_cnt),
4281 [C_PCIC_POST_HD_Q_UNC_ERR] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0,
4282                                 CNTR_NORMAL,
4283                                 access_pcic_post_hd_q_unc_err_cnt),
4284 [C_PCIC_RETRY_SOT_MEM_UNC_ERR] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0,
4285                                 CNTR_NORMAL,
4286                                 access_pcic_retry_sot_mem_unc_err_cnt),
4287 [C_PCIC_RETRY_MEM_UNC_ERR] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0,
4288                                 CNTR_NORMAL,
4289                                 access_pcic_retry_mem_unc_err),
4290 [C_PCIC_N_POST_DAT_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0,
4291                                 CNTR_NORMAL,
4292                                 access_pcic_n_post_dat_q_parity_err_cnt),
4293 [C_PCIC_N_POST_H_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0,
4294                                 CNTR_NORMAL,
4295                                 access_pcic_n_post_h_q_parity_err_cnt),
4296 [C_PCIC_CPL_DAT_Q_COR_ERR] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0,
4297                                 CNTR_NORMAL,
4298                                 access_pcic_cpl_dat_q_cor_err_cnt),
4299 [C_PCIC_CPL_HD_Q_COR_ERR] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0,
4300                                 CNTR_NORMAL,
4301                                 access_pcic_cpl_hd_q_cor_err_cnt),
4302 [C_PCIC_POST_DAT_Q_COR_ERR] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0,
4303                                 CNTR_NORMAL,
4304                                 access_pcic_post_dat_q_cor_err_cnt),
4305 [C_PCIC_POST_HD_Q_COR_ERR] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0,
4306                                 CNTR_NORMAL,
4307                                 access_pcic_post_hd_q_cor_err_cnt),
4308 [C_PCIC_RETRY_SOT_MEM_COR_ERR] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0,
4309                                 CNTR_NORMAL,
4310                                 access_pcic_retry_sot_mem_cor_err_cnt),
4311 [C_PCIC_RETRY_MEM_COR_ERR] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0,
4312                                 CNTR_NORMAL,
4313                                 access_pcic_retry_mem_cor_err_cnt),
4314 [C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR] = CNTR_ELEM(
4315                                 "CceCli1AsyncFifoDbgParityError", 0, 0,
4316                                 CNTR_NORMAL,
4317                                 access_cce_cli1_async_fifo_dbg_parity_err_cnt),
4318 [C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR] = CNTR_ELEM(
4319                                 "CceCli1AsyncFifoRxdmaParityError", 0, 0,
4320                                 CNTR_NORMAL,
4321                                 access_cce_cli1_async_fifo_rxdma_parity_err_cnt
4322                                 ),
4323 [C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR] = CNTR_ELEM(
4324                         "CceCli1AsyncFifoSdmaHdParityErr", 0, 0,
4325                         CNTR_NORMAL,
4326                         access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt),
4327 [C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR] = CNTR_ELEM(
4328                         "CceCli1AsyncFifoPioCrdtParityErr", 0, 0,
4329                         CNTR_NORMAL,
4330                         access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt),
4331 [C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0,
4332                         0, CNTR_NORMAL,
4333                         access_cce_cli2_async_fifo_parity_err_cnt),
4334 [C_CCE_CSR_CFG_BUS_PARITY_ERR] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0,
4335                         CNTR_NORMAL,
4336                         access_cce_csr_cfg_bus_parity_err_cnt),
4337 [C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0,
4338                         0, CNTR_NORMAL,
4339                         access_cce_cli0_async_fifo_parity_err_cnt),
4340 [C_CCE_RSPD_DATA_PARITY_ERR] = CNTR_ELEM("CceRspdDataParityErr", 0, 0,
4341                         CNTR_NORMAL,
4342                         access_cce_rspd_data_parity_err_cnt),
4343 [C_CCE_TRGT_ACCESS_ERR] = CNTR_ELEM("CceTrgtAccessErr", 0, 0,
4344                         CNTR_NORMAL,
4345                         access_cce_trgt_access_err_cnt),
4346 [C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0,
4347                         0, CNTR_NORMAL,
4348                         access_cce_trgt_async_fifo_parity_err_cnt),
4349 [C_CCE_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0,
4350                         CNTR_NORMAL,
4351                         access_cce_csr_write_bad_addr_err_cnt),
4352 [C_CCE_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0,
4353                         CNTR_NORMAL,
4354                         access_cce_csr_read_bad_addr_err_cnt),
4355 [C_CCE_CSR_PARITY_ERR] = CNTR_ELEM("CceCsrParityErr", 0, 0,
4356                         CNTR_NORMAL,
4357                         access_ccs_csr_parity_err_cnt),
4358
4359 /* RcvErrStatus */
4360 [C_RX_CSR_PARITY_ERR] = CNTR_ELEM("RxCsrParityErr", 0, 0,
4361                         CNTR_NORMAL,
4362                         access_rx_csr_parity_err_cnt),
4363 [C_RX_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0,
4364                         CNTR_NORMAL,
4365                         access_rx_csr_write_bad_addr_err_cnt),
4366 [C_RX_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0,
4367                         CNTR_NORMAL,
4368                         access_rx_csr_read_bad_addr_err_cnt),
4369 [C_RX_DMA_CSR_UNC_ERR] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0,
4370                         CNTR_NORMAL,
4371                         access_rx_dma_csr_unc_err_cnt),
4372 [C_RX_DMA_DQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0,
4373                         CNTR_NORMAL,
4374                         access_rx_dma_dq_fsm_encoding_err_cnt),
4375 [C_RX_DMA_EQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0,
4376                         CNTR_NORMAL,
4377                         access_rx_dma_eq_fsm_encoding_err_cnt),
4378 [C_RX_DMA_CSR_PARITY_ERR] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0,
4379                         CNTR_NORMAL,
4380                         access_rx_dma_csr_parity_err_cnt),
4381 [C_RX_RBUF_DATA_COR_ERR] = CNTR_ELEM("RxRbufDataCorErr", 0, 0,
4382                         CNTR_NORMAL,
4383                         access_rx_rbuf_data_cor_err_cnt),
4384 [C_RX_RBUF_DATA_UNC_ERR] = CNTR_ELEM("RxRbufDataUncErr", 0, 0,
4385                         CNTR_NORMAL,
4386                         access_rx_rbuf_data_unc_err_cnt),
4387 [C_RX_DMA_DATA_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0,
4388                         CNTR_NORMAL,
4389                         access_rx_dma_data_fifo_rd_cor_err_cnt),
4390 [C_RX_DMA_DATA_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0,
4391                         CNTR_NORMAL,
4392                         access_rx_dma_data_fifo_rd_unc_err_cnt),
4393 [C_RX_DMA_HDR_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0,
4394                         CNTR_NORMAL,
4395                         access_rx_dma_hdr_fifo_rd_cor_err_cnt),
4396 [C_RX_DMA_HDR_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0,
4397                         CNTR_NORMAL,
4398                         access_rx_dma_hdr_fifo_rd_unc_err_cnt),
4399 [C_RX_RBUF_DESC_PART2_COR_ERR] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0,
4400                         CNTR_NORMAL,
4401                         access_rx_rbuf_desc_part2_cor_err_cnt),
4402 [C_RX_RBUF_DESC_PART2_UNC_ERR] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0,
4403                         CNTR_NORMAL,
4404                         access_rx_rbuf_desc_part2_unc_err_cnt),
4405 [C_RX_RBUF_DESC_PART1_COR_ERR] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0,
4406                         CNTR_NORMAL,
4407                         access_rx_rbuf_desc_part1_cor_err_cnt),
4408 [C_RX_RBUF_DESC_PART1_UNC_ERR] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0,
4409                         CNTR_NORMAL,
4410                         access_rx_rbuf_desc_part1_unc_err_cnt),
4411 [C_RX_HQ_INTR_FSM_ERR] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0,
4412                         CNTR_NORMAL,
4413                         access_rx_hq_intr_fsm_err_cnt),
4414 [C_RX_HQ_INTR_CSR_PARITY_ERR] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0,
4415                         CNTR_NORMAL,
4416                         access_rx_hq_intr_csr_parity_err_cnt),
4417 [C_RX_LOOKUP_CSR_PARITY_ERR] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0,
4418                         CNTR_NORMAL,
4419                         access_rx_lookup_csr_parity_err_cnt),
4420 [C_RX_LOOKUP_RCV_ARRAY_COR_ERR] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0,
4421                         CNTR_NORMAL,
4422                         access_rx_lookup_rcv_array_cor_err_cnt),
4423 [C_RX_LOOKUP_RCV_ARRAY_UNC_ERR] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0,
4424                         CNTR_NORMAL,
4425                         access_rx_lookup_rcv_array_unc_err_cnt),
4426 [C_RX_LOOKUP_DES_PART2_PARITY_ERR] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0,
4427                         0, CNTR_NORMAL,
4428                         access_rx_lookup_des_part2_parity_err_cnt),
4429 [C_RX_LOOKUP_DES_PART1_UNC_COR_ERR] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0,
4430                         0, CNTR_NORMAL,
4431                         access_rx_lookup_des_part1_unc_cor_err_cnt),
4432 [C_RX_LOOKUP_DES_PART1_UNC_ERR] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0,
4433                         CNTR_NORMAL,
4434                         access_rx_lookup_des_part1_unc_err_cnt),
4435 [C_RX_RBUF_NEXT_FREE_BUF_COR_ERR] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0,
4436                         CNTR_NORMAL,
4437                         access_rx_rbuf_next_free_buf_cor_err_cnt),
4438 [C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0,
4439                         CNTR_NORMAL,
4440                         access_rx_rbuf_next_free_buf_unc_err_cnt),
4441 [C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR] = CNTR_ELEM(
4442                         "RxRbufFlInitWrAddrParityErr", 0, 0,
4443                         CNTR_NORMAL,
4444                         access_rbuf_fl_init_wr_addr_parity_err_cnt),
4445 [C_RX_RBUF_FL_INITDONE_PARITY_ERR] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0,
4446                         0, CNTR_NORMAL,
4447                         access_rx_rbuf_fl_initdone_parity_err_cnt),
4448 [C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0,
4449                         0, CNTR_NORMAL,
4450                         access_rx_rbuf_fl_write_addr_parity_err_cnt),
4451 [C_RX_RBUF_FL_RD_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0,
4452                         CNTR_NORMAL,
4453                         access_rx_rbuf_fl_rd_addr_parity_err_cnt),
4454 [C_RX_RBUF_EMPTY_ERR] = CNTR_ELEM("RxRbufEmptyErr", 0, 0,
4455                         CNTR_NORMAL,
4456                         access_rx_rbuf_empty_err_cnt),
4457 [C_RX_RBUF_FULL_ERR] = CNTR_ELEM("RxRbufFullErr", 0, 0,
4458                         CNTR_NORMAL,
4459                         access_rx_rbuf_full_err_cnt),
4460 [C_RX_RBUF_BAD_LOOKUP_ERR] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0,
4461                         CNTR_NORMAL,
4462                         access_rbuf_bad_lookup_err_cnt),
4463 [C_RX_RBUF_CTX_ID_PARITY_ERR] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0,
4464                         CNTR_NORMAL,
4465                         access_rbuf_ctx_id_parity_err_cnt),
4466 [C_RX_RBUF_CSR_QEOPDW_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0,
4467                         CNTR_NORMAL,
4468                         access_rbuf_csr_qeopdw_parity_err_cnt),
4469 [C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR] = CNTR_ELEM(
4470                         "RxRbufCsrQNumOfPktParityErr", 0, 0,
4471                         CNTR_NORMAL,
4472                         access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt),
4473 [C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR] = CNTR_ELEM(
4474                         "RxRbufCsrQTlPtrParityErr", 0, 0,
4475                         CNTR_NORMAL,
4476                         access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt),
4477 [C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0,
4478                         0, CNTR_NORMAL,
4479                         access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt),
4480 [C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0,
4481                         0, CNTR_NORMAL,
4482                         access_rx_rbuf_csr_q_vld_bit_parity_err_cnt),
4483 [C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQNextBufParityErr",
4484                         0, 0, CNTR_NORMAL,
4485                         access_rx_rbuf_csr_q_next_buf_parity_err_cnt),
4486 [C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0,
4487                         0, CNTR_NORMAL,
4488                         access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt),
4489 [C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR] = CNTR_ELEM(
4490                         "RxRbufCsrQHeadBufNumParityErr", 0, 0,
4491                         CNTR_NORMAL,
4492                         access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt),
4493 [C_RX_RBUF_BLOCK_LIST_READ_COR_ERR] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0,
4494                         0, CNTR_NORMAL,
4495                         access_rx_rbuf_block_list_read_cor_err_cnt),
4496 [C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0,
4497                         0, CNTR_NORMAL,
4498                         access_rx_rbuf_block_list_read_unc_err_cnt),
4499 [C_RX_RBUF_LOOKUP_DES_COR_ERR] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0,
4500                         CNTR_NORMAL,
4501                         access_rx_rbuf_lookup_des_cor_err_cnt),
4502 [C_RX_RBUF_LOOKUP_DES_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0,
4503                         CNTR_NORMAL,
4504                         access_rx_rbuf_lookup_des_unc_err_cnt),
4505 [C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR] = CNTR_ELEM(
4506                         "RxRbufLookupDesRegUncCorErr", 0, 0,
4507                         CNTR_NORMAL,
4508                         access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt),
4509 [C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0,
4510                         CNTR_NORMAL,
4511                         access_rx_rbuf_lookup_des_reg_unc_err_cnt),
4512 [C_RX_RBUF_FREE_LIST_COR_ERR] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0,
4513                         CNTR_NORMAL,
4514                         access_rx_rbuf_free_list_cor_err_cnt),
4515 [C_RX_RBUF_FREE_LIST_UNC_ERR] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0,
4516                         CNTR_NORMAL,
4517                         access_rx_rbuf_free_list_unc_err_cnt),
4518 [C_RX_RCV_FSM_ENCODING_ERR] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0,
4519                         CNTR_NORMAL,
4520                         access_rx_rcv_fsm_encoding_err_cnt),
4521 [C_RX_DMA_FLAG_COR_ERR] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0,
4522                         CNTR_NORMAL,
4523                         access_rx_dma_flag_cor_err_cnt),
4524 [C_RX_DMA_FLAG_UNC_ERR] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0,
4525                         CNTR_NORMAL,
4526                         access_rx_dma_flag_unc_err_cnt),
4527 [C_RX_DC_SOP_EOP_PARITY_ERR] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0,
4528                         CNTR_NORMAL,
4529                         access_rx_dc_sop_eop_parity_err_cnt),
4530 [C_RX_RCV_CSR_PARITY_ERR] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0,
4531                         CNTR_NORMAL,
4532                         access_rx_rcv_csr_parity_err_cnt),
4533 [C_RX_RCV_QP_MAP_TABLE_COR_ERR] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0,
4534                         CNTR_NORMAL,
4535                         access_rx_rcv_qp_map_table_cor_err_cnt),
4536 [C_RX_RCV_QP_MAP_TABLE_UNC_ERR] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0,
4537                         CNTR_NORMAL,
4538                         access_rx_rcv_qp_map_table_unc_err_cnt),
4539 [C_RX_RCV_DATA_COR_ERR] = CNTR_ELEM("RxRcvDataCorErr", 0, 0,
4540                         CNTR_NORMAL,
4541                         access_rx_rcv_data_cor_err_cnt),
4542 [C_RX_RCV_DATA_UNC_ERR] = CNTR_ELEM("RxRcvDataUncErr", 0, 0,
4543                         CNTR_NORMAL,
4544                         access_rx_rcv_data_unc_err_cnt),
4545 [C_RX_RCV_HDR_COR_ERR] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0,
4546                         CNTR_NORMAL,
4547                         access_rx_rcv_hdr_cor_err_cnt),
4548 [C_RX_RCV_HDR_UNC_ERR] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0,
4549                         CNTR_NORMAL,
4550                         access_rx_rcv_hdr_unc_err_cnt),
4551 [C_RX_DC_INTF_PARITY_ERR] = CNTR_ELEM("RxDcIntfParityErr", 0, 0,
4552                         CNTR_NORMAL,
4553                         access_rx_dc_intf_parity_err_cnt),
4554 [C_RX_DMA_CSR_COR_ERR] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0,
4555                         CNTR_NORMAL,
4556                         access_rx_dma_csr_cor_err_cnt),
4557 /* SendPioErrStatus */
4558 [C_PIO_PEC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0,
4559                         CNTR_NORMAL,
4560                         access_pio_pec_sop_head_parity_err_cnt),
4561 [C_PIO_PCC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0,
4562                         CNTR_NORMAL,
4563                         access_pio_pcc_sop_head_parity_err_cnt),
4564 [C_PIO_LAST_RETURNED_CNT_PARITY_ERR] = CNTR_ELEM("PioLastReturnedCntParityErr",
4565                         0, 0, CNTR_NORMAL,
4566                         access_pio_last_returned_cnt_parity_err_cnt),
4567 [C_PIO_CURRENT_FREE_CNT_PARITY_ERR] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0,
4568                         0, CNTR_NORMAL,
4569                         access_pio_current_free_cnt_parity_err_cnt),
4570 [C_PIO_RSVD_31_ERR] = CNTR_ELEM("Pio Reserved 31", 0, 0,
4571                         CNTR_NORMAL,
4572                         access_pio_reserved_31_err_cnt),
4573 [C_PIO_RSVD_30_ERR] = CNTR_ELEM("Pio Reserved 30", 0, 0,
4574                         CNTR_NORMAL,
4575                         access_pio_reserved_30_err_cnt),
4576 [C_PIO_PPMC_SOP_LEN_ERR] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0,
4577                         CNTR_NORMAL,
4578                         access_pio_ppmc_sop_len_err_cnt),
4579 [C_PIO_PPMC_BQC_MEM_PARITY_ERR] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0,
4580                         CNTR_NORMAL,
4581                         access_pio_ppmc_bqc_mem_parity_err_cnt),
4582 [C_PIO_VL_FIFO_PARITY_ERR] = CNTR_ELEM("PioVlFifoParityErr", 0, 0,
4583                         CNTR_NORMAL,
4584                         access_pio_vl_fifo_parity_err_cnt),
4585 [C_PIO_VLF_SOP_PARITY_ERR] = CNTR_ELEM("PioVlfSopParityErr", 0, 0,
4586                         CNTR_NORMAL,
4587                         access_pio_vlf_sop_parity_err_cnt),
4588 [C_PIO_VLF_V1_LEN_PARITY_ERR] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0,
4589                         CNTR_NORMAL,
4590                         access_pio_vlf_v1_len_parity_err_cnt),
4591 [C_PIO_BLOCK_QW_COUNT_PARITY_ERR] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0,
4592                         CNTR_NORMAL,
4593                         access_pio_block_qw_count_parity_err_cnt),
4594 [C_PIO_WRITE_QW_VALID_PARITY_ERR] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0,
4595                         CNTR_NORMAL,
4596                         access_pio_write_qw_valid_parity_err_cnt),
4597 [C_PIO_STATE_MACHINE_ERR] = CNTR_ELEM("PioStateMachineErr", 0, 0,
4598                         CNTR_NORMAL,
4599                         access_pio_state_machine_err_cnt),
4600 [C_PIO_WRITE_DATA_PARITY_ERR] = CNTR_ELEM("PioWriteDataParityErr", 0, 0,
4601                         CNTR_NORMAL,
4602                         access_pio_write_data_parity_err_cnt),
4603 [C_PIO_HOST_ADDR_MEM_COR_ERR] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0,
4604                         CNTR_NORMAL,
4605                         access_pio_host_addr_mem_cor_err_cnt),
4606 [C_PIO_HOST_ADDR_MEM_UNC_ERR] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0,
4607                         CNTR_NORMAL,
4608                         access_pio_host_addr_mem_unc_err_cnt),
4609 [C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0,
4610                         CNTR_NORMAL,
4611                         access_pio_pkt_evict_sm_or_arb_sm_err_cnt),
4612 [C_PIO_INIT_SM_IN_ERR] = CNTR_ELEM("PioInitSmInErr", 0, 0,
4613                         CNTR_NORMAL,
4614                         access_pio_init_sm_in_err_cnt),
4615 [C_PIO_PPMC_PBL_FIFO_ERR] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0,
4616                         CNTR_NORMAL,
4617                         access_pio_ppmc_pbl_fifo_err_cnt),
4618 [C_PIO_CREDIT_RET_FIFO_PARITY_ERR] = CNTR_ELEM("PioCreditRetFifoParityErr", 0,
4619                         0, CNTR_NORMAL,
4620                         access_pio_credit_ret_fifo_parity_err_cnt),
4621 [C_PIO_V1_LEN_MEM_BANK1_COR_ERR] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0,
4622                         CNTR_NORMAL,
4623                         access_pio_v1_len_mem_bank1_cor_err_cnt),
4624 [C_PIO_V1_LEN_MEM_BANK0_COR_ERR] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0,
4625                         CNTR_NORMAL,
4626                         access_pio_v1_len_mem_bank0_cor_err_cnt),
4627 [C_PIO_V1_LEN_MEM_BANK1_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0,
4628                         CNTR_NORMAL,
4629                         access_pio_v1_len_mem_bank1_unc_err_cnt),
4630 [C_PIO_V1_LEN_MEM_BANK0_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0,
4631                         CNTR_NORMAL,
4632                         access_pio_v1_len_mem_bank0_unc_err_cnt),
4633 [C_PIO_SM_PKT_RESET_PARITY_ERR] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0,
4634                         CNTR_NORMAL,
4635                         access_pio_sm_pkt_reset_parity_err_cnt),
4636 [C_PIO_PKT_EVICT_FIFO_PARITY_ERR] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0,
4637                         CNTR_NORMAL,
4638                         access_pio_pkt_evict_fifo_parity_err_cnt),
4639 [C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR] = CNTR_ELEM(
4640                         "PioSbrdctrlCrrelFifoParityErr", 0, 0,
4641                         CNTR_NORMAL,
4642                         access_pio_sbrdctrl_crrel_fifo_parity_err_cnt),
4643 [C_PIO_SBRDCTL_CRREL_PARITY_ERR] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0,
4644                         CNTR_NORMAL,
4645                         access_pio_sbrdctl_crrel_parity_err_cnt),
4646 [C_PIO_PEC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPecFifoParityErr", 0, 0,
4647                         CNTR_NORMAL,
4648                         access_pio_pec_fifo_parity_err_cnt),
4649 [C_PIO_PCC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPccFifoParityErr", 0, 0,
4650                         CNTR_NORMAL,
4651                         access_pio_pcc_fifo_parity_err_cnt),
4652 [C_PIO_SB_MEM_FIFO1_ERR] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0,
4653                         CNTR_NORMAL,
4654                         access_pio_sb_mem_fifo1_err_cnt),
4655 [C_PIO_SB_MEM_FIFO0_ERR] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0,
4656                         CNTR_NORMAL,
4657                         access_pio_sb_mem_fifo0_err_cnt),
4658 [C_PIO_CSR_PARITY_ERR] = CNTR_ELEM("PioCsrParityErr", 0, 0,
4659                         CNTR_NORMAL,
4660                         access_pio_csr_parity_err_cnt),
4661 [C_PIO_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0,
4662                         CNTR_NORMAL,
4663                         access_pio_write_addr_parity_err_cnt),
4664 [C_PIO_WRITE_BAD_CTXT_ERR] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0,
4665                         CNTR_NORMAL,
4666                         access_pio_write_bad_ctxt_err_cnt),
4667 /* SendDmaErrStatus */
4668 [C_SDMA_PCIE_REQ_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0,
4669                         0, CNTR_NORMAL,
4670                         access_sdma_pcie_req_tracking_cor_err_cnt),
4671 [C_SDMA_PCIE_REQ_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0,
4672                         0, CNTR_NORMAL,
4673                         access_sdma_pcie_req_tracking_unc_err_cnt),
4674 [C_SDMA_CSR_PARITY_ERR] = CNTR_ELEM("SDmaCsrParityErr", 0, 0,
4675                         CNTR_NORMAL,
4676                         access_sdma_csr_parity_err_cnt),
4677 [C_SDMA_RPY_TAG_ERR] = CNTR_ELEM("SDmaRpyTagErr", 0, 0,
4678                         CNTR_NORMAL,
4679                         access_sdma_rpy_tag_err_cnt),
4680 /* SendEgressErrStatus */
4681 [C_TX_READ_PIO_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0,
4682                         CNTR_NORMAL,
4683                         access_tx_read_pio_memory_csr_unc_err_cnt),
4684 [C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0,
4685                         0, CNTR_NORMAL,
4686                         access_tx_read_sdma_memory_csr_err_cnt),
4687 [C_TX_EGRESS_FIFO_COR_ERR] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0,
4688                         CNTR_NORMAL,
4689                         access_tx_egress_fifo_cor_err_cnt),
4690 [C_TX_READ_PIO_MEMORY_COR_ERR] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0,
4691                         CNTR_NORMAL,
4692                         access_tx_read_pio_memory_cor_err_cnt),
4693 [C_TX_READ_SDMA_MEMORY_COR_ERR] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0,
4694                         CNTR_NORMAL,
4695                         access_tx_read_sdma_memory_cor_err_cnt),
4696 [C_TX_SB_HDR_COR_ERR] = CNTR_ELEM("TxSbHdrCorErr", 0, 0,
4697                         CNTR_NORMAL,
4698                         access_tx_sb_hdr_cor_err_cnt),
4699 [C_TX_CREDIT_OVERRUN_ERR] = CNTR_ELEM("TxCreditOverrunErr", 0, 0,
4700                         CNTR_NORMAL,
4701                         access_tx_credit_overrun_err_cnt),
4702 [C_TX_LAUNCH_FIFO8_COR_ERR] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0,
4703                         CNTR_NORMAL,
4704                         access_tx_launch_fifo8_cor_err_cnt),
4705 [C_TX_LAUNCH_FIFO7_COR_ERR] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0,
4706                         CNTR_NORMAL,
4707                         access_tx_launch_fifo7_cor_err_cnt),
4708 [C_TX_LAUNCH_FIFO6_COR_ERR] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0,
4709                         CNTR_NORMAL,
4710                         access_tx_launch_fifo6_cor_err_cnt),
4711 [C_TX_LAUNCH_FIFO5_COR_ERR] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0,
4712                         CNTR_NORMAL,
4713                         access_tx_launch_fifo5_cor_err_cnt),
4714 [C_TX_LAUNCH_FIFO4_COR_ERR] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0,
4715                         CNTR_NORMAL,
4716                         access_tx_launch_fifo4_cor_err_cnt),
4717 [C_TX_LAUNCH_FIFO3_COR_ERR] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0,
4718                         CNTR_NORMAL,
4719                         access_tx_launch_fifo3_cor_err_cnt),
4720 [C_TX_LAUNCH_FIFO2_COR_ERR] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0,
4721                         CNTR_NORMAL,
4722                         access_tx_launch_fifo2_cor_err_cnt),
4723 [C_TX_LAUNCH_FIFO1_COR_ERR] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0,
4724                         CNTR_NORMAL,
4725                         access_tx_launch_fifo1_cor_err_cnt),
4726 [C_TX_LAUNCH_FIFO0_COR_ERR] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0,
4727                         CNTR_NORMAL,
4728                         access_tx_launch_fifo0_cor_err_cnt),
4729 [C_TX_CREDIT_RETURN_VL_ERR] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0,
4730                         CNTR_NORMAL,
4731                         access_tx_credit_return_vl_err_cnt),
4732 [C_TX_HCRC_INSERTION_ERR] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0,
4733                         CNTR_NORMAL,
4734                         access_tx_hcrc_insertion_err_cnt),
4735 [C_TX_EGRESS_FIFI_UNC_ERR] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0,
4736                         CNTR_NORMAL,
4737                         access_tx_egress_fifo_unc_err_cnt),
4738 [C_TX_READ_PIO_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0,
4739                         CNTR_NORMAL,
4740                         access_tx_read_pio_memory_unc_err_cnt),
4741 [C_TX_READ_SDMA_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0,
4742                         CNTR_NORMAL,
4743                         access_tx_read_sdma_memory_unc_err_cnt),
4744 [C_TX_SB_HDR_UNC_ERR] = CNTR_ELEM("TxSbHdrUncErr", 0, 0,
4745                         CNTR_NORMAL,
4746                         access_tx_sb_hdr_unc_err_cnt),
4747 [C_TX_CREDIT_RETURN_PARITY_ERR] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0,
4748                         CNTR_NORMAL,
4749                         access_tx_credit_return_partiy_err_cnt),
4750 [C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr",
4751                         0, 0, CNTR_NORMAL,
4752                         access_tx_launch_fifo8_unc_or_parity_err_cnt),
4753 [C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr",
4754                         0, 0, CNTR_NORMAL,
4755                         access_tx_launch_fifo7_unc_or_parity_err_cnt),
4756 [C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr",
4757                         0, 0, CNTR_NORMAL,
4758                         access_tx_launch_fifo6_unc_or_parity_err_cnt),
4759 [C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr",
4760                         0, 0, CNTR_NORMAL,
4761                         access_tx_launch_fifo5_unc_or_parity_err_cnt),
4762 [C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr",
4763                         0, 0, CNTR_NORMAL,
4764                         access_tx_launch_fifo4_unc_or_parity_err_cnt),
4765 [C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr",
4766                         0, 0, CNTR_NORMAL,
4767                         access_tx_launch_fifo3_unc_or_parity_err_cnt),
4768 [C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr",
4769                         0, 0, CNTR_NORMAL,
4770                         access_tx_launch_fifo2_unc_or_parity_err_cnt),
4771 [C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr",
4772                         0, 0, CNTR_NORMAL,
4773                         access_tx_launch_fifo1_unc_or_parity_err_cnt),
4774 [C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr",
4775                         0, 0, CNTR_NORMAL,
4776                         access_tx_launch_fifo0_unc_or_parity_err_cnt),
4777 [C_TX_SDMA15_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma15DisallowedPacketErr",
4778                         0, 0, CNTR_NORMAL,
4779                         access_tx_sdma15_disallowed_packet_err_cnt),
4780 [C_TX_SDMA14_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma14DisallowedPacketErr",
4781                         0, 0, CNTR_NORMAL,
4782                         access_tx_sdma14_disallowed_packet_err_cnt),
4783 [C_TX_SDMA13_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma13DisallowedPacketErr",
4784                         0, 0, CNTR_NORMAL,
4785                         access_tx_sdma13_disallowed_packet_err_cnt),
4786 [C_TX_SDMA12_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma12DisallowedPacketErr",
4787                         0, 0, CNTR_NORMAL,
4788                         access_tx_sdma12_disallowed_packet_err_cnt),
4789 [C_TX_SDMA11_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma11DisallowedPacketErr",
4790                         0, 0, CNTR_NORMAL,
4791                         access_tx_sdma11_disallowed_packet_err_cnt),
4792 [C_TX_SDMA10_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma10DisallowedPacketErr",
4793                         0, 0, CNTR_NORMAL,
4794                         access_tx_sdma10_disallowed_packet_err_cnt),
4795 [C_TX_SDMA9_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma9DisallowedPacketErr",
4796                         0, 0, CNTR_NORMAL,
4797                         access_tx_sdma9_disallowed_packet_err_cnt),
4798 [C_TX_SDMA8_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma8DisallowedPacketErr",
4799                         0, 0, CNTR_NORMAL,
4800                         access_tx_sdma8_disallowed_packet_err_cnt),
4801 [C_TX_SDMA7_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma7DisallowedPacketErr",
4802                         0, 0, CNTR_NORMAL,
4803                         access_tx_sdma7_disallowed_packet_err_cnt),
4804 [C_TX_SDMA6_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma6DisallowedPacketErr",
4805                         0, 0, CNTR_NORMAL,
4806                         access_tx_sdma6_disallowed_packet_err_cnt),
4807 [C_TX_SDMA5_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma5DisallowedPacketErr",
4808                         0, 0, CNTR_NORMAL,
4809                         access_tx_sdma5_disallowed_packet_err_cnt),
4810 [C_TX_SDMA4_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma4DisallowedPacketErr",
4811                         0, 0, CNTR_NORMAL,
4812                         access_tx_sdma4_disallowed_packet_err_cnt),
4813 [C_TX_SDMA3_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma3DisallowedPacketErr",
4814                         0, 0, CNTR_NORMAL,
4815                         access_tx_sdma3_disallowed_packet_err_cnt),
4816 [C_TX_SDMA2_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma2DisallowedPacketErr",
4817                         0, 0, CNTR_NORMAL,
4818                         access_tx_sdma2_disallowed_packet_err_cnt),
4819 [C_TX_SDMA1_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma1DisallowedPacketErr",
4820                         0, 0, CNTR_NORMAL,
4821                         access_tx_sdma1_disallowed_packet_err_cnt),
4822 [C_TX_SDMA0_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma0DisallowedPacketErr",
4823                         0, 0, CNTR_NORMAL,
4824                         access_tx_sdma0_disallowed_packet_err_cnt),
4825 [C_TX_CONFIG_PARITY_ERR] = CNTR_ELEM("TxConfigParityErr", 0, 0,
4826                         CNTR_NORMAL,
4827                         access_tx_config_parity_err_cnt),
4828 [C_TX_SBRD_CTL_CSR_PARITY_ERR] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0,
4829                         CNTR_NORMAL,
4830                         access_tx_sbrd_ctl_csr_parity_err_cnt),
4831 [C_TX_LAUNCH_CSR_PARITY_ERR] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0,
4832                         CNTR_NORMAL,
4833                         access_tx_launch_csr_parity_err_cnt),
4834 [C_TX_ILLEGAL_CL_ERR] = CNTR_ELEM("TxIllegalVLErr", 0, 0,
4835                         CNTR_NORMAL,
4836                         access_tx_illegal_vl_err_cnt),
4837 [C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR] = CNTR_ELEM(
4838                         "TxSbrdCtlStateMachineParityErr", 0, 0,
4839                         CNTR_NORMAL,
4840                         access_tx_sbrd_ctl_state_machine_parity_err_cnt),
4841 [C_TX_RESERVED_10] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0,
4842                         CNTR_NORMAL,
4843                         access_egress_reserved_10_err_cnt),
4844 [C_TX_RESERVED_9] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0,
4845                         CNTR_NORMAL,
4846                         access_egress_reserved_9_err_cnt),
4847 [C_TX_SDMA_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxSdmaLaunchIntfParityErr",
4848                         0, 0, CNTR_NORMAL,
4849                         access_tx_sdma_launch_intf_parity_err_cnt),
4850 [C_TX_PIO_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0,
4851                         CNTR_NORMAL,
4852                         access_tx_pio_launch_intf_parity_err_cnt),
4853 [C_TX_RESERVED_6] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0,
4854                         CNTR_NORMAL,
4855                         access_egress_reserved_6_err_cnt),
4856 [C_TX_INCORRECT_LINK_STATE_ERR] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0,
4857                         CNTR_NORMAL,
4858                         access_tx_incorrect_link_state_err_cnt),
4859 [C_TX_LINK_DOWN_ERR] = CNTR_ELEM("TxLinkdownErr", 0, 0,
4860                         CNTR_NORMAL,
4861                         access_tx_linkdown_err_cnt),
4862 [C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR] = CNTR_ELEM(
4863                         "EgressFifoUnderrunOrParityErr", 0, 0,
4864                         CNTR_NORMAL,
4865                         access_tx_egress_fifi_underrun_or_parity_err_cnt),
4866 [C_TX_RESERVED_2] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0,
4867                         CNTR_NORMAL,
4868                         access_egress_reserved_2_err_cnt),
4869 [C_TX_PKT_INTEGRITY_MEM_UNC_ERR] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0,
4870                         CNTR_NORMAL,
4871                         access_tx_pkt_integrity_mem_unc_err_cnt),
4872 [C_TX_PKT_INTEGRITY_MEM_COR_ERR] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0,
4873                         CNTR_NORMAL,
4874                         access_tx_pkt_integrity_mem_cor_err_cnt),
4875 /* SendErrStatus */
4876 [C_SEND_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0,
4877                         CNTR_NORMAL,
4878                         access_send_csr_write_bad_addr_err_cnt),
4879 [C_SEND_CSR_READ_BAD_ADD_ERR] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0,
4880                         CNTR_NORMAL,
4881                         access_send_csr_read_bad_addr_err_cnt),
4882 [C_SEND_CSR_PARITY_ERR] = CNTR_ELEM("SendCsrParityErr", 0, 0,
4883                         CNTR_NORMAL,
4884                         access_send_csr_parity_cnt),
4885 /* SendCtxtErrStatus */
4886 [C_PIO_WRITE_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0,
4887                         CNTR_NORMAL,
4888                         access_pio_write_out_of_bounds_err_cnt),
4889 [C_PIO_WRITE_OVERFLOW_ERR] = CNTR_ELEM("PioWriteOverflowErr", 0, 0,
4890                         CNTR_NORMAL,
4891                         access_pio_write_overflow_err_cnt),
4892 [C_PIO_WRITE_CROSSES_BOUNDARY_ERR] = CNTR_ELEM("PioWriteCrossesBoundaryErr",
4893                         0, 0, CNTR_NORMAL,
4894                         access_pio_write_crosses_boundary_err_cnt),
4895 [C_PIO_DISALLOWED_PACKET_ERR] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0,
4896                         CNTR_NORMAL,
4897                         access_pio_disallowed_packet_err_cnt),
4898 [C_PIO_INCONSISTENT_SOP_ERR] = CNTR_ELEM("PioInconsistentSopErr", 0, 0,
4899                         CNTR_NORMAL,
4900                         access_pio_inconsistent_sop_err_cnt),
4901 /* SendDmaEngErrStatus */
4902 [C_SDMA_HEADER_REQUEST_FIFO_COR_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr",
4903                         0, 0, CNTR_NORMAL,
4904                         access_sdma_header_request_fifo_cor_err_cnt),
4905 [C_SDMA_HEADER_STORAGE_COR_ERR] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0,
4906                         CNTR_NORMAL,
4907                         access_sdma_header_storage_cor_err_cnt),
4908 [C_SDMA_PACKET_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0,
4909                         CNTR_NORMAL,
4910                         access_sdma_packet_tracking_cor_err_cnt),
4911 [C_SDMA_ASSEMBLY_COR_ERR] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0,
4912                         CNTR_NORMAL,
4913                         access_sdma_assembly_cor_err_cnt),
4914 [C_SDMA_DESC_TABLE_COR_ERR] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0,
4915                         CNTR_NORMAL,
4916                         access_sdma_desc_table_cor_err_cnt),
4917 [C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr",
4918                         0, 0, CNTR_NORMAL,
4919                         access_sdma_header_request_fifo_unc_err_cnt),
4920 [C_SDMA_HEADER_STORAGE_UNC_ERR] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0,
4921                         CNTR_NORMAL,
4922                         access_sdma_header_storage_unc_err_cnt),
4923 [C_SDMA_PACKET_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0,
4924                         CNTR_NORMAL,
4925                         access_sdma_packet_tracking_unc_err_cnt),
4926 [C_SDMA_ASSEMBLY_UNC_ERR] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0,
4927                         CNTR_NORMAL,
4928                         access_sdma_assembly_unc_err_cnt),
4929 [C_SDMA_DESC_TABLE_UNC_ERR] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0,
4930                         CNTR_NORMAL,
4931                         access_sdma_desc_table_unc_err_cnt),
4932 [C_SDMA_TIMEOUT_ERR] = CNTR_ELEM("SDmaTimeoutErr", 0, 0,
4933                         CNTR_NORMAL,
4934                         access_sdma_timeout_err_cnt),
4935 [C_SDMA_HEADER_LENGTH_ERR] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0,
4936                         CNTR_NORMAL,
4937                         access_sdma_header_length_err_cnt),
4938 [C_SDMA_HEADER_ADDRESS_ERR] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0,
4939                         CNTR_NORMAL,
4940                         access_sdma_header_address_err_cnt),
4941 [C_SDMA_HEADER_SELECT_ERR] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0,
4942                         CNTR_NORMAL,
4943                         access_sdma_header_select_err_cnt),
4944 [C_SMDA_RESERVED_9] = CNTR_ELEM("SDma Reserved 9", 0, 0,
4945                         CNTR_NORMAL,
4946                         access_sdma_reserved_9_err_cnt),
4947 [C_SDMA_PACKET_DESC_OVERFLOW_ERR] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0,
4948                         CNTR_NORMAL,
4949                         access_sdma_packet_desc_overflow_err_cnt),
4950 [C_SDMA_LENGTH_MISMATCH_ERR] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0,
4951                         CNTR_NORMAL,
4952                         access_sdma_length_mismatch_err_cnt),
4953 [C_SDMA_HALT_ERR] = CNTR_ELEM("SDmaHaltErr", 0, 0,
4954                         CNTR_NORMAL,
4955                         access_sdma_halt_err_cnt),
4956 [C_SDMA_MEM_READ_ERR] = CNTR_ELEM("SDmaMemReadErr", 0, 0,
4957                         CNTR_NORMAL,
4958                         access_sdma_mem_read_err_cnt),
4959 [C_SDMA_FIRST_DESC_ERR] = CNTR_ELEM("SDmaFirstDescErr", 0, 0,
4960                         CNTR_NORMAL,
4961                         access_sdma_first_desc_err_cnt),
4962 [C_SDMA_TAIL_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0,
4963                         CNTR_NORMAL,
4964                         access_sdma_tail_out_of_bounds_err_cnt),
4965 [C_SDMA_TOO_LONG_ERR] = CNTR_ELEM("SDmaTooLongErr", 0, 0,
4966                         CNTR_NORMAL,
4967                         access_sdma_too_long_err_cnt),
4968 [C_SDMA_GEN_MISMATCH_ERR] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0,
4969                         CNTR_NORMAL,
4970                         access_sdma_gen_mismatch_err_cnt),
4971 [C_SDMA_WRONG_DW_ERR] = CNTR_ELEM("SDmaWrongDwErr", 0, 0,
4972                         CNTR_NORMAL,
4973                         access_sdma_wrong_dw_err_cnt),
4974 };
4975
4976 static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = {
4977 [C_TX_UNSUP_VL] = TXE32_PORT_CNTR_ELEM(TxUnVLErr, SEND_UNSUP_VL_ERR_CNT,
4978                         CNTR_NORMAL),
4979 [C_TX_INVAL_LEN] = TXE32_PORT_CNTR_ELEM(TxInvalLen, SEND_LEN_ERR_CNT,
4980                         CNTR_NORMAL),
4981 [C_TX_MM_LEN_ERR] = TXE32_PORT_CNTR_ELEM(TxMMLenErr, SEND_MAX_MIN_LEN_ERR_CNT,
4982                         CNTR_NORMAL),
4983 [C_TX_UNDERRUN] = TXE32_PORT_CNTR_ELEM(TxUnderrun, SEND_UNDERRUN_CNT,
4984                         CNTR_NORMAL),
4985 [C_TX_FLOW_STALL] = TXE32_PORT_CNTR_ELEM(TxFlowStall, SEND_FLOW_STALL_CNT,
4986                         CNTR_NORMAL),
4987 [C_TX_DROPPED] = TXE32_PORT_CNTR_ELEM(TxDropped, SEND_DROPPED_PKT_CNT,
4988                         CNTR_NORMAL),
4989 [C_TX_HDR_ERR] = TXE32_PORT_CNTR_ELEM(TxHdrErr, SEND_HEADERS_ERR_CNT,
4990                         CNTR_NORMAL),
4991 [C_TX_PKT] = TXE64_PORT_CNTR_ELEM(TxPkt, SEND_DATA_PKT_CNT, CNTR_NORMAL),
4992 [C_TX_WORDS] = TXE64_PORT_CNTR_ELEM(TxWords, SEND_DWORD_CNT, CNTR_NORMAL),
4993 [C_TX_WAIT] = TXE64_PORT_CNTR_ELEM(TxWait, SEND_WAIT_CNT, CNTR_SYNTH),
4994 [C_TX_FLIT_VL] = TXE64_PORT_CNTR_ELEM(TxFlitVL, SEND_DATA_VL0_CNT,
4995                                       CNTR_SYNTH | CNTR_VL),
4996 [C_TX_PKT_VL] = TXE64_PORT_CNTR_ELEM(TxPktVL, SEND_DATA_PKT_VL0_CNT,
4997                                      CNTR_SYNTH | CNTR_VL),
4998 [C_TX_WAIT_VL] = TXE64_PORT_CNTR_ELEM(TxWaitVL, SEND_WAIT_VL0_CNT,
4999                                       CNTR_SYNTH | CNTR_VL),
5000 [C_RX_PKT] = RXE64_PORT_CNTR_ELEM(RxPkt, RCV_DATA_PKT_CNT, CNTR_NORMAL),
5001 [C_RX_WORDS] = RXE64_PORT_CNTR_ELEM(RxWords, RCV_DWORD_CNT, CNTR_NORMAL),
5002 [C_SW_LINK_DOWN] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH | CNTR_32BIT,
5003                              access_sw_link_dn_cnt),
5004 [C_SW_LINK_UP] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH | CNTR_32BIT,
5005                            access_sw_link_up_cnt),
5006 [C_SW_UNKNOWN_FRAME] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL,
5007                                  access_sw_unknown_frame_cnt),
5008 [C_SW_XMIT_DSCD] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH | CNTR_32BIT,
5009                              access_sw_xmit_discards),
5010 [C_SW_XMIT_DSCD_VL] = CNTR_ELEM("XmitDscdVl", 0, 0,
5011                                 CNTR_SYNTH | CNTR_32BIT | CNTR_VL,
5012                                 access_sw_xmit_discards),
5013 [C_SW_XMIT_CSTR_ERR] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH,
5014                                  access_xmit_constraint_errs),
5015 [C_SW_RCV_CSTR_ERR] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH,
5016                                 access_rcv_constraint_errs),
5017 [C_SW_IBP_LOOP_PKTS] = SW_IBP_CNTR(LoopPkts, loop_pkts),
5018 [C_SW_IBP_RC_RESENDS] = SW_IBP_CNTR(RcResend, rc_resends),
5019 [C_SW_IBP_RNR_NAKS] = SW_IBP_CNTR(RnrNak, rnr_naks),
5020 [C_SW_IBP_OTHER_NAKS] = SW_IBP_CNTR(OtherNak, other_naks),
5021 [C_SW_IBP_RC_TIMEOUTS] = SW_IBP_CNTR(RcTimeOut, rc_timeouts),
5022 [C_SW_IBP_PKT_DROPS] = SW_IBP_CNTR(PktDrop, pkt_drops),
5023 [C_SW_IBP_DMA_WAIT] = SW_IBP_CNTR(DmaWait, dmawait),
5024 [C_SW_IBP_RC_SEQNAK] = SW_IBP_CNTR(RcSeqNak, rc_seqnak),
5025 [C_SW_IBP_RC_DUPREQ] = SW_IBP_CNTR(RcDupRew, rc_dupreq),
5026 [C_SW_IBP_RDMA_SEQ] = SW_IBP_CNTR(RdmaSeq, rdma_seq),
5027 [C_SW_IBP_UNALIGNED] = SW_IBP_CNTR(Unaligned, unaligned),
5028 [C_SW_IBP_SEQ_NAK] = SW_IBP_CNTR(SeqNak, seq_naks),
5029 [C_SW_CPU_RC_ACKS] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL,
5030                                access_sw_cpu_rc_acks),
5031 [C_SW_CPU_RC_QACKS] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL,
5032                                 access_sw_cpu_rc_qacks),
5033 [C_SW_CPU_RC_DELAYED_COMP] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL,
5034                                        access_sw_cpu_rc_delayed_comp),
5035 [OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1),
5036 [OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3),
5037 [OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5),
5038 [OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7),
5039 [OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9),
5040 [OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11),
5041 [OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13),
5042 [OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15),
5043 [OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17),
5044 [OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19),
5045 [OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21),
5046 [OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23),
5047 [OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25),
5048 [OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27),
5049 [OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29),
5050 [OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31),
5051 [OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33),
5052 [OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35),
5053 [OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37),
5054 [OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39),
5055 [OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41),
5056 [OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43),
5057 [OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45),
5058 [OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47),
5059 [OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49),
5060 [OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51),
5061 [OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53),
5062 [OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55),
5063 [OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57),
5064 [OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59),
5065 [OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61),
5066 [OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63),
5067 [OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65),
5068 [OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67),
5069 [OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69),
5070 [OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71),
5071 [OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73),
5072 [OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75),
5073 [OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77),
5074 [OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79),
5075 [OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81),
5076 [OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83),
5077 [OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85),
5078 [OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87),
5079 [OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89),
5080 [OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91),
5081 [OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93),
5082 [OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95),
5083 [OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97),
5084 [OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99),
5085 [OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101),
5086 [OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103),
5087 [OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105),
5088 [OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107),
5089 [OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109),
5090 [OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111),
5091 [OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113),
5092 [OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115),
5093 [OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117),
5094 [OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119),
5095 [OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121),
5096 [OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123),
5097 [OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125),
5098 [OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127),
5099 [OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129),
5100 [OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131),
5101 [OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133),
5102 [OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135),
5103 [OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137),
5104 [OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139),
5105 [OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141),
5106 [OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143),
5107 [OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145),
5108 [OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147),
5109 [OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149),
5110 [OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151),
5111 [OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153),
5112 [OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155),
5113 [OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157),
5114 [OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159),
5115 };
5116
5117 /* ======================================================================== */
5118
5119 /* return true if this is chip revision revision a */
5120 int is_ax(struct hfi1_devdata *dd)
5121 {
5122         u8 chip_rev_minor =
5123                 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5124                         & CCE_REVISION_CHIP_REV_MINOR_MASK;
5125         return (chip_rev_minor & 0xf0) == 0;
5126 }
5127
5128 /* return true if this is chip revision revision b */
5129 int is_bx(struct hfi1_devdata *dd)
5130 {
5131         u8 chip_rev_minor =
5132                 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5133                         & CCE_REVISION_CHIP_REV_MINOR_MASK;
5134         return (chip_rev_minor & 0xF0) == 0x10;
5135 }
5136
5137 /*
5138  * Append string s to buffer buf.  Arguments curp and len are the current
5139  * position and remaining length, respectively.
5140  *
5141  * return 0 on success, 1 on out of room
5142  */
5143 static int append_str(char *buf, char **curp, int *lenp, const char *s)
5144 {
5145         char *p = *curp;
5146         int len = *lenp;
5147         int result = 0; /* success */
5148         char c;
5149
5150         /* add a comma, if first in the buffer */
5151         if (p != buf) {
5152                 if (len == 0) {
5153                         result = 1; /* out of room */
5154                         goto done;
5155                 }
5156                 *p++ = ',';
5157                 len--;
5158         }
5159
5160         /* copy the string */
5161         while ((c = *s++) != 0) {
5162                 if (len == 0) {
5163                         result = 1; /* out of room */
5164                         goto done;
5165                 }
5166                 *p++ = c;
5167                 len--;
5168         }
5169
5170 done:
5171         /* write return values */
5172         *curp = p;
5173         *lenp = len;
5174
5175         return result;
5176 }
5177
5178 /*
5179  * Using the given flag table, print a comma separated string into
5180  * the buffer.  End in '*' if the buffer is too short.
5181  */
5182 static char *flag_string(char *buf, int buf_len, u64 flags,
5183                          struct flag_table *table, int table_size)
5184 {
5185         char extra[32];
5186         char *p = buf;
5187         int len = buf_len;
5188         int no_room = 0;
5189         int i;
5190
5191         /* make sure there is at least 2 so we can form "*" */
5192         if (len < 2)
5193                 return "";
5194
5195         len--;  /* leave room for a nul */
5196         for (i = 0; i < table_size; i++) {
5197                 if (flags & table[i].flag) {
5198                         no_room = append_str(buf, &p, &len, table[i].str);
5199                         if (no_room)
5200                                 break;
5201                         flags &= ~table[i].flag;
5202                 }
5203         }
5204
5205         /* any undocumented bits left? */
5206         if (!no_room && flags) {
5207                 snprintf(extra, sizeof(extra), "bits 0x%llx", flags);
5208                 no_room = append_str(buf, &p, &len, extra);
5209         }
5210
5211         /* add * if ran out of room */
5212         if (no_room) {
5213                 /* may need to back up to add space for a '*' */
5214                 if (len == 0)
5215                         --p;
5216                 *p++ = '*';
5217         }
5218
5219         /* add final nul - space already allocated above */
5220         *p = 0;
5221         return buf;
5222 }
5223
5224 /* first 8 CCE error interrupt source names */
5225 static const char * const cce_misc_names[] = {
5226         "CceErrInt",            /* 0 */
5227         "RxeErrInt",            /* 1 */
5228         "MiscErrInt",           /* 2 */
5229         "Reserved3",            /* 3 */
5230         "PioErrInt",            /* 4 */
5231         "SDmaErrInt",           /* 5 */
5232         "EgressErrInt",         /* 6 */
5233         "TxeErrInt"             /* 7 */
5234 };
5235
5236 /*
5237  * Return the miscellaneous error interrupt name.
5238  */
5239 static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source)
5240 {
5241         if (source < ARRAY_SIZE(cce_misc_names))
5242                 strncpy(buf, cce_misc_names[source], bsize);
5243         else
5244                 snprintf(buf, bsize, "Reserved%u",
5245                          source + IS_GENERAL_ERR_START);
5246
5247         return buf;
5248 }
5249
5250 /*
5251  * Return the SDMA engine error interrupt name.
5252  */
5253 static char *is_sdma_eng_err_name(char *buf, size_t bsize, unsigned int source)
5254 {
5255         snprintf(buf, bsize, "SDmaEngErrInt%u", source);
5256         return buf;
5257 }
5258
5259 /*
5260  * Return the send context error interrupt name.
5261  */
5262 static char *is_sendctxt_err_name(char *buf, size_t bsize, unsigned int source)
5263 {
5264         snprintf(buf, bsize, "SendCtxtErrInt%u", source);
5265         return buf;
5266 }
5267
5268 static const char * const various_names[] = {
5269         "PbcInt",
5270         "GpioAssertInt",
5271         "Qsfp1Int",
5272         "Qsfp2Int",
5273         "TCritInt"
5274 };
5275
5276 /*
5277  * Return the various interrupt name.
5278  */
5279 static char *is_various_name(char *buf, size_t bsize, unsigned int source)
5280 {
5281         if (source < ARRAY_SIZE(various_names))
5282                 strncpy(buf, various_names[source], bsize);
5283         else
5284                 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START);
5285         return buf;
5286 }
5287
5288 /*
5289  * Return the DC interrupt name.
5290  */
5291 static char *is_dc_name(char *buf, size_t bsize, unsigned int source)
5292 {
5293         static const char * const dc_int_names[] = {
5294                 "common",
5295                 "lcb",
5296                 "8051",
5297                 "lbm"   /* local block merge */
5298         };
5299
5300         if (source < ARRAY_SIZE(dc_int_names))
5301                 snprintf(buf, bsize, "dc_%s_int", dc_int_names[source]);
5302         else
5303                 snprintf(buf, bsize, "DCInt%u", source);
5304         return buf;
5305 }
5306
5307 static const char * const sdma_int_names[] = {
5308         "SDmaInt",
5309         "SdmaIdleInt",
5310         "SdmaProgressInt",
5311 };
5312
5313 /*
5314  * Return the SDMA engine interrupt name.
5315  */
5316 static char *is_sdma_eng_name(char *buf, size_t bsize, unsigned int source)
5317 {
5318         /* what interrupt */
5319         unsigned int what  = source / TXE_NUM_SDMA_ENGINES;
5320         /* which engine */
5321         unsigned int which = source % TXE_NUM_SDMA_ENGINES;
5322
5323         if (likely(what < 3))
5324                 snprintf(buf, bsize, "%s%u", sdma_int_names[what], which);
5325         else
5326                 snprintf(buf, bsize, "Invalid SDMA interrupt %u", source);
5327         return buf;
5328 }
5329
5330 /*
5331  * Return the receive available interrupt name.
5332  */
5333 static char *is_rcv_avail_name(char *buf, size_t bsize, unsigned int source)
5334 {
5335         snprintf(buf, bsize, "RcvAvailInt%u", source);
5336         return buf;
5337 }
5338
5339 /*
5340  * Return the receive urgent interrupt name.
5341  */
5342 static char *is_rcv_urgent_name(char *buf, size_t bsize, unsigned int source)
5343 {
5344         snprintf(buf, bsize, "RcvUrgentInt%u", source);
5345         return buf;
5346 }
5347
5348 /*
5349  * Return the send credit interrupt name.
5350  */
5351 static char *is_send_credit_name(char *buf, size_t bsize, unsigned int source)
5352 {
5353         snprintf(buf, bsize, "SendCreditInt%u", source);
5354         return buf;
5355 }
5356
5357 /*
5358  * Return the reserved interrupt name.
5359  */
5360 static char *is_reserved_name(char *buf, size_t bsize, unsigned int source)
5361 {
5362         snprintf(buf, bsize, "Reserved%u", source + IS_RESERVED_START);
5363         return buf;
5364 }
5365
5366 static char *cce_err_status_string(char *buf, int buf_len, u64 flags)
5367 {
5368         return flag_string(buf, buf_len, flags,
5369                            cce_err_status_flags,
5370                            ARRAY_SIZE(cce_err_status_flags));
5371 }
5372
5373 static char *rxe_err_status_string(char *buf, int buf_len, u64 flags)
5374 {
5375         return flag_string(buf, buf_len, flags,
5376                            rxe_err_status_flags,
5377                            ARRAY_SIZE(rxe_err_status_flags));
5378 }
5379
5380 static char *misc_err_status_string(char *buf, int buf_len, u64 flags)
5381 {
5382         return flag_string(buf, buf_len, flags, misc_err_status_flags,
5383                            ARRAY_SIZE(misc_err_status_flags));
5384 }
5385
5386 static char *pio_err_status_string(char *buf, int buf_len, u64 flags)
5387 {
5388         return flag_string(buf, buf_len, flags,
5389                            pio_err_status_flags,
5390                            ARRAY_SIZE(pio_err_status_flags));
5391 }
5392
5393 static char *sdma_err_status_string(char *buf, int buf_len, u64 flags)
5394 {
5395         return flag_string(buf, buf_len, flags,
5396                            sdma_err_status_flags,
5397                            ARRAY_SIZE(sdma_err_status_flags));
5398 }
5399
5400 static char *egress_err_status_string(char *buf, int buf_len, u64 flags)
5401 {
5402         return flag_string(buf, buf_len, flags,
5403                            egress_err_status_flags,
5404                            ARRAY_SIZE(egress_err_status_flags));
5405 }
5406
5407 static char *egress_err_info_string(char *buf, int buf_len, u64 flags)
5408 {
5409         return flag_string(buf, buf_len, flags,
5410                            egress_err_info_flags,
5411                            ARRAY_SIZE(egress_err_info_flags));
5412 }
5413
5414 static char *send_err_status_string(char *buf, int buf_len, u64 flags)
5415 {
5416         return flag_string(buf, buf_len, flags,
5417                            send_err_status_flags,
5418                            ARRAY_SIZE(send_err_status_flags));
5419 }
5420
5421 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5422 {
5423         char buf[96];
5424         int i = 0;
5425
5426         /*
5427          * For most these errors, there is nothing that can be done except
5428          * report or record it.
5429          */
5430         dd_dev_info(dd, "CCE Error: %s\n",
5431                     cce_err_status_string(buf, sizeof(buf), reg));
5432
5433         if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) &&
5434             is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) {
5435                 /* this error requires a manual drop into SPC freeze mode */
5436                 /* then a fix up */
5437                 start_freeze_handling(dd->pport, FREEZE_SELF);
5438         }
5439
5440         for (i = 0; i < NUM_CCE_ERR_STATUS_COUNTERS; i++) {
5441                 if (reg & (1ull << i)) {
5442                         incr_cntr64(&dd->cce_err_status_cnt[i]);
5443                         /* maintain a counter over all cce_err_status errors */
5444                         incr_cntr64(&dd->sw_cce_err_status_aggregate);
5445                 }
5446         }
5447 }
5448
5449 /*
5450  * Check counters for receive errors that do not have an interrupt
5451  * associated with them.
5452  */
5453 #define RCVERR_CHECK_TIME 10
5454 static void update_rcverr_timer(unsigned long opaque)
5455 {
5456         struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
5457         struct hfi1_pportdata *ppd = dd->pport;
5458         u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL);
5459
5460         if (dd->rcv_ovfl_cnt < cur_ovfl_cnt &&
5461             ppd->port_error_action & OPA_PI_MASK_EX_BUFFER_OVERRUN) {
5462                 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__);
5463                 set_link_down_reason(
5464                 ppd, OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN, 0,
5465                 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN);
5466                 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
5467         }
5468         dd->rcv_ovfl_cnt = (u32)cur_ovfl_cnt;
5469
5470         mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5471 }
5472
5473 static int init_rcverr(struct hfi1_devdata *dd)
5474 {
5475         setup_timer(&dd->rcverr_timer, update_rcverr_timer, (unsigned long)dd);
5476         /* Assume the hardware counter has been reset */
5477         dd->rcv_ovfl_cnt = 0;
5478         return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5479 }
5480
5481 static void free_rcverr(struct hfi1_devdata *dd)
5482 {
5483         if (dd->rcverr_timer.data)
5484                 del_timer_sync(&dd->rcverr_timer);
5485         dd->rcverr_timer.data = 0;
5486 }
5487
5488 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5489 {
5490         char buf[96];
5491         int i = 0;
5492
5493         dd_dev_info(dd, "Receive Error: %s\n",
5494                     rxe_err_status_string(buf, sizeof(buf), reg));
5495
5496         if (reg & ALL_RXE_FREEZE_ERR) {
5497                 int flags = 0;
5498
5499                 /*
5500                  * Freeze mode recovery is disabled for the errors
5501                  * in RXE_FREEZE_ABORT_MASK
5502                  */
5503                 if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK))
5504                         flags = FREEZE_ABORT;
5505
5506                 start_freeze_handling(dd->pport, flags);
5507         }
5508
5509         for (i = 0; i < NUM_RCV_ERR_STATUS_COUNTERS; i++) {
5510                 if (reg & (1ull << i))
5511                         incr_cntr64(&dd->rcv_err_status_cnt[i]);
5512         }
5513 }
5514
5515 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5516 {
5517         char buf[96];
5518         int i = 0;
5519
5520         dd_dev_info(dd, "Misc Error: %s",
5521                     misc_err_status_string(buf, sizeof(buf), reg));
5522         for (i = 0; i < NUM_MISC_ERR_STATUS_COUNTERS; i++) {
5523                 if (reg & (1ull << i))
5524                         incr_cntr64(&dd->misc_err_status_cnt[i]);
5525         }
5526 }
5527
5528 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5529 {
5530         char buf[96];
5531         int i = 0;
5532
5533         dd_dev_info(dd, "PIO Error: %s\n",
5534                     pio_err_status_string(buf, sizeof(buf), reg));
5535
5536         if (reg & ALL_PIO_FREEZE_ERR)
5537                 start_freeze_handling(dd->pport, 0);
5538
5539         for (i = 0; i < NUM_SEND_PIO_ERR_STATUS_COUNTERS; i++) {
5540                 if (reg & (1ull << i))
5541                         incr_cntr64(&dd->send_pio_err_status_cnt[i]);
5542         }
5543 }
5544
5545 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5546 {
5547         char buf[96];
5548         int i = 0;
5549
5550         dd_dev_info(dd, "SDMA Error: %s\n",
5551                     sdma_err_status_string(buf, sizeof(buf), reg));
5552
5553         if (reg & ALL_SDMA_FREEZE_ERR)
5554                 start_freeze_handling(dd->pport, 0);
5555
5556         for (i = 0; i < NUM_SEND_DMA_ERR_STATUS_COUNTERS; i++) {
5557                 if (reg & (1ull << i))
5558                         incr_cntr64(&dd->send_dma_err_status_cnt[i]);
5559         }
5560 }
5561
5562 static inline void __count_port_discards(struct hfi1_pportdata *ppd)
5563 {
5564         incr_cntr64(&ppd->port_xmit_discards);
5565 }
5566
5567 static void count_port_inactive(struct hfi1_devdata *dd)
5568 {
5569         __count_port_discards(dd->pport);
5570 }
5571
5572 /*
5573  * We have had a "disallowed packet" error during egress. Determine the
5574  * integrity check which failed, and update relevant error counter, etc.
5575  *
5576  * Note that the SEND_EGRESS_ERR_INFO register has only a single
5577  * bit of state per integrity check, and so we can miss the reason for an
5578  * egress error if more than one packet fails the same integrity check
5579  * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO.
5580  */
5581 static void handle_send_egress_err_info(struct hfi1_devdata *dd,
5582                                         int vl)
5583 {
5584         struct hfi1_pportdata *ppd = dd->pport;
5585         u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */
5586         u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO);
5587         char buf[96];
5588
5589         /* clear down all observed info as quickly as possible after read */
5590         write_csr(dd, SEND_EGRESS_ERR_INFO, info);
5591
5592         dd_dev_info(dd,
5593                     "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n",
5594                     info, egress_err_info_string(buf, sizeof(buf), info), src);
5595
5596         /* Eventually add other counters for each bit */
5597         if (info & PORT_DISCARD_EGRESS_ERRS) {
5598                 int weight, i;
5599
5600                 /*
5601                  * Count all applicable bits as individual errors and
5602                  * attribute them to the packet that triggered this handler.
5603                  * This may not be completely accurate due to limitations
5604                  * on the available hardware error information.  There is
5605                  * a single information register and any number of error
5606                  * packets may have occurred and contributed to it before
5607                  * this routine is called.  This means that:
5608                  * a) If multiple packets with the same error occur before
5609                  *    this routine is called, earlier packets are missed.
5610                  *    There is only a single bit for each error type.
5611                  * b) Errors may not be attributed to the correct VL.
5612                  *    The driver is attributing all bits in the info register
5613                  *    to the packet that triggered this call, but bits
5614                  *    could be an accumulation of different packets with
5615                  *    different VLs.
5616                  * c) A single error packet may have multiple counts attached
5617                  *    to it.  There is no way for the driver to know if
5618                  *    multiple bits set in the info register are due to a
5619                  *    single packet or multiple packets.  The driver assumes
5620                  *    multiple packets.
5621                  */
5622                 weight = hweight64(info & PORT_DISCARD_EGRESS_ERRS);
5623                 for (i = 0; i < weight; i++) {
5624                         __count_port_discards(ppd);
5625                         if (vl >= 0 && vl < TXE_NUM_DATA_VL)
5626                                 incr_cntr64(&ppd->port_xmit_discards_vl[vl]);
5627                         else if (vl == 15)
5628                                 incr_cntr64(&ppd->port_xmit_discards_vl
5629                                             [C_VL_15]);
5630                 }
5631         }
5632 }
5633
5634 /*
5635  * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5636  * register. Does it represent a 'port inactive' error?
5637  */
5638 static inline int port_inactive_err(u64 posn)
5639 {
5640         return (posn >= SEES(TX_LINKDOWN) &&
5641                 posn <= SEES(TX_INCORRECT_LINK_STATE));
5642 }
5643
5644 /*
5645  * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5646  * register. Does it represent a 'disallowed packet' error?
5647  */
5648 static inline int disallowed_pkt_err(int posn)
5649 {
5650         return (posn >= SEES(TX_SDMA0_DISALLOWED_PACKET) &&
5651                 posn <= SEES(TX_SDMA15_DISALLOWED_PACKET));
5652 }
5653
5654 /*
5655  * Input value is a bit position of one of the SDMA engine disallowed
5656  * packet errors.  Return which engine.  Use of this must be guarded by
5657  * disallowed_pkt_err().
5658  */
5659 static inline int disallowed_pkt_engine(int posn)
5660 {
5661         return posn - SEES(TX_SDMA0_DISALLOWED_PACKET);
5662 }
5663
5664 /*
5665  * Translate an SDMA engine to a VL.  Return -1 if the tranlation cannot
5666  * be done.
5667  */
5668 static int engine_to_vl(struct hfi1_devdata *dd, int engine)
5669 {
5670         struct sdma_vl_map *m;
5671         int vl;
5672
5673         /* range check */
5674         if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES)
5675                 return -1;
5676
5677         rcu_read_lock();
5678         m = rcu_dereference(dd->sdma_map);
5679         vl = m->engine_to_vl[engine];
5680         rcu_read_unlock();
5681
5682         return vl;
5683 }
5684
5685 /*
5686  * Translate the send context (sofware index) into a VL.  Return -1 if the
5687  * translation cannot be done.
5688  */
5689 static int sc_to_vl(struct hfi1_devdata *dd, int sw_index)
5690 {
5691         struct send_context_info *sci;
5692         struct send_context *sc;
5693         int i;
5694
5695         sci = &dd->send_contexts[sw_index];
5696
5697         /* there is no information for user (PSM) and ack contexts */
5698         if ((sci->type != SC_KERNEL) && (sci->type != SC_VL15))
5699                 return -1;
5700
5701         sc = sci->sc;
5702         if (!sc)
5703                 return -1;
5704         if (dd->vld[15].sc == sc)
5705                 return 15;
5706         for (i = 0; i < num_vls; i++)
5707                 if (dd->vld[i].sc == sc)
5708                         return i;
5709
5710         return -1;
5711 }
5712
5713 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5714 {
5715         u64 reg_copy = reg, handled = 0;
5716         char buf[96];
5717         int i = 0;
5718
5719         if (reg & ALL_TXE_EGRESS_FREEZE_ERR)
5720                 start_freeze_handling(dd->pport, 0);
5721         else if (is_ax(dd) &&
5722                  (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) &&
5723                  (dd->icode != ICODE_FUNCTIONAL_SIMULATOR))
5724                 start_freeze_handling(dd->pport, 0);
5725
5726         while (reg_copy) {
5727                 int posn = fls64(reg_copy);
5728                 /* fls64() returns a 1-based offset, we want it zero based */
5729                 int shift = posn - 1;
5730                 u64 mask = 1ULL << shift;
5731
5732                 if (port_inactive_err(shift)) {
5733                         count_port_inactive(dd);
5734                         handled |= mask;
5735                 } else if (disallowed_pkt_err(shift)) {
5736                         int vl = engine_to_vl(dd, disallowed_pkt_engine(shift));
5737
5738                         handle_send_egress_err_info(dd, vl);
5739                         handled |= mask;
5740                 }
5741                 reg_copy &= ~mask;
5742         }
5743
5744         reg &= ~handled;
5745
5746         if (reg)
5747                 dd_dev_info(dd, "Egress Error: %s\n",
5748                             egress_err_status_string(buf, sizeof(buf), reg));
5749
5750         for (i = 0; i < NUM_SEND_EGRESS_ERR_STATUS_COUNTERS; i++) {
5751                 if (reg & (1ull << i))
5752                         incr_cntr64(&dd->send_egress_err_status_cnt[i]);
5753         }
5754 }
5755
5756 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5757 {
5758         char buf[96];
5759         int i = 0;
5760
5761         dd_dev_info(dd, "Send Error: %s\n",
5762                     send_err_status_string(buf, sizeof(buf), reg));
5763
5764         for (i = 0; i < NUM_SEND_ERR_STATUS_COUNTERS; i++) {
5765                 if (reg & (1ull << i))
5766                         incr_cntr64(&dd->send_err_status_cnt[i]);
5767         }
5768 }
5769
5770 /*
5771  * The maximum number of times the error clear down will loop before
5772  * blocking a repeating error.  This value is arbitrary.
5773  */
5774 #define MAX_CLEAR_COUNT 20
5775
5776 /*
5777  * Clear and handle an error register.  All error interrupts are funneled
5778  * through here to have a central location to correctly handle single-
5779  * or multi-shot errors.
5780  *
5781  * For non per-context registers, call this routine with a context value
5782  * of 0 so the per-context offset is zero.
5783  *
5784  * If the handler loops too many times, assume that something is wrong
5785  * and can't be fixed, so mask the error bits.
5786  */
5787 static void interrupt_clear_down(struct hfi1_devdata *dd,
5788                                  u32 context,
5789                                  const struct err_reg_info *eri)
5790 {
5791         u64 reg;
5792         u32 count;
5793
5794         /* read in a loop until no more errors are seen */
5795         count = 0;
5796         while (1) {
5797                 reg = read_kctxt_csr(dd, context, eri->status);
5798                 if (reg == 0)
5799                         break;
5800                 write_kctxt_csr(dd, context, eri->clear, reg);
5801                 if (likely(eri->handler))
5802                         eri->handler(dd, context, reg);
5803                 count++;
5804                 if (count > MAX_CLEAR_COUNT) {
5805                         u64 mask;
5806
5807                         dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n",
5808                                    eri->desc, reg);
5809                         /*
5810                          * Read-modify-write so any other masked bits
5811                          * remain masked.
5812                          */
5813                         mask = read_kctxt_csr(dd, context, eri->mask);
5814                         mask &= ~reg;
5815                         write_kctxt_csr(dd, context, eri->mask, mask);
5816                         break;
5817                 }
5818         }
5819 }
5820
5821 /*
5822  * CCE block "misc" interrupt.  Source is < 16.
5823  */
5824 static void is_misc_err_int(struct hfi1_devdata *dd, unsigned int source)
5825 {
5826         const struct err_reg_info *eri = &misc_errs[source];
5827
5828         if (eri->handler) {
5829                 interrupt_clear_down(dd, 0, eri);
5830         } else {
5831                 dd_dev_err(dd, "Unexpected misc interrupt (%u) - reserved\n",
5832                            source);
5833         }
5834 }
5835
5836 static char *send_context_err_status_string(char *buf, int buf_len, u64 flags)
5837 {
5838         return flag_string(buf, buf_len, flags,
5839                            sc_err_status_flags,
5840                            ARRAY_SIZE(sc_err_status_flags));
5841 }
5842
5843 /*
5844  * Send context error interrupt.  Source (hw_context) is < 160.
5845  *
5846  * All send context errors cause the send context to halt.  The normal
5847  * clear-down mechanism cannot be used because we cannot clear the
5848  * error bits until several other long-running items are done first.
5849  * This is OK because with the context halted, nothing else is going
5850  * to happen on it anyway.
5851  */
5852 static void is_sendctxt_err_int(struct hfi1_devdata *dd,
5853                                 unsigned int hw_context)
5854 {
5855         struct send_context_info *sci;
5856         struct send_context *sc;
5857         char flags[96];
5858         u64 status;
5859         u32 sw_index;
5860         int i = 0;
5861
5862         sw_index = dd->hw_to_sw[hw_context];
5863         if (sw_index >= dd->num_send_contexts) {
5864                 dd_dev_err(dd,
5865                            "out of range sw index %u for send context %u\n",
5866                            sw_index, hw_context);
5867                 return;
5868         }
5869         sci = &dd->send_contexts[sw_index];
5870         sc = sci->sc;
5871         if (!sc) {
5872                 dd_dev_err(dd, "%s: context %u(%u): no sc?\n", __func__,
5873                            sw_index, hw_context);
5874                 return;
5875         }
5876
5877         /* tell the software that a halt has begun */
5878         sc_stop(sc, SCF_HALTED);
5879
5880         status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS);
5881
5882         dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context,
5883                     send_context_err_status_string(flags, sizeof(flags),
5884                                                    status));
5885
5886         if (status & SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK)
5887                 handle_send_egress_err_info(dd, sc_to_vl(dd, sw_index));
5888
5889         /*
5890          * Automatically restart halted kernel contexts out of interrupt
5891          * context.  User contexts must ask the driver to restart the context.
5892          */
5893         if (sc->type != SC_USER)
5894                 queue_work(dd->pport->hfi1_wq, &sc->halt_work);
5895
5896         /*
5897          * Update the counters for the corresponding status bits.
5898          * Note that these particular counters are aggregated over all
5899          * 160 contexts.
5900          */
5901         for (i = 0; i < NUM_SEND_CTXT_ERR_STATUS_COUNTERS; i++) {
5902                 if (status & (1ull << i))
5903                         incr_cntr64(&dd->sw_ctxt_err_status_cnt[i]);
5904         }
5905 }
5906
5907 static void handle_sdma_eng_err(struct hfi1_devdata *dd,
5908                                 unsigned int source, u64 status)
5909 {
5910         struct sdma_engine *sde;
5911         int i = 0;
5912
5913         sde = &dd->per_sdma[source];
5914 #ifdef CONFIG_SDMA_VERBOSITY
5915         dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5916                    slashstrip(__FILE__), __LINE__, __func__);
5917         dd_dev_err(sde->dd, "CONFIG SDMA(%u) source: %u status 0x%llx\n",
5918                    sde->this_idx, source, (unsigned long long)status);
5919 #endif
5920         sde->err_cnt++;
5921         sdma_engine_error(sde, status);
5922
5923         /*
5924         * Update the counters for the corresponding status bits.
5925         * Note that these particular counters are aggregated over
5926         * all 16 DMA engines.
5927         */
5928         for (i = 0; i < NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS; i++) {
5929                 if (status & (1ull << i))
5930                         incr_cntr64(&dd->sw_send_dma_eng_err_status_cnt[i]);
5931         }
5932 }
5933
5934 /*
5935  * CCE block SDMA error interrupt.  Source is < 16.
5936  */
5937 static void is_sdma_eng_err_int(struct hfi1_devdata *dd, unsigned int source)
5938 {
5939 #ifdef CONFIG_SDMA_VERBOSITY
5940         struct sdma_engine *sde = &dd->per_sdma[source];
5941
5942         dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5943                    slashstrip(__FILE__), __LINE__, __func__);
5944         dd_dev_err(dd, "CONFIG SDMA(%u) source: %u\n", sde->this_idx,
5945                    source);
5946         sdma_dumpstate(sde);
5947 #endif
5948         interrupt_clear_down(dd, source, &sdma_eng_err);
5949 }
5950
5951 /*
5952  * CCE block "various" interrupt.  Source is < 8.
5953  */
5954 static void is_various_int(struct hfi1_devdata *dd, unsigned int source)
5955 {
5956         const struct err_reg_info *eri = &various_err[source];
5957
5958         /*
5959          * TCritInt cannot go through interrupt_clear_down()
5960          * because it is not a second tier interrupt. The handler
5961          * should be called directly.
5962          */
5963         if (source == TCRIT_INT_SOURCE)
5964                 handle_temp_err(dd);
5965         else if (eri->handler)
5966                 interrupt_clear_down(dd, 0, eri);
5967         else
5968                 dd_dev_info(dd,
5969                             "%s: Unimplemented/reserved interrupt %d\n",
5970                             __func__, source);
5971 }
5972
5973 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg)
5974 {
5975         /* src_ctx is always zero */
5976         struct hfi1_pportdata *ppd = dd->pport;
5977         unsigned long flags;
5978         u64 qsfp_int_mgmt = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
5979
5980         if (reg & QSFP_HFI0_MODPRST_N) {
5981                 if (!qsfp_mod_present(ppd)) {
5982                         dd_dev_info(dd, "%s: QSFP module removed\n",
5983                                     __func__);
5984
5985                         ppd->driver_link_ready = 0;
5986                         /*
5987                          * Cable removed, reset all our information about the
5988                          * cache and cable capabilities
5989                          */
5990
5991                         spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
5992                         /*
5993                          * We don't set cache_refresh_required here as we expect
5994                          * an interrupt when a cable is inserted
5995                          */
5996                         ppd->qsfp_info.cache_valid = 0;
5997                         ppd->qsfp_info.reset_needed = 0;
5998                         ppd->qsfp_info.limiting_active = 0;
5999                         spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
6000                                                flags);
6001                         /* Invert the ModPresent pin now to detect plug-in */
6002                         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6003                                   ASIC_QSFP1_INVERT, qsfp_int_mgmt);
6004
6005                         if ((ppd->offline_disabled_reason >
6006                           HFI1_ODR_MASK(
6007                           OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) ||
6008                           (ppd->offline_disabled_reason ==
6009                           HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)))
6010                                 ppd->offline_disabled_reason =
6011                                 HFI1_ODR_MASK(
6012                                 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED);
6013
6014                         if (ppd->host_link_state == HLS_DN_POLL) {
6015                                 /*
6016                                  * The link is still in POLL. This means
6017                                  * that the normal link down processing
6018                                  * will not happen. We have to do it here
6019                                  * before turning the DC off.
6020                                  */
6021                                 queue_work(ppd->hfi1_wq, &ppd->link_down_work);
6022                         }
6023                 } else {
6024                         dd_dev_info(dd, "%s: QSFP module inserted\n",
6025                                     __func__);
6026
6027                         spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6028                         ppd->qsfp_info.cache_valid = 0;
6029                         ppd->qsfp_info.cache_refresh_required = 1;
6030                         spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
6031                                                flags);
6032
6033                         /*
6034                          * Stop inversion of ModPresent pin to detect
6035                          * removal of the cable
6036                          */
6037                         qsfp_int_mgmt &= ~(u64)QSFP_HFI0_MODPRST_N;
6038                         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6039                                   ASIC_QSFP1_INVERT, qsfp_int_mgmt);
6040
6041                         ppd->offline_disabled_reason =
6042                                 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
6043                 }
6044         }
6045
6046         if (reg & QSFP_HFI0_INT_N) {
6047                 dd_dev_info(dd, "%s: Interrupt received from QSFP module\n",
6048                             __func__);
6049                 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6050                 ppd->qsfp_info.check_interrupt_flags = 1;
6051                 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags);
6052         }
6053
6054         /* Schedule the QSFP work only if there is a cable attached. */
6055         if (qsfp_mod_present(ppd))
6056                 queue_work(ppd->hfi1_wq, &ppd->qsfp_info.qsfp_work);
6057 }
6058
6059 static int request_host_lcb_access(struct hfi1_devdata *dd)
6060 {
6061         int ret;
6062
6063         ret = do_8051_command(dd, HCMD_MISC,
6064                               (u64)HCMD_MISC_REQUEST_LCB_ACCESS <<
6065                               LOAD_DATA_FIELD_ID_SHIFT, NULL);
6066         if (ret != HCMD_SUCCESS) {
6067                 dd_dev_err(dd, "%s: command failed with error %d\n",
6068                            __func__, ret);
6069         }
6070         return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6071 }
6072
6073 static int request_8051_lcb_access(struct hfi1_devdata *dd)
6074 {
6075         int ret;
6076
6077         ret = do_8051_command(dd, HCMD_MISC,
6078                               (u64)HCMD_MISC_GRANT_LCB_ACCESS <<
6079                               LOAD_DATA_FIELD_ID_SHIFT, NULL);
6080         if (ret != HCMD_SUCCESS) {
6081                 dd_dev_err(dd, "%s: command failed with error %d\n",
6082                            __func__, ret);
6083         }
6084         return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6085 }
6086
6087 /*
6088  * Set the LCB selector - allow host access.  The DCC selector always
6089  * points to the host.
6090  */
6091 static inline void set_host_lcb_access(struct hfi1_devdata *dd)
6092 {
6093         write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6094                   DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK |
6095                   DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK);
6096 }
6097
6098 /*
6099  * Clear the LCB selector - allow 8051 access.  The DCC selector always
6100  * points to the host.
6101  */
6102 static inline void set_8051_lcb_access(struct hfi1_devdata *dd)
6103 {
6104         write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6105                   DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK);
6106 }
6107
6108 /*
6109  * Acquire LCB access from the 8051.  If the host already has access,
6110  * just increment a counter.  Otherwise, inform the 8051 that the
6111  * host is taking access.
6112  *
6113  * Returns:
6114  *      0 on success
6115  *      -EBUSY if the 8051 has control and cannot be disturbed
6116  *      -errno if unable to acquire access from the 8051
6117  */
6118 int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6119 {
6120         struct hfi1_pportdata *ppd = dd->pport;
6121         int ret = 0;
6122
6123         /*
6124          * Use the host link state lock so the operation of this routine
6125          * { link state check, selector change, count increment } can occur
6126          * as a unit against a link state change.  Otherwise there is a
6127          * race between the state change and the count increment.
6128          */
6129         if (sleep_ok) {
6130                 mutex_lock(&ppd->hls_lock);
6131         } else {
6132                 while (!mutex_trylock(&ppd->hls_lock))
6133                         udelay(1);
6134         }
6135
6136         /* this access is valid only when the link is up */
6137         if (ppd->host_link_state & HLS_DOWN) {
6138                 dd_dev_info(dd, "%s: link state %s not up\n",
6139                             __func__, link_state_name(ppd->host_link_state));
6140                 ret = -EBUSY;
6141                 goto done;
6142         }
6143
6144         if (dd->lcb_access_count == 0) {
6145                 ret = request_host_lcb_access(dd);
6146                 if (ret) {
6147                         dd_dev_err(dd,
6148                                    "%s: unable to acquire LCB access, err %d\n",
6149                                    __func__, ret);
6150                         goto done;
6151                 }
6152                 set_host_lcb_access(dd);
6153         }
6154         dd->lcb_access_count++;
6155 done:
6156         mutex_unlock(&ppd->hls_lock);
6157         return ret;
6158 }
6159
6160 /*
6161  * Release LCB access by decrementing the use count.  If the count is moving
6162  * from 1 to 0, inform 8051 that it has control back.
6163  *
6164  * Returns:
6165  *      0 on success
6166  *      -errno if unable to release access to the 8051
6167  */
6168 int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6169 {
6170         int ret = 0;
6171
6172         /*
6173          * Use the host link state lock because the acquire needed it.
6174          * Here, we only need to keep { selector change, count decrement }
6175          * as a unit.
6176          */
6177         if (sleep_ok) {
6178                 mutex_lock(&dd->pport->hls_lock);
6179         } else {
6180                 while (!mutex_trylock(&dd->pport->hls_lock))
6181                         udelay(1);
6182         }
6183
6184         if (dd->lcb_access_count == 0) {
6185                 dd_dev_err(dd, "%s: LCB access count is zero.  Skipping.\n",
6186                            __func__);
6187                 goto done;
6188         }
6189
6190         if (dd->lcb_access_count == 1) {
6191                 set_8051_lcb_access(dd);
6192                 ret = request_8051_lcb_access(dd);
6193                 if (ret) {
6194                         dd_dev_err(dd,
6195                                    "%s: unable to release LCB access, err %d\n",
6196                                    __func__, ret);
6197                         /* restore host access if the grant didn't work */
6198                         set_host_lcb_access(dd);
6199                         goto done;
6200                 }
6201         }
6202         dd->lcb_access_count--;
6203 done:
6204         mutex_unlock(&dd->pport->hls_lock);
6205         return ret;
6206 }
6207
6208 /*
6209  * Initialize LCB access variables and state.  Called during driver load,
6210  * after most of the initialization is finished.
6211  *
6212  * The DC default is LCB access on for the host.  The driver defaults to
6213  * leaving access to the 8051.  Assign access now - this constrains the call
6214  * to this routine to be after all LCB set-up is done.  In particular, after
6215  * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts()
6216  */
6217 static void init_lcb_access(struct hfi1_devdata *dd)
6218 {
6219         dd->lcb_access_count = 0;
6220 }
6221
6222 /*
6223  * Write a response back to a 8051 request.
6224  */
6225 static void hreq_response(struct hfi1_devdata *dd, u8 return_code, u16 rsp_data)
6226 {
6227         write_csr(dd, DC_DC8051_CFG_EXT_DEV_0,
6228                   DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK |
6229                   (u64)return_code <<
6230                   DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT |
6231                   (u64)rsp_data << DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
6232 }
6233
6234 /*
6235  * Handle host requests from the 8051.
6236  */
6237 static void handle_8051_request(struct hfi1_pportdata *ppd)
6238 {
6239         struct hfi1_devdata *dd = ppd->dd;
6240         u64 reg;
6241         u16 data = 0;
6242         u8 type;
6243
6244         reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1);
6245         if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0)
6246                 return; /* no request */
6247
6248         /* zero out COMPLETED so the response is seen */
6249         write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0);
6250
6251         /* extract request details */
6252         type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT)
6253                         & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK;
6254         data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT)
6255                         & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK;
6256
6257         switch (type) {
6258         case HREQ_LOAD_CONFIG:
6259         case HREQ_SAVE_CONFIG:
6260         case HREQ_READ_CONFIG:
6261         case HREQ_SET_TX_EQ_ABS:
6262         case HREQ_SET_TX_EQ_REL:
6263         case HREQ_ENABLE:
6264                 dd_dev_info(dd, "8051 request: request 0x%x not supported\n",
6265                             type);
6266                 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6267                 break;
6268         case HREQ_CONFIG_DONE:
6269                 hreq_response(dd, HREQ_SUCCESS, 0);
6270                 break;
6271
6272         case HREQ_INTERFACE_TEST:
6273                 hreq_response(dd, HREQ_SUCCESS, data);
6274                 break;
6275         default:
6276                 dd_dev_err(dd, "8051 request: unknown request 0x%x\n", type);
6277                 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6278                 break;
6279         }
6280 }
6281
6282 static void write_global_credit(struct hfi1_devdata *dd,
6283                                 u8 vau, u16 total, u16 shared)
6284 {
6285         write_csr(dd, SEND_CM_GLOBAL_CREDIT,
6286                   ((u64)total <<
6287                    SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT) |
6288                   ((u64)shared <<
6289                    SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT) |
6290                   ((u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT));
6291 }
6292
6293 /*
6294  * Set up initial VL15 credits of the remote.  Assumes the rest of
6295  * the CM credit registers are zero from a previous global or credit reset .
6296  */
6297 void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf)
6298 {
6299         /* leave shared count at zero for both global and VL15 */
6300         write_global_credit(dd, vau, vl15buf, 0);
6301
6302         /* We may need some credits for another VL when sending packets
6303          * with the snoop interface. Dividing it down the middle for VL15
6304          * and VL0 should suffice.
6305          */
6306         if (unlikely(dd->hfi1_snoop.mode_flag == HFI1_PORT_SNOOP_MODE)) {
6307                 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)(vl15buf >> 1)
6308                     << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
6309                 write_csr(dd, SEND_CM_CREDIT_VL, (u64)(vl15buf >> 1)
6310                     << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT);
6311         } else {
6312                 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
6313                         << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
6314         }
6315 }
6316
6317 /*
6318  * Zero all credit details from the previous connection and
6319  * reset the CM manager's internal counters.
6320  */
6321 void reset_link_credits(struct hfi1_devdata *dd)
6322 {
6323         int i;
6324
6325         /* remove all previous VL credit limits */
6326         for (i = 0; i < TXE_NUM_DATA_VL; i++)
6327                 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
6328         write_csr(dd, SEND_CM_CREDIT_VL15, 0);
6329         write_global_credit(dd, 0, 0, 0);
6330         /* reset the CM block */
6331         pio_send_control(dd, PSC_CM_RESET);
6332 }
6333
6334 /* convert a vCU to a CU */
6335 static u32 vcu_to_cu(u8 vcu)
6336 {
6337         return 1 << vcu;
6338 }
6339
6340 /* convert a CU to a vCU */
6341 static u8 cu_to_vcu(u32 cu)
6342 {
6343         return ilog2(cu);
6344 }
6345
6346 /* convert a vAU to an AU */
6347 static u32 vau_to_au(u8 vau)
6348 {
6349         return 8 * (1 << vau);
6350 }
6351
6352 static void set_linkup_defaults(struct hfi1_pportdata *ppd)
6353 {
6354         ppd->sm_trap_qp = 0x0;
6355         ppd->sa_qp = 0x1;
6356 }
6357
6358 /*
6359  * Graceful LCB shutdown.  This leaves the LCB FIFOs in reset.
6360  */
6361 static void lcb_shutdown(struct hfi1_devdata *dd, int abort)
6362 {
6363         u64 reg;
6364
6365         /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6366         write_csr(dd, DC_LCB_CFG_RUN, 0);
6367         /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6368         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET,
6369                   1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT);
6370         /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6371         dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN);
6372         reg = read_csr(dd, DCC_CFG_RESET);
6373         write_csr(dd, DCC_CFG_RESET, reg |
6374                   (1ull << DCC_CFG_RESET_RESET_LCB_SHIFT) |
6375                   (1ull << DCC_CFG_RESET_RESET_RX_FPE_SHIFT));
6376         (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */
6377         if (!abort) {
6378                 udelay(1);    /* must hold for the longer of 16cclks or 20ns */
6379                 write_csr(dd, DCC_CFG_RESET, reg);
6380                 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6381         }
6382 }
6383
6384 /*
6385  * This routine should be called after the link has been transitioned to
6386  * OFFLINE (OFFLINE state has the side effect of putting the SerDes into
6387  * reset).
6388  *
6389  * The expectation is that the caller of this routine would have taken
6390  * care of properly transitioning the link into the correct state.
6391  */
6392 static void dc_shutdown(struct hfi1_devdata *dd)
6393 {
6394         unsigned long flags;
6395
6396         spin_lock_irqsave(&dd->dc8051_lock, flags);
6397         if (dd->dc_shutdown) {
6398                 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6399                 return;
6400         }
6401         dd->dc_shutdown = 1;
6402         spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6403         /* Shutdown the LCB */
6404         lcb_shutdown(dd, 1);
6405         /*
6406          * Going to OFFLINE would have causes the 8051 to put the
6407          * SerDes into reset already. Just need to shut down the 8051,
6408          * itself.
6409          */
6410         write_csr(dd, DC_DC8051_CFG_RST, 0x1);
6411 }
6412
6413 /*
6414  * Calling this after the DC has been brought out of reset should not
6415  * do any damage.
6416  */
6417 static void dc_start(struct hfi1_devdata *dd)
6418 {
6419         unsigned long flags;
6420         int ret;
6421
6422         spin_lock_irqsave(&dd->dc8051_lock, flags);
6423         if (!dd->dc_shutdown)
6424                 goto done;
6425         spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6426         /* Take the 8051 out of reset */
6427         write_csr(dd, DC_DC8051_CFG_RST, 0ull);
6428         /* Wait until 8051 is ready */
6429         ret = wait_fm_ready(dd, TIMEOUT_8051_START);
6430         if (ret) {
6431                 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n",
6432                            __func__);
6433         }
6434         /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6435         write_csr(dd, DCC_CFG_RESET, 0x10);
6436         /* lcb_shutdown() with abort=1 does not restore these */
6437         write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6438         spin_lock_irqsave(&dd->dc8051_lock, flags);
6439         dd->dc_shutdown = 0;
6440 done:
6441         spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6442 }
6443
6444 /*
6445  * These LCB adjustments are for the Aurora SerDes core in the FPGA.
6446  */
6447 static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd)
6448 {
6449         u64 rx_radr, tx_radr;
6450         u32 version;
6451
6452         if (dd->icode != ICODE_FPGA_EMULATION)
6453                 return;
6454
6455         /*
6456          * These LCB defaults on emulator _s are good, nothing to do here:
6457          *      LCB_CFG_TX_FIFOS_RADR
6458          *      LCB_CFG_RX_FIFOS_RADR
6459          *      LCB_CFG_LN_DCLK
6460          *      LCB_CFG_IGNORE_LOST_RCLK
6461          */
6462         if (is_emulator_s(dd))
6463                 return;
6464         /* else this is _p */
6465
6466         version = emulator_rev(dd);
6467         if (!is_ax(dd))
6468                 version = 0x2d; /* all B0 use 0x2d or higher settings */
6469
6470         if (version <= 0x12) {
6471                 /* release 0x12 and below */
6472
6473                 /*
6474                  * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9
6475                  * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9
6476                  * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa
6477                  */
6478                 rx_radr =
6479                       0xaull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6480                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6481                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6482                 /*
6483                  * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default)
6484                  * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6
6485                  */
6486                 tx_radr = 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6487         } else if (version <= 0x18) {
6488                 /* release 0x13 up to 0x18 */
6489                 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6490                 rx_radr =
6491                       0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6492                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6493                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6494                 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6495         } else if (version == 0x19) {
6496                 /* release 0x19 */
6497                 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */
6498                 rx_radr =
6499                       0xAull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6500                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6501                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6502                 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6503         } else if (version == 0x1a) {
6504                 /* release 0x1a */
6505                 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6506                 rx_radr =
6507                       0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6508                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6509                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6510                 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6511                 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull);
6512         } else {
6513                 /* release 0x1b and higher */
6514                 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */
6515                 rx_radr =
6516                       0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6517                     | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6518                     | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6519                 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6520         }
6521
6522         write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr);
6523         /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */
6524         write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
6525                   DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
6526         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr);
6527 }
6528
6529 /*
6530  * Handle a SMA idle message
6531  *
6532  * This is a work-queue function outside of the interrupt.
6533  */
6534 void handle_sma_message(struct work_struct *work)
6535 {
6536         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6537                                                         sma_message_work);
6538         struct hfi1_devdata *dd = ppd->dd;
6539         u64 msg;
6540         int ret;
6541
6542         /*
6543          * msg is bytes 1-4 of the 40-bit idle message - the command code
6544          * is stripped off
6545          */
6546         ret = read_idle_sma(dd, &msg);
6547         if (ret)
6548                 return;
6549         dd_dev_info(dd, "%s: SMA message 0x%llx\n", __func__, msg);
6550         /*
6551          * React to the SMA message.  Byte[1] (0 for us) is the command.
6552          */
6553         switch (msg & 0xff) {
6554         case SMA_IDLE_ARM:
6555                 /*
6556                  * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6557                  * State Transitions
6558                  *
6559                  * Only expected in INIT or ARMED, discard otherwise.
6560                  */
6561                 if (ppd->host_link_state & (HLS_UP_INIT | HLS_UP_ARMED))
6562                         ppd->neighbor_normal = 1;
6563                 break;
6564         case SMA_IDLE_ACTIVE:
6565                 /*
6566                  * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6567                  * State Transitions
6568                  *
6569                  * Can activate the node.  Discard otherwise.
6570                  */
6571                 if (ppd->host_link_state == HLS_UP_ARMED &&
6572                     ppd->is_active_optimize_enabled) {
6573                         ppd->neighbor_normal = 1;
6574                         ret = set_link_state(ppd, HLS_UP_ACTIVE);
6575                         if (ret)
6576                                 dd_dev_err(
6577                                         dd,
6578                                         "%s: received Active SMA idle message, couldn't set link to Active\n",
6579                                         __func__);
6580                 }
6581                 break;
6582         default:
6583                 dd_dev_err(dd,
6584                            "%s: received unexpected SMA idle message 0x%llx\n",
6585                            __func__, msg);
6586                 break;
6587         }
6588 }
6589
6590 static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear)
6591 {
6592         u64 rcvctrl;
6593         unsigned long flags;
6594
6595         spin_lock_irqsave(&dd->rcvctrl_lock, flags);
6596         rcvctrl = read_csr(dd, RCV_CTRL);
6597         rcvctrl |= add;
6598         rcvctrl &= ~clear;
6599         write_csr(dd, RCV_CTRL, rcvctrl);
6600         spin_unlock_irqrestore(&dd->rcvctrl_lock, flags);
6601 }
6602
6603 static inline void add_rcvctrl(struct hfi1_devdata *dd, u64 add)
6604 {
6605         adjust_rcvctrl(dd, add, 0);
6606 }
6607
6608 static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear)
6609 {
6610         adjust_rcvctrl(dd, 0, clear);
6611 }
6612
6613 /*
6614  * Called from all interrupt handlers to start handling an SPC freeze.
6615  */
6616 void start_freeze_handling(struct hfi1_pportdata *ppd, int flags)
6617 {
6618         struct hfi1_devdata *dd = ppd->dd;
6619         struct send_context *sc;
6620         int i;
6621
6622         if (flags & FREEZE_SELF)
6623                 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6624
6625         /* enter frozen mode */
6626         dd->flags |= HFI1_FROZEN;
6627
6628         /* notify all SDMA engines that they are going into a freeze */
6629         sdma_freeze_notify(dd, !!(flags & FREEZE_LINK_DOWN));
6630
6631         /* do halt pre-handling on all enabled send contexts */
6632         for (i = 0; i < dd->num_send_contexts; i++) {
6633                 sc = dd->send_contexts[i].sc;
6634                 if (sc && (sc->flags & SCF_ENABLED))
6635                         sc_stop(sc, SCF_FROZEN | SCF_HALTED);
6636         }
6637
6638         /* Send context are frozen. Notify user space */
6639         hfi1_set_uevent_bits(ppd, _HFI1_EVENT_FROZEN_BIT);
6640
6641         if (flags & FREEZE_ABORT) {
6642                 dd_dev_err(dd,
6643                            "Aborted freeze recovery. Please REBOOT system\n");
6644                 return;
6645         }
6646         /* queue non-interrupt handler */
6647         queue_work(ppd->hfi1_wq, &ppd->freeze_work);
6648 }
6649
6650 /*
6651  * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen,
6652  * depending on the "freeze" parameter.
6653  *
6654  * No need to return an error if it times out, our only option
6655  * is to proceed anyway.
6656  */
6657 static void wait_for_freeze_status(struct hfi1_devdata *dd, int freeze)
6658 {
6659         unsigned long timeout;
6660         u64 reg;
6661
6662         timeout = jiffies + msecs_to_jiffies(FREEZE_STATUS_TIMEOUT);
6663         while (1) {
6664                 reg = read_csr(dd, CCE_STATUS);
6665                 if (freeze) {
6666                         /* waiting until all indicators are set */
6667                         if ((reg & ALL_FROZE) == ALL_FROZE)
6668                                 return; /* all done */
6669                 } else {
6670                         /* waiting until all indicators are clear */
6671                         if ((reg & ALL_FROZE) == 0)
6672                                 return; /* all done */
6673                 }
6674
6675                 if (time_after(jiffies, timeout)) {
6676                         dd_dev_err(dd,
6677                                    "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing",
6678                                    freeze ? "" : "un", reg & ALL_FROZE,
6679                                    freeze ? ALL_FROZE : 0ull);
6680                         return;
6681                 }
6682                 usleep_range(80, 120);
6683         }
6684 }
6685
6686 /*
6687  * Do all freeze handling for the RXE block.
6688  */
6689 static void rxe_freeze(struct hfi1_devdata *dd)
6690 {
6691         int i;
6692
6693         /* disable port */
6694         clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6695
6696         /* disable all receive contexts */
6697         for (i = 0; i < dd->num_rcv_contexts; i++)
6698                 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, i);
6699 }
6700
6701 /*
6702  * Unfreeze handling for the RXE block - kernel contexts only.
6703  * This will also enable the port.  User contexts will do unfreeze
6704  * handling on a per-context basis as they call into the driver.
6705  *
6706  */
6707 static void rxe_kernel_unfreeze(struct hfi1_devdata *dd)
6708 {
6709         u32 rcvmask;
6710         int i;
6711
6712         /* enable all kernel contexts */
6713         for (i = 0; i < dd->n_krcv_queues; i++) {
6714                 rcvmask = HFI1_RCVCTRL_CTXT_ENB;
6715                 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
6716                 rcvmask |= HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, DMA_RTAIL) ?
6717                         HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
6718                 hfi1_rcvctrl(dd, rcvmask, i);
6719         }
6720
6721         /* enable port */
6722         add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6723 }
6724
6725 /*
6726  * Non-interrupt SPC freeze handling.
6727  *
6728  * This is a work-queue function outside of the triggering interrupt.
6729  */
6730 void handle_freeze(struct work_struct *work)
6731 {
6732         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6733                                                                 freeze_work);
6734         struct hfi1_devdata *dd = ppd->dd;
6735
6736         /* wait for freeze indicators on all affected blocks */
6737         wait_for_freeze_status(dd, 1);
6738
6739         /* SPC is now frozen */
6740
6741         /* do send PIO freeze steps */
6742         pio_freeze(dd);
6743
6744         /* do send DMA freeze steps */
6745         sdma_freeze(dd);
6746
6747         /* do send egress freeze steps - nothing to do */
6748
6749         /* do receive freeze steps */
6750         rxe_freeze(dd);
6751
6752         /*
6753          * Unfreeze the hardware - clear the freeze, wait for each
6754          * block's frozen bit to clear, then clear the frozen flag.
6755          */
6756         write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6757         wait_for_freeze_status(dd, 0);
6758
6759         if (is_ax(dd)) {
6760                 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6761                 wait_for_freeze_status(dd, 1);
6762                 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6763                 wait_for_freeze_status(dd, 0);
6764         }
6765
6766         /* do send PIO unfreeze steps for kernel contexts */
6767         pio_kernel_unfreeze(dd);
6768
6769         /* do send DMA unfreeze steps */
6770         sdma_unfreeze(dd);
6771
6772         /* do send egress unfreeze steps - nothing to do */
6773
6774         /* do receive unfreeze steps for kernel contexts */
6775         rxe_kernel_unfreeze(dd);
6776
6777         /*
6778          * The unfreeze procedure touches global device registers when
6779          * it disables and re-enables RXE. Mark the device unfrozen
6780          * after all that is done so other parts of the driver waiting
6781          * for the device to unfreeze don't do things out of order.
6782          *
6783          * The above implies that the meaning of HFI1_FROZEN flag is
6784          * "Device has gone into freeze mode and freeze mode handling
6785          * is still in progress."
6786          *
6787          * The flag will be removed when freeze mode processing has
6788          * completed.
6789          */
6790         dd->flags &= ~HFI1_FROZEN;
6791         wake_up(&dd->event_queue);
6792
6793         /* no longer frozen */
6794 }
6795
6796 /*
6797  * Handle a link up interrupt from the 8051.
6798  *
6799  * This is a work-queue function outside of the interrupt.
6800  */
6801 void handle_link_up(struct work_struct *work)
6802 {
6803         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6804                                                   link_up_work);
6805         set_link_state(ppd, HLS_UP_INIT);
6806
6807         /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
6808         read_ltp_rtt(ppd->dd);
6809         /*
6810          * OPA specifies that certain counters are cleared on a transition
6811          * to link up, so do that.
6812          */
6813         clear_linkup_counters(ppd->dd);
6814         /*
6815          * And (re)set link up default values.
6816          */
6817         set_linkup_defaults(ppd);
6818
6819         /* enforce link speed enabled */
6820         if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) {
6821                 /* oops - current speed is not enabled, bounce */
6822                 dd_dev_err(ppd->dd,
6823                            "Link speed active 0x%x is outside enabled 0x%x, downing link\n",
6824                            ppd->link_speed_active, ppd->link_speed_enabled);
6825                 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0,
6826                                      OPA_LINKDOWN_REASON_SPEED_POLICY);
6827                 set_link_state(ppd, HLS_DN_OFFLINE);
6828                 tune_serdes(ppd);
6829                 start_link(ppd);
6830         }
6831 }
6832
6833 /*
6834  * Several pieces of LNI information were cached for SMA in ppd.
6835  * Reset these on link down
6836  */
6837 static void reset_neighbor_info(struct hfi1_pportdata *ppd)
6838 {
6839         ppd->neighbor_guid = 0;
6840         ppd->neighbor_port_number = 0;
6841         ppd->neighbor_type = 0;
6842         ppd->neighbor_fm_security = 0;
6843 }
6844
6845 static const char * const link_down_reason_strs[] = {
6846         [OPA_LINKDOWN_REASON_NONE] = "None",
6847         [OPA_LINKDOWN_REASON_RCV_ERROR_0] = "Recive error 0",
6848         [OPA_LINKDOWN_REASON_BAD_PKT_LEN] = "Bad packet length",
6849         [OPA_LINKDOWN_REASON_PKT_TOO_LONG] = "Packet too long",
6850         [OPA_LINKDOWN_REASON_PKT_TOO_SHORT] = "Packet too short",
6851         [OPA_LINKDOWN_REASON_BAD_SLID] = "Bad SLID",
6852         [OPA_LINKDOWN_REASON_BAD_DLID] = "Bad DLID",
6853         [OPA_LINKDOWN_REASON_BAD_L2] = "Bad L2",
6854         [OPA_LINKDOWN_REASON_BAD_SC] = "Bad SC",
6855         [OPA_LINKDOWN_REASON_RCV_ERROR_8] = "Receive error 8",
6856         [OPA_LINKDOWN_REASON_BAD_MID_TAIL] = "Bad mid tail",
6857         [OPA_LINKDOWN_REASON_RCV_ERROR_10] = "Receive error 10",
6858         [OPA_LINKDOWN_REASON_PREEMPT_ERROR] = "Preempt error",
6859         [OPA_LINKDOWN_REASON_PREEMPT_VL15] = "Preempt vl15",
6860         [OPA_LINKDOWN_REASON_BAD_VL_MARKER] = "Bad VL marker",
6861         [OPA_LINKDOWN_REASON_RCV_ERROR_14] = "Receive error 14",
6862         [OPA_LINKDOWN_REASON_RCV_ERROR_15] = "Receive error 15",
6863         [OPA_LINKDOWN_REASON_BAD_HEAD_DIST] = "Bad head distance",
6864         [OPA_LINKDOWN_REASON_BAD_TAIL_DIST] = "Bad tail distance",
6865         [OPA_LINKDOWN_REASON_BAD_CTRL_DIST] = "Bad control distance",
6866         [OPA_LINKDOWN_REASON_BAD_CREDIT_ACK] = "Bad credit ack",
6867         [OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER] = "Unsupported VL marker",
6868         [OPA_LINKDOWN_REASON_BAD_PREEMPT] = "Bad preempt",
6869         [OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT] = "Bad control flit",
6870         [OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT] = "Exceed multicast limit",
6871         [OPA_LINKDOWN_REASON_RCV_ERROR_24] = "Receive error 24",
6872         [OPA_LINKDOWN_REASON_RCV_ERROR_25] = "Receive error 25",
6873         [OPA_LINKDOWN_REASON_RCV_ERROR_26] = "Receive error 26",
6874         [OPA_LINKDOWN_REASON_RCV_ERROR_27] = "Receive error 27",
6875         [OPA_LINKDOWN_REASON_RCV_ERROR_28] = "Receive error 28",
6876         [OPA_LINKDOWN_REASON_RCV_ERROR_29] = "Receive error 29",
6877         [OPA_LINKDOWN_REASON_RCV_ERROR_30] = "Receive error 30",
6878         [OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN] =
6879                                         "Excessive buffer overrun",
6880         [OPA_LINKDOWN_REASON_UNKNOWN] = "Unknown",
6881         [OPA_LINKDOWN_REASON_REBOOT] = "Reboot",
6882         [OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN] = "Neighbor unknown",
6883         [OPA_LINKDOWN_REASON_FM_BOUNCE] = "FM bounce",
6884         [OPA_LINKDOWN_REASON_SPEED_POLICY] = "Speed policy",
6885         [OPA_LINKDOWN_REASON_WIDTH_POLICY] = "Width policy",
6886         [OPA_LINKDOWN_REASON_DISCONNECTED] = "Disconnected",
6887         [OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED] =
6888                                         "Local media not installed",
6889         [OPA_LINKDOWN_REASON_NOT_INSTALLED] = "Not installed",
6890         [OPA_LINKDOWN_REASON_CHASSIS_CONFIG] = "Chassis config",
6891         [OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED] =
6892                                         "End to end not installed",
6893         [OPA_LINKDOWN_REASON_POWER_POLICY] = "Power policy",
6894         [OPA_LINKDOWN_REASON_LINKSPEED_POLICY] = "Link speed policy",
6895         [OPA_LINKDOWN_REASON_LINKWIDTH_POLICY] = "Link width policy",
6896         [OPA_LINKDOWN_REASON_SWITCH_MGMT] = "Switch management",
6897         [OPA_LINKDOWN_REASON_SMA_DISABLED] = "SMA disabled",
6898         [OPA_LINKDOWN_REASON_TRANSIENT] = "Transient"
6899 };
6900
6901 /* return the neighbor link down reason string */
6902 static const char *link_down_reason_str(u8 reason)
6903 {
6904         const char *str = NULL;
6905
6906         if (reason < ARRAY_SIZE(link_down_reason_strs))
6907                 str = link_down_reason_strs[reason];
6908         if (!str)
6909                 str = "(invalid)";
6910
6911         return str;
6912 }
6913
6914 /*
6915  * Handle a link down interrupt from the 8051.
6916  *
6917  * This is a work-queue function outside of the interrupt.
6918  */
6919 void handle_link_down(struct work_struct *work)
6920 {
6921         u8 lcl_reason, neigh_reason = 0;
6922         u8 link_down_reason;
6923         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6924                                                   link_down_work);
6925         int was_up;
6926         static const char ldr_str[] = "Link down reason: ";
6927
6928         if ((ppd->host_link_state &
6929              (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) &&
6930              ppd->port_type == PORT_TYPE_FIXED)
6931                 ppd->offline_disabled_reason =
6932                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED);
6933
6934         /* Go offline first, then deal with reading/writing through 8051 */
6935         was_up = !!(ppd->host_link_state & HLS_UP);
6936         set_link_state(ppd, HLS_DN_OFFLINE);
6937
6938         if (was_up) {
6939                 lcl_reason = 0;
6940                 /* link down reason is only valid if the link was up */
6941                 read_link_down_reason(ppd->dd, &link_down_reason);
6942                 switch (link_down_reason) {
6943                 case LDR_LINK_TRANSFER_ACTIVE_LOW:
6944                         /* the link went down, no idle message reason */
6945                         dd_dev_info(ppd->dd, "%sUnexpected link down\n",
6946                                     ldr_str);
6947                         break;
6948                 case LDR_RECEIVED_LINKDOWN_IDLE_MSG:
6949                         /*
6950                          * The neighbor reason is only valid if an idle message
6951                          * was received for it.
6952                          */
6953                         read_planned_down_reason_code(ppd->dd, &neigh_reason);
6954                         dd_dev_info(ppd->dd,
6955                                     "%sNeighbor link down message %d, %s\n",
6956                                     ldr_str, neigh_reason,
6957                                     link_down_reason_str(neigh_reason));
6958                         break;
6959                 case LDR_RECEIVED_HOST_OFFLINE_REQ:
6960                         dd_dev_info(ppd->dd,
6961                                     "%sHost requested link to go offline\n",
6962                                     ldr_str);
6963                         break;
6964                 default:
6965                         dd_dev_info(ppd->dd, "%sUnknown reason 0x%x\n",
6966                                     ldr_str, link_down_reason);
6967                         break;
6968                 }
6969
6970                 /*
6971                  * If no reason, assume peer-initiated but missed
6972                  * LinkGoingDown idle flits.
6973                  */
6974                 if (neigh_reason == 0)
6975                         lcl_reason = OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN;
6976         } else {
6977                 /* went down while polling or going up */
6978                 lcl_reason = OPA_LINKDOWN_REASON_TRANSIENT;
6979         }
6980
6981         set_link_down_reason(ppd, lcl_reason, neigh_reason, 0);
6982
6983         /* inform the SMA when the link transitions from up to down */
6984         if (was_up && ppd->local_link_down_reason.sma == 0 &&
6985             ppd->neigh_link_down_reason.sma == 0) {
6986                 ppd->local_link_down_reason.sma =
6987                                         ppd->local_link_down_reason.latest;
6988                 ppd->neigh_link_down_reason.sma =
6989                                         ppd->neigh_link_down_reason.latest;
6990         }
6991
6992         reset_neighbor_info(ppd);
6993
6994         /* disable the port */
6995         clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6996
6997         /*
6998          * If there is no cable attached, turn the DC off. Otherwise,
6999          * start the link bring up.
7000          */
7001         if (ppd->port_type == PORT_TYPE_QSFP && !qsfp_mod_present(ppd)) {
7002                 dc_shutdown(ppd->dd);
7003         } else {
7004                 tune_serdes(ppd);
7005                 start_link(ppd);
7006         }
7007 }
7008
7009 void handle_link_bounce(struct work_struct *work)
7010 {
7011         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7012                                                         link_bounce_work);
7013
7014         /*
7015          * Only do something if the link is currently up.
7016          */
7017         if (ppd->host_link_state & HLS_UP) {
7018                 set_link_state(ppd, HLS_DN_OFFLINE);
7019                 tune_serdes(ppd);
7020                 start_link(ppd);
7021         } else {
7022                 dd_dev_info(ppd->dd, "%s: link not up (%s), nothing to do\n",
7023                             __func__, link_state_name(ppd->host_link_state));
7024         }
7025 }
7026
7027 /*
7028  * Mask conversion: Capability exchange to Port LTP.  The capability
7029  * exchange has an implicit 16b CRC that is mandatory.
7030  */
7031 static int cap_to_port_ltp(int cap)
7032 {
7033         int port_ltp = PORT_LTP_CRC_MODE_16; /* this mode is mandatory */
7034
7035         if (cap & CAP_CRC_14B)
7036                 port_ltp |= PORT_LTP_CRC_MODE_14;
7037         if (cap & CAP_CRC_48B)
7038                 port_ltp |= PORT_LTP_CRC_MODE_48;
7039         if (cap & CAP_CRC_12B_16B_PER_LANE)
7040                 port_ltp |= PORT_LTP_CRC_MODE_PER_LANE;
7041
7042         return port_ltp;
7043 }
7044
7045 /*
7046  * Convert an OPA Port LTP mask to capability mask
7047  */
7048 int port_ltp_to_cap(int port_ltp)
7049 {
7050         int cap_mask = 0;
7051
7052         if (port_ltp & PORT_LTP_CRC_MODE_14)
7053                 cap_mask |= CAP_CRC_14B;
7054         if (port_ltp & PORT_LTP_CRC_MODE_48)
7055                 cap_mask |= CAP_CRC_48B;
7056         if (port_ltp & PORT_LTP_CRC_MODE_PER_LANE)
7057                 cap_mask |= CAP_CRC_12B_16B_PER_LANE;
7058
7059         return cap_mask;
7060 }
7061
7062 /*
7063  * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
7064  */
7065 static int lcb_to_port_ltp(int lcb_crc)
7066 {
7067         int port_ltp = 0;
7068
7069         if (lcb_crc == LCB_CRC_12B_16B_PER_LANE)
7070                 port_ltp = PORT_LTP_CRC_MODE_PER_LANE;
7071         else if (lcb_crc == LCB_CRC_48B)
7072                 port_ltp = PORT_LTP_CRC_MODE_48;
7073         else if (lcb_crc == LCB_CRC_14B)
7074                 port_ltp = PORT_LTP_CRC_MODE_14;
7075         else
7076                 port_ltp = PORT_LTP_CRC_MODE_16;
7077
7078         return port_ltp;
7079 }
7080
7081 /*
7082  * Our neighbor has indicated that we are allowed to act as a fabric
7083  * manager, so place the full management partition key in the second
7084  * (0-based) pkey array position (see OPAv1, section 20.2.2.6.8). Note
7085  * that we should already have the limited management partition key in
7086  * array element 1, and also that the port is not yet up when
7087  * add_full_mgmt_pkey() is invoked.
7088  */
7089 static void add_full_mgmt_pkey(struct hfi1_pportdata *ppd)
7090 {
7091         struct hfi1_devdata *dd = ppd->dd;
7092
7093         /* Sanity check - ppd->pkeys[2] should be 0, or already initalized */
7094         if (!((ppd->pkeys[2] == 0) || (ppd->pkeys[2] == FULL_MGMT_P_KEY)))
7095                 dd_dev_warn(dd, "%s pkey[2] already set to 0x%x, resetting it to 0x%x\n",
7096                             __func__, ppd->pkeys[2], FULL_MGMT_P_KEY);
7097         ppd->pkeys[2] = FULL_MGMT_P_KEY;
7098         (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
7099         hfi1_event_pkey_change(ppd->dd, ppd->port);
7100 }
7101
7102 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd)
7103 {
7104         if (ppd->pkeys[2] != 0) {
7105                 ppd->pkeys[2] = 0;
7106                 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
7107                 hfi1_event_pkey_change(ppd->dd, ppd->port);
7108         }
7109 }
7110
7111 /*
7112  * Convert the given link width to the OPA link width bitmask.
7113  */
7114 static u16 link_width_to_bits(struct hfi1_devdata *dd, u16 width)
7115 {
7116         switch (width) {
7117         case 0:
7118                 /*
7119                  * Simulator and quick linkup do not set the width.
7120                  * Just set it to 4x without complaint.
7121                  */
7122                 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || quick_linkup)
7123                         return OPA_LINK_WIDTH_4X;
7124                 return 0; /* no lanes up */
7125         case 1: return OPA_LINK_WIDTH_1X;
7126         case 2: return OPA_LINK_WIDTH_2X;
7127         case 3: return OPA_LINK_WIDTH_3X;
7128         default:
7129                 dd_dev_info(dd, "%s: invalid width %d, using 4\n",
7130                             __func__, width);
7131                 /* fall through */
7132         case 4: return OPA_LINK_WIDTH_4X;
7133         }
7134 }
7135
7136 /*
7137  * Do a population count on the bottom nibble.
7138  */
7139 static const u8 bit_counts[16] = {
7140         0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4
7141 };
7142
7143 static inline u8 nibble_to_count(u8 nibble)
7144 {
7145         return bit_counts[nibble & 0xf];
7146 }
7147
7148 /*
7149  * Read the active lane information from the 8051 registers and return
7150  * their widths.
7151  *
7152  * Active lane information is found in these 8051 registers:
7153  *      enable_lane_tx
7154  *      enable_lane_rx
7155  */
7156 static void get_link_widths(struct hfi1_devdata *dd, u16 *tx_width,
7157                             u16 *rx_width)
7158 {
7159         u16 tx, rx;
7160         u8 enable_lane_rx;
7161         u8 enable_lane_tx;
7162         u8 tx_polarity_inversion;
7163         u8 rx_polarity_inversion;
7164         u8 max_rate;
7165
7166         /* read the active lanes */
7167         read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
7168                          &rx_polarity_inversion, &max_rate);
7169         read_local_lni(dd, &enable_lane_rx);
7170
7171         /* convert to counts */
7172         tx = nibble_to_count(enable_lane_tx);
7173         rx = nibble_to_count(enable_lane_rx);
7174
7175         /*
7176          * Set link_speed_active here, overriding what was set in
7177          * handle_verify_cap().  The ASIC 8051 firmware does not correctly
7178          * set the max_rate field in handle_verify_cap until v0.19.
7179          */
7180         if ((dd->icode == ICODE_RTL_SILICON) &&
7181             (dd->dc8051_ver < dc8051_ver(0, 19))) {
7182                 /* max_rate: 0 = 12.5G, 1 = 25G */
7183                 switch (max_rate) {
7184                 case 0:
7185                         dd->pport[0].link_speed_active = OPA_LINK_SPEED_12_5G;
7186                         break;
7187                 default:
7188                         dd_dev_err(dd,
7189                                    "%s: unexpected max rate %d, using 25Gb\n",
7190                                    __func__, (int)max_rate);
7191                         /* fall through */
7192                 case 1:
7193                         dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G;
7194                         break;
7195                 }
7196         }
7197
7198         dd_dev_info(dd,
7199                     "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n",
7200                     enable_lane_tx, tx, enable_lane_rx, rx);
7201         *tx_width = link_width_to_bits(dd, tx);
7202         *rx_width = link_width_to_bits(dd, rx);
7203 }
7204
7205 /*
7206  * Read verify_cap_local_fm_link_width[1] to obtain the link widths.
7207  * Valid after the end of VerifyCap and during LinkUp.  Does not change
7208  * after link up.  I.e. look elsewhere for downgrade information.
7209  *
7210  * Bits are:
7211  *      + bits [7:4] contain the number of active transmitters
7212  *      + bits [3:0] contain the number of active receivers
7213  * These are numbers 1 through 4 and can be different values if the
7214  * link is asymmetric.
7215  *
7216  * verify_cap_local_fm_link_width[0] retains its original value.
7217  */
7218 static void get_linkup_widths(struct hfi1_devdata *dd, u16 *tx_width,
7219                               u16 *rx_width)
7220 {
7221         u16 widths, tx, rx;
7222         u8 misc_bits, local_flags;
7223         u16 active_tx, active_rx;
7224
7225         read_vc_local_link_width(dd, &misc_bits, &local_flags, &widths);
7226         tx = widths >> 12;
7227         rx = (widths >> 8) & 0xf;
7228
7229         *tx_width = link_width_to_bits(dd, tx);
7230         *rx_width = link_width_to_bits(dd, rx);
7231
7232         /* print the active widths */
7233         get_link_widths(dd, &active_tx, &active_rx);
7234 }
7235
7236 /*
7237  * Set ppd->link_width_active and ppd->link_width_downgrade_active using
7238  * hardware information when the link first comes up.
7239  *
7240  * The link width is not available until after VerifyCap.AllFramesReceived
7241  * (the trigger for handle_verify_cap), so this is outside that routine
7242  * and should be called when the 8051 signals linkup.
7243  */
7244 void get_linkup_link_widths(struct hfi1_pportdata *ppd)
7245 {
7246         u16 tx_width, rx_width;
7247
7248         /* get end-of-LNI link widths */
7249         get_linkup_widths(ppd->dd, &tx_width, &rx_width);
7250
7251         /* use tx_width as the link is supposed to be symmetric on link up */
7252         ppd->link_width_active = tx_width;
7253         /* link width downgrade active (LWD.A) starts out matching LW.A */
7254         ppd->link_width_downgrade_tx_active = ppd->link_width_active;
7255         ppd->link_width_downgrade_rx_active = ppd->link_width_active;
7256         /* per OPA spec, on link up LWD.E resets to LWD.S */
7257         ppd->link_width_downgrade_enabled = ppd->link_width_downgrade_supported;
7258         /* cache the active egress rate (units {10^6 bits/sec]) */
7259         ppd->current_egress_rate = active_egress_rate(ppd);
7260 }
7261
7262 /*
7263  * Handle a verify capabilities interrupt from the 8051.
7264  *
7265  * This is a work-queue function outside of the interrupt.
7266  */
7267 void handle_verify_cap(struct work_struct *work)
7268 {
7269         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7270                                                                 link_vc_work);
7271         struct hfi1_devdata *dd = ppd->dd;
7272         u64 reg;
7273         u8 power_management;
7274         u8 continious;
7275         u8 vcu;
7276         u8 vau;
7277         u8 z;
7278         u16 vl15buf;
7279         u16 link_widths;
7280         u16 crc_mask;
7281         u16 crc_val;
7282         u16 device_id;
7283         u16 active_tx, active_rx;
7284         u8 partner_supported_crc;
7285         u8 remote_tx_rate;
7286         u8 device_rev;
7287
7288         set_link_state(ppd, HLS_VERIFY_CAP);
7289
7290         lcb_shutdown(dd, 0);
7291         adjust_lcb_for_fpga_serdes(dd);
7292
7293         /*
7294          * These are now valid:
7295          *      remote VerifyCap fields in the general LNI config
7296          *      CSR DC8051_STS_REMOTE_GUID
7297          *      CSR DC8051_STS_REMOTE_NODE_TYPE
7298          *      CSR DC8051_STS_REMOTE_FM_SECURITY
7299          *      CSR DC8051_STS_REMOTE_PORT_NO
7300          */
7301
7302         read_vc_remote_phy(dd, &power_management, &continious);
7303         read_vc_remote_fabric(dd, &vau, &z, &vcu, &vl15buf,
7304                               &partner_supported_crc);
7305         read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths);
7306         read_remote_device_id(dd, &device_id, &device_rev);
7307         /*
7308          * And the 'MgmtAllowed' information, which is exchanged during
7309          * LNI, is also be available at this point.
7310          */
7311         read_mgmt_allowed(dd, &ppd->mgmt_allowed);
7312         /* print the active widths */
7313         get_link_widths(dd, &active_tx, &active_rx);
7314         dd_dev_info(dd,
7315                     "Peer PHY: power management 0x%x, continuous updates 0x%x\n",
7316                     (int)power_management, (int)continious);
7317         dd_dev_info(dd,
7318                     "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n",
7319                     (int)vau, (int)z, (int)vcu, (int)vl15buf,
7320                     (int)partner_supported_crc);
7321         dd_dev_info(dd, "Peer Link Width: tx rate 0x%x, widths 0x%x\n",
7322                     (u32)remote_tx_rate, (u32)link_widths);
7323         dd_dev_info(dd, "Peer Device ID: 0x%04x, Revision 0x%02x\n",
7324                     (u32)device_id, (u32)device_rev);
7325         /*
7326          * The peer vAU value just read is the peer receiver value.  HFI does
7327          * not support a transmit vAU of 0 (AU == 8).  We advertised that
7328          * with Z=1 in the fabric capabilities sent to the peer.  The peer
7329          * will see our Z=1, and, if it advertised a vAU of 0, will move its
7330          * receive to vAU of 1 (AU == 16).  Do the same here.  We do not care
7331          * about the peer Z value - our sent vAU is 3 (hardwired) and is not
7332          * subject to the Z value exception.
7333          */
7334         if (vau == 0)
7335                 vau = 1;
7336         set_up_vl15(dd, vau, vl15buf);
7337
7338         /* set up the LCB CRC mode */
7339         crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc;
7340
7341         /* order is important: use the lowest bit in common */
7342         if (crc_mask & CAP_CRC_14B)
7343                 crc_val = LCB_CRC_14B;
7344         else if (crc_mask & CAP_CRC_48B)
7345                 crc_val = LCB_CRC_48B;
7346         else if (crc_mask & CAP_CRC_12B_16B_PER_LANE)
7347                 crc_val = LCB_CRC_12B_16B_PER_LANE;
7348         else
7349                 crc_val = LCB_CRC_16B;
7350
7351         dd_dev_info(dd, "Final LCB CRC mode: %d\n", (int)crc_val);
7352         write_csr(dd, DC_LCB_CFG_CRC_MODE,
7353                   (u64)crc_val << DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT);
7354
7355         /* set (14b only) or clear sideband credit */
7356         reg = read_csr(dd, SEND_CM_CTRL);
7357         if (crc_val == LCB_CRC_14B && crc_14b_sideband) {
7358                 write_csr(dd, SEND_CM_CTRL,
7359                           reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
7360         } else {
7361                 write_csr(dd, SEND_CM_CTRL,
7362                           reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
7363         }
7364
7365         ppd->link_speed_active = 0;     /* invalid value */
7366         if (dd->dc8051_ver < dc8051_ver(0, 20)) {
7367                 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */
7368                 switch (remote_tx_rate) {
7369                 case 0:
7370                         ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7371                         break;
7372                 case 1:
7373                         ppd->link_speed_active = OPA_LINK_SPEED_25G;
7374                         break;
7375                 }
7376         } else {
7377                 /* actual rate is highest bit of the ANDed rates */
7378                 u8 rate = remote_tx_rate & ppd->local_tx_rate;
7379
7380                 if (rate & 2)
7381                         ppd->link_speed_active = OPA_LINK_SPEED_25G;
7382                 else if (rate & 1)
7383                         ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7384         }
7385         if (ppd->link_speed_active == 0) {
7386                 dd_dev_err(dd, "%s: unexpected remote tx rate %d, using 25Gb\n",
7387                            __func__, (int)remote_tx_rate);
7388                 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7389         }
7390
7391         /*
7392          * Cache the values of the supported, enabled, and active
7393          * LTP CRC modes to return in 'portinfo' queries. But the bit
7394          * flags that are returned in the portinfo query differ from
7395          * what's in the link_crc_mask, crc_sizes, and crc_val
7396          * variables. Convert these here.
7397          */
7398         ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
7399                 /* supported crc modes */
7400         ppd->port_ltp_crc_mode |=
7401                 cap_to_port_ltp(ppd->port_crc_mode_enabled) << 4;
7402                 /* enabled crc modes */
7403         ppd->port_ltp_crc_mode |= lcb_to_port_ltp(crc_val);
7404                 /* active crc mode */
7405
7406         /* set up the remote credit return table */
7407         assign_remote_cm_au_table(dd, vcu);
7408
7409         /*
7410          * The LCB is reset on entry to handle_verify_cap(), so this must
7411          * be applied on every link up.
7412          *
7413          * Adjust LCB error kill enable to kill the link if
7414          * these RBUF errors are seen:
7415          *      REPLAY_BUF_MBE_SMASK
7416          *      FLIT_INPUT_BUF_MBE_SMASK
7417          */
7418         if (is_ax(dd)) {                        /* fixed in B0 */
7419                 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN);
7420                 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
7421                         | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK;
7422                 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg);
7423         }
7424
7425         /* pull LCB fifos out of reset - all fifo clocks must be stable */
7426         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
7427
7428         /* give 8051 access to the LCB CSRs */
7429         write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
7430         set_8051_lcb_access(dd);
7431
7432         ppd->neighbor_guid =
7433                 read_csr(dd, DC_DC8051_STS_REMOTE_GUID);
7434         ppd->neighbor_port_number = read_csr(dd, DC_DC8051_STS_REMOTE_PORT_NO) &
7435                                         DC_DC8051_STS_REMOTE_PORT_NO_VAL_SMASK;
7436         ppd->neighbor_type =
7437                 read_csr(dd, DC_DC8051_STS_REMOTE_NODE_TYPE) &
7438                 DC_DC8051_STS_REMOTE_NODE_TYPE_VAL_MASK;
7439         ppd->neighbor_fm_security =
7440                 read_csr(dd, DC_DC8051_STS_REMOTE_FM_SECURITY) &
7441                 DC_DC8051_STS_LOCAL_FM_SECURITY_DISABLED_MASK;
7442         dd_dev_info(dd,
7443                     "Neighbor Guid: %llx Neighbor type %d MgmtAllowed %d FM security bypass %d\n",
7444                     ppd->neighbor_guid, ppd->neighbor_type,
7445                     ppd->mgmt_allowed, ppd->neighbor_fm_security);
7446         if (ppd->mgmt_allowed)
7447                 add_full_mgmt_pkey(ppd);
7448
7449         /* tell the 8051 to go to LinkUp */
7450         set_link_state(ppd, HLS_GOING_UP);
7451 }
7452
7453 /*
7454  * Apply the link width downgrade enabled policy against the current active
7455  * link widths.
7456  *
7457  * Called when the enabled policy changes or the active link widths change.
7458  */
7459 void apply_link_downgrade_policy(struct hfi1_pportdata *ppd, int refresh_widths)
7460 {
7461         int do_bounce = 0;
7462         int tries;
7463         u16 lwde;
7464         u16 tx, rx;
7465
7466         /* use the hls lock to avoid a race with actual link up */
7467         tries = 0;
7468 retry:
7469         mutex_lock(&ppd->hls_lock);
7470         /* only apply if the link is up */
7471         if (ppd->host_link_state & HLS_DOWN) {
7472                 /* still going up..wait and retry */
7473                 if (ppd->host_link_state & HLS_GOING_UP) {
7474                         if (++tries < 1000) {
7475                                 mutex_unlock(&ppd->hls_lock);
7476                                 usleep_range(100, 120); /* arbitrary */
7477                                 goto retry;
7478                         }
7479                         dd_dev_err(ppd->dd,
7480                                    "%s: giving up waiting for link state change\n",
7481                                    __func__);
7482                 }
7483                 goto done;
7484         }
7485
7486         lwde = ppd->link_width_downgrade_enabled;
7487
7488         if (refresh_widths) {
7489                 get_link_widths(ppd->dd, &tx, &rx);
7490                 ppd->link_width_downgrade_tx_active = tx;
7491                 ppd->link_width_downgrade_rx_active = rx;
7492         }
7493
7494         if (ppd->link_width_downgrade_tx_active == 0 ||
7495             ppd->link_width_downgrade_rx_active == 0) {
7496                 /* the 8051 reported a dead link as a downgrade */
7497                 dd_dev_err(ppd->dd, "Link downgrade is really a link down, ignoring\n");
7498         } else if (lwde == 0) {
7499                 /* downgrade is disabled */
7500
7501                 /* bounce if not at starting active width */
7502                 if ((ppd->link_width_active !=
7503                      ppd->link_width_downgrade_tx_active) ||
7504                     (ppd->link_width_active !=
7505                      ppd->link_width_downgrade_rx_active)) {
7506                         dd_dev_err(ppd->dd,
7507                                    "Link downgrade is disabled and link has downgraded, downing link\n");
7508                         dd_dev_err(ppd->dd,
7509                                    "  original 0x%x, tx active 0x%x, rx active 0x%x\n",
7510                                    ppd->link_width_active,
7511                                    ppd->link_width_downgrade_tx_active,
7512                                    ppd->link_width_downgrade_rx_active);
7513                         do_bounce = 1;
7514                 }
7515         } else if ((lwde & ppd->link_width_downgrade_tx_active) == 0 ||
7516                    (lwde & ppd->link_width_downgrade_rx_active) == 0) {
7517                 /* Tx or Rx is outside the enabled policy */
7518                 dd_dev_err(ppd->dd,
7519                            "Link is outside of downgrade allowed, downing link\n");
7520                 dd_dev_err(ppd->dd,
7521                            "  enabled 0x%x, tx active 0x%x, rx active 0x%x\n",
7522                            lwde, ppd->link_width_downgrade_tx_active,
7523                            ppd->link_width_downgrade_rx_active);
7524                 do_bounce = 1;
7525         }
7526
7527 done:
7528         mutex_unlock(&ppd->hls_lock);
7529
7530         if (do_bounce) {
7531                 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_WIDTH_POLICY, 0,
7532                                      OPA_LINKDOWN_REASON_WIDTH_POLICY);
7533                 set_link_state(ppd, HLS_DN_OFFLINE);
7534                 tune_serdes(ppd);
7535                 start_link(ppd);
7536         }
7537 }
7538
7539 /*
7540  * Handle a link downgrade interrupt from the 8051.
7541  *
7542  * This is a work-queue function outside of the interrupt.
7543  */
7544 void handle_link_downgrade(struct work_struct *work)
7545 {
7546         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7547                                                         link_downgrade_work);
7548
7549         dd_dev_info(ppd->dd, "8051: Link width downgrade\n");
7550         apply_link_downgrade_policy(ppd, 1);
7551 }
7552
7553 static char *dcc_err_string(char *buf, int buf_len, u64 flags)
7554 {
7555         return flag_string(buf, buf_len, flags, dcc_err_flags,
7556                 ARRAY_SIZE(dcc_err_flags));
7557 }
7558
7559 static char *lcb_err_string(char *buf, int buf_len, u64 flags)
7560 {
7561         return flag_string(buf, buf_len, flags, lcb_err_flags,
7562                 ARRAY_SIZE(lcb_err_flags));
7563 }
7564
7565 static char *dc8051_err_string(char *buf, int buf_len, u64 flags)
7566 {
7567         return flag_string(buf, buf_len, flags, dc8051_err_flags,
7568                 ARRAY_SIZE(dc8051_err_flags));
7569 }
7570
7571 static char *dc8051_info_err_string(char *buf, int buf_len, u64 flags)
7572 {
7573         return flag_string(buf, buf_len, flags, dc8051_info_err_flags,
7574                 ARRAY_SIZE(dc8051_info_err_flags));
7575 }
7576
7577 static char *dc8051_info_host_msg_string(char *buf, int buf_len, u64 flags)
7578 {
7579         return flag_string(buf, buf_len, flags, dc8051_info_host_msg_flags,
7580                 ARRAY_SIZE(dc8051_info_host_msg_flags));
7581 }
7582
7583 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg)
7584 {
7585         struct hfi1_pportdata *ppd = dd->pport;
7586         u64 info, err, host_msg;
7587         int queue_link_down = 0;
7588         char buf[96];
7589
7590         /* look at the flags */
7591         if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) {
7592                 /* 8051 information set by firmware */
7593                 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */
7594                 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051);
7595                 err = (info >> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT)
7596                         & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK;
7597                 host_msg = (info >>
7598                         DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT)
7599                         & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK;
7600
7601                 /*
7602                  * Handle error flags.
7603                  */
7604                 if (err & FAILED_LNI) {
7605                         /*
7606                          * LNI error indications are cleared by the 8051
7607                          * only when starting polling.  Only pay attention
7608                          * to them when in the states that occur during
7609                          * LNI.
7610                          */
7611                         if (ppd->host_link_state
7612                             & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
7613                                 queue_link_down = 1;
7614                                 dd_dev_info(dd, "Link error: %s\n",
7615                                             dc8051_info_err_string(buf,
7616                                                                    sizeof(buf),
7617                                                                    err &
7618                                                                    FAILED_LNI));
7619                         }
7620                         err &= ~(u64)FAILED_LNI;
7621                 }
7622                 /* unknown frames can happen durning LNI, just count */
7623                 if (err & UNKNOWN_FRAME) {
7624                         ppd->unknown_frame_count++;
7625                         err &= ~(u64)UNKNOWN_FRAME;
7626                 }
7627                 if (err) {
7628                         /* report remaining errors, but do not do anything */
7629                         dd_dev_err(dd, "8051 info error: %s\n",
7630                                    dc8051_info_err_string(buf, sizeof(buf),
7631                                                           err));
7632                 }
7633
7634                 /*
7635                  * Handle host message flags.
7636                  */
7637                 if (host_msg & HOST_REQ_DONE) {
7638                         /*
7639                          * Presently, the driver does a busy wait for
7640                          * host requests to complete.  This is only an
7641                          * informational message.
7642                          * NOTE: The 8051 clears the host message
7643                          * information *on the next 8051 command*.
7644                          * Therefore, when linkup is achieved,
7645                          * this flag will still be set.
7646                          */
7647                         host_msg &= ~(u64)HOST_REQ_DONE;
7648                 }
7649                 if (host_msg & BC_SMA_MSG) {
7650                         queue_work(ppd->hfi1_wq, &ppd->sma_message_work);
7651                         host_msg &= ~(u64)BC_SMA_MSG;
7652                 }
7653                 if (host_msg & LINKUP_ACHIEVED) {
7654                         dd_dev_info(dd, "8051: Link up\n");
7655                         queue_work(ppd->hfi1_wq, &ppd->link_up_work);
7656                         host_msg &= ~(u64)LINKUP_ACHIEVED;
7657                 }
7658                 if (host_msg & EXT_DEVICE_CFG_REQ) {
7659                         handle_8051_request(ppd);
7660                         host_msg &= ~(u64)EXT_DEVICE_CFG_REQ;
7661                 }
7662                 if (host_msg & VERIFY_CAP_FRAME) {
7663                         queue_work(ppd->hfi1_wq, &ppd->link_vc_work);
7664                         host_msg &= ~(u64)VERIFY_CAP_FRAME;
7665                 }
7666                 if (host_msg & LINK_GOING_DOWN) {
7667                         const char *extra = "";
7668                         /* no downgrade action needed if going down */
7669                         if (host_msg & LINK_WIDTH_DOWNGRADED) {
7670                                 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7671                                 extra = " (ignoring downgrade)";
7672                         }
7673                         dd_dev_info(dd, "8051: Link down%s\n", extra);
7674                         queue_link_down = 1;
7675                         host_msg &= ~(u64)LINK_GOING_DOWN;
7676                 }
7677                 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7678                         queue_work(ppd->hfi1_wq, &ppd->link_downgrade_work);
7679                         host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7680                 }
7681                 if (host_msg) {
7682                         /* report remaining messages, but do not do anything */
7683                         dd_dev_info(dd, "8051 info host message: %s\n",
7684                                     dc8051_info_host_msg_string(buf,
7685                                                                 sizeof(buf),
7686                                                                 host_msg));
7687                 }
7688
7689                 reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK;
7690         }
7691         if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) {
7692                 /*
7693                  * Lost the 8051 heartbeat.  If this happens, we
7694                  * receive constant interrupts about it.  Disable
7695                  * the interrupt after the first.
7696                  */
7697                 dd_dev_err(dd, "Lost 8051 heartbeat\n");
7698                 write_csr(dd, DC_DC8051_ERR_EN,
7699                           read_csr(dd, DC_DC8051_ERR_EN) &
7700                           ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK);
7701
7702                 reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK;
7703         }
7704         if (reg) {
7705                 /* report the error, but do not do anything */
7706                 dd_dev_err(dd, "8051 error: %s\n",
7707                            dc8051_err_string(buf, sizeof(buf), reg));
7708         }
7709
7710         if (queue_link_down) {
7711                 /*
7712                  * if the link is already going down or disabled, do not
7713                  * queue another
7714                  */
7715                 if ((ppd->host_link_state &
7716                     (HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN)) ||
7717                     ppd->link_enabled == 0) {
7718                         dd_dev_info(dd, "%s: not queuing link down\n",
7719                                     __func__);
7720                 } else {
7721                         queue_work(ppd->hfi1_wq, &ppd->link_down_work);
7722                 }
7723         }
7724 }
7725
7726 static const char * const fm_config_txt[] = {
7727 [0] =
7728         "BadHeadDist: Distance violation between two head flits",
7729 [1] =
7730         "BadTailDist: Distance violation between two tail flits",
7731 [2] =
7732         "BadCtrlDist: Distance violation between two credit control flits",
7733 [3] =
7734         "BadCrdAck: Credits return for unsupported VL",
7735 [4] =
7736         "UnsupportedVLMarker: Received VL Marker",
7737 [5] =
7738         "BadPreempt: Exceeded the preemption nesting level",
7739 [6] =
7740         "BadControlFlit: Received unsupported control flit",
7741 /* no 7 */
7742 [8] =
7743         "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL",
7744 };
7745
7746 static const char * const port_rcv_txt[] = {
7747 [1] =
7748         "BadPktLen: Illegal PktLen",
7749 [2] =
7750         "PktLenTooLong: Packet longer than PktLen",
7751 [3] =
7752         "PktLenTooShort: Packet shorter than PktLen",
7753 [4] =
7754         "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)",
7755 [5] =
7756         "BadDLID: Illegal DLID (0, doesn't match HFI)",
7757 [6] =
7758         "BadL2: Illegal L2 opcode",
7759 [7] =
7760         "BadSC: Unsupported SC",
7761 [9] =
7762         "BadRC: Illegal RC",
7763 [11] =
7764         "PreemptError: Preempting with same VL",
7765 [12] =
7766         "PreemptVL15: Preempting a VL15 packet",
7767 };
7768
7769 #define OPA_LDR_FMCONFIG_OFFSET 16
7770 #define OPA_LDR_PORTRCV_OFFSET 0
7771 static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7772 {
7773         u64 info, hdr0, hdr1;
7774         const char *extra;
7775         char buf[96];
7776         struct hfi1_pportdata *ppd = dd->pport;
7777         u8 lcl_reason = 0;
7778         int do_bounce = 0;
7779
7780         if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) {
7781                 if (!(dd->err_info_uncorrectable & OPA_EI_STATUS_SMASK)) {
7782                         info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE);
7783                         dd->err_info_uncorrectable = info & OPA_EI_CODE_SMASK;
7784                         /* set status bit */
7785                         dd->err_info_uncorrectable |= OPA_EI_STATUS_SMASK;
7786                 }
7787                 reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK;
7788         }
7789
7790         if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) {
7791                 struct hfi1_pportdata *ppd = dd->pport;
7792                 /* this counter saturates at (2^32) - 1 */
7793                 if (ppd->link_downed < (u32)UINT_MAX)
7794                         ppd->link_downed++;
7795                 reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK;
7796         }
7797
7798         if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) {
7799                 u8 reason_valid = 1;
7800
7801                 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG);
7802                 if (!(dd->err_info_fmconfig & OPA_EI_STATUS_SMASK)) {
7803                         dd->err_info_fmconfig = info & OPA_EI_CODE_SMASK;
7804                         /* set status bit */
7805                         dd->err_info_fmconfig |= OPA_EI_STATUS_SMASK;
7806                 }
7807                 switch (info) {
7808                 case 0:
7809                 case 1:
7810                 case 2:
7811                 case 3:
7812                 case 4:
7813                 case 5:
7814                 case 6:
7815                         extra = fm_config_txt[info];
7816                         break;
7817                 case 8:
7818                         extra = fm_config_txt[info];
7819                         if (ppd->port_error_action &
7820                             OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) {
7821                                 do_bounce = 1;
7822                                 /*
7823                                  * lcl_reason cannot be derived from info
7824                                  * for this error
7825                                  */
7826                                 lcl_reason =
7827                                   OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER;
7828                         }
7829                         break;
7830                 default:
7831                         reason_valid = 0;
7832                         snprintf(buf, sizeof(buf), "reserved%lld", info);
7833                         extra = buf;
7834                         break;
7835                 }
7836
7837                 if (reason_valid && !do_bounce) {
7838                         do_bounce = ppd->port_error_action &
7839                                         (1 << (OPA_LDR_FMCONFIG_OFFSET + info));
7840                         lcl_reason = info + OPA_LINKDOWN_REASON_BAD_HEAD_DIST;
7841                 }
7842
7843                 /* just report this */
7844                 dd_dev_info(dd, "DCC Error: fmconfig error: %s\n", extra);
7845                 reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK;
7846         }
7847
7848         if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) {
7849                 u8 reason_valid = 1;
7850
7851                 info = read_csr(dd, DCC_ERR_INFO_PORTRCV);
7852                 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0);
7853                 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1);
7854                 if (!(dd->err_info_rcvport.status_and_code &
7855                       OPA_EI_STATUS_SMASK)) {
7856                         dd->err_info_rcvport.status_and_code =
7857                                 info & OPA_EI_CODE_SMASK;
7858                         /* set status bit */
7859                         dd->err_info_rcvport.status_and_code |=
7860                                 OPA_EI_STATUS_SMASK;
7861                         /*
7862                          * save first 2 flits in the packet that caused
7863                          * the error
7864                          */
7865                         dd->err_info_rcvport.packet_flit1 = hdr0;
7866                         dd->err_info_rcvport.packet_flit2 = hdr1;
7867                 }
7868                 switch (info) {
7869                 case 1:
7870                 case 2:
7871                 case 3:
7872                 case 4:
7873                 case 5:
7874                 case 6:
7875                 case 7:
7876                 case 9:
7877                 case 11:
7878                 case 12:
7879                         extra = port_rcv_txt[info];
7880                         break;
7881                 default:
7882                         reason_valid = 0;
7883                         snprintf(buf, sizeof(buf), "reserved%lld", info);
7884                         extra = buf;
7885                         break;
7886                 }
7887
7888                 if (reason_valid && !do_bounce) {
7889                         do_bounce = ppd->port_error_action &
7890                                         (1 << (OPA_LDR_PORTRCV_OFFSET + info));
7891                         lcl_reason = info + OPA_LINKDOWN_REASON_RCV_ERROR_0;
7892                 }
7893
7894                 /* just report this */
7895                 dd_dev_info(dd, "DCC Error: PortRcv error: %s\n", extra);
7896                 dd_dev_info(dd, "           hdr0 0x%llx, hdr1 0x%llx\n",
7897                             hdr0, hdr1);
7898
7899                 reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK;
7900         }
7901
7902         if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) {
7903                 /* informative only */
7904                 dd_dev_info(dd, "8051 access to LCB blocked\n");
7905                 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK;
7906         }
7907         if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) {
7908                 /* informative only */
7909                 dd_dev_info(dd, "host access to LCB blocked\n");
7910                 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK;
7911         }
7912
7913         /* report any remaining errors */
7914         if (reg)
7915                 dd_dev_info(dd, "DCC Error: %s\n",
7916                             dcc_err_string(buf, sizeof(buf), reg));
7917
7918         if (lcl_reason == 0)
7919                 lcl_reason = OPA_LINKDOWN_REASON_UNKNOWN;
7920
7921         if (do_bounce) {
7922                 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__);
7923                 set_link_down_reason(ppd, lcl_reason, 0, lcl_reason);
7924                 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
7925         }
7926 }
7927
7928 static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7929 {
7930         char buf[96];
7931
7932         dd_dev_info(dd, "LCB Error: %s\n",
7933                     lcb_err_string(buf, sizeof(buf), reg));
7934 }
7935
7936 /*
7937  * CCE block DC interrupt.  Source is < 8.
7938  */
7939 static void is_dc_int(struct hfi1_devdata *dd, unsigned int source)
7940 {
7941         const struct err_reg_info *eri = &dc_errs[source];
7942
7943         if (eri->handler) {
7944                 interrupt_clear_down(dd, 0, eri);
7945         } else if (source == 3 /* dc_lbm_int */) {
7946                 /*
7947                  * This indicates that a parity error has occurred on the
7948                  * address/control lines presented to the LBM.  The error
7949                  * is a single pulse, there is no associated error flag,
7950                  * and it is non-maskable.  This is because if a parity
7951                  * error occurs on the request the request is dropped.
7952                  * This should never occur, but it is nice to know if it
7953                  * ever does.
7954                  */
7955                 dd_dev_err(dd, "Parity error in DC LBM block\n");
7956         } else {
7957                 dd_dev_err(dd, "Invalid DC interrupt %u\n", source);
7958         }
7959 }
7960
7961 /*
7962  * TX block send credit interrupt.  Source is < 160.
7963  */
7964 static void is_send_credit_int(struct hfi1_devdata *dd, unsigned int source)
7965 {
7966         sc_group_release_update(dd, source);
7967 }
7968
7969 /*
7970  * TX block SDMA interrupt.  Source is < 48.
7971  *
7972  * SDMA interrupts are grouped by type:
7973  *
7974  *       0 -  N-1 = SDma
7975  *       N - 2N-1 = SDmaProgress
7976  *      2N - 3N-1 = SDmaIdle
7977  */
7978 static void is_sdma_eng_int(struct hfi1_devdata *dd, unsigned int source)
7979 {
7980         /* what interrupt */
7981         unsigned int what  = source / TXE_NUM_SDMA_ENGINES;
7982         /* which engine */
7983         unsigned int which = source % TXE_NUM_SDMA_ENGINES;
7984
7985 #ifdef CONFIG_SDMA_VERBOSITY
7986         dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", which,
7987                    slashstrip(__FILE__), __LINE__, __func__);
7988         sdma_dumpstate(&dd->per_sdma[which]);
7989 #endif
7990
7991         if (likely(what < 3 && which < dd->num_sdma)) {
7992                 sdma_engine_interrupt(&dd->per_sdma[which], 1ull << source);
7993         } else {
7994                 /* should not happen */
7995                 dd_dev_err(dd, "Invalid SDMA interrupt 0x%x\n", source);
7996         }
7997 }
7998
7999 /*
8000  * RX block receive available interrupt.  Source is < 160.
8001  */
8002 static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source)
8003 {
8004         struct hfi1_ctxtdata *rcd;
8005         char *err_detail;
8006
8007         if (likely(source < dd->num_rcv_contexts)) {
8008                 rcd = dd->rcd[source];
8009                 if (rcd) {
8010                         if (source < dd->first_user_ctxt)
8011                                 rcd->do_interrupt(rcd, 0);
8012                         else
8013                                 handle_user_interrupt(rcd);
8014                         return; /* OK */
8015                 }
8016                 /* received an interrupt, but no rcd */
8017                 err_detail = "dataless";
8018         } else {
8019                 /* received an interrupt, but are not using that context */
8020                 err_detail = "out of range";
8021         }
8022         dd_dev_err(dd, "unexpected %s receive available context interrupt %u\n",
8023                    err_detail, source);
8024 }
8025
8026 /*
8027  * RX block receive urgent interrupt.  Source is < 160.
8028  */
8029 static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source)
8030 {
8031         struct hfi1_ctxtdata *rcd;
8032         char *err_detail;
8033
8034         if (likely(source < dd->num_rcv_contexts)) {
8035                 rcd = dd->rcd[source];
8036                 if (rcd) {
8037                         /* only pay attention to user urgent interrupts */
8038                         if (source >= dd->first_user_ctxt)
8039                                 handle_user_interrupt(rcd);
8040                         return; /* OK */
8041                 }
8042                 /* received an interrupt, but no rcd */
8043                 err_detail = "dataless";
8044         } else {
8045                 /* received an interrupt, but are not using that context */
8046                 err_detail = "out of range";
8047         }
8048         dd_dev_err(dd, "unexpected %s receive urgent context interrupt %u\n",
8049                    err_detail, source);
8050 }
8051
8052 /*
8053  * Reserved range interrupt.  Should not be called in normal operation.
8054  */
8055 static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source)
8056 {
8057         char name[64];
8058
8059         dd_dev_err(dd, "unexpected %s interrupt\n",
8060                    is_reserved_name(name, sizeof(name), source));
8061 }
8062
8063 static const struct is_table is_table[] = {
8064 /*
8065  * start                 end
8066  *                              name func               interrupt func
8067  */
8068 { IS_GENERAL_ERR_START,  IS_GENERAL_ERR_END,
8069                                 is_misc_err_name,       is_misc_err_int },
8070 { IS_SDMAENG_ERR_START,  IS_SDMAENG_ERR_END,
8071                                 is_sdma_eng_err_name,   is_sdma_eng_err_int },
8072 { IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END,
8073                                 is_sendctxt_err_name,   is_sendctxt_err_int },
8074 { IS_SDMA_START,             IS_SDMA_END,
8075                                 is_sdma_eng_name,       is_sdma_eng_int },
8076 { IS_VARIOUS_START,          IS_VARIOUS_END,
8077                                 is_various_name,        is_various_int },
8078 { IS_DC_START,       IS_DC_END,
8079                                 is_dc_name,             is_dc_int },
8080 { IS_RCVAVAIL_START,     IS_RCVAVAIL_END,
8081                                 is_rcv_avail_name,      is_rcv_avail_int },
8082 { IS_RCVURGENT_START,    IS_RCVURGENT_END,
8083                                 is_rcv_urgent_name,     is_rcv_urgent_int },
8084 { IS_SENDCREDIT_START,   IS_SENDCREDIT_END,
8085                                 is_send_credit_name,    is_send_credit_int},
8086 { IS_RESERVED_START,     IS_RESERVED_END,
8087                                 is_reserved_name,       is_reserved_int},
8088 };
8089
8090 /*
8091  * Interrupt source interrupt - called when the given source has an interrupt.
8092  * Source is a bit index into an array of 64-bit integers.
8093  */
8094 static void is_interrupt(struct hfi1_devdata *dd, unsigned int source)
8095 {
8096         const struct is_table *entry;
8097
8098         /* avoids a double compare by walking the table in-order */
8099         for (entry = &is_table[0]; entry->is_name; entry++) {
8100                 if (source < entry->end) {
8101                         trace_hfi1_interrupt(dd, entry, source);
8102                         entry->is_int(dd, source - entry->start);
8103                         return;
8104                 }
8105         }
8106         /* fell off the end */
8107         dd_dev_err(dd, "invalid interrupt source %u\n", source);
8108 }
8109
8110 /*
8111  * General interrupt handler.  This is able to correctly handle
8112  * all interrupts in case INTx is used.
8113  */
8114 static irqreturn_t general_interrupt(int irq, void *data)
8115 {
8116         struct hfi1_devdata *dd = data;
8117         u64 regs[CCE_NUM_INT_CSRS];
8118         u32 bit;
8119         int i;
8120
8121         this_cpu_inc(*dd->int_counter);
8122
8123         /* phase 1: scan and clear all handled interrupts */
8124         for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
8125                 if (dd->gi_mask[i] == 0) {
8126                         regs[i] = 0;    /* used later */
8127                         continue;
8128                 }
8129                 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) &
8130                                 dd->gi_mask[i];
8131                 /* only clear if anything is set */
8132                 if (regs[i])
8133                         write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]);
8134         }
8135
8136         /* phase 2: call the appropriate handler */
8137         for_each_set_bit(bit, (unsigned long *)&regs[0],
8138                          CCE_NUM_INT_CSRS * 64) {
8139                 is_interrupt(dd, bit);
8140         }
8141
8142         return IRQ_HANDLED;
8143 }
8144
8145 static irqreturn_t sdma_interrupt(int irq, void *data)
8146 {
8147         struct sdma_engine *sde = data;
8148         struct hfi1_devdata *dd = sde->dd;
8149         u64 status;
8150
8151 #ifdef CONFIG_SDMA_VERBOSITY
8152         dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
8153                    slashstrip(__FILE__), __LINE__, __func__);
8154         sdma_dumpstate(sde);
8155 #endif
8156
8157         this_cpu_inc(*dd->int_counter);
8158
8159         /* This read_csr is really bad in the hot path */
8160         status = read_csr(dd,
8161                           CCE_INT_STATUS + (8 * (IS_SDMA_START / 64)))
8162                           & sde->imask;
8163         if (likely(status)) {
8164                 /* clear the interrupt(s) */
8165                 write_csr(dd,
8166                           CCE_INT_CLEAR + (8 * (IS_SDMA_START / 64)),
8167                           status);
8168
8169                 /* handle the interrupt(s) */
8170                 sdma_engine_interrupt(sde, status);
8171         } else
8172                 dd_dev_err(dd, "SDMA engine %u interrupt, but no status bits set\n",
8173                            sde->this_idx);
8174
8175         return IRQ_HANDLED;
8176 }
8177
8178 /*
8179  * Clear the receive interrupt.  Use a read of the interrupt clear CSR
8180  * to insure that the write completed.  This does NOT guarantee that
8181  * queued DMA writes to memory from the chip are pushed.
8182  */
8183 static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd)
8184 {
8185         struct hfi1_devdata *dd = rcd->dd;
8186         u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg);
8187
8188         mmiowb();       /* make sure everything before is written */
8189         write_csr(dd, addr, rcd->imask);
8190         /* force the above write on the chip and get a value back */
8191         (void)read_csr(dd, addr);
8192 }
8193
8194 /* force the receive interrupt */
8195 void force_recv_intr(struct hfi1_ctxtdata *rcd)
8196 {
8197         write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
8198 }
8199
8200 /*
8201  * Return non-zero if a packet is present.
8202  *
8203  * This routine is called when rechecking for packets after the RcvAvail
8204  * interrupt has been cleared down.  First, do a quick check of memory for
8205  * a packet present.  If not found, use an expensive CSR read of the context
8206  * tail to determine the actual tail.  The CSR read is necessary because there
8207  * is no method to push pending DMAs to memory other than an interrupt and we
8208  * are trying to determine if we need to force an interrupt.
8209  */
8210 static inline int check_packet_present(struct hfi1_ctxtdata *rcd)
8211 {
8212         u32 tail;
8213         int present;
8214
8215         if (!HFI1_CAP_IS_KSET(DMA_RTAIL))
8216                 present = (rcd->seq_cnt ==
8217                                 rhf_rcv_seq(rhf_to_cpu(get_rhf_addr(rcd))));
8218         else /* is RDMA rtail */
8219                 present = (rcd->head != get_rcvhdrtail(rcd));
8220
8221         if (present)
8222                 return 1;
8223
8224         /* fall back to a CSR read, correct indpendent of DMA_RTAIL */
8225         tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
8226         return rcd->head != tail;
8227 }
8228
8229 /*
8230  * Receive packet IRQ handler.  This routine expects to be on its own IRQ.
8231  * This routine will try to handle packets immediately (latency), but if
8232  * it finds too many, it will invoke the thread handler (bandwitdh).  The
8233  * chip receive interrupt is *not* cleared down until this or the thread (if
8234  * invoked) is finished.  The intent is to avoid extra interrupts while we
8235  * are processing packets anyway.
8236  */
8237 static irqreturn_t receive_context_interrupt(int irq, void *data)
8238 {
8239         struct hfi1_ctxtdata *rcd = data;
8240         struct hfi1_devdata *dd = rcd->dd;
8241         int disposition;
8242         int present;
8243
8244         trace_hfi1_receive_interrupt(dd, rcd->ctxt);
8245         this_cpu_inc(*dd->int_counter);
8246         aspm_ctx_disable(rcd);
8247
8248         /* receive interrupt remains blocked while processing packets */
8249         disposition = rcd->do_interrupt(rcd, 0);
8250
8251         /*
8252          * Too many packets were seen while processing packets in this
8253          * IRQ handler.  Invoke the handler thread.  The receive interrupt
8254          * remains blocked.
8255          */
8256         if (disposition == RCV_PKT_LIMIT)
8257                 return IRQ_WAKE_THREAD;
8258
8259         /*
8260          * The packet processor detected no more packets.  Clear the receive
8261          * interrupt and recheck for a packet packet that may have arrived
8262          * after the previous check and interrupt clear.  If a packet arrived,
8263          * force another interrupt.
8264          */
8265         clear_recv_intr(rcd);
8266         present = check_packet_present(rcd);
8267         if (present)
8268                 force_recv_intr(rcd);
8269
8270         return IRQ_HANDLED;
8271 }
8272
8273 /*
8274  * Receive packet thread handler.  This expects to be invoked with the
8275  * receive interrupt still blocked.
8276  */
8277 static irqreturn_t receive_context_thread(int irq, void *data)
8278 {
8279         struct hfi1_ctxtdata *rcd = data;
8280         int present;
8281
8282         /* receive interrupt is still blocked from the IRQ handler */
8283         (void)rcd->do_interrupt(rcd, 1);
8284
8285         /*
8286          * The packet processor will only return if it detected no more
8287          * packets.  Hold IRQs here so we can safely clear the interrupt and
8288          * recheck for a packet that may have arrived after the previous
8289          * check and the interrupt clear.  If a packet arrived, force another
8290          * interrupt.
8291          */
8292         local_irq_disable();
8293         clear_recv_intr(rcd);
8294         present = check_packet_present(rcd);
8295         if (present)
8296                 force_recv_intr(rcd);
8297         local_irq_enable();
8298
8299         return IRQ_HANDLED;
8300 }
8301
8302 /* ========================================================================= */
8303
8304 u32 read_physical_state(struct hfi1_devdata *dd)
8305 {
8306         u64 reg;
8307
8308         reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
8309         return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT)
8310                                 & DC_DC8051_STS_CUR_STATE_PORT_MASK;
8311 }
8312
8313 u32 read_logical_state(struct hfi1_devdata *dd)
8314 {
8315         u64 reg;
8316
8317         reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8318         return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT)
8319                                 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK;
8320 }
8321
8322 static void set_logical_state(struct hfi1_devdata *dd, u32 chip_lstate)
8323 {
8324         u64 reg;
8325
8326         reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8327         /* clear current state, set new state */
8328         reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK;
8329         reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT;
8330         write_csr(dd, DCC_CFG_PORT_CONFIG, reg);
8331 }
8332
8333 /*
8334  * Use the 8051 to read a LCB CSR.
8335  */
8336 static int read_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 *data)
8337 {
8338         u32 regno;
8339         int ret;
8340
8341         if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8342                 if (acquire_lcb_access(dd, 0) == 0) {
8343                         *data = read_csr(dd, addr);
8344                         release_lcb_access(dd, 0);
8345                         return 0;
8346                 }
8347                 return -EBUSY;
8348         }
8349
8350         /* register is an index of LCB registers: (offset - base) / 8 */
8351         regno = (addr - DC_LCB_CFG_RUN) >> 3;
8352         ret = do_8051_command(dd, HCMD_READ_LCB_CSR, regno, data);
8353         if (ret != HCMD_SUCCESS)
8354                 return -EBUSY;
8355         return 0;
8356 }
8357
8358 /*
8359  * Read an LCB CSR.  Access may not be in host control, so check.
8360  * Return 0 on success, -EBUSY on failure.
8361  */
8362 int read_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 *data)
8363 {
8364         struct hfi1_pportdata *ppd = dd->pport;
8365
8366         /* if up, go through the 8051 for the value */
8367         if (ppd->host_link_state & HLS_UP)
8368                 return read_lcb_via_8051(dd, addr, data);
8369         /* if going up or down, no access */
8370         if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE))
8371                 return -EBUSY;
8372         /* otherwise, host has access */
8373         *data = read_csr(dd, addr);
8374         return 0;
8375 }
8376
8377 /*
8378  * Use the 8051 to write a LCB CSR.
8379  */
8380 static int write_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 data)
8381 {
8382         u32 regno;
8383         int ret;
8384
8385         if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR ||
8386             (dd->dc8051_ver < dc8051_ver(0, 20))) {
8387                 if (acquire_lcb_access(dd, 0) == 0) {
8388                         write_csr(dd, addr, data);
8389                         release_lcb_access(dd, 0);
8390                         return 0;
8391                 }
8392                 return -EBUSY;
8393         }
8394
8395         /* register is an index of LCB registers: (offset - base) / 8 */
8396         regno = (addr - DC_LCB_CFG_RUN) >> 3;
8397         ret = do_8051_command(dd, HCMD_WRITE_LCB_CSR, regno, &data);
8398         if (ret != HCMD_SUCCESS)
8399                 return -EBUSY;
8400         return 0;
8401 }
8402
8403 /*
8404  * Write an LCB CSR.  Access may not be in host control, so check.
8405  * Return 0 on success, -EBUSY on failure.
8406  */
8407 int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data)
8408 {
8409         struct hfi1_pportdata *ppd = dd->pport;
8410
8411         /* if up, go through the 8051 for the value */
8412         if (ppd->host_link_state & HLS_UP)
8413                 return write_lcb_via_8051(dd, addr, data);
8414         /* if going up or down, no access */
8415         if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE))
8416                 return -EBUSY;
8417         /* otherwise, host has access */
8418         write_csr(dd, addr, data);
8419         return 0;
8420 }
8421
8422 /*
8423  * Returns:
8424  *      < 0 = Linux error, not able to get access
8425  *      > 0 = 8051 command RETURN_CODE
8426  */
8427 static int do_8051_command(
8428         struct hfi1_devdata *dd,
8429         u32 type,
8430         u64 in_data,
8431         u64 *out_data)
8432 {
8433         u64 reg, completed;
8434         int return_code;
8435         unsigned long flags;
8436         unsigned long timeout;
8437
8438         hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data);
8439
8440         /*
8441          * Alternative to holding the lock for a long time:
8442          * - keep busy wait - have other users bounce off
8443          */
8444         spin_lock_irqsave(&dd->dc8051_lock, flags);
8445
8446         /* We can't send any commands to the 8051 if it's in reset */
8447         if (dd->dc_shutdown) {
8448                 return_code = -ENODEV;
8449                 goto fail;
8450         }
8451
8452         /*
8453          * If an 8051 host command timed out previously, then the 8051 is
8454          * stuck.
8455          *
8456          * On first timeout, attempt to reset and restart the entire DC
8457          * block (including 8051). (Is this too big of a hammer?)
8458          *
8459          * If the 8051 times out a second time, the reset did not bring it
8460          * back to healthy life. In that case, fail any subsequent commands.
8461          */
8462         if (dd->dc8051_timed_out) {
8463                 if (dd->dc8051_timed_out > 1) {
8464                         dd_dev_err(dd,
8465                                    "Previous 8051 host command timed out, skipping command %u\n",
8466                                    type);
8467                         return_code = -ENXIO;
8468                         goto fail;
8469                 }
8470                 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
8471                 dc_shutdown(dd);
8472                 dc_start(dd);
8473                 spin_lock_irqsave(&dd->dc8051_lock, flags);
8474         }
8475
8476         /*
8477          * If there is no timeout, then the 8051 command interface is
8478          * waiting for a command.
8479          */
8480
8481         /*
8482          * When writing a LCB CSR, out_data contains the full value to
8483          * to be written, while in_data contains the relative LCB
8484          * address in 7:0.  Do the work here, rather than the caller,
8485          * of distrubting the write data to where it needs to go:
8486          *
8487          * Write data
8488          *   39:00 -> in_data[47:8]
8489          *   47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE
8490          *   63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA
8491          */
8492         if (type == HCMD_WRITE_LCB_CSR) {
8493                 in_data |= ((*out_data) & 0xffffffffffull) << 8;
8494                 reg = ((((*out_data) >> 40) & 0xff) <<
8495                                 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT)
8496                       | ((((*out_data) >> 48) & 0xffff) <<
8497                                 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
8498                 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg);
8499         }
8500
8501         /*
8502          * Do two writes: the first to stabilize the type and req_data, the
8503          * second to activate.
8504          */
8505         reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK)
8506                         << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
8507                 | (in_data & DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK)
8508                         << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT;
8509         write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8510         reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK;
8511         write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8512
8513         /* wait for completion, alternate: interrupt */
8514         timeout = jiffies + msecs_to_jiffies(DC8051_COMMAND_TIMEOUT);
8515         while (1) {
8516                 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1);
8517                 completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK;
8518                 if (completed)
8519                         break;
8520                 if (time_after(jiffies, timeout)) {
8521                         dd->dc8051_timed_out++;
8522                         dd_dev_err(dd, "8051 host command %u timeout\n", type);
8523                         if (out_data)
8524                                 *out_data = 0;
8525                         return_code = -ETIMEDOUT;
8526                         goto fail;
8527                 }
8528                 udelay(2);
8529         }
8530
8531         if (out_data) {
8532                 *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT)
8533                                 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK;
8534                 if (type == HCMD_READ_LCB_CSR) {
8535                         /* top 16 bits are in a different register */
8536                         *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1)
8537                                 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK)
8538                                 << (48
8539                                     - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT);
8540                 }
8541         }
8542         return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT)
8543                                 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK;
8544         dd->dc8051_timed_out = 0;
8545         /*
8546          * Clear command for next user.
8547          */
8548         write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0);
8549
8550 fail:
8551         spin_unlock_irqrestore(&dd->dc8051_lock, flags);
8552
8553         return return_code;
8554 }
8555
8556 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state)
8557 {
8558         return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL);
8559 }
8560
8561 int load_8051_config(struct hfi1_devdata *dd, u8 field_id,
8562                      u8 lane_id, u32 config_data)
8563 {
8564         u64 data;
8565         int ret;
8566
8567         data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT
8568                 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT
8569                 | (u64)config_data << LOAD_DATA_DATA_SHIFT;
8570         ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL);
8571         if (ret != HCMD_SUCCESS) {
8572                 dd_dev_err(dd,
8573                            "load 8051 config: field id %d, lane %d, err %d\n",
8574                            (int)field_id, (int)lane_id, ret);
8575         }
8576         return ret;
8577 }
8578
8579 /*
8580  * Read the 8051 firmware "registers".  Use the RAM directly.  Always
8581  * set the result, even on error.
8582  * Return 0 on success, -errno on failure
8583  */
8584 int read_8051_config(struct hfi1_devdata *dd, u8 field_id, u8 lane_id,
8585                      u32 *result)
8586 {
8587         u64 big_data;
8588         u32 addr;
8589         int ret;
8590
8591         /* address start depends on the lane_id */
8592         if (lane_id < 4)
8593                 addr = (4 * NUM_GENERAL_FIELDS)
8594                         + (lane_id * 4 * NUM_LANE_FIELDS);
8595         else
8596                 addr = 0;
8597         addr += field_id * 4;
8598
8599         /* read is in 8-byte chunks, hardware will truncate the address down */
8600         ret = read_8051_data(dd, addr, 8, &big_data);
8601
8602         if (ret == 0) {
8603                 /* extract the 4 bytes we want */
8604                 if (addr & 0x4)
8605                         *result = (u32)(big_data >> 32);
8606                 else
8607                         *result = (u32)big_data;
8608         } else {
8609                 *result = 0;
8610                 dd_dev_err(dd, "%s: direct read failed, lane %d, field %d!\n",
8611                            __func__, lane_id, field_id);
8612         }
8613
8614         return ret;
8615 }
8616
8617 static int write_vc_local_phy(struct hfi1_devdata *dd, u8 power_management,
8618                               u8 continuous)
8619 {
8620         u32 frame;
8621
8622         frame = continuous << CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT
8623                 | power_management << POWER_MANAGEMENT_SHIFT;
8624         return load_8051_config(dd, VERIFY_CAP_LOCAL_PHY,
8625                                 GENERAL_CONFIG, frame);
8626 }
8627
8628 static int write_vc_local_fabric(struct hfi1_devdata *dd, u8 vau, u8 z, u8 vcu,
8629                                  u16 vl15buf, u8 crc_sizes)
8630 {
8631         u32 frame;
8632
8633         frame = (u32)vau << VAU_SHIFT
8634                 | (u32)z << Z_SHIFT
8635                 | (u32)vcu << VCU_SHIFT
8636                 | (u32)vl15buf << VL15BUF_SHIFT
8637                 | (u32)crc_sizes << CRC_SIZES_SHIFT;
8638         return load_8051_config(dd, VERIFY_CAP_LOCAL_FABRIC,
8639                                 GENERAL_CONFIG, frame);
8640 }
8641
8642 static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
8643                                      u8 *flag_bits, u16 *link_widths)
8644 {
8645         u32 frame;
8646
8647         read_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
8648                          &frame);
8649         *misc_bits = (frame >> MISC_CONFIG_BITS_SHIFT) & MISC_CONFIG_BITS_MASK;
8650         *flag_bits = (frame >> LOCAL_FLAG_BITS_SHIFT) & LOCAL_FLAG_BITS_MASK;
8651         *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8652 }
8653
8654 static int write_vc_local_link_width(struct hfi1_devdata *dd,
8655                                      u8 misc_bits,
8656                                      u8 flag_bits,
8657                                      u16 link_widths)
8658 {
8659         u32 frame;
8660
8661         frame = (u32)misc_bits << MISC_CONFIG_BITS_SHIFT
8662                 | (u32)flag_bits << LOCAL_FLAG_BITS_SHIFT
8663                 | (u32)link_widths << LINK_WIDTH_SHIFT;
8664         return load_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
8665                      frame);
8666 }
8667
8668 static int write_local_device_id(struct hfi1_devdata *dd, u16 device_id,
8669                                  u8 device_rev)
8670 {
8671         u32 frame;
8672
8673         frame = ((u32)device_id << LOCAL_DEVICE_ID_SHIFT)
8674                 | ((u32)device_rev << LOCAL_DEVICE_REV_SHIFT);
8675         return load_8051_config(dd, LOCAL_DEVICE_ID, GENERAL_CONFIG, frame);
8676 }
8677
8678 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
8679                                   u8 *device_rev)
8680 {
8681         u32 frame;
8682
8683         read_8051_config(dd, REMOTE_DEVICE_ID, GENERAL_CONFIG, &frame);
8684         *device_id = (frame >> REMOTE_DEVICE_ID_SHIFT) & REMOTE_DEVICE_ID_MASK;
8685         *device_rev = (frame >> REMOTE_DEVICE_REV_SHIFT)
8686                         & REMOTE_DEVICE_REV_MASK;
8687 }
8688
8689 void read_misc_status(struct hfi1_devdata *dd, u8 *ver_a, u8 *ver_b)
8690 {
8691         u32 frame;
8692
8693         read_8051_config(dd, MISC_STATUS, GENERAL_CONFIG, &frame);
8694         *ver_a = (frame >> STS_FM_VERSION_A_SHIFT) & STS_FM_VERSION_A_MASK;
8695         *ver_b = (frame >> STS_FM_VERSION_B_SHIFT) & STS_FM_VERSION_B_MASK;
8696 }
8697
8698 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
8699                                u8 *continuous)
8700 {
8701         u32 frame;
8702
8703         read_8051_config(dd, VERIFY_CAP_REMOTE_PHY, GENERAL_CONFIG, &frame);
8704         *power_management = (frame >> POWER_MANAGEMENT_SHIFT)
8705                                         & POWER_MANAGEMENT_MASK;
8706         *continuous = (frame >> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT)
8707                                         & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK;
8708 }
8709
8710 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
8711                                   u8 *vcu, u16 *vl15buf, u8 *crc_sizes)
8712 {
8713         u32 frame;
8714
8715         read_8051_config(dd, VERIFY_CAP_REMOTE_FABRIC, GENERAL_CONFIG, &frame);
8716         *vau = (frame >> VAU_SHIFT) & VAU_MASK;
8717         *z = (frame >> Z_SHIFT) & Z_MASK;
8718         *vcu = (frame >> VCU_SHIFT) & VCU_MASK;
8719         *vl15buf = (frame >> VL15BUF_SHIFT) & VL15BUF_MASK;
8720         *crc_sizes = (frame >> CRC_SIZES_SHIFT) & CRC_SIZES_MASK;
8721 }
8722
8723 static void read_vc_remote_link_width(struct hfi1_devdata *dd,
8724                                       u8 *remote_tx_rate,
8725                                       u16 *link_widths)
8726 {
8727         u32 frame;
8728
8729         read_8051_config(dd, VERIFY_CAP_REMOTE_LINK_WIDTH, GENERAL_CONFIG,
8730                          &frame);
8731         *remote_tx_rate = (frame >> REMOTE_TX_RATE_SHIFT)
8732                                 & REMOTE_TX_RATE_MASK;
8733         *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8734 }
8735
8736 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx)
8737 {
8738         u32 frame;
8739
8740         read_8051_config(dd, LOCAL_LNI_INFO, GENERAL_CONFIG, &frame);
8741         *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK;
8742 }
8743
8744 static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed)
8745 {
8746         u32 frame;
8747
8748         read_8051_config(dd, REMOTE_LNI_INFO, GENERAL_CONFIG, &frame);
8749         *mgmt_allowed = (frame >> MGMT_ALLOWED_SHIFT) & MGMT_ALLOWED_MASK;
8750 }
8751
8752 static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls)
8753 {
8754         read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls);
8755 }
8756
8757 static void read_last_remote_state(struct hfi1_devdata *dd, u32 *lrs)
8758 {
8759         read_8051_config(dd, LAST_REMOTE_STATE_COMPLETE, GENERAL_CONFIG, lrs);
8760 }
8761
8762 void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality)
8763 {
8764         u32 frame;
8765         int ret;
8766
8767         *link_quality = 0;
8768         if (dd->pport->host_link_state & HLS_UP) {
8769                 ret = read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG,
8770                                        &frame);
8771                 if (ret == 0)
8772                         *link_quality = (frame >> LINK_QUALITY_SHIFT)
8773                                                 & LINK_QUALITY_MASK;
8774         }
8775 }
8776
8777 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc)
8778 {
8779         u32 frame;
8780
8781         read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, &frame);
8782         *pdrrc = (frame >> DOWN_REMOTE_REASON_SHIFT) & DOWN_REMOTE_REASON_MASK;
8783 }
8784
8785 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr)
8786 {
8787         u32 frame;
8788
8789         read_8051_config(dd, LINK_DOWN_REASON, GENERAL_CONFIG, &frame);
8790         *ldr = (frame & 0xff);
8791 }
8792
8793 static int read_tx_settings(struct hfi1_devdata *dd,
8794                             u8 *enable_lane_tx,
8795                             u8 *tx_polarity_inversion,
8796                             u8 *rx_polarity_inversion,
8797                             u8 *max_rate)
8798 {
8799         u32 frame;
8800         int ret;
8801
8802         ret = read_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, &frame);
8803         *enable_lane_tx = (frame >> ENABLE_LANE_TX_SHIFT)
8804                                 & ENABLE_LANE_TX_MASK;
8805         *tx_polarity_inversion = (frame >> TX_POLARITY_INVERSION_SHIFT)
8806                                 & TX_POLARITY_INVERSION_MASK;
8807         *rx_polarity_inversion = (frame >> RX_POLARITY_INVERSION_SHIFT)
8808                                 & RX_POLARITY_INVERSION_MASK;
8809         *max_rate = (frame >> MAX_RATE_SHIFT) & MAX_RATE_MASK;
8810         return ret;
8811 }
8812
8813 static int write_tx_settings(struct hfi1_devdata *dd,
8814                              u8 enable_lane_tx,
8815                              u8 tx_polarity_inversion,
8816                              u8 rx_polarity_inversion,
8817                              u8 max_rate)
8818 {
8819         u32 frame;
8820
8821         /* no need to mask, all variable sizes match field widths */
8822         frame = enable_lane_tx << ENABLE_LANE_TX_SHIFT
8823                 | tx_polarity_inversion << TX_POLARITY_INVERSION_SHIFT
8824                 | rx_polarity_inversion << RX_POLARITY_INVERSION_SHIFT
8825                 | max_rate << MAX_RATE_SHIFT;
8826         return load_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, frame);
8827 }
8828
8829 /*
8830  * Read an idle LCB message.
8831  *
8832  * Returns 0 on success, -EINVAL on error
8833  */
8834 static int read_idle_message(struct hfi1_devdata *dd, u64 type, u64 *data_out)
8835 {
8836         int ret;
8837
8838         ret = do_8051_command(dd, HCMD_READ_LCB_IDLE_MSG, type, data_out);
8839         if (ret != HCMD_SUCCESS) {
8840                 dd_dev_err(dd, "read idle message: type %d, err %d\n",
8841                            (u32)type, ret);
8842                 return -EINVAL;
8843         }
8844         dd_dev_info(dd, "%s: read idle message 0x%llx\n", __func__, *data_out);
8845         /* return only the payload as we already know the type */
8846         *data_out >>= IDLE_PAYLOAD_SHIFT;
8847         return 0;
8848 }
8849
8850 /*
8851  * Read an idle SMA message.  To be done in response to a notification from
8852  * the 8051.
8853  *
8854  * Returns 0 on success, -EINVAL on error
8855  */
8856 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data)
8857 {
8858         return read_idle_message(dd, (u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT,
8859                                  data);
8860 }
8861
8862 /*
8863  * Send an idle LCB message.
8864  *
8865  * Returns 0 on success, -EINVAL on error
8866  */
8867 static int send_idle_message(struct hfi1_devdata *dd, u64 data)
8868 {
8869         int ret;
8870
8871         dd_dev_info(dd, "%s: sending idle message 0x%llx\n", __func__, data);
8872         ret = do_8051_command(dd, HCMD_SEND_LCB_IDLE_MSG, data, NULL);
8873         if (ret != HCMD_SUCCESS) {
8874                 dd_dev_err(dd, "send idle message: data 0x%llx, err %d\n",
8875                            data, ret);
8876                 return -EINVAL;
8877         }
8878         return 0;
8879 }
8880
8881 /*
8882  * Send an idle SMA message.
8883  *
8884  * Returns 0 on success, -EINVAL on error
8885  */
8886 int send_idle_sma(struct hfi1_devdata *dd, u64 message)
8887 {
8888         u64 data;
8889
8890         data = ((message & IDLE_PAYLOAD_MASK) << IDLE_PAYLOAD_SHIFT) |
8891                 ((u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT);
8892         return send_idle_message(dd, data);
8893 }
8894
8895 /*
8896  * Initialize the LCB then do a quick link up.  This may or may not be
8897  * in loopback.
8898  *
8899  * return 0 on success, -errno on error
8900  */
8901 static int do_quick_linkup(struct hfi1_devdata *dd)
8902 {
8903         u64 reg;
8904         unsigned long timeout;
8905         int ret;
8906
8907         lcb_shutdown(dd, 0);
8908
8909         if (loopback) {
8910                 /* LCB_CFG_LOOPBACK.VAL = 2 */
8911                 /* LCB_CFG_LANE_WIDTH.VAL = 0 */
8912                 write_csr(dd, DC_LCB_CFG_LOOPBACK,
8913                           IB_PACKET_TYPE << DC_LCB_CFG_LOOPBACK_VAL_SHIFT);
8914                 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
8915         }
8916
8917         /* start the LCBs */
8918         /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */
8919         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
8920
8921         /* simulator only loopback steps */
8922         if (loopback && dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8923                 /* LCB_CFG_RUN.EN = 1 */
8924                 write_csr(dd, DC_LCB_CFG_RUN,
8925                           1ull << DC_LCB_CFG_RUN_EN_SHIFT);
8926
8927                 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */
8928                 timeout = jiffies + msecs_to_jiffies(10);
8929                 while (1) {
8930                         reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE);
8931                         if (reg)
8932                                 break;
8933                         if (time_after(jiffies, timeout)) {
8934                                 dd_dev_err(dd,
8935                                            "timeout waiting for LINK_TRANSFER_ACTIVE\n");
8936                                 return -ETIMEDOUT;
8937                         }
8938                         udelay(2);
8939                 }
8940
8941                 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP,
8942                           1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT);
8943         }
8944
8945         if (!loopback) {
8946                 /*
8947                  * When doing quick linkup and not in loopback, both
8948                  * sides must be done with LCB set-up before either
8949                  * starts the quick linkup.  Put a delay here so that
8950                  * both sides can be started and have a chance to be
8951                  * done with LCB set up before resuming.
8952                  */
8953                 dd_dev_err(dd,
8954                            "Pausing for peer to be finished with LCB set up\n");
8955                 msleep(5000);
8956                 dd_dev_err(dd, "Continuing with quick linkup\n");
8957         }
8958
8959         write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
8960         set_8051_lcb_access(dd);
8961
8962         /*
8963          * State "quick" LinkUp request sets the physical link state to
8964          * LinkUp without a verify capability sequence.
8965          * This state is in simulator v37 and later.
8966          */
8967         ret = set_physical_link_state(dd, PLS_QUICK_LINKUP);
8968         if (ret != HCMD_SUCCESS) {
8969                 dd_dev_err(dd,
8970                            "%s: set physical link state to quick LinkUp failed with return %d\n",
8971                            __func__, ret);
8972
8973                 set_host_lcb_access(dd);
8974                 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
8975
8976                 if (ret >= 0)
8977                         ret = -EINVAL;
8978                 return ret;
8979         }
8980
8981         return 0; /* success */
8982 }
8983
8984 /*
8985  * Set the SerDes to internal loopback mode.
8986  * Returns 0 on success, -errno on error.
8987  */
8988 static int set_serdes_loopback_mode(struct hfi1_devdata *dd)
8989 {
8990         int ret;
8991
8992         ret = set_physical_link_state(dd, PLS_INTERNAL_SERDES_LOOPBACK);
8993         if (ret == HCMD_SUCCESS)
8994                 return 0;
8995         dd_dev_err(dd,
8996                    "Set physical link state to SerDes Loopback failed with return %d\n",
8997                    ret);
8998         if (ret >= 0)
8999                 ret = -EINVAL;
9000         return ret;
9001 }
9002
9003 /*
9004  * Do all special steps to set up loopback.
9005  */
9006 static int init_loopback(struct hfi1_devdata *dd)
9007 {
9008         dd_dev_info(dd, "Entering loopback mode\n");
9009
9010         /* all loopbacks should disable self GUID check */
9011         write_csr(dd, DC_DC8051_CFG_MODE,
9012                   (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK));
9013
9014         /*
9015          * The simulator has only one loopback option - LCB.  Switch
9016          * to that option, which includes quick link up.
9017          *
9018          * Accept all valid loopback values.
9019          */
9020         if ((dd->icode == ICODE_FUNCTIONAL_SIMULATOR) &&
9021             (loopback == LOOPBACK_SERDES || loopback == LOOPBACK_LCB ||
9022              loopback == LOOPBACK_CABLE)) {
9023                 loopback = LOOPBACK_LCB;
9024                 quick_linkup = 1;
9025                 return 0;
9026         }
9027
9028         /* handle serdes loopback */
9029         if (loopback == LOOPBACK_SERDES) {
9030                 /* internal serdes loopack needs quick linkup on RTL */
9031                 if (dd->icode == ICODE_RTL_SILICON)
9032                         quick_linkup = 1;
9033                 return set_serdes_loopback_mode(dd);
9034         }
9035
9036         /* LCB loopback - handled at poll time */
9037         if (loopback == LOOPBACK_LCB) {
9038                 quick_linkup = 1; /* LCB is always quick linkup */
9039
9040                 /* not supported in emulation due to emulation RTL changes */
9041                 if (dd->icode == ICODE_FPGA_EMULATION) {
9042                         dd_dev_err(dd,
9043                                    "LCB loopback not supported in emulation\n");
9044                         return -EINVAL;
9045                 }
9046                 return 0;
9047         }
9048
9049         /* external cable loopback requires no extra steps */
9050         if (loopback == LOOPBACK_CABLE)
9051                 return 0;
9052
9053         dd_dev_err(dd, "Invalid loopback mode %d\n", loopback);
9054         return -EINVAL;
9055 }
9056
9057 /*
9058  * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
9059  * used in the Verify Capability link width attribute.
9060  */
9061 static u16 opa_to_vc_link_widths(u16 opa_widths)
9062 {
9063         int i;
9064         u16 result = 0;
9065
9066         static const struct link_bits {
9067                 u16 from;
9068                 u16 to;
9069         } opa_link_xlate[] = {
9070                 { OPA_LINK_WIDTH_1X, 1 << (1 - 1)  },
9071                 { OPA_LINK_WIDTH_2X, 1 << (2 - 1)  },
9072                 { OPA_LINK_WIDTH_3X, 1 << (3 - 1)  },
9073                 { OPA_LINK_WIDTH_4X, 1 << (4 - 1)  },
9074         };
9075
9076         for (i = 0; i < ARRAY_SIZE(opa_link_xlate); i++) {
9077                 if (opa_widths & opa_link_xlate[i].from)
9078                         result |= opa_link_xlate[i].to;
9079         }
9080         return result;
9081 }
9082
9083 /*
9084  * Set link attributes before moving to polling.
9085  */
9086 static int set_local_link_attributes(struct hfi1_pportdata *ppd)
9087 {
9088         struct hfi1_devdata *dd = ppd->dd;
9089         u8 enable_lane_tx;
9090         u8 tx_polarity_inversion;
9091         u8 rx_polarity_inversion;
9092         int ret;
9093
9094         /* reset our fabric serdes to clear any lingering problems */
9095         fabric_serdes_reset(dd);
9096
9097         /* set the local tx rate - need to read-modify-write */
9098         ret = read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
9099                                &rx_polarity_inversion, &ppd->local_tx_rate);
9100         if (ret)
9101                 goto set_local_link_attributes_fail;
9102
9103         if (dd->dc8051_ver < dc8051_ver(0, 20)) {
9104                 /* set the tx rate to the fastest enabled */
9105                 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
9106                         ppd->local_tx_rate = 1;
9107                 else
9108                         ppd->local_tx_rate = 0;
9109         } else {
9110                 /* set the tx rate to all enabled */
9111                 ppd->local_tx_rate = 0;
9112                 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
9113                         ppd->local_tx_rate |= 2;
9114                 if (ppd->link_speed_enabled & OPA_LINK_SPEED_12_5G)
9115                         ppd->local_tx_rate |= 1;
9116         }
9117
9118         enable_lane_tx = 0xF; /* enable all four lanes */
9119         ret = write_tx_settings(dd, enable_lane_tx, tx_polarity_inversion,
9120                                 rx_polarity_inversion, ppd->local_tx_rate);
9121         if (ret != HCMD_SUCCESS)
9122                 goto set_local_link_attributes_fail;
9123
9124         /*
9125          * DC supports continuous updates.
9126          */
9127         ret = write_vc_local_phy(dd,
9128                                  0 /* no power management */,
9129                                  1 /* continuous updates */);
9130         if (ret != HCMD_SUCCESS)
9131                 goto set_local_link_attributes_fail;
9132
9133         /* z=1 in the next call: AU of 0 is not supported by the hardware */
9134         ret = write_vc_local_fabric(dd, dd->vau, 1, dd->vcu, dd->vl15_init,
9135                                     ppd->port_crc_mode_enabled);
9136         if (ret != HCMD_SUCCESS)
9137                 goto set_local_link_attributes_fail;
9138
9139         ret = write_vc_local_link_width(dd, 0, 0,
9140                                         opa_to_vc_link_widths(
9141                                                 ppd->link_width_enabled));
9142         if (ret != HCMD_SUCCESS)
9143                 goto set_local_link_attributes_fail;
9144
9145         /* let peer know who we are */
9146         ret = write_local_device_id(dd, dd->pcidev->device, dd->minrev);
9147         if (ret == HCMD_SUCCESS)
9148                 return 0;
9149
9150 set_local_link_attributes_fail:
9151         dd_dev_err(dd,
9152                    "Failed to set local link attributes, return 0x%x\n",
9153                    ret);
9154         return ret;
9155 }
9156
9157 /*
9158  * Call this to start the link.
9159  * Do not do anything if the link is disabled.
9160  * Returns 0 if link is disabled, moved to polling, or the driver is not ready.
9161  */
9162 int start_link(struct hfi1_pportdata *ppd)
9163 {
9164         if (!ppd->link_enabled) {
9165                 dd_dev_info(ppd->dd,
9166                             "%s: stopping link start because link is disabled\n",
9167                             __func__);
9168                 return 0;
9169         }
9170         if (!ppd->driver_link_ready) {
9171                 dd_dev_info(ppd->dd,
9172                             "%s: stopping link start because driver is not ready\n",
9173                             __func__);
9174                 return 0;
9175         }
9176
9177         /*
9178          * FULL_MGMT_P_KEY is cleared from the pkey table, so that the
9179          * pkey table can be configured properly if the HFI unit is connected
9180          * to switch port with MgmtAllowed=NO
9181          */
9182         clear_full_mgmt_pkey(ppd);
9183
9184         return set_link_state(ppd, HLS_DN_POLL);
9185 }
9186
9187 static void wait_for_qsfp_init(struct hfi1_pportdata *ppd)
9188 {
9189         struct hfi1_devdata *dd = ppd->dd;
9190         u64 mask;
9191         unsigned long timeout;
9192
9193         /*
9194          * Some QSFP cables have a quirk that asserts the IntN line as a side
9195          * effect of power up on plug-in. We ignore this false positive
9196          * interrupt until the module has finished powering up by waiting for
9197          * a minimum timeout of the module inrush initialization time of
9198          * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the
9199          * module have stabilized.
9200          */
9201         msleep(500);
9202
9203         /*
9204          * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1)
9205          */
9206         timeout = jiffies + msecs_to_jiffies(2000);
9207         while (1) {
9208                 mask = read_csr(dd, dd->hfi1_id ?
9209                                 ASIC_QSFP2_IN : ASIC_QSFP1_IN);
9210                 if (!(mask & QSFP_HFI0_INT_N))
9211                         break;
9212                 if (time_after(jiffies, timeout)) {
9213                         dd_dev_info(dd, "%s: No IntN detected, reset complete\n",
9214                                     __func__);
9215                         break;
9216                 }
9217                 udelay(2);
9218         }
9219 }
9220
9221 static void set_qsfp_int_n(struct hfi1_pportdata *ppd, u8 enable)
9222 {
9223         struct hfi1_devdata *dd = ppd->dd;
9224         u64 mask;
9225
9226         mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK);
9227         if (enable) {
9228                 /*
9229                  * Clear the status register to avoid an immediate interrupt
9230                  * when we re-enable the IntN pin
9231                  */
9232                 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9233                           QSFP_HFI0_INT_N);
9234                 mask |= (u64)QSFP_HFI0_INT_N;
9235         } else {
9236                 mask &= ~(u64)QSFP_HFI0_INT_N;
9237         }
9238         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
9239 }
9240
9241 void reset_qsfp(struct hfi1_pportdata *ppd)
9242 {
9243         struct hfi1_devdata *dd = ppd->dd;
9244         u64 mask, qsfp_mask;
9245
9246         /* Disable INT_N from triggering QSFP interrupts */
9247         set_qsfp_int_n(ppd, 0);
9248
9249         /* Reset the QSFP */
9250         mask = (u64)QSFP_HFI0_RESET_N;
9251
9252         qsfp_mask = read_csr(dd,
9253                              dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT);
9254         qsfp_mask &= ~mask;
9255         write_csr(dd,
9256                   dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
9257
9258         udelay(10);
9259
9260         qsfp_mask |= mask;
9261         write_csr(dd,
9262                   dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
9263
9264         wait_for_qsfp_init(ppd);
9265
9266         /*
9267          * Allow INT_N to trigger the QSFP interrupt to watch
9268          * for alarms and warnings
9269          */
9270         set_qsfp_int_n(ppd, 1);
9271 }
9272
9273 static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd,
9274                                         u8 *qsfp_interrupt_status)
9275 {
9276         struct hfi1_devdata *dd = ppd->dd;
9277
9278         if ((qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_ALARM) ||
9279             (qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_WARNING))
9280                 dd_dev_info(dd, "%s: QSFP cable on fire\n",
9281                             __func__);
9282
9283         if ((qsfp_interrupt_status[0] & QSFP_LOW_TEMP_ALARM) ||
9284             (qsfp_interrupt_status[0] & QSFP_LOW_TEMP_WARNING))
9285                 dd_dev_info(dd, "%s: QSFP cable temperature too low\n",
9286                             __func__);
9287
9288         /*
9289          * The remaining alarms/warnings don't matter if the link is down.
9290          */
9291         if (ppd->host_link_state & HLS_DOWN)
9292                 return 0;
9293
9294         if ((qsfp_interrupt_status[1] & QSFP_HIGH_VCC_ALARM) ||
9295             (qsfp_interrupt_status[1] & QSFP_HIGH_VCC_WARNING))
9296                 dd_dev_info(dd, "%s: QSFP supply voltage too high\n",
9297                             __func__);
9298
9299         if ((qsfp_interrupt_status[1] & QSFP_LOW_VCC_ALARM) ||
9300             (qsfp_interrupt_status[1] & QSFP_LOW_VCC_WARNING))
9301                 dd_dev_info(dd, "%s: QSFP supply voltage too low\n",
9302                             __func__);
9303
9304         /* Byte 2 is vendor specific */
9305
9306         if ((qsfp_interrupt_status[3] & QSFP_HIGH_POWER_ALARM) ||
9307             (qsfp_interrupt_status[3] & QSFP_HIGH_POWER_WARNING))
9308                 dd_dev_info(dd, "%s: Cable RX channel 1/2 power too high\n",
9309                             __func__);
9310
9311         if ((qsfp_interrupt_status[3] & QSFP_LOW_POWER_ALARM) ||
9312             (qsfp_interrupt_status[3] & QSFP_LOW_POWER_WARNING))
9313                 dd_dev_info(dd, "%s: Cable RX channel 1/2 power too low\n",
9314                             __func__);
9315
9316         if ((qsfp_interrupt_status[4] & QSFP_HIGH_POWER_ALARM) ||
9317             (qsfp_interrupt_status[4] & QSFP_HIGH_POWER_WARNING))
9318                 dd_dev_info(dd, "%s: Cable RX channel 3/4 power too high\n",
9319                             __func__);
9320
9321         if ((qsfp_interrupt_status[4] & QSFP_LOW_POWER_ALARM) ||
9322             (qsfp_interrupt_status[4] & QSFP_LOW_POWER_WARNING))
9323                 dd_dev_info(dd, "%s: Cable RX channel 3/4 power too low\n",
9324                             __func__);
9325
9326         if ((qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_ALARM) ||
9327             (qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_WARNING))
9328                 dd_dev_info(dd, "%s: Cable TX channel 1/2 bias too high\n",
9329                             __func__);
9330
9331         if ((qsfp_interrupt_status[5] & QSFP_LOW_BIAS_ALARM) ||
9332             (qsfp_interrupt_status[5] & QSFP_LOW_BIAS_WARNING))
9333                 dd_dev_info(dd, "%s: Cable TX channel 1/2 bias too low\n",
9334                             __func__);
9335
9336         if ((qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_ALARM) ||
9337             (qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_WARNING))
9338                 dd_dev_info(dd, "%s: Cable TX channel 3/4 bias too high\n",
9339                             __func__);
9340
9341         if ((qsfp_interrupt_status[6] & QSFP_LOW_BIAS_ALARM) ||
9342             (qsfp_interrupt_status[6] & QSFP_LOW_BIAS_WARNING))
9343                 dd_dev_info(dd, "%s: Cable TX channel 3/4 bias too low\n",
9344                             __func__);
9345
9346         if ((qsfp_interrupt_status[7] & QSFP_HIGH_POWER_ALARM) ||
9347             (qsfp_interrupt_status[7] & QSFP_HIGH_POWER_WARNING))
9348                 dd_dev_info(dd, "%s: Cable TX channel 1/2 power too high\n",
9349                             __func__);
9350
9351         if ((qsfp_interrupt_status[7] & QSFP_LOW_POWER_ALARM) ||
9352             (qsfp_interrupt_status[7] & QSFP_LOW_POWER_WARNING))
9353                 dd_dev_info(dd, "%s: Cable TX channel 1/2 power too low\n",
9354                             __func__);
9355
9356         if ((qsfp_interrupt_status[8] & QSFP_HIGH_POWER_ALARM) ||
9357             (qsfp_interrupt_status[8] & QSFP_HIGH_POWER_WARNING))
9358                 dd_dev_info(dd, "%s: Cable TX channel 3/4 power too high\n",
9359                             __func__);
9360
9361         if ((qsfp_interrupt_status[8] & QSFP_LOW_POWER_ALARM) ||
9362             (qsfp_interrupt_status[8] & QSFP_LOW_POWER_WARNING))
9363                 dd_dev_info(dd, "%s: Cable TX channel 3/4 power too low\n",
9364                             __func__);
9365
9366         /* Bytes 9-10 and 11-12 are reserved */
9367         /* Bytes 13-15 are vendor specific */
9368
9369         return 0;
9370 }
9371
9372 /* This routine will only be scheduled if the QSFP module present is asserted */
9373 void qsfp_event(struct work_struct *work)
9374 {
9375         struct qsfp_data *qd;
9376         struct hfi1_pportdata *ppd;
9377         struct hfi1_devdata *dd;
9378
9379         qd = container_of(work, struct qsfp_data, qsfp_work);
9380         ppd = qd->ppd;
9381         dd = ppd->dd;
9382
9383         /* Sanity check */
9384         if (!qsfp_mod_present(ppd))
9385                 return;
9386
9387         /*
9388          * Turn DC back on after cable has been re-inserted. Up until
9389          * now, the DC has been in reset to save power.
9390          */
9391         dc_start(dd);
9392
9393         if (qd->cache_refresh_required) {
9394                 set_qsfp_int_n(ppd, 0);
9395
9396                 wait_for_qsfp_init(ppd);
9397
9398                 /*
9399                  * Allow INT_N to trigger the QSFP interrupt to watch
9400                  * for alarms and warnings
9401                  */
9402                 set_qsfp_int_n(ppd, 1);
9403
9404                 tune_serdes(ppd);
9405
9406                 start_link(ppd);
9407         }
9408
9409         if (qd->check_interrupt_flags) {
9410                 u8 qsfp_interrupt_status[16] = {0,};
9411
9412                 if (one_qsfp_read(ppd, dd->hfi1_id, 6,
9413                                   &qsfp_interrupt_status[0], 16) != 16) {
9414                         dd_dev_info(dd,
9415                                     "%s: Failed to read status of QSFP module\n",
9416                                     __func__);
9417                 } else {
9418                         unsigned long flags;
9419
9420                         handle_qsfp_error_conditions(
9421                                         ppd, qsfp_interrupt_status);
9422                         spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
9423                         ppd->qsfp_info.check_interrupt_flags = 0;
9424                         spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
9425                                                flags);
9426                 }
9427         }
9428 }
9429
9430 static void init_qsfp_int(struct hfi1_devdata *dd)
9431 {
9432         struct hfi1_pportdata *ppd = dd->pport;
9433         u64 qsfp_mask, cce_int_mask;
9434         const int qsfp1_int_smask = QSFP1_INT % 64;
9435         const int qsfp2_int_smask = QSFP2_INT % 64;
9436
9437         /*
9438          * disable QSFP1 interrupts for HFI1, QSFP2 interrupts for HFI0
9439          * Qsfp1Int and Qsfp2Int are adjacent bits in the same CSR,
9440          * therefore just one of QSFP1_INT/QSFP2_INT can be used to find
9441          * the index of the appropriate CSR in the CCEIntMask CSR array
9442          */
9443         cce_int_mask = read_csr(dd, CCE_INT_MASK +
9444                                 (8 * (QSFP1_INT / 64)));
9445         if (dd->hfi1_id) {
9446                 cce_int_mask &= ~((u64)1 << qsfp1_int_smask);
9447                 write_csr(dd, CCE_INT_MASK + (8 * (QSFP1_INT / 64)),
9448                           cce_int_mask);
9449         } else {
9450                 cce_int_mask &= ~((u64)1 << qsfp2_int_smask);
9451                 write_csr(dd, CCE_INT_MASK + (8 * (QSFP2_INT / 64)),
9452                           cce_int_mask);
9453         }
9454
9455         qsfp_mask = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
9456         /* Clear current status to avoid spurious interrupts */
9457         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9458                   qsfp_mask);
9459         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK,
9460                   qsfp_mask);
9461
9462         set_qsfp_int_n(ppd, 0);
9463
9464         /* Handle active low nature of INT_N and MODPRST_N pins */
9465         if (qsfp_mod_present(ppd))
9466                 qsfp_mask &= ~(u64)QSFP_HFI0_MODPRST_N;
9467         write_csr(dd,
9468                   dd->hfi1_id ? ASIC_QSFP2_INVERT : ASIC_QSFP1_INVERT,
9469                   qsfp_mask);
9470 }
9471
9472 /*
9473  * Do a one-time initialize of the LCB block.
9474  */
9475 static void init_lcb(struct hfi1_devdata *dd)
9476 {
9477         /* simulator does not correctly handle LCB cclk loopback, skip */
9478         if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
9479                 return;
9480
9481         /* the DC has been reset earlier in the driver load */
9482
9483         /* set LCB for cclk loopback on the port */
9484         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01);
9485         write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00);
9486         write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00);
9487         write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
9488         write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08);
9489         write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02);
9490         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00);
9491 }
9492
9493 int bringup_serdes(struct hfi1_pportdata *ppd)
9494 {
9495         struct hfi1_devdata *dd = ppd->dd;
9496         u64 guid;
9497         int ret;
9498
9499         if (HFI1_CAP_IS_KSET(EXTENDED_PSN))
9500                 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK);
9501
9502         guid = ppd->guid;
9503         if (!guid) {
9504                 if (dd->base_guid)
9505                         guid = dd->base_guid + ppd->port - 1;
9506                 ppd->guid = guid;
9507         }
9508
9509         /* Set linkinit_reason on power up per OPA spec */
9510         ppd->linkinit_reason = OPA_LINKINIT_REASON_LINKUP;
9511
9512         /* one-time init of the LCB */
9513         init_lcb(dd);
9514
9515         if (loopback) {
9516                 ret = init_loopback(dd);
9517                 if (ret < 0)
9518                         return ret;
9519         }
9520
9521         get_port_type(ppd);
9522         if (ppd->port_type == PORT_TYPE_QSFP) {
9523                 set_qsfp_int_n(ppd, 0);
9524                 wait_for_qsfp_init(ppd);
9525                 set_qsfp_int_n(ppd, 1);
9526         }
9527
9528         /*
9529          * Tune the SerDes to a ballpark setting for
9530          * optimal signal and bit error rate
9531          * Needs to be done before starting the link
9532          */
9533         tune_serdes(ppd);
9534
9535         return start_link(ppd);
9536 }
9537
9538 void hfi1_quiet_serdes(struct hfi1_pportdata *ppd)
9539 {
9540         struct hfi1_devdata *dd = ppd->dd;
9541
9542         /*
9543          * Shut down the link and keep it down.   First turn off that the
9544          * driver wants to allow the link to be up (driver_link_ready).
9545          * Then make sure the link is not automatically restarted
9546          * (link_enabled).  Cancel any pending restart.  And finally
9547          * go offline.
9548          */
9549         ppd->driver_link_ready = 0;
9550         ppd->link_enabled = 0;
9551
9552         ppd->offline_disabled_reason =
9553                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_SMA_DISABLED);
9554         set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SMA_DISABLED, 0,
9555                              OPA_LINKDOWN_REASON_SMA_DISABLED);
9556         set_link_state(ppd, HLS_DN_OFFLINE);
9557
9558         /* disable the port */
9559         clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
9560 }
9561
9562 static inline int init_cpu_counters(struct hfi1_devdata *dd)
9563 {
9564         struct hfi1_pportdata *ppd;
9565         int i;
9566
9567         ppd = (struct hfi1_pportdata *)(dd + 1);
9568         for (i = 0; i < dd->num_pports; i++, ppd++) {
9569                 ppd->ibport_data.rvp.rc_acks = NULL;
9570                 ppd->ibport_data.rvp.rc_qacks = NULL;
9571                 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64);
9572                 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64);
9573                 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64);
9574                 if (!ppd->ibport_data.rvp.rc_acks ||
9575                     !ppd->ibport_data.rvp.rc_delayed_comp ||
9576                     !ppd->ibport_data.rvp.rc_qacks)
9577                         return -ENOMEM;
9578         }
9579
9580         return 0;
9581 }
9582
9583 static const char * const pt_names[] = {
9584         "expected",
9585         "eager",
9586         "invalid"
9587 };
9588
9589 static const char *pt_name(u32 type)
9590 {
9591         return type >= ARRAY_SIZE(pt_names) ? "unknown" : pt_names[type];
9592 }
9593
9594 /*
9595  * index is the index into the receive array
9596  */
9597 void hfi1_put_tid(struct hfi1_devdata *dd, u32 index,
9598                   u32 type, unsigned long pa, u16 order)
9599 {
9600         u64 reg;
9601         void __iomem *base = (dd->rcvarray_wc ? dd->rcvarray_wc :
9602                               (dd->kregbase + RCV_ARRAY));
9603
9604         if (!(dd->flags & HFI1_PRESENT))
9605                 goto done;
9606
9607         if (type == PT_INVALID) {
9608                 pa = 0;
9609         } else if (type > PT_INVALID) {
9610                 dd_dev_err(dd,
9611                            "unexpected receive array type %u for index %u, not handled\n",
9612                            type, index);
9613                 goto done;
9614         }
9615
9616         hfi1_cdbg(TID, "type %s, index 0x%x, pa 0x%lx, bsize 0x%lx",
9617                   pt_name(type), index, pa, (unsigned long)order);
9618
9619 #define RT_ADDR_SHIFT 12        /* 4KB kernel address boundary */
9620         reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK
9621                 | (u64)order << RCV_ARRAY_RT_BUF_SIZE_SHIFT
9622                 | ((pa >> RT_ADDR_SHIFT) & RCV_ARRAY_RT_ADDR_MASK)
9623                                         << RCV_ARRAY_RT_ADDR_SHIFT;
9624         writeq(reg, base + (index * 8));
9625
9626         if (type == PT_EAGER)
9627                 /*
9628                  * Eager entries are written one-by-one so we have to push them
9629                  * after we write the entry.
9630                  */
9631                 flush_wc();
9632 done:
9633         return;
9634 }
9635
9636 void hfi1_clear_tids(struct hfi1_ctxtdata *rcd)
9637 {
9638         struct hfi1_devdata *dd = rcd->dd;
9639         u32 i;
9640
9641         /* this could be optimized */
9642         for (i = rcd->eager_base; i < rcd->eager_base +
9643                      rcd->egrbufs.alloced; i++)
9644                 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9645
9646         for (i = rcd->expected_base;
9647                         i < rcd->expected_base + rcd->expected_count; i++)
9648                 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9649 }
9650
9651 struct hfi1_message_header *hfi1_get_msgheader(
9652                                 struct hfi1_devdata *dd, __le32 *rhf_addr)
9653 {
9654         u32 offset = rhf_hdrq_offset(rhf_to_cpu(rhf_addr));
9655
9656         return (struct hfi1_message_header *)
9657                 (rhf_addr - dd->rhf_offset + offset);
9658 }
9659
9660 static const char * const ib_cfg_name_strings[] = {
9661         "HFI1_IB_CFG_LIDLMC",
9662         "HFI1_IB_CFG_LWID_DG_ENB",
9663         "HFI1_IB_CFG_LWID_ENB",
9664         "HFI1_IB_CFG_LWID",
9665         "HFI1_IB_CFG_SPD_ENB",
9666         "HFI1_IB_CFG_SPD",
9667         "HFI1_IB_CFG_RXPOL_ENB",
9668         "HFI1_IB_CFG_LREV_ENB",
9669         "HFI1_IB_CFG_LINKLATENCY",
9670         "HFI1_IB_CFG_HRTBT",
9671         "HFI1_IB_CFG_OP_VLS",
9672         "HFI1_IB_CFG_VL_HIGH_CAP",
9673         "HFI1_IB_CFG_VL_LOW_CAP",
9674         "HFI1_IB_CFG_OVERRUN_THRESH",
9675         "HFI1_IB_CFG_PHYERR_THRESH",
9676         "HFI1_IB_CFG_LINKDEFAULT",
9677         "HFI1_IB_CFG_PKEYS",
9678         "HFI1_IB_CFG_MTU",
9679         "HFI1_IB_CFG_LSTATE",
9680         "HFI1_IB_CFG_VL_HIGH_LIMIT",
9681         "HFI1_IB_CFG_PMA_TICKS",
9682         "HFI1_IB_CFG_PORT"
9683 };
9684
9685 static const char *ib_cfg_name(int which)
9686 {
9687         if (which < 0 || which >= ARRAY_SIZE(ib_cfg_name_strings))
9688                 return "invalid";
9689         return ib_cfg_name_strings[which];
9690 }
9691
9692 int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which)
9693 {
9694         struct hfi1_devdata *dd = ppd->dd;
9695         int val = 0;
9696
9697         switch (which) {
9698         case HFI1_IB_CFG_LWID_ENB: /* allowed Link-width */
9699                 val = ppd->link_width_enabled;
9700                 break;
9701         case HFI1_IB_CFG_LWID: /* currently active Link-width */
9702                 val = ppd->link_width_active;
9703                 break;
9704         case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
9705                 val = ppd->link_speed_enabled;
9706                 break;
9707         case HFI1_IB_CFG_SPD: /* current Link speed */
9708                 val = ppd->link_speed_active;
9709                 break;
9710
9711         case HFI1_IB_CFG_RXPOL_ENB: /* Auto-RX-polarity enable */
9712         case HFI1_IB_CFG_LREV_ENB: /* Auto-Lane-reversal enable */
9713         case HFI1_IB_CFG_LINKLATENCY:
9714                 goto unimplemented;
9715
9716         case HFI1_IB_CFG_OP_VLS:
9717                 val = ppd->vls_operational;
9718                 break;
9719         case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */
9720                 val = VL_ARB_HIGH_PRIO_TABLE_SIZE;
9721                 break;
9722         case HFI1_IB_CFG_VL_LOW_CAP: /* VL arb low priority table size */
9723                 val = VL_ARB_LOW_PRIO_TABLE_SIZE;
9724                 break;
9725         case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
9726                 val = ppd->overrun_threshold;
9727                 break;
9728         case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
9729                 val = ppd->phy_error_threshold;
9730                 break;
9731         case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
9732                 val = dd->link_default;
9733                 break;
9734
9735         case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */
9736         case HFI1_IB_CFG_PMA_TICKS:
9737         default:
9738 unimplemented:
9739                 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
9740                         dd_dev_info(
9741                                 dd,
9742                                 "%s: which %s: not implemented\n",
9743                                 __func__,
9744                                 ib_cfg_name(which));
9745                 break;
9746         }
9747
9748         return val;
9749 }
9750
9751 /*
9752  * The largest MAD packet size.
9753  */
9754 #define MAX_MAD_PACKET 2048
9755
9756 /*
9757  * Return the maximum header bytes that can go on the _wire_
9758  * for this device. This count includes the ICRC which is
9759  * not part of the packet held in memory but it is appended
9760  * by the HW.
9761  * This is dependent on the device's receive header entry size.
9762  * HFI allows this to be set per-receive context, but the
9763  * driver presently enforces a global value.
9764  */
9765 u32 lrh_max_header_bytes(struct hfi1_devdata *dd)
9766 {
9767         /*
9768          * The maximum non-payload (MTU) bytes in LRH.PktLen are
9769          * the Receive Header Entry Size minus the PBC (or RHF) size
9770          * plus one DW for the ICRC appended by HW.
9771          *
9772          * dd->rcd[0].rcvhdrqentsize is in DW.
9773          * We use rcd[0] as all context will have the same value. Also,
9774          * the first kernel context would have been allocated by now so
9775          * we are guaranteed a valid value.
9776          */
9777         return (dd->rcd[0]->rcvhdrqentsize - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2;
9778 }
9779
9780 /*
9781  * Set Send Length
9782  * @ppd - per port data
9783  *
9784  * Set the MTU by limiting how many DWs may be sent.  The SendLenCheck*
9785  * registers compare against LRH.PktLen, so use the max bytes included
9786  * in the LRH.
9787  *
9788  * This routine changes all VL values except VL15, which it maintains at
9789  * the same value.
9790  */
9791 static void set_send_length(struct hfi1_pportdata *ppd)
9792 {
9793         struct hfi1_devdata *dd = ppd->dd;
9794         u32 max_hb = lrh_max_header_bytes(dd), dcmtu;
9795         u32 maxvlmtu = dd->vld[15].mtu;
9796         u64 len1 = 0, len2 = (((dd->vld[15].mtu + max_hb) >> 2)
9797                               & SEND_LEN_CHECK1_LEN_VL15_MASK) <<
9798                 SEND_LEN_CHECK1_LEN_VL15_SHIFT;
9799         int i, j;
9800         u32 thres;
9801
9802         for (i = 0; i < ppd->vls_supported; i++) {
9803                 if (dd->vld[i].mtu > maxvlmtu)
9804                         maxvlmtu = dd->vld[i].mtu;
9805                 if (i <= 3)
9806                         len1 |= (((dd->vld[i].mtu + max_hb) >> 2)
9807                                  & SEND_LEN_CHECK0_LEN_VL0_MASK) <<
9808                                 ((i % 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT);
9809                 else
9810                         len2 |= (((dd->vld[i].mtu + max_hb) >> 2)
9811                                  & SEND_LEN_CHECK1_LEN_VL4_MASK) <<
9812                                 ((i % 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT);
9813         }
9814         write_csr(dd, SEND_LEN_CHECK0, len1);
9815         write_csr(dd, SEND_LEN_CHECK1, len2);
9816         /* adjust kernel credit return thresholds based on new MTUs */
9817         /* all kernel receive contexts have the same hdrqentsize */
9818         for (i = 0; i < ppd->vls_supported; i++) {
9819                 thres = min(sc_percent_to_threshold(dd->vld[i].sc, 50),
9820                             sc_mtu_to_threshold(dd->vld[i].sc,
9821                                                 dd->vld[i].mtu,
9822                                                 dd->rcd[0]->rcvhdrqentsize));
9823                 for (j = 0; j < INIT_SC_PER_VL; j++)
9824                         sc_set_cr_threshold(
9825                                         pio_select_send_context_vl(dd, j, i),
9826                                             thres);
9827         }
9828         thres = min(sc_percent_to_threshold(dd->vld[15].sc, 50),
9829                     sc_mtu_to_threshold(dd->vld[15].sc,
9830                                         dd->vld[15].mtu,
9831                                         dd->rcd[0]->rcvhdrqentsize));
9832         sc_set_cr_threshold(dd->vld[15].sc, thres);
9833
9834         /* Adjust maximum MTU for the port in DC */
9835         dcmtu = maxvlmtu == 10240 ? DCC_CFG_PORT_MTU_CAP_10240 :
9836                 (ilog2(maxvlmtu >> 8) + 1);
9837         len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG);
9838         len1 &= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK;
9839         len1 |= ((u64)dcmtu & DCC_CFG_PORT_CONFIG_MTU_CAP_MASK) <<
9840                 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT;
9841         write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1);
9842 }
9843
9844 static void set_lidlmc(struct hfi1_pportdata *ppd)
9845 {
9846         int i;
9847         u64 sreg = 0;
9848         struct hfi1_devdata *dd = ppd->dd;
9849         u32 mask = ~((1U << ppd->lmc) - 1);
9850         u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1);
9851
9852         if (dd->hfi1_snoop.mode_flag)
9853                 dd_dev_info(dd, "Set lid/lmc while snooping");
9854
9855         c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
9856                 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK);
9857         c1 |= ((ppd->lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK)
9858                         << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT) |
9859               ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK)
9860                         << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT);
9861         write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1);
9862
9863         /*
9864          * Iterate over all the send contexts and set their SLID check
9865          */
9866         sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) <<
9867                         SEND_CTXT_CHECK_SLID_MASK_SHIFT) |
9868                (((ppd->lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) <<
9869                         SEND_CTXT_CHECK_SLID_VALUE_SHIFT);
9870
9871         for (i = 0; i < dd->chip_send_contexts; i++) {
9872                 hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x",
9873                           i, (u32)sreg);
9874                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, sreg);
9875         }
9876
9877         /* Now we have to do the same thing for the sdma engines */
9878         sdma_update_lmc(dd, mask, ppd->lid);
9879 }
9880
9881 static int wait_phy_linkstate(struct hfi1_devdata *dd, u32 state, u32 msecs)
9882 {
9883         unsigned long timeout;
9884         u32 curr_state;
9885
9886         timeout = jiffies + msecs_to_jiffies(msecs);
9887         while (1) {
9888                 curr_state = read_physical_state(dd);
9889                 if (curr_state == state)
9890                         break;
9891                 if (time_after(jiffies, timeout)) {
9892                         dd_dev_err(dd,
9893                                    "timeout waiting for phy link state 0x%x, current state is 0x%x\n",
9894                                    state, curr_state);
9895                         return -ETIMEDOUT;
9896                 }
9897                 usleep_range(1950, 2050); /* sleep 2ms-ish */
9898         }
9899
9900         return 0;
9901 }
9902
9903 static const char *state_completed_string(u32 completed)
9904 {
9905         static const char * const state_completed[] = {
9906                 "EstablishComm",
9907                 "OptimizeEQ",
9908                 "VerifyCap"
9909         };
9910
9911         if (completed < ARRAY_SIZE(state_completed))
9912                 return state_completed[completed];
9913
9914         return "unknown";
9915 }
9916
9917 static const char all_lanes_dead_timeout_expired[] =
9918         "All lanes were inactive – was the interconnect media removed?";
9919 static const char tx_out_of_policy[] =
9920         "Passing lanes on local port do not meet the local link width policy";
9921 static const char no_state_complete[] =
9922         "State timeout occurred before link partner completed the state";
9923 static const char * const state_complete_reasons[] = {
9924         [0x00] = "Reason unknown",
9925         [0x01] = "Link was halted by driver, refer to LinkDownReason",
9926         [0x02] = "Link partner reported failure",
9927         [0x10] = "Unable to achieve frame sync on any lane",
9928         [0x11] =
9929           "Unable to find a common bit rate with the link partner",
9930         [0x12] =
9931           "Unable to achieve frame sync on sufficient lanes to meet the local link width policy",
9932         [0x13] =
9933           "Unable to identify preset equalization on sufficient lanes to meet the local link width policy",
9934         [0x14] = no_state_complete,
9935         [0x15] =
9936           "State timeout occurred before link partner identified equalization presets",
9937         [0x16] =
9938           "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy",
9939         [0x17] = tx_out_of_policy,
9940         [0x20] = all_lanes_dead_timeout_expired,
9941         [0x21] =
9942           "Unable to achieve acceptable BER on sufficient lanes to meet the local link width policy",
9943         [0x22] = no_state_complete,
9944         [0x23] =
9945           "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy",
9946         [0x24] = tx_out_of_policy,
9947         [0x30] = all_lanes_dead_timeout_expired,
9948         [0x31] =
9949           "State timeout occurred waiting for host to process received frames",
9950         [0x32] = no_state_complete,
9951         [0x33] =
9952           "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy",
9953         [0x34] = tx_out_of_policy,
9954 };
9955
9956 static const char *state_complete_reason_code_string(struct hfi1_pportdata *ppd,
9957                                                      u32 code)
9958 {
9959         const char *str = NULL;
9960
9961         if (code < ARRAY_SIZE(state_complete_reasons))
9962                 str = state_complete_reasons[code];
9963
9964         if (str)
9965                 return str;
9966         return "Reserved";
9967 }
9968
9969 /* describe the given last state complete frame */
9970 static void decode_state_complete(struct hfi1_pportdata *ppd, u32 frame,
9971                                   const char *prefix)
9972 {
9973         struct hfi1_devdata *dd = ppd->dd;
9974         u32 success;
9975         u32 state;
9976         u32 reason;
9977         u32 lanes;
9978
9979         /*
9980          * Decode frame:
9981          *  [ 0: 0] - success
9982          *  [ 3: 1] - state
9983          *  [ 7: 4] - next state timeout
9984          *  [15: 8] - reason code
9985          *  [31:16] - lanes
9986          */
9987         success = frame & 0x1;
9988         state = (frame >> 1) & 0x7;
9989         reason = (frame >> 8) & 0xff;
9990         lanes = (frame >> 16) & 0xffff;
9991
9992         dd_dev_err(dd, "Last %s LNI state complete frame 0x%08x:\n",
9993                    prefix, frame);
9994         dd_dev_err(dd, "    last reported state state: %s (0x%x)\n",
9995                    state_completed_string(state), state);
9996         dd_dev_err(dd, "    state successfully completed: %s\n",
9997                    success ? "yes" : "no");
9998         dd_dev_err(dd, "    fail reason 0x%x: %s\n",
9999                    reason, state_complete_reason_code_string(ppd, reason));
10000         dd_dev_err(dd, "    passing lane mask: 0x%x", lanes);
10001 }
10002
10003 /*
10004  * Read the last state complete frames and explain them.  This routine
10005  * expects to be called if the link went down during link negotiation
10006  * and initialization (LNI).  That is, anywhere between polling and link up.
10007  */
10008 static void check_lni_states(struct hfi1_pportdata *ppd)
10009 {
10010         u32 last_local_state;
10011         u32 last_remote_state;
10012
10013         read_last_local_state(ppd->dd, &last_local_state);
10014         read_last_remote_state(ppd->dd, &last_remote_state);
10015
10016         /*
10017          * Don't report anything if there is nothing to report.  A value of
10018          * 0 means the link was taken down while polling and there was no
10019          * training in-process.
10020          */
10021         if (last_local_state == 0 && last_remote_state == 0)
10022                 return;
10023
10024         decode_state_complete(ppd, last_local_state, "transmitted");
10025         decode_state_complete(ppd, last_remote_state, "received");
10026 }
10027
10028 /*
10029  * Helper for set_link_state().  Do not call except from that routine.
10030  * Expects ppd->hls_mutex to be held.
10031  *
10032  * @rem_reason value to be sent to the neighbor
10033  *
10034  * LinkDownReasons only set if transition succeeds.
10035  */
10036 static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason)
10037 {
10038         struct hfi1_devdata *dd = ppd->dd;
10039         u32 pstate, previous_state;
10040         int ret;
10041         int do_transition;
10042         int do_wait;
10043
10044         previous_state = ppd->host_link_state;
10045         ppd->host_link_state = HLS_GOING_OFFLINE;
10046         pstate = read_physical_state(dd);
10047         if (pstate == PLS_OFFLINE) {
10048                 do_transition = 0;      /* in right state */
10049                 do_wait = 0;            /* ...no need to wait */
10050         } else if ((pstate & 0xff) == PLS_OFFLINE) {
10051                 do_transition = 0;      /* in an offline transient state */
10052                 do_wait = 1;            /* ...wait for it to settle */
10053         } else {
10054                 do_transition = 1;      /* need to move to offline */
10055                 do_wait = 1;            /* ...will need to wait */
10056         }
10057
10058         if (do_transition) {
10059                 ret = set_physical_link_state(dd,
10060                                               (rem_reason << 8) | PLS_OFFLINE);
10061
10062                 if (ret != HCMD_SUCCESS) {
10063                         dd_dev_err(dd,
10064                                    "Failed to transition to Offline link state, return %d\n",
10065                                    ret);
10066                         return -EINVAL;
10067                 }
10068                 if (ppd->offline_disabled_reason ==
10069                                 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))
10070                         ppd->offline_disabled_reason =
10071                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
10072         }
10073
10074         if (do_wait) {
10075                 /* it can take a while for the link to go down */
10076                 ret = wait_phy_linkstate(dd, PLS_OFFLINE, 10000);
10077                 if (ret < 0)
10078                         return ret;
10079         }
10080
10081         /* make sure the logical state is also down */
10082         wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000);
10083
10084         /*
10085          * Now in charge of LCB - must be after the physical state is
10086          * offline.quiet and before host_link_state is changed.
10087          */
10088         set_host_lcb_access(dd);
10089         write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
10090         ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */
10091
10092         if (ppd->port_type == PORT_TYPE_QSFP &&
10093             ppd->qsfp_info.limiting_active &&
10094             qsfp_mod_present(ppd)) {
10095                 int ret;
10096
10097                 ret = acquire_chip_resource(dd, qsfp_resource(dd), QSFP_WAIT);
10098                 if (ret == 0) {
10099                         set_qsfp_tx(ppd, 0);
10100                         release_chip_resource(dd, qsfp_resource(dd));
10101                 } else {
10102                         /* not fatal, but should warn */
10103                         dd_dev_err(dd,
10104                                    "Unable to acquire lock to turn off QSFP TX\n");
10105                 }
10106         }
10107
10108         /*
10109          * The LNI has a mandatory wait time after the physical state
10110          * moves to Offline.Quiet.  The wait time may be different
10111          * depending on how the link went down.  The 8051 firmware
10112          * will observe the needed wait time and only move to ready
10113          * when that is completed.  The largest of the quiet timeouts
10114          * is 6s, so wait that long and then at least 0.5s more for
10115          * other transitions, and another 0.5s for a buffer.
10116          */
10117         ret = wait_fm_ready(dd, 7000);
10118         if (ret) {
10119                 dd_dev_err(dd,
10120                            "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n");
10121                 /* state is really offline, so make it so */
10122                 ppd->host_link_state = HLS_DN_OFFLINE;
10123                 return ret;
10124         }
10125
10126         /*
10127          * The state is now offline and the 8051 is ready to accept host
10128          * requests.
10129          *      - change our state
10130          *      - notify others if we were previously in a linkup state
10131          */
10132         ppd->host_link_state = HLS_DN_OFFLINE;
10133         if (previous_state & HLS_UP) {
10134                 /* went down while link was up */
10135                 handle_linkup_change(dd, 0);
10136         } else if (previous_state
10137                         & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
10138                 /* went down while attempting link up */
10139                 check_lni_states(ppd);
10140         }
10141
10142         /* the active link width (downgrade) is 0 on link down */
10143         ppd->link_width_active = 0;
10144         ppd->link_width_downgrade_tx_active = 0;
10145         ppd->link_width_downgrade_rx_active = 0;
10146         ppd->current_egress_rate = 0;
10147         return 0;
10148 }
10149
10150 /* return the link state name */
10151 static const char *link_state_name(u32 state)
10152 {
10153         const char *name;
10154         int n = ilog2(state);
10155         static const char * const names[] = {
10156                 [__HLS_UP_INIT_BP]       = "INIT",
10157                 [__HLS_UP_ARMED_BP]      = "ARMED",
10158                 [__HLS_UP_ACTIVE_BP]     = "ACTIVE",
10159                 [__HLS_DN_DOWNDEF_BP]    = "DOWNDEF",
10160                 [__HLS_DN_POLL_BP]       = "POLL",
10161                 [__HLS_DN_DISABLE_BP]    = "DISABLE",
10162                 [__HLS_DN_OFFLINE_BP]    = "OFFLINE",
10163                 [__HLS_VERIFY_CAP_BP]    = "VERIFY_CAP",
10164                 [__HLS_GOING_UP_BP]      = "GOING_UP",
10165                 [__HLS_GOING_OFFLINE_BP] = "GOING_OFFLINE",
10166                 [__HLS_LINK_COOLDOWN_BP] = "LINK_COOLDOWN"
10167         };
10168
10169         name = n < ARRAY_SIZE(names) ? names[n] : NULL;
10170         return name ? name : "unknown";
10171 }
10172
10173 /* return the link state reason name */
10174 static const char *link_state_reason_name(struct hfi1_pportdata *ppd, u32 state)
10175 {
10176         if (state == HLS_UP_INIT) {
10177                 switch (ppd->linkinit_reason) {
10178                 case OPA_LINKINIT_REASON_LINKUP:
10179                         return "(LINKUP)";
10180                 case OPA_LINKINIT_REASON_FLAPPING:
10181                         return "(FLAPPING)";
10182                 case OPA_LINKINIT_OUTSIDE_POLICY:
10183                         return "(OUTSIDE_POLICY)";
10184                 case OPA_LINKINIT_QUARANTINED:
10185                         return "(QUARANTINED)";
10186                 case OPA_LINKINIT_INSUFIC_CAPABILITY:
10187                         return "(INSUFIC_CAPABILITY)";
10188                 default:
10189                         break;
10190                 }
10191         }
10192         return "";
10193 }
10194
10195 /*
10196  * driver_physical_state - convert the driver's notion of a port's
10197  * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*).
10198  * Return -1 (converted to a u32) to indicate error.
10199  */
10200 u32 driver_physical_state(struct hfi1_pportdata *ppd)
10201 {
10202         switch (ppd->host_link_state) {
10203         case HLS_UP_INIT:
10204         case HLS_UP_ARMED:
10205         case HLS_UP_ACTIVE:
10206                 return IB_PORTPHYSSTATE_LINKUP;
10207         case HLS_DN_POLL:
10208                 return IB_PORTPHYSSTATE_POLLING;
10209         case HLS_DN_DISABLE:
10210                 return IB_PORTPHYSSTATE_DISABLED;
10211         case HLS_DN_OFFLINE:
10212                 return OPA_PORTPHYSSTATE_OFFLINE;
10213         case HLS_VERIFY_CAP:
10214                 return IB_PORTPHYSSTATE_POLLING;
10215         case HLS_GOING_UP:
10216                 return IB_PORTPHYSSTATE_POLLING;
10217         case HLS_GOING_OFFLINE:
10218                 return OPA_PORTPHYSSTATE_OFFLINE;
10219         case HLS_LINK_COOLDOWN:
10220                 return OPA_PORTPHYSSTATE_OFFLINE;
10221         case HLS_DN_DOWNDEF:
10222         default:
10223                 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
10224                            ppd->host_link_state);
10225                 return  -1;
10226         }
10227 }
10228
10229 /*
10230  * driver_logical_state - convert the driver's notion of a port's
10231  * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1
10232  * (converted to a u32) to indicate error.
10233  */
10234 u32 driver_logical_state(struct hfi1_pportdata *ppd)
10235 {
10236         if (ppd->host_link_state && (ppd->host_link_state & HLS_DOWN))
10237                 return IB_PORT_DOWN;
10238
10239         switch (ppd->host_link_state & HLS_UP) {
10240         case HLS_UP_INIT:
10241                 return IB_PORT_INIT;
10242         case HLS_UP_ARMED:
10243                 return IB_PORT_ARMED;
10244         case HLS_UP_ACTIVE:
10245                 return IB_PORT_ACTIVE;
10246         default:
10247                 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
10248                            ppd->host_link_state);
10249         return -1;
10250         }
10251 }
10252
10253 void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason,
10254                           u8 neigh_reason, u8 rem_reason)
10255 {
10256         if (ppd->local_link_down_reason.latest == 0 &&
10257             ppd->neigh_link_down_reason.latest == 0) {
10258                 ppd->local_link_down_reason.latest = lcl_reason;
10259                 ppd->neigh_link_down_reason.latest = neigh_reason;
10260                 ppd->remote_link_down_reason = rem_reason;
10261         }
10262 }
10263
10264 /*
10265  * Change the physical and/or logical link state.
10266  *
10267  * Do not call this routine while inside an interrupt.  It contains
10268  * calls to routines that can take multiple seconds to finish.
10269  *
10270  * Returns 0 on success, -errno on failure.
10271  */
10272 int set_link_state(struct hfi1_pportdata *ppd, u32 state)
10273 {
10274         struct hfi1_devdata *dd = ppd->dd;
10275         struct ib_event event = {.device = NULL};
10276         int ret1, ret = 0;
10277         int orig_new_state, poll_bounce;
10278
10279         mutex_lock(&ppd->hls_lock);
10280
10281         orig_new_state = state;
10282         if (state == HLS_DN_DOWNDEF)
10283                 state = dd->link_default;
10284
10285         /* interpret poll -> poll as a link bounce */
10286         poll_bounce = ppd->host_link_state == HLS_DN_POLL &&
10287                       state == HLS_DN_POLL;
10288
10289         dd_dev_info(dd, "%s: current %s, new %s %s%s\n", __func__,
10290                     link_state_name(ppd->host_link_state),
10291                     link_state_name(orig_new_state),
10292                     poll_bounce ? "(bounce) " : "",
10293                     link_state_reason_name(ppd, state));
10294
10295         /*
10296          * If we're going to a (HLS_*) link state that implies the logical
10297          * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then
10298          * reset is_sm_config_started to 0.
10299          */
10300         if (!(state & (HLS_UP_ARMED | HLS_UP_ACTIVE)))
10301                 ppd->is_sm_config_started = 0;
10302
10303         /*
10304          * Do nothing if the states match.  Let a poll to poll link bounce
10305          * go through.
10306          */
10307         if (ppd->host_link_state == state && !poll_bounce)
10308                 goto done;
10309
10310         switch (state) {
10311         case HLS_UP_INIT:
10312                 if (ppd->host_link_state == HLS_DN_POLL &&
10313                     (quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) {
10314                         /*
10315                          * Quick link up jumps from polling to here.
10316                          *
10317                          * Whether in normal or loopback mode, the
10318                          * simulator jumps from polling to link up.
10319                          * Accept that here.
10320                          */
10321                         /* OK */
10322                 } else if (ppd->host_link_state != HLS_GOING_UP) {
10323                         goto unexpected;
10324                 }
10325
10326                 ppd->host_link_state = HLS_UP_INIT;
10327                 ret = wait_logical_linkstate(ppd, IB_PORT_INIT, 1000);
10328                 if (ret) {
10329                         /* logical state didn't change, stay at going_up */
10330                         ppd->host_link_state = HLS_GOING_UP;
10331                         dd_dev_err(dd,
10332                                    "%s: logical state did not change to INIT\n",
10333                                    __func__);
10334                 } else {
10335                         /* clear old transient LINKINIT_REASON code */
10336                         if (ppd->linkinit_reason >= OPA_LINKINIT_REASON_CLEAR)
10337                                 ppd->linkinit_reason =
10338                                         OPA_LINKINIT_REASON_LINKUP;
10339
10340                         /* enable the port */
10341                         add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
10342
10343                         handle_linkup_change(dd, 1);
10344                 }
10345                 break;
10346         case HLS_UP_ARMED:
10347                 if (ppd->host_link_state != HLS_UP_INIT)
10348                         goto unexpected;
10349
10350                 ppd->host_link_state = HLS_UP_ARMED;
10351                 set_logical_state(dd, LSTATE_ARMED);
10352                 ret = wait_logical_linkstate(ppd, IB_PORT_ARMED, 1000);
10353                 if (ret) {
10354                         /* logical state didn't change, stay at init */
10355                         ppd->host_link_state = HLS_UP_INIT;
10356                         dd_dev_err(dd,
10357                                    "%s: logical state did not change to ARMED\n",
10358                                    __func__);
10359                 }
10360                 /*
10361                  * The simulator does not currently implement SMA messages,
10362                  * so neighbor_normal is not set.  Set it here when we first
10363                  * move to Armed.
10364                  */
10365                 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
10366                         ppd->neighbor_normal = 1;
10367                 break;
10368         case HLS_UP_ACTIVE:
10369                 if (ppd->host_link_state != HLS_UP_ARMED)
10370                         goto unexpected;
10371
10372                 ppd->host_link_state = HLS_UP_ACTIVE;
10373                 set_logical_state(dd, LSTATE_ACTIVE);
10374                 ret = wait_logical_linkstate(ppd, IB_PORT_ACTIVE, 1000);
10375                 if (ret) {
10376                         /* logical state didn't change, stay at armed */
10377                         ppd->host_link_state = HLS_UP_ARMED;
10378                         dd_dev_err(dd,
10379                                    "%s: logical state did not change to ACTIVE\n",
10380                                    __func__);
10381                 } else {
10382                         /* tell all engines to go running */
10383                         sdma_all_running(dd);
10384
10385                         /* Signal the IB layer that the port has went active */
10386                         event.device = &dd->verbs_dev.rdi.ibdev;
10387                         event.element.port_num = ppd->port;
10388                         event.event = IB_EVENT_PORT_ACTIVE;
10389                 }
10390                 break;
10391         case HLS_DN_POLL:
10392                 if ((ppd->host_link_state == HLS_DN_DISABLE ||
10393                      ppd->host_link_state == HLS_DN_OFFLINE) &&
10394                     dd->dc_shutdown)
10395                         dc_start(dd);
10396                 /* Hand LED control to the DC */
10397                 write_csr(dd, DCC_CFG_LED_CNTRL, 0);
10398
10399                 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10400                         u8 tmp = ppd->link_enabled;
10401
10402                         ret = goto_offline(ppd, ppd->remote_link_down_reason);
10403                         if (ret) {
10404                                 ppd->link_enabled = tmp;
10405                                 break;
10406                         }
10407                         ppd->remote_link_down_reason = 0;
10408
10409                         if (ppd->driver_link_ready)
10410                                 ppd->link_enabled = 1;
10411                 }
10412
10413                 set_all_slowpath(ppd->dd);
10414                 ret = set_local_link_attributes(ppd);
10415                 if (ret)
10416                         break;
10417
10418                 ppd->port_error_action = 0;
10419                 ppd->host_link_state = HLS_DN_POLL;
10420
10421                 if (quick_linkup) {
10422                         /* quick linkup does not go into polling */
10423                         ret = do_quick_linkup(dd);
10424                 } else {
10425                         ret1 = set_physical_link_state(dd, PLS_POLLING);
10426                         if (ret1 != HCMD_SUCCESS) {
10427                                 dd_dev_err(dd,
10428                                            "Failed to transition to Polling link state, return 0x%x\n",
10429                                            ret1);
10430                                 ret = -EINVAL;
10431                         }
10432                 }
10433                 ppd->offline_disabled_reason =
10434                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE);
10435                 /*
10436                  * If an error occurred above, go back to offline.  The
10437                  * caller may reschedule another attempt.
10438                  */
10439                 if (ret)
10440                         goto_offline(ppd, 0);
10441                 break;
10442         case HLS_DN_DISABLE:
10443                 /* link is disabled */
10444                 ppd->link_enabled = 0;
10445
10446                 /* allow any state to transition to disabled */
10447
10448                 /* must transition to offline first */
10449                 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10450                         ret = goto_offline(ppd, ppd->remote_link_down_reason);
10451                         if (ret)
10452                                 break;
10453                         ppd->remote_link_down_reason = 0;
10454                 }
10455
10456                 ret1 = set_physical_link_state(dd, PLS_DISABLED);
10457                 if (ret1 != HCMD_SUCCESS) {
10458                         dd_dev_err(dd,
10459                                    "Failed to transition to Disabled link state, return 0x%x\n",
10460                                    ret1);
10461                         ret = -EINVAL;
10462                         break;
10463                 }
10464                 ppd->host_link_state = HLS_DN_DISABLE;
10465                 dc_shutdown(dd);
10466                 break;
10467         case HLS_DN_OFFLINE:
10468                 if (ppd->host_link_state == HLS_DN_DISABLE)
10469                         dc_start(dd);
10470
10471                 /* allow any state to transition to offline */
10472                 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10473                 if (!ret)
10474                         ppd->remote_link_down_reason = 0;
10475                 break;
10476         case HLS_VERIFY_CAP:
10477                 if (ppd->host_link_state != HLS_DN_POLL)
10478                         goto unexpected;
10479                 ppd->host_link_state = HLS_VERIFY_CAP;
10480                 break;
10481         case HLS_GOING_UP:
10482                 if (ppd->host_link_state != HLS_VERIFY_CAP)
10483                         goto unexpected;
10484
10485                 ret1 = set_physical_link_state(dd, PLS_LINKUP);
10486                 if (ret1 != HCMD_SUCCESS) {
10487                         dd_dev_err(dd,
10488                                    "Failed to transition to link up state, return 0x%x\n",
10489                                    ret1);
10490                         ret = -EINVAL;
10491                         break;
10492                 }
10493                 ppd->host_link_state = HLS_GOING_UP;
10494                 break;
10495
10496         case HLS_GOING_OFFLINE:         /* transient within goto_offline() */
10497         case HLS_LINK_COOLDOWN:         /* transient within goto_offline() */
10498         default:
10499                 dd_dev_info(dd, "%s: state 0x%x: not supported\n",
10500                             __func__, state);
10501                 ret = -EINVAL;
10502                 break;
10503         }
10504
10505         goto done;
10506
10507 unexpected:
10508         dd_dev_err(dd, "%s: unexpected state transition from %s to %s\n",
10509                    __func__, link_state_name(ppd->host_link_state),
10510                    link_state_name(state));
10511         ret = -EINVAL;
10512
10513 done:
10514         mutex_unlock(&ppd->hls_lock);
10515
10516         if (event.device)
10517                 ib_dispatch_event(&event);
10518
10519         return ret;
10520 }
10521
10522 int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val)
10523 {
10524         u64 reg;
10525         int ret = 0;
10526
10527         switch (which) {
10528         case HFI1_IB_CFG_LIDLMC:
10529                 set_lidlmc(ppd);
10530                 break;
10531         case HFI1_IB_CFG_VL_HIGH_LIMIT:
10532                 /*
10533                  * The VL Arbitrator high limit is sent in units of 4k
10534                  * bytes, while HFI stores it in units of 64 bytes.
10535                  */
10536                 val *= 4096 / 64;
10537                 reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK)
10538                         << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT;
10539                 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg);
10540                 break;
10541         case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
10542                 /* HFI only supports POLL as the default link down state */
10543                 if (val != HLS_DN_POLL)
10544                         ret = -EINVAL;
10545                 break;
10546         case HFI1_IB_CFG_OP_VLS:
10547                 if (ppd->vls_operational != val) {
10548                         ppd->vls_operational = val;
10549                         if (!ppd->port)
10550                                 ret = -EINVAL;
10551                 }
10552                 break;
10553         /*
10554          * For link width, link width downgrade, and speed enable, always AND
10555          * the setting with what is actually supported.  This has two benefits.
10556          * First, enabled can't have unsupported values, no matter what the
10557          * SM or FM might want.  Second, the ALL_SUPPORTED wildcards that mean
10558          * "fill in with your supported value" have all the bits in the
10559          * field set, so simply ANDing with supported has the desired result.
10560          */
10561         case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */
10562                 ppd->link_width_enabled = val & ppd->link_width_supported;
10563                 break;
10564         case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */
10565                 ppd->link_width_downgrade_enabled =
10566                                 val & ppd->link_width_downgrade_supported;
10567                 break;
10568         case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
10569                 ppd->link_speed_enabled = val & ppd->link_speed_supported;
10570                 break;
10571         case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
10572                 /*
10573                  * HFI does not follow IB specs, save this value
10574                  * so we can report it, if asked.
10575                  */
10576                 ppd->overrun_threshold = val;
10577                 break;
10578         case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
10579                 /*
10580                  * HFI does not follow IB specs, save this value
10581                  * so we can report it, if asked.
10582                  */
10583                 ppd->phy_error_threshold = val;
10584                 break;
10585
10586         case HFI1_IB_CFG_MTU:
10587                 set_send_length(ppd);
10588                 break;
10589
10590         case HFI1_IB_CFG_PKEYS:
10591                 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
10592                         set_partition_keys(ppd);
10593                 break;
10594
10595         default:
10596                 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
10597                         dd_dev_info(ppd->dd,
10598                                     "%s: which %s, val 0x%x: not implemented\n",
10599                                     __func__, ib_cfg_name(which), val);
10600                 break;
10601         }
10602         return ret;
10603 }
10604
10605 /* begin functions related to vl arbitration table caching */
10606 static void init_vl_arb_caches(struct hfi1_pportdata *ppd)
10607 {
10608         int i;
10609
10610         BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10611                         VL_ARB_LOW_PRIO_TABLE_SIZE);
10612         BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10613                         VL_ARB_HIGH_PRIO_TABLE_SIZE);
10614
10615         /*
10616          * Note that we always return values directly from the
10617          * 'vl_arb_cache' (and do no CSR reads) in response to a
10618          * 'Get(VLArbTable)'. This is obviously correct after a
10619          * 'Set(VLArbTable)', since the cache will then be up to
10620          * date. But it's also correct prior to any 'Set(VLArbTable)'
10621          * since then both the cache, and the relevant h/w registers
10622          * will be zeroed.
10623          */
10624
10625         for (i = 0; i < MAX_PRIO_TABLE; i++)
10626                 spin_lock_init(&ppd->vl_arb_cache[i].lock);
10627 }
10628
10629 /*
10630  * vl_arb_lock_cache
10631  *
10632  * All other vl_arb_* functions should be called only after locking
10633  * the cache.
10634  */
10635 static inline struct vl_arb_cache *
10636 vl_arb_lock_cache(struct hfi1_pportdata *ppd, int idx)
10637 {
10638         if (idx != LO_PRIO_TABLE && idx != HI_PRIO_TABLE)
10639                 return NULL;
10640         spin_lock(&ppd->vl_arb_cache[idx].lock);
10641         return &ppd->vl_arb_cache[idx];
10642 }
10643
10644 static inline void vl_arb_unlock_cache(struct hfi1_pportdata *ppd, int idx)
10645 {
10646         spin_unlock(&ppd->vl_arb_cache[idx].lock);
10647 }
10648
10649 static void vl_arb_get_cache(struct vl_arb_cache *cache,
10650                              struct ib_vl_weight_elem *vl)
10651 {
10652         memcpy(vl, cache->table, VL_ARB_TABLE_SIZE * sizeof(*vl));
10653 }
10654
10655 static void vl_arb_set_cache(struct vl_arb_cache *cache,
10656                              struct ib_vl_weight_elem *vl)
10657 {
10658         memcpy(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10659 }
10660
10661 static int vl_arb_match_cache(struct vl_arb_cache *cache,
10662                               struct ib_vl_weight_elem *vl)
10663 {
10664         return !memcmp(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10665 }
10666
10667 /* end functions related to vl arbitration table caching */
10668
10669 static int set_vl_weights(struct hfi1_pportdata *ppd, u32 target,
10670                           u32 size, struct ib_vl_weight_elem *vl)
10671 {
10672         struct hfi1_devdata *dd = ppd->dd;
10673         u64 reg;
10674         unsigned int i, is_up = 0;
10675         int drain, ret = 0;
10676
10677         mutex_lock(&ppd->hls_lock);
10678
10679         if (ppd->host_link_state & HLS_UP)
10680                 is_up = 1;
10681
10682         drain = !is_ax(dd) && is_up;
10683
10684         if (drain)
10685                 /*
10686                  * Before adjusting VL arbitration weights, empty per-VL
10687                  * FIFOs, otherwise a packet whose VL weight is being
10688                  * set to 0 could get stuck in a FIFO with no chance to
10689                  * egress.
10690                  */
10691                 ret = stop_drain_data_vls(dd);
10692
10693         if (ret) {
10694                 dd_dev_err(
10695                         dd,
10696                         "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n",
10697                         __func__);
10698                 goto err;
10699         }
10700
10701         for (i = 0; i < size; i++, vl++) {
10702                 /*
10703                  * NOTE: The low priority shift and mask are used here, but
10704                  * they are the same for both the low and high registers.
10705                  */
10706                 reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK)
10707                                 << SEND_LOW_PRIORITY_LIST_VL_SHIFT)
10708                       | (((u64)vl->weight
10709                                 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK)
10710                                 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT);
10711                 write_csr(dd, target + (i * 8), reg);
10712         }
10713         pio_send_control(dd, PSC_GLOBAL_VLARB_ENABLE);
10714
10715         if (drain)
10716                 open_fill_data_vls(dd); /* reopen all VLs */
10717
10718 err:
10719         mutex_unlock(&ppd->hls_lock);
10720
10721         return ret;
10722 }
10723
10724 /*
10725  * Read one credit merge VL register.
10726  */
10727 static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr,
10728                            struct vl_limit *vll)
10729 {
10730         u64 reg = read_csr(dd, csr);
10731
10732         vll->dedicated = cpu_to_be16(
10733                 (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT)
10734                 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK);
10735         vll->shared = cpu_to_be16(
10736                 (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT)
10737                 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK);
10738 }
10739
10740 /*
10741  * Read the current credit merge limits.
10742  */
10743 static int get_buffer_control(struct hfi1_devdata *dd,
10744                               struct buffer_control *bc, u16 *overall_limit)
10745 {
10746         u64 reg;
10747         int i;
10748
10749         /* not all entries are filled in */
10750         memset(bc, 0, sizeof(*bc));
10751
10752         /* OPA and HFI have a 1-1 mapping */
10753         for (i = 0; i < TXE_NUM_DATA_VL; i++)
10754                 read_one_cm_vl(dd, SEND_CM_CREDIT_VL + (8 * i), &bc->vl[i]);
10755
10756         /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */
10757         read_one_cm_vl(dd, SEND_CM_CREDIT_VL15, &bc->vl[15]);
10758
10759         reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10760         bc->overall_shared_limit = cpu_to_be16(
10761                 (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT)
10762                 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK);
10763         if (overall_limit)
10764                 *overall_limit = (reg
10765                         >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT)
10766                         & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK;
10767         return sizeof(struct buffer_control);
10768 }
10769
10770 static int get_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
10771 {
10772         u64 reg;
10773         int i;
10774
10775         /* each register contains 16 SC->VLnt mappings, 4 bits each */
10776         reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0);
10777         for (i = 0; i < sizeof(u64); i++) {
10778                 u8 byte = *(((u8 *)&reg) + i);
10779
10780                 dp->vlnt[2 * i] = byte & 0xf;
10781                 dp->vlnt[(2 * i) + 1] = (byte & 0xf0) >> 4;
10782         }
10783
10784         reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16);
10785         for (i = 0; i < sizeof(u64); i++) {
10786                 u8 byte = *(((u8 *)&reg) + i);
10787
10788                 dp->vlnt[16 + (2 * i)] = byte & 0xf;
10789                 dp->vlnt[16 + (2 * i) + 1] = (byte & 0xf0) >> 4;
10790         }
10791         return sizeof(struct sc2vlnt);
10792 }
10793
10794 static void get_vlarb_preempt(struct hfi1_devdata *dd, u32 nelems,
10795                               struct ib_vl_weight_elem *vl)
10796 {
10797         unsigned int i;
10798
10799         for (i = 0; i < nelems; i++, vl++) {
10800                 vl->vl = 0xf;
10801                 vl->weight = 0;
10802         }
10803 }
10804
10805 static void set_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
10806 {
10807         write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0,
10808                   DC_SC_VL_VAL(15_0,
10809                                0, dp->vlnt[0] & 0xf,
10810                                1, dp->vlnt[1] & 0xf,
10811                                2, dp->vlnt[2] & 0xf,
10812                                3, dp->vlnt[3] & 0xf,
10813                                4, dp->vlnt[4] & 0xf,
10814                                5, dp->vlnt[5] & 0xf,
10815                                6, dp->vlnt[6] & 0xf,
10816                                7, dp->vlnt[7] & 0xf,
10817                                8, dp->vlnt[8] & 0xf,
10818                                9, dp->vlnt[9] & 0xf,
10819                                10, dp->vlnt[10] & 0xf,
10820                                11, dp->vlnt[11] & 0xf,
10821                                12, dp->vlnt[12] & 0xf,
10822                                13, dp->vlnt[13] & 0xf,
10823                                14, dp->vlnt[14] & 0xf,
10824                                15, dp->vlnt[15] & 0xf));
10825         write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16,
10826                   DC_SC_VL_VAL(31_16,
10827                                16, dp->vlnt[16] & 0xf,
10828                                17, dp->vlnt[17] & 0xf,
10829                                18, dp->vlnt[18] & 0xf,
10830                                19, dp->vlnt[19] & 0xf,
10831                                20, dp->vlnt[20] & 0xf,
10832                                21, dp->vlnt[21] & 0xf,
10833                                22, dp->vlnt[22] & 0xf,
10834                                23, dp->vlnt[23] & 0xf,
10835                                24, dp->vlnt[24] & 0xf,
10836                                25, dp->vlnt[25] & 0xf,
10837                                26, dp->vlnt[26] & 0xf,
10838                                27, dp->vlnt[27] & 0xf,
10839                                28, dp->vlnt[28] & 0xf,
10840                                29, dp->vlnt[29] & 0xf,
10841                                30, dp->vlnt[30] & 0xf,
10842                                31, dp->vlnt[31] & 0xf));
10843 }
10844
10845 static void nonzero_msg(struct hfi1_devdata *dd, int idx, const char *what,
10846                         u16 limit)
10847 {
10848         if (limit != 0)
10849                 dd_dev_info(dd, "Invalid %s limit %d on VL %d, ignoring\n",
10850                             what, (int)limit, idx);
10851 }
10852
10853 /* change only the shared limit portion of SendCmGLobalCredit */
10854 static void set_global_shared(struct hfi1_devdata *dd, u16 limit)
10855 {
10856         u64 reg;
10857
10858         reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10859         reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK;
10860         reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT;
10861         write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
10862 }
10863
10864 /* change only the total credit limit portion of SendCmGLobalCredit */
10865 static void set_global_limit(struct hfi1_devdata *dd, u16 limit)
10866 {
10867         u64 reg;
10868
10869         reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10870         reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK;
10871         reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT;
10872         write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
10873 }
10874
10875 /* set the given per-VL shared limit */
10876 static void set_vl_shared(struct hfi1_devdata *dd, int vl, u16 limit)
10877 {
10878         u64 reg;
10879         u32 addr;
10880
10881         if (vl < TXE_NUM_DATA_VL)
10882                 addr = SEND_CM_CREDIT_VL + (8 * vl);
10883         else
10884                 addr = SEND_CM_CREDIT_VL15;
10885
10886         reg = read_csr(dd, addr);
10887         reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK;
10888         reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT;
10889         write_csr(dd, addr, reg);
10890 }
10891
10892 /* set the given per-VL dedicated limit */
10893 static void set_vl_dedicated(struct hfi1_devdata *dd, int vl, u16 limit)
10894 {
10895         u64 reg;
10896         u32 addr;
10897
10898         if (vl < TXE_NUM_DATA_VL)
10899                 addr = SEND_CM_CREDIT_VL + (8 * vl);
10900         else
10901                 addr = SEND_CM_CREDIT_VL15;
10902
10903         reg = read_csr(dd, addr);
10904         reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK;
10905         reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT;
10906         write_csr(dd, addr, reg);
10907 }
10908
10909 /* spin until the given per-VL status mask bits clear */
10910 static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask,
10911                                      const char *which)
10912 {
10913         unsigned long timeout;
10914         u64 reg;
10915
10916         timeout = jiffies + msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT);
10917         while (1) {
10918                 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask;
10919
10920                 if (reg == 0)
10921                         return; /* success */
10922                 if (time_after(jiffies, timeout))
10923                         break;          /* timed out */
10924                 udelay(1);
10925         }
10926
10927         dd_dev_err(dd,
10928                    "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n",
10929                    which, VL_STATUS_CLEAR_TIMEOUT, mask, reg);
10930         /*
10931          * If this occurs, it is likely there was a credit loss on the link.
10932          * The only recovery from that is a link bounce.
10933          */
10934         dd_dev_err(dd,
10935                    "Continuing anyway.  A credit loss may occur.  Suggest a link bounce\n");
10936 }
10937
10938 /*
10939  * The number of credits on the VLs may be changed while everything
10940  * is "live", but the following algorithm must be followed due to
10941  * how the hardware is actually implemented.  In particular,
10942  * Return_Credit_Status[] is the only correct status check.
10943  *
10944  * if (reducing Global_Shared_Credit_Limit or any shared limit changing)
10945  *     set Global_Shared_Credit_Limit = 0
10946  *     use_all_vl = 1
10947  * mask0 = all VLs that are changing either dedicated or shared limits
10948  * set Shared_Limit[mask0] = 0
10949  * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0
10950  * if (changing any dedicated limit)
10951  *     mask1 = all VLs that are lowering dedicated limits
10952  *     lower Dedicated_Limit[mask1]
10953  *     spin until Return_Credit_Status[mask1] == 0
10954  *     raise Dedicated_Limits
10955  * raise Shared_Limits
10956  * raise Global_Shared_Credit_Limit
10957  *
10958  * lower = if the new limit is lower, set the limit to the new value
10959  * raise = if the new limit is higher than the current value (may be changed
10960  *      earlier in the algorithm), set the new limit to the new value
10961  */
10962 int set_buffer_control(struct hfi1_pportdata *ppd,
10963                        struct buffer_control *new_bc)
10964 {
10965         struct hfi1_devdata *dd = ppd->dd;
10966         u64 changing_mask, ld_mask, stat_mask;
10967         int change_count;
10968         int i, use_all_mask;
10969         int this_shared_changing;
10970         int vl_count = 0, ret;
10971         /*
10972          * A0: add the variable any_shared_limit_changing below and in the
10973          * algorithm above.  If removing A0 support, it can be removed.
10974          */
10975         int any_shared_limit_changing;
10976         struct buffer_control cur_bc;
10977         u8 changing[OPA_MAX_VLS];
10978         u8 lowering_dedicated[OPA_MAX_VLS];
10979         u16 cur_total;
10980         u32 new_total = 0;
10981         const u64 all_mask =
10982         SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
10983          | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK
10984          | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK
10985          | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK
10986          | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK
10987          | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK
10988          | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK
10989          | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK
10990          | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK;
10991
10992 #define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15)
10993 #define NUM_USABLE_VLS 16       /* look at VL15 and less */
10994
10995         /* find the new total credits, do sanity check on unused VLs */
10996         for (i = 0; i < OPA_MAX_VLS; i++) {
10997                 if (valid_vl(i)) {
10998                         new_total += be16_to_cpu(new_bc->vl[i].dedicated);
10999                         continue;
11000                 }
11001                 nonzero_msg(dd, i, "dedicated",
11002                             be16_to_cpu(new_bc->vl[i].dedicated));
11003                 nonzero_msg(dd, i, "shared",
11004                             be16_to_cpu(new_bc->vl[i].shared));
11005                 new_bc->vl[i].dedicated = 0;
11006                 new_bc->vl[i].shared = 0;
11007         }
11008         new_total += be16_to_cpu(new_bc->overall_shared_limit);
11009
11010         /* fetch the current values */
11011         get_buffer_control(dd, &cur_bc, &cur_total);
11012
11013         /*
11014          * Create the masks we will use.
11015          */
11016         memset(changing, 0, sizeof(changing));
11017         memset(lowering_dedicated, 0, sizeof(lowering_dedicated));
11018         /*
11019          * NOTE: Assumes that the individual VL bits are adjacent and in
11020          * increasing order
11021          */
11022         stat_mask =
11023                 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK;
11024         changing_mask = 0;
11025         ld_mask = 0;
11026         change_count = 0;
11027         any_shared_limit_changing = 0;
11028         for (i = 0; i < NUM_USABLE_VLS; i++, stat_mask <<= 1) {
11029                 if (!valid_vl(i))
11030                         continue;
11031                 this_shared_changing = new_bc->vl[i].shared
11032                                                 != cur_bc.vl[i].shared;
11033                 if (this_shared_changing)
11034                         any_shared_limit_changing = 1;
11035                 if (new_bc->vl[i].dedicated != cur_bc.vl[i].dedicated ||
11036                     this_shared_changing) {
11037                         changing[i] = 1;
11038                         changing_mask |= stat_mask;
11039                         change_count++;
11040                 }
11041                 if (be16_to_cpu(new_bc->vl[i].dedicated) <
11042                                         be16_to_cpu(cur_bc.vl[i].dedicated)) {
11043                         lowering_dedicated[i] = 1;
11044                         ld_mask |= stat_mask;
11045                 }
11046         }
11047
11048         /* bracket the credit change with a total adjustment */
11049         if (new_total > cur_total)
11050                 set_global_limit(dd, new_total);
11051
11052         /*
11053          * Start the credit change algorithm.
11054          */
11055         use_all_mask = 0;
11056         if ((be16_to_cpu(new_bc->overall_shared_limit) <
11057              be16_to_cpu(cur_bc.overall_shared_limit)) ||
11058             (is_ax(dd) && any_shared_limit_changing)) {
11059                 set_global_shared(dd, 0);
11060                 cur_bc.overall_shared_limit = 0;
11061                 use_all_mask = 1;
11062         }
11063
11064         for (i = 0; i < NUM_USABLE_VLS; i++) {
11065                 if (!valid_vl(i))
11066                         continue;
11067
11068                 if (changing[i]) {
11069                         set_vl_shared(dd, i, 0);
11070                         cur_bc.vl[i].shared = 0;
11071                 }
11072         }
11073
11074         wait_for_vl_status_clear(dd, use_all_mask ? all_mask : changing_mask,
11075                                  "shared");
11076
11077         if (change_count > 0) {
11078                 for (i = 0; i < NUM_USABLE_VLS; i++) {
11079                         if (!valid_vl(i))
11080                                 continue;
11081
11082                         if (lowering_dedicated[i]) {
11083                                 set_vl_dedicated(dd, i,
11084                                                  be16_to_cpu(new_bc->
11085                                                              vl[i].dedicated));
11086                                 cur_bc.vl[i].dedicated =
11087                                                 new_bc->vl[i].dedicated;
11088                         }
11089                 }
11090
11091                 wait_for_vl_status_clear(dd, ld_mask, "dedicated");
11092
11093                 /* now raise all dedicated that are going up */
11094                 for (i = 0; i < NUM_USABLE_VLS; i++) {
11095                         if (!valid_vl(i))
11096                                 continue;
11097
11098                         if (be16_to_cpu(new_bc->vl[i].dedicated) >
11099                                         be16_to_cpu(cur_bc.vl[i].dedicated))
11100                                 set_vl_dedicated(dd, i,
11101                                                  be16_to_cpu(new_bc->
11102                                                              vl[i].dedicated));
11103                 }
11104         }
11105
11106         /* next raise all shared that are going up */
11107         for (i = 0; i < NUM_USABLE_VLS; i++) {
11108                 if (!valid_vl(i))
11109                         continue;
11110
11111                 if (be16_to_cpu(new_bc->vl[i].shared) >
11112                                 be16_to_cpu(cur_bc.vl[i].shared))
11113                         set_vl_shared(dd, i, be16_to_cpu(new_bc->vl[i].shared));
11114         }
11115
11116         /* finally raise the global shared */
11117         if (be16_to_cpu(new_bc->overall_shared_limit) >
11118             be16_to_cpu(cur_bc.overall_shared_limit))
11119                 set_global_shared(dd,
11120                                   be16_to_cpu(new_bc->overall_shared_limit));
11121
11122         /* bracket the credit change with a total adjustment */
11123         if (new_total < cur_total)
11124                 set_global_limit(dd, new_total);
11125
11126         /*
11127          * Determine the actual number of operational VLS using the number of
11128          * dedicated and shared credits for each VL.
11129          */
11130         if (change_count > 0) {
11131                 for (i = 0; i < TXE_NUM_DATA_VL; i++)
11132                         if (be16_to_cpu(new_bc->vl[i].dedicated) > 0 ||
11133                             be16_to_cpu(new_bc->vl[i].shared) > 0)
11134                                 vl_count++;
11135                 ppd->actual_vls_operational = vl_count;
11136                 ret = sdma_map_init(dd, ppd->port - 1, vl_count ?
11137                                     ppd->actual_vls_operational :
11138                                     ppd->vls_operational,
11139                                     NULL);
11140                 if (ret == 0)
11141                         ret = pio_map_init(dd, ppd->port - 1, vl_count ?
11142                                            ppd->actual_vls_operational :
11143                                            ppd->vls_operational, NULL);
11144                 if (ret)
11145                         return ret;
11146         }
11147         return 0;
11148 }
11149
11150 /*
11151  * Read the given fabric manager table. Return the size of the
11152  * table (in bytes) on success, and a negative error code on
11153  * failure.
11154  */
11155 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t)
11156
11157 {
11158         int size;
11159         struct vl_arb_cache *vlc;
11160
11161         switch (which) {
11162         case FM_TBL_VL_HIGH_ARB:
11163                 size = 256;
11164                 /*
11165                  * OPA specifies 128 elements (of 2 bytes each), though
11166                  * HFI supports only 16 elements in h/w.
11167                  */
11168                 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
11169                 vl_arb_get_cache(vlc, t);
11170                 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11171                 break;
11172         case FM_TBL_VL_LOW_ARB:
11173                 size = 256;
11174                 /*
11175                  * OPA specifies 128 elements (of 2 bytes each), though
11176                  * HFI supports only 16 elements in h/w.
11177                  */
11178                 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
11179                 vl_arb_get_cache(vlc, t);
11180                 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11181                 break;
11182         case FM_TBL_BUFFER_CONTROL:
11183                 size = get_buffer_control(ppd->dd, t, NULL);
11184                 break;
11185         case FM_TBL_SC2VLNT:
11186                 size = get_sc2vlnt(ppd->dd, t);
11187                 break;
11188         case FM_TBL_VL_PREEMPT_ELEMS:
11189                 size = 256;
11190                 /* OPA specifies 128 elements, of 2 bytes each */
11191                 get_vlarb_preempt(ppd->dd, OPA_MAX_VLS, t);
11192                 break;
11193         case FM_TBL_VL_PREEMPT_MATRIX:
11194                 size = 256;
11195                 /*
11196                  * OPA specifies that this is the same size as the VL
11197                  * arbitration tables (i.e., 256 bytes).
11198                  */
11199                 break;
11200         default:
11201                 return -EINVAL;
11202         }
11203         return size;
11204 }
11205
11206 /*
11207  * Write the given fabric manager table.
11208  */
11209 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t)
11210 {
11211         int ret = 0;
11212         struct vl_arb_cache *vlc;
11213
11214         switch (which) {
11215         case FM_TBL_VL_HIGH_ARB:
11216                 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
11217                 if (vl_arb_match_cache(vlc, t)) {
11218                         vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11219                         break;
11220                 }
11221                 vl_arb_set_cache(vlc, t);
11222                 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11223                 ret = set_vl_weights(ppd, SEND_HIGH_PRIORITY_LIST,
11224                                      VL_ARB_HIGH_PRIO_TABLE_SIZE, t);
11225                 break;
11226         case FM_TBL_VL_LOW_ARB:
11227                 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
11228                 if (vl_arb_match_cache(vlc, t)) {
11229                         vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11230                         break;
11231                 }
11232                 vl_arb_set_cache(vlc, t);
11233                 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11234                 ret = set_vl_weights(ppd, SEND_LOW_PRIORITY_LIST,
11235                                      VL_ARB_LOW_PRIO_TABLE_SIZE, t);
11236                 break;
11237         case FM_TBL_BUFFER_CONTROL:
11238                 ret = set_buffer_control(ppd, t);
11239                 break;
11240         case FM_TBL_SC2VLNT:
11241                 set_sc2vlnt(ppd->dd, t);
11242                 break;
11243         default:
11244                 ret = -EINVAL;
11245         }
11246         return ret;
11247 }
11248
11249 /*
11250  * Disable all data VLs.
11251  *
11252  * Return 0 if disabled, non-zero if the VLs cannot be disabled.
11253  */
11254 static int disable_data_vls(struct hfi1_devdata *dd)
11255 {
11256         if (is_ax(dd))
11257                 return 1;
11258
11259         pio_send_control(dd, PSC_DATA_VL_DISABLE);
11260
11261         return 0;
11262 }
11263
11264 /*
11265  * open_fill_data_vls() - the counterpart to stop_drain_data_vls().
11266  * Just re-enables all data VLs (the "fill" part happens
11267  * automatically - the name was chosen for symmetry with
11268  * stop_drain_data_vls()).
11269  *
11270  * Return 0 if successful, non-zero if the VLs cannot be enabled.
11271  */
11272 int open_fill_data_vls(struct hfi1_devdata *dd)
11273 {
11274         if (is_ax(dd))
11275                 return 1;
11276
11277         pio_send_control(dd, PSC_DATA_VL_ENABLE);
11278
11279         return 0;
11280 }
11281
11282 /*
11283  * drain_data_vls() - assumes that disable_data_vls() has been called,
11284  * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA
11285  * engines to drop to 0.
11286  */
11287 static void drain_data_vls(struct hfi1_devdata *dd)
11288 {
11289         sc_wait(dd);
11290         sdma_wait(dd);
11291         pause_for_credit_return(dd);
11292 }
11293
11294 /*
11295  * stop_drain_data_vls() - disable, then drain all per-VL fifos.
11296  *
11297  * Use open_fill_data_vls() to resume using data VLs.  This pair is
11298  * meant to be used like this:
11299  *
11300  * stop_drain_data_vls(dd);
11301  * // do things with per-VL resources
11302  * open_fill_data_vls(dd);
11303  */
11304 int stop_drain_data_vls(struct hfi1_devdata *dd)
11305 {
11306         int ret;
11307
11308         ret = disable_data_vls(dd);
11309         if (ret == 0)
11310                 drain_data_vls(dd);
11311
11312         return ret;
11313 }
11314
11315 /*
11316  * Convert a nanosecond time to a cclock count.  No matter how slow
11317  * the cclock, a non-zero ns will always have a non-zero result.
11318  */
11319 u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns)
11320 {
11321         u32 cclocks;
11322
11323         if (dd->icode == ICODE_FPGA_EMULATION)
11324                 cclocks = (ns * 1000) / FPGA_CCLOCK_PS;
11325         else  /* simulation pretends to be ASIC */
11326                 cclocks = (ns * 1000) / ASIC_CCLOCK_PS;
11327         if (ns && !cclocks)     /* if ns nonzero, must be at least 1 */
11328                 cclocks = 1;
11329         return cclocks;
11330 }
11331
11332 /*
11333  * Convert a cclock count to nanoseconds. Not matter how slow
11334  * the cclock, a non-zero cclocks will always have a non-zero result.
11335  */
11336 u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclocks)
11337 {
11338         u32 ns;
11339
11340         if (dd->icode == ICODE_FPGA_EMULATION)
11341                 ns = (cclocks * FPGA_CCLOCK_PS) / 1000;
11342         else  /* simulation pretends to be ASIC */
11343                 ns = (cclocks * ASIC_CCLOCK_PS) / 1000;
11344         if (cclocks && !ns)
11345                 ns = 1;
11346         return ns;
11347 }
11348
11349 /*
11350  * Dynamically adjust the receive interrupt timeout for a context based on
11351  * incoming packet rate.
11352  *
11353  * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero.
11354  */
11355 static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts)
11356 {
11357         struct hfi1_devdata *dd = rcd->dd;
11358         u32 timeout = rcd->rcvavail_timeout;
11359
11360         /*
11361          * This algorithm doubles or halves the timeout depending on whether
11362          * the number of packets received in this interrupt were less than or
11363          * greater equal the interrupt count.
11364          *
11365          * The calculations below do not allow a steady state to be achieved.
11366          * Only at the endpoints it is possible to have an unchanging
11367          * timeout.
11368          */
11369         if (npkts < rcv_intr_count) {
11370                 /*
11371                  * Not enough packets arrived before the timeout, adjust
11372                  * timeout downward.
11373                  */
11374                 if (timeout < 2) /* already at minimum? */
11375                         return;
11376                 timeout >>= 1;
11377         } else {
11378                 /*
11379                  * More than enough packets arrived before the timeout, adjust
11380                  * timeout upward.
11381                  */
11382                 if (timeout >= dd->rcv_intr_timeout_csr) /* already at max? */
11383                         return;
11384                 timeout = min(timeout << 1, dd->rcv_intr_timeout_csr);
11385         }
11386
11387         rcd->rcvavail_timeout = timeout;
11388         /*
11389          * timeout cannot be larger than rcv_intr_timeout_csr which has already
11390          * been verified to be in range
11391          */
11392         write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT,
11393                         (u64)timeout <<
11394                         RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11395 }
11396
11397 void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd,
11398                     u32 intr_adjust, u32 npkts)
11399 {
11400         struct hfi1_devdata *dd = rcd->dd;
11401         u64 reg;
11402         u32 ctxt = rcd->ctxt;
11403
11404         /*
11405          * Need to write timeout register before updating RcvHdrHead to ensure
11406          * that a new value is used when the HW decides to restart counting.
11407          */
11408         if (intr_adjust)
11409                 adjust_rcv_timeout(rcd, npkts);
11410         if (updegr) {
11411                 reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK)
11412                         << RCV_EGR_INDEX_HEAD_HEAD_SHIFT;
11413                 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg);
11414         }
11415         mmiowb();
11416         reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) |
11417                 (((u64)hd & RCV_HDR_HEAD_HEAD_MASK)
11418                         << RCV_HDR_HEAD_HEAD_SHIFT);
11419         write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11420         mmiowb();
11421 }
11422
11423 u32 hdrqempty(struct hfi1_ctxtdata *rcd)
11424 {
11425         u32 head, tail;
11426
11427         head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD)
11428                 & RCV_HDR_HEAD_HEAD_SMASK) >> RCV_HDR_HEAD_HEAD_SHIFT;
11429
11430         if (rcd->rcvhdrtail_kvaddr)
11431                 tail = get_rcvhdrtail(rcd);
11432         else
11433                 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
11434
11435         return head == tail;
11436 }
11437
11438 /*
11439  * Context Control and Receive Array encoding for buffer size:
11440  *      0x0 invalid
11441  *      0x1   4 KB
11442  *      0x2   8 KB
11443  *      0x3  16 KB
11444  *      0x4  32 KB
11445  *      0x5  64 KB
11446  *      0x6 128 KB
11447  *      0x7 256 KB
11448  *      0x8 512 KB (Receive Array only)
11449  *      0x9   1 MB (Receive Array only)
11450  *      0xa   2 MB (Receive Array only)
11451  *
11452  *      0xB-0xF - reserved (Receive Array only)
11453  *
11454  *
11455  * This routine assumes that the value has already been sanity checked.
11456  */
11457 static u32 encoded_size(u32 size)
11458 {
11459         switch (size) {
11460         case   4 * 1024: return 0x1;
11461         case   8 * 1024: return 0x2;
11462         case  16 * 1024: return 0x3;
11463         case  32 * 1024: return 0x4;
11464         case  64 * 1024: return 0x5;
11465         case 128 * 1024: return 0x6;
11466         case 256 * 1024: return 0x7;
11467         case 512 * 1024: return 0x8;
11468         case   1 * 1024 * 1024: return 0x9;
11469         case   2 * 1024 * 1024: return 0xa;
11470         }
11471         return 0x1;     /* if invalid, go with the minimum size */
11472 }
11473
11474 void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, int ctxt)
11475 {
11476         struct hfi1_ctxtdata *rcd;
11477         u64 rcvctrl, reg;
11478         int did_enable = 0;
11479
11480         rcd = dd->rcd[ctxt];
11481         if (!rcd)
11482                 return;
11483
11484         hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op);
11485
11486         rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL);
11487         /* if the context already enabled, don't do the extra steps */
11488         if ((op & HFI1_RCVCTRL_CTXT_ENB) &&
11489             !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) {
11490                 /* reset the tail and hdr addresses, and sequence count */
11491                 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR,
11492                                 rcd->rcvhdrq_phys);
11493                 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL))
11494                         write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11495                                         rcd->rcvhdrqtailaddr_phys);
11496                 rcd->seq_cnt = 1;
11497
11498                 /* reset the cached receive header queue head value */
11499                 rcd->head = 0;
11500
11501                 /*
11502                  * Zero the receive header queue so we don't get false
11503                  * positives when checking the sequence number.  The
11504                  * sequence numbers could land exactly on the same spot.
11505                  * E.g. a rcd restart before the receive header wrapped.
11506                  */
11507                 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size);
11508
11509                 /* starting timeout */
11510                 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr;
11511
11512                 /* enable the context */
11513                 rcvctrl |= RCV_CTXT_CTRL_ENABLE_SMASK;
11514
11515                 /* clean the egr buffer size first */
11516                 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11517                 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size)
11518                                 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK)
11519                                         << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT;
11520
11521                 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
11522                 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0);
11523                 did_enable = 1;
11524
11525                 /* zero RcvEgrIndexHead */
11526                 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0);
11527
11528                 /* set eager count and base index */
11529                 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT)
11530                         & RCV_EGR_CTRL_EGR_CNT_MASK)
11531                        << RCV_EGR_CTRL_EGR_CNT_SHIFT) |
11532                         (((rcd->eager_base >> RCV_SHIFT)
11533                           & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK)
11534                          << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT);
11535                 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg);
11536
11537                 /*
11538                  * Set TID (expected) count and base index.
11539                  * rcd->expected_count is set to individual RcvArray entries,
11540                  * not pairs, and the CSR takes a pair-count in groups of
11541                  * four, so divide by 8.
11542                  */
11543                 reg = (((rcd->expected_count >> RCV_SHIFT)
11544                                         & RCV_TID_CTRL_TID_PAIR_CNT_MASK)
11545                                 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT) |
11546                       (((rcd->expected_base >> RCV_SHIFT)
11547                                         & RCV_TID_CTRL_TID_BASE_INDEX_MASK)
11548                                 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT);
11549                 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg);
11550                 if (ctxt == HFI1_CTRL_CTXT)
11551                         write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT);
11552         }
11553         if (op & HFI1_RCVCTRL_CTXT_DIS) {
11554                 write_csr(dd, RCV_VL15, 0);
11555                 /*
11556                  * When receive context is being disabled turn on tail
11557                  * update with a dummy tail address and then disable
11558                  * receive context.
11559                  */
11560                 if (dd->rcvhdrtail_dummy_physaddr) {
11561                         write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11562                                         dd->rcvhdrtail_dummy_physaddr);
11563                         /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
11564                         rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11565                 }
11566
11567                 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK;
11568         }
11569         if (op & HFI1_RCVCTRL_INTRAVAIL_ENB)
11570                 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11571         if (op & HFI1_RCVCTRL_INTRAVAIL_DIS)
11572                 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11573         if (op & HFI1_RCVCTRL_TAILUPD_ENB && rcd->rcvhdrqtailaddr_phys)
11574                 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11575         if (op & HFI1_RCVCTRL_TAILUPD_DIS) {
11576                 /* See comment on RcvCtxtCtrl.TailUpd above */
11577                 if (!(op & HFI1_RCVCTRL_CTXT_DIS))
11578                         rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11579         }
11580         if (op & HFI1_RCVCTRL_TIDFLOW_ENB)
11581                 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11582         if (op & HFI1_RCVCTRL_TIDFLOW_DIS)
11583                 rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11584         if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) {
11585                 /*
11586                  * In one-packet-per-eager mode, the size comes from
11587                  * the RcvArray entry.
11588                  */
11589                 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11590                 rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11591         }
11592         if (op & HFI1_RCVCTRL_ONE_PKT_EGR_DIS)
11593                 rcvctrl &= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11594         if (op & HFI1_RCVCTRL_NO_RHQ_DROP_ENB)
11595                 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11596         if (op & HFI1_RCVCTRL_NO_RHQ_DROP_DIS)
11597                 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11598         if (op & HFI1_RCVCTRL_NO_EGR_DROP_ENB)
11599                 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11600         if (op & HFI1_RCVCTRL_NO_EGR_DROP_DIS)
11601                 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11602         rcd->rcvctrl = rcvctrl;
11603         hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl);
11604         write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcd->rcvctrl);
11605
11606         /* work around sticky RcvCtxtStatus.BlockedRHQFull */
11607         if (did_enable &&
11608             (rcvctrl & RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK)) {
11609                 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11610                 if (reg != 0) {
11611                         dd_dev_info(dd, "ctxt %d status %lld (blocked)\n",
11612                                     ctxt, reg);
11613                         read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11614                         write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10);
11615                         write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00);
11616                         read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11617                         reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11618                         dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n",
11619                                     ctxt, reg, reg == 0 ? "not" : "still");
11620                 }
11621         }
11622
11623         if (did_enable) {
11624                 /*
11625                  * The interrupt timeout and count must be set after
11626                  * the context is enabled to take effect.
11627                  */
11628                 /* set interrupt timeout */
11629                 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT,
11630                                 (u64)rcd->rcvavail_timeout <<
11631                                 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11632
11633                 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
11634                 reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT;
11635                 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11636         }
11637
11638         if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS))
11639                 /*
11640                  * If the context has been disabled and the Tail Update has
11641                  * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
11642                  * so it doesn't contain an address that is invalid.
11643                  */
11644                 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11645                                 dd->rcvhdrtail_dummy_physaddr);
11646 }
11647
11648 u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp)
11649 {
11650         int ret;
11651         u64 val = 0;
11652
11653         if (namep) {
11654                 ret = dd->cntrnameslen;
11655                 *namep = dd->cntrnames;
11656         } else {
11657                 const struct cntr_entry *entry;
11658                 int i, j;
11659
11660                 ret = (dd->ndevcntrs) * sizeof(u64);
11661
11662                 /* Get the start of the block of counters */
11663                 *cntrp = dd->cntrs;
11664
11665                 /*
11666                  * Now go and fill in each counter in the block.
11667                  */
11668                 for (i = 0; i < DEV_CNTR_LAST; i++) {
11669                         entry = &dev_cntrs[i];
11670                         hfi1_cdbg(CNTR, "reading %s", entry->name);
11671                         if (entry->flags & CNTR_DISABLED) {
11672                                 /* Nothing */
11673                                 hfi1_cdbg(CNTR, "\tDisabled\n");
11674                         } else {
11675                                 if (entry->flags & CNTR_VL) {
11676                                         hfi1_cdbg(CNTR, "\tPer VL\n");
11677                                         for (j = 0; j < C_VL_COUNT; j++) {
11678                                                 val = entry->rw_cntr(entry,
11679                                                                   dd, j,
11680                                                                   CNTR_MODE_R,
11681                                                                   0);
11682                                                 hfi1_cdbg(
11683                                                    CNTR,
11684                                                    "\t\tRead 0x%llx for %d\n",
11685                                                    val, j);
11686                                                 dd->cntrs[entry->offset + j] =
11687                                                                             val;
11688                                         }
11689                                 } else if (entry->flags & CNTR_SDMA) {
11690                                         hfi1_cdbg(CNTR,
11691                                                   "\t Per SDMA Engine\n");
11692                                         for (j = 0; j < dd->chip_sdma_engines;
11693                                              j++) {
11694                                                 val =
11695                                                 entry->rw_cntr(entry, dd, j,
11696                                                                CNTR_MODE_R, 0);
11697                                                 hfi1_cdbg(CNTR,
11698                                                           "\t\tRead 0x%llx for %d\n",
11699                                                           val, j);
11700                                                 dd->cntrs[entry->offset + j] =
11701                                                                         val;
11702                                         }
11703                                 } else {
11704                                         val = entry->rw_cntr(entry, dd,
11705                                                         CNTR_INVALID_VL,
11706                                                         CNTR_MODE_R, 0);
11707                                         dd->cntrs[entry->offset] = val;
11708                                         hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11709                                 }
11710                         }
11711                 }
11712         }
11713         return ret;
11714 }
11715
11716 /*
11717  * Used by sysfs to create files for hfi stats to read
11718  */
11719 u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp)
11720 {
11721         int ret;
11722         u64 val = 0;
11723
11724         if (namep) {
11725                 ret = ppd->dd->portcntrnameslen;
11726                 *namep = ppd->dd->portcntrnames;
11727         } else {
11728                 const struct cntr_entry *entry;
11729                 int i, j;
11730
11731                 ret = ppd->dd->nportcntrs * sizeof(u64);
11732                 *cntrp = ppd->cntrs;
11733
11734                 for (i = 0; i < PORT_CNTR_LAST; i++) {
11735                         entry = &port_cntrs[i];
11736                         hfi1_cdbg(CNTR, "reading %s", entry->name);
11737                         if (entry->flags & CNTR_DISABLED) {
11738                                 /* Nothing */
11739                                 hfi1_cdbg(CNTR, "\tDisabled\n");
11740                                 continue;
11741                         }
11742
11743                         if (entry->flags & CNTR_VL) {
11744                                 hfi1_cdbg(CNTR, "\tPer VL");
11745                                 for (j = 0; j < C_VL_COUNT; j++) {
11746                                         val = entry->rw_cntr(entry, ppd, j,
11747                                                                CNTR_MODE_R,
11748                                                                0);
11749                                         hfi1_cdbg(
11750                                            CNTR,
11751                                            "\t\tRead 0x%llx for %d",
11752                                            val, j);
11753                                         ppd->cntrs[entry->offset + j] = val;
11754                                 }
11755                         } else {
11756                                 val = entry->rw_cntr(entry, ppd,
11757                                                        CNTR_INVALID_VL,
11758                                                        CNTR_MODE_R,
11759                                                        0);
11760                                 ppd->cntrs[entry->offset] = val;
11761                                 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11762                         }
11763                 }
11764         }
11765         return ret;
11766 }
11767
11768 static void free_cntrs(struct hfi1_devdata *dd)
11769 {
11770         struct hfi1_pportdata *ppd;
11771         int i;
11772
11773         if (dd->synth_stats_timer.data)
11774                 del_timer_sync(&dd->synth_stats_timer);
11775         dd->synth_stats_timer.data = 0;
11776         ppd = (struct hfi1_pportdata *)(dd + 1);
11777         for (i = 0; i < dd->num_pports; i++, ppd++) {
11778                 kfree(ppd->cntrs);
11779                 kfree(ppd->scntrs);
11780                 free_percpu(ppd->ibport_data.rvp.rc_acks);
11781                 free_percpu(ppd->ibport_data.rvp.rc_qacks);
11782                 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp);
11783                 ppd->cntrs = NULL;
11784                 ppd->scntrs = NULL;
11785                 ppd->ibport_data.rvp.rc_acks = NULL;
11786                 ppd->ibport_data.rvp.rc_qacks = NULL;
11787                 ppd->ibport_data.rvp.rc_delayed_comp = NULL;
11788         }
11789         kfree(dd->portcntrnames);
11790         dd->portcntrnames = NULL;
11791         kfree(dd->cntrs);
11792         dd->cntrs = NULL;
11793         kfree(dd->scntrs);
11794         dd->scntrs = NULL;
11795         kfree(dd->cntrnames);
11796         dd->cntrnames = NULL;
11797 }
11798
11799 static u64 read_dev_port_cntr(struct hfi1_devdata *dd, struct cntr_entry *entry,
11800                               u64 *psval, void *context, int vl)
11801 {
11802         u64 val;
11803         u64 sval = *psval;
11804
11805         if (entry->flags & CNTR_DISABLED) {
11806                 dd_dev_err(dd, "Counter %s not enabled", entry->name);
11807                 return 0;
11808         }
11809
11810         hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
11811
11812         val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0);
11813
11814         /* If its a synthetic counter there is more work we need to do */
11815         if (entry->flags & CNTR_SYNTH) {
11816                 if (sval == CNTR_MAX) {
11817                         /* No need to read already saturated */
11818                         return CNTR_MAX;
11819                 }
11820
11821                 if (entry->flags & CNTR_32BIT) {
11822                         /* 32bit counters can wrap multiple times */
11823                         u64 upper = sval >> 32;
11824                         u64 lower = (sval << 32) >> 32;
11825
11826                         if (lower > val) { /* hw wrapped */
11827                                 if (upper == CNTR_32BIT_MAX)
11828                                         val = CNTR_MAX;
11829                                 else
11830                                         upper++;
11831                         }
11832
11833                         if (val != CNTR_MAX)
11834                                 val = (upper << 32) | val;
11835
11836                 } else {
11837                         /* If we rolled we are saturated */
11838                         if ((val < sval) || (val > CNTR_MAX))
11839                                 val = CNTR_MAX;
11840                 }
11841         }
11842
11843         *psval = val;
11844
11845         hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
11846
11847         return val;
11848 }
11849
11850 static u64 write_dev_port_cntr(struct hfi1_devdata *dd,
11851                                struct cntr_entry *entry,
11852                                u64 *psval, void *context, int vl, u64 data)
11853 {
11854         u64 val;
11855
11856         if (entry->flags & CNTR_DISABLED) {
11857                 dd_dev_err(dd, "Counter %s not enabled", entry->name);
11858                 return 0;
11859         }
11860
11861         hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
11862
11863         if (entry->flags & CNTR_SYNTH) {
11864                 *psval = data;
11865                 if (entry->flags & CNTR_32BIT) {
11866                         val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
11867                                              (data << 32) >> 32);
11868                         val = data; /* return the full 64bit value */
11869                 } else {
11870                         val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
11871                                              data);
11872                 }
11873         } else {
11874                 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data);
11875         }
11876
11877         *psval = val;
11878
11879         hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
11880
11881         return val;
11882 }
11883
11884 u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl)
11885 {
11886         struct cntr_entry *entry;
11887         u64 *sval;
11888
11889         entry = &dev_cntrs[index];
11890         sval = dd->scntrs + entry->offset;
11891
11892         if (vl != CNTR_INVALID_VL)
11893                 sval += vl;
11894
11895         return read_dev_port_cntr(dd, entry, sval, dd, vl);
11896 }
11897
11898 u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data)
11899 {
11900         struct cntr_entry *entry;
11901         u64 *sval;
11902
11903         entry = &dev_cntrs[index];
11904         sval = dd->scntrs + entry->offset;
11905
11906         if (vl != CNTR_INVALID_VL)
11907                 sval += vl;
11908
11909         return write_dev_port_cntr(dd, entry, sval, dd, vl, data);
11910 }
11911
11912 u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl)
11913 {
11914         struct cntr_entry *entry;
11915         u64 *sval;
11916
11917         entry = &port_cntrs[index];
11918         sval = ppd->scntrs + entry->offset;
11919
11920         if (vl != CNTR_INVALID_VL)
11921                 sval += vl;
11922
11923         if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
11924             (index <= C_RCV_HDR_OVF_LAST)) {
11925                 /* We do not want to bother for disabled contexts */
11926                 return 0;
11927         }
11928
11929         return read_dev_port_cntr(ppd->dd, entry, sval, ppd, vl);
11930 }
11931
11932 u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data)
11933 {
11934         struct cntr_entry *entry;
11935         u64 *sval;
11936
11937         entry = &port_cntrs[index];
11938         sval = ppd->scntrs + entry->offset;
11939
11940         if (vl != CNTR_INVALID_VL)
11941                 sval += vl;
11942
11943         if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
11944             (index <= C_RCV_HDR_OVF_LAST)) {
11945                 /* We do not want to bother for disabled contexts */
11946                 return 0;
11947         }
11948
11949         return write_dev_port_cntr(ppd->dd, entry, sval, ppd, vl, data);
11950 }
11951
11952 static void update_synth_timer(unsigned long opaque)
11953 {
11954         u64 cur_tx;
11955         u64 cur_rx;
11956         u64 total_flits;
11957         u8 update = 0;
11958         int i, j, vl;
11959         struct hfi1_pportdata *ppd;
11960         struct cntr_entry *entry;
11961
11962         struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
11963
11964         /*
11965          * Rather than keep beating on the CSRs pick a minimal set that we can
11966          * check to watch for potential roll over. We can do this by looking at
11967          * the number of flits sent/recv. If the total flits exceeds 32bits then
11968          * we have to iterate all the counters and update.
11969          */
11970         entry = &dev_cntrs[C_DC_RCV_FLITS];
11971         cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
11972
11973         entry = &dev_cntrs[C_DC_XMIT_FLITS];
11974         cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
11975
11976         hfi1_cdbg(
11977             CNTR,
11978             "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n",
11979             dd->unit, cur_tx, cur_rx, dd->last_tx, dd->last_rx);
11980
11981         if ((cur_tx < dd->last_tx) || (cur_rx < dd->last_rx)) {
11982                 /*
11983                  * May not be strictly necessary to update but it won't hurt and
11984                  * simplifies the logic here.
11985                  */
11986                 update = 1;
11987                 hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating",
11988                           dd->unit);
11989         } else {
11990                 total_flits = (cur_tx - dd->last_tx) + (cur_rx - dd->last_rx);
11991                 hfi1_cdbg(CNTR,
11992                           "[%d] total flits 0x%llx limit 0x%llx\n", dd->unit,
11993                           total_flits, (u64)CNTR_32BIT_MAX);
11994                 if (total_flits >= CNTR_32BIT_MAX) {
11995                         hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating",
11996                                   dd->unit);
11997                         update = 1;
11998                 }
11999         }
12000
12001         if (update) {
12002                 hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit);
12003                 for (i = 0; i < DEV_CNTR_LAST; i++) {
12004                         entry = &dev_cntrs[i];
12005                         if (entry->flags & CNTR_VL) {
12006                                 for (vl = 0; vl < C_VL_COUNT; vl++)
12007                                         read_dev_cntr(dd, i, vl);
12008                         } else {
12009                                 read_dev_cntr(dd, i, CNTR_INVALID_VL);
12010                         }
12011                 }
12012                 ppd = (struct hfi1_pportdata *)(dd + 1);
12013                 for (i = 0; i < dd->num_pports; i++, ppd++) {
12014                         for (j = 0; j < PORT_CNTR_LAST; j++) {
12015                                 entry = &port_cntrs[j];
12016                                 if (entry->flags & CNTR_VL) {
12017                                         for (vl = 0; vl < C_VL_COUNT; vl++)
12018                                                 read_port_cntr(ppd, j, vl);
12019                                 } else {
12020                                         read_port_cntr(ppd, j, CNTR_INVALID_VL);
12021                                 }
12022                         }
12023                 }
12024
12025                 /*
12026                  * We want the value in the register. The goal is to keep track
12027                  * of the number of "ticks" not the counter value. In other
12028                  * words if the register rolls we want to notice it and go ahead
12029                  * and force an update.
12030                  */
12031                 entry = &dev_cntrs[C_DC_XMIT_FLITS];
12032                 dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
12033                                                 CNTR_MODE_R, 0);
12034
12035                 entry = &dev_cntrs[C_DC_RCV_FLITS];
12036                 dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
12037                                                 CNTR_MODE_R, 0);
12038
12039                 hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx",
12040                           dd->unit, dd->last_tx, dd->last_rx);
12041
12042         } else {
12043                 hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit);
12044         }
12045
12046         mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
12047 }
12048
12049 #define C_MAX_NAME 13 /* 12 chars + one for /0 */
12050 static int init_cntrs(struct hfi1_devdata *dd)
12051 {
12052         int i, rcv_ctxts, j;
12053         size_t sz;
12054         char *p;
12055         char name[C_MAX_NAME];
12056         struct hfi1_pportdata *ppd;
12057         const char *bit_type_32 = ",32";
12058         const int bit_type_32_sz = strlen(bit_type_32);
12059
12060         /* set up the stats timer; the add_timer is done at the end */
12061         setup_timer(&dd->synth_stats_timer, update_synth_timer,
12062                     (unsigned long)dd);
12063
12064         /***********************/
12065         /* per device counters */
12066         /***********************/
12067
12068         /* size names and determine how many we have*/
12069         dd->ndevcntrs = 0;
12070         sz = 0;
12071
12072         for (i = 0; i < DEV_CNTR_LAST; i++) {
12073                 if (dev_cntrs[i].flags & CNTR_DISABLED) {
12074                         hfi1_dbg_early("\tSkipping %s\n", dev_cntrs[i].name);
12075                         continue;
12076                 }
12077
12078                 if (dev_cntrs[i].flags & CNTR_VL) {
12079                         dev_cntrs[i].offset = dd->ndevcntrs;
12080                         for (j = 0; j < C_VL_COUNT; j++) {
12081                                 snprintf(name, C_MAX_NAME, "%s%d",
12082                                          dev_cntrs[i].name, vl_from_idx(j));
12083                                 sz += strlen(name);
12084                                 /* Add ",32" for 32-bit counters */
12085                                 if (dev_cntrs[i].flags & CNTR_32BIT)
12086                                         sz += bit_type_32_sz;
12087                                 sz++;
12088                                 dd->ndevcntrs++;
12089                         }
12090                 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
12091                         dev_cntrs[i].offset = dd->ndevcntrs;
12092                         for (j = 0; j < dd->chip_sdma_engines; j++) {
12093                                 snprintf(name, C_MAX_NAME, "%s%d",
12094                                          dev_cntrs[i].name, j);
12095                                 sz += strlen(name);
12096                                 /* Add ",32" for 32-bit counters */
12097                                 if (dev_cntrs[i].flags & CNTR_32BIT)
12098                                         sz += bit_type_32_sz;
12099                                 sz++;
12100                                 dd->ndevcntrs++;
12101                         }
12102                 } else {
12103                         /* +1 for newline. */
12104                         sz += strlen(dev_cntrs[i].name) + 1;
12105                         /* Add ",32" for 32-bit counters */
12106                         if (dev_cntrs[i].flags & CNTR_32BIT)
12107                                 sz += bit_type_32_sz;
12108                         dev_cntrs[i].offset = dd->ndevcntrs;
12109                         dd->ndevcntrs++;
12110                 }
12111         }
12112
12113         /* allocate space for the counter values */
12114         dd->cntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
12115         if (!dd->cntrs)
12116                 goto bail;
12117
12118         dd->scntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
12119         if (!dd->scntrs)
12120                 goto bail;
12121
12122         /* allocate space for the counter names */
12123         dd->cntrnameslen = sz;
12124         dd->cntrnames = kmalloc(sz, GFP_KERNEL);
12125         if (!dd->cntrnames)
12126                 goto bail;
12127
12128         /* fill in the names */
12129         for (p = dd->cntrnames, i = 0; i < DEV_CNTR_LAST; i++) {
12130                 if (dev_cntrs[i].flags & CNTR_DISABLED) {
12131                         /* Nothing */
12132                 } else if (dev_cntrs[i].flags & CNTR_VL) {
12133                         for (j = 0; j < C_VL_COUNT; j++) {
12134                                 snprintf(name, C_MAX_NAME, "%s%d",
12135                                          dev_cntrs[i].name,
12136                                          vl_from_idx(j));
12137                                 memcpy(p, name, strlen(name));
12138                                 p += strlen(name);
12139
12140                                 /* Counter is 32 bits */
12141                                 if (dev_cntrs[i].flags & CNTR_32BIT) {
12142                                         memcpy(p, bit_type_32, bit_type_32_sz);
12143                                         p += bit_type_32_sz;
12144                                 }
12145
12146                                 *p++ = '\n';
12147                         }
12148                 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
12149                         for (j = 0; j < dd->chip_sdma_engines; j++) {
12150                                 snprintf(name, C_MAX_NAME, "%s%d",
12151                                          dev_cntrs[i].name, j);
12152                                 memcpy(p, name, strlen(name));
12153                                 p += strlen(name);
12154
12155                                 /* Counter is 32 bits */
12156                                 if (dev_cntrs[i].flags & CNTR_32BIT) {
12157                                         memcpy(p, bit_type_32, bit_type_32_sz);
12158                                         p += bit_type_32_sz;
12159                                 }
12160
12161                                 *p++ = '\n';
12162                         }
12163                 } else {
12164                         memcpy(p, dev_cntrs[i].name, strlen(dev_cntrs[i].name));
12165                         p += strlen(dev_cntrs[i].name);
12166
12167                         /* Counter is 32 bits */
12168                         if (dev_cntrs[i].flags & CNTR_32BIT) {
12169                                 memcpy(p, bit_type_32, bit_type_32_sz);
12170                                 p += bit_type_32_sz;
12171                         }
12172
12173                         *p++ = '\n';
12174                 }
12175         }
12176
12177         /*********************/
12178         /* per port counters */
12179         /*********************/
12180
12181         /*
12182          * Go through the counters for the overflows and disable the ones we
12183          * don't need. This varies based on platform so we need to do it
12184          * dynamically here.
12185          */
12186         rcv_ctxts = dd->num_rcv_contexts;
12187         for (i = C_RCV_HDR_OVF_FIRST + rcv_ctxts;
12188              i <= C_RCV_HDR_OVF_LAST; i++) {
12189                 port_cntrs[i].flags |= CNTR_DISABLED;
12190         }
12191
12192         /* size port counter names and determine how many we have*/
12193         sz = 0;
12194         dd->nportcntrs = 0;
12195         for (i = 0; i < PORT_CNTR_LAST; i++) {
12196                 if (port_cntrs[i].flags & CNTR_DISABLED) {
12197                         hfi1_dbg_early("\tSkipping %s\n", port_cntrs[i].name);
12198                         continue;
12199                 }
12200
12201                 if (port_cntrs[i].flags & CNTR_VL) {
12202                         port_cntrs[i].offset = dd->nportcntrs;
12203                         for (j = 0; j < C_VL_COUNT; j++) {
12204                                 snprintf(name, C_MAX_NAME, "%s%d",
12205                                          port_cntrs[i].name, vl_from_idx(j));
12206                                 sz += strlen(name);
12207                                 /* Add ",32" for 32-bit counters */
12208                                 if (port_cntrs[i].flags & CNTR_32BIT)
12209                                         sz += bit_type_32_sz;
12210                                 sz++;
12211                                 dd->nportcntrs++;
12212                         }
12213                 } else {
12214                         /* +1 for newline */
12215                         sz += strlen(port_cntrs[i].name) + 1;
12216                         /* Add ",32" for 32-bit counters */
12217                         if (port_cntrs[i].flags & CNTR_32BIT)
12218                                 sz += bit_type_32_sz;
12219                         port_cntrs[i].offset = dd->nportcntrs;
12220                         dd->nportcntrs++;
12221                 }
12222         }
12223
12224         /* allocate space for the counter names */
12225         dd->portcntrnameslen = sz;
12226         dd->portcntrnames = kmalloc(sz, GFP_KERNEL);
12227         if (!dd->portcntrnames)
12228                 goto bail;
12229
12230         /* fill in port cntr names */
12231         for (p = dd->portcntrnames, i = 0; i < PORT_CNTR_LAST; i++) {
12232                 if (port_cntrs[i].flags & CNTR_DISABLED)
12233                         continue;
12234
12235                 if (port_cntrs[i].flags & CNTR_VL) {
12236                         for (j = 0; j < C_VL_COUNT; j++) {
12237                                 snprintf(name, C_MAX_NAME, "%s%d",
12238                                          port_cntrs[i].name, vl_from_idx(j));
12239                                 memcpy(p, name, strlen(name));
12240                                 p += strlen(name);
12241
12242                                 /* Counter is 32 bits */
12243                                 if (port_cntrs[i].flags & CNTR_32BIT) {
12244                                         memcpy(p, bit_type_32, bit_type_32_sz);
12245                                         p += bit_type_32_sz;
12246                                 }
12247
12248                                 *p++ = '\n';
12249                         }
12250                 } else {
12251                         memcpy(p, port_cntrs[i].name,
12252                                strlen(port_cntrs[i].name));
12253                         p += strlen(port_cntrs[i].name);
12254
12255                         /* Counter is 32 bits */
12256                         if (port_cntrs[i].flags & CNTR_32BIT) {
12257                                 memcpy(p, bit_type_32, bit_type_32_sz);
12258                                 p += bit_type_32_sz;
12259                         }
12260
12261                         *p++ = '\n';
12262                 }
12263         }
12264
12265         /* allocate per port storage for counter values */
12266         ppd = (struct hfi1_pportdata *)(dd + 1);
12267         for (i = 0; i < dd->num_pports; i++, ppd++) {
12268                 ppd->cntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12269                 if (!ppd->cntrs)
12270                         goto bail;
12271
12272                 ppd->scntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12273                 if (!ppd->scntrs)
12274                         goto bail;
12275         }
12276
12277         /* CPU counters need to be allocated and zeroed */
12278         if (init_cpu_counters(dd))
12279                 goto bail;
12280
12281         mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
12282         return 0;
12283 bail:
12284         free_cntrs(dd);
12285         return -ENOMEM;
12286 }
12287
12288 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate)
12289 {
12290         switch (chip_lstate) {
12291         default:
12292                 dd_dev_err(dd,
12293                            "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n",
12294                            chip_lstate);
12295                 /* fall through */
12296         case LSTATE_DOWN:
12297                 return IB_PORT_DOWN;
12298         case LSTATE_INIT:
12299                 return IB_PORT_INIT;
12300         case LSTATE_ARMED:
12301                 return IB_PORT_ARMED;
12302         case LSTATE_ACTIVE:
12303                 return IB_PORT_ACTIVE;
12304         }
12305 }
12306
12307 u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate)
12308 {
12309         /* look at the HFI meta-states only */
12310         switch (chip_pstate & 0xf0) {
12311         default:
12312                 dd_dev_err(dd, "Unexpected chip physical state of 0x%x\n",
12313                            chip_pstate);
12314                 /* fall through */
12315         case PLS_DISABLED:
12316                 return IB_PORTPHYSSTATE_DISABLED;
12317         case PLS_OFFLINE:
12318                 return OPA_PORTPHYSSTATE_OFFLINE;
12319         case PLS_POLLING:
12320                 return IB_PORTPHYSSTATE_POLLING;
12321         case PLS_CONFIGPHY:
12322                 return IB_PORTPHYSSTATE_TRAINING;
12323         case PLS_LINKUP:
12324                 return IB_PORTPHYSSTATE_LINKUP;
12325         case PLS_PHYTEST:
12326                 return IB_PORTPHYSSTATE_PHY_TEST;
12327         }
12328 }
12329
12330 /* return the OPA port logical state name */
12331 const char *opa_lstate_name(u32 lstate)
12332 {
12333         static const char * const port_logical_names[] = {
12334                 "PORT_NOP",
12335                 "PORT_DOWN",
12336                 "PORT_INIT",
12337                 "PORT_ARMED",
12338                 "PORT_ACTIVE",
12339                 "PORT_ACTIVE_DEFER",
12340         };
12341         if (lstate < ARRAY_SIZE(port_logical_names))
12342                 return port_logical_names[lstate];
12343         return "unknown";
12344 }
12345
12346 /* return the OPA port physical state name */
12347 const char *opa_pstate_name(u32 pstate)
12348 {
12349         static const char * const port_physical_names[] = {
12350                 "PHYS_NOP",
12351                 "reserved1",
12352                 "PHYS_POLL",
12353                 "PHYS_DISABLED",
12354                 "PHYS_TRAINING",
12355                 "PHYS_LINKUP",
12356                 "PHYS_LINK_ERR_RECOVER",
12357                 "PHYS_PHY_TEST",
12358                 "reserved8",
12359                 "PHYS_OFFLINE",
12360                 "PHYS_GANGED",
12361                 "PHYS_TEST",
12362         };
12363         if (pstate < ARRAY_SIZE(port_physical_names))
12364                 return port_physical_names[pstate];
12365         return "unknown";
12366 }
12367
12368 /*
12369  * Read the hardware link state and set the driver's cached value of it.
12370  * Return the (new) current value.
12371  */
12372 u32 get_logical_state(struct hfi1_pportdata *ppd)
12373 {
12374         u32 new_state;
12375
12376         new_state = chip_to_opa_lstate(ppd->dd, read_logical_state(ppd->dd));
12377         if (new_state != ppd->lstate) {
12378                 dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n",
12379                             opa_lstate_name(new_state), new_state);
12380                 ppd->lstate = new_state;
12381         }
12382         /*
12383          * Set port status flags in the page mapped into userspace
12384          * memory. Do it here to ensure a reliable state - this is
12385          * the only function called by all state handling code.
12386          * Always set the flags due to the fact that the cache value
12387          * might have been changed explicitly outside of this
12388          * function.
12389          */
12390         if (ppd->statusp) {
12391                 switch (ppd->lstate) {
12392                 case IB_PORT_DOWN:
12393                 case IB_PORT_INIT:
12394                         *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
12395                                            HFI1_STATUS_IB_READY);
12396                         break;
12397                 case IB_PORT_ARMED:
12398                         *ppd->statusp |= HFI1_STATUS_IB_CONF;
12399                         break;
12400                 case IB_PORT_ACTIVE:
12401                         *ppd->statusp |= HFI1_STATUS_IB_READY;
12402                         break;
12403                 }
12404         }
12405         return ppd->lstate;
12406 }
12407
12408 /**
12409  * wait_logical_linkstate - wait for an IB link state change to occur
12410  * @ppd: port device
12411  * @state: the state to wait for
12412  * @msecs: the number of milliseconds to wait
12413  *
12414  * Wait up to msecs milliseconds for IB link state change to occur.
12415  * For now, take the easy polling route.
12416  * Returns 0 if state reached, otherwise -ETIMEDOUT.
12417  */
12418 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
12419                                   int msecs)
12420 {
12421         unsigned long timeout;
12422
12423         timeout = jiffies + msecs_to_jiffies(msecs);
12424         while (1) {
12425                 if (get_logical_state(ppd) == state)
12426                         return 0;
12427                 if (time_after(jiffies, timeout))
12428                         break;
12429                 msleep(20);
12430         }
12431         dd_dev_err(ppd->dd, "timeout waiting for link state 0x%x\n", state);
12432
12433         return -ETIMEDOUT;
12434 }
12435
12436 u8 hfi1_ibphys_portstate(struct hfi1_pportdata *ppd)
12437 {
12438         u32 pstate;
12439         u32 ib_pstate;
12440
12441         pstate = read_physical_state(ppd->dd);
12442         ib_pstate = chip_to_opa_pstate(ppd->dd, pstate);
12443         if (ppd->last_pstate != ib_pstate) {
12444                 dd_dev_info(ppd->dd,
12445                             "%s: physical state changed to %s (0x%x), phy 0x%x\n",
12446                             __func__, opa_pstate_name(ib_pstate), ib_pstate,
12447                             pstate);
12448                 ppd->last_pstate = ib_pstate;
12449         }
12450         return ib_pstate;
12451 }
12452
12453 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
12454 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12455
12456 #define SET_STATIC_RATE_CONTROL_SMASK(r) \
12457 (r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12458
12459 int hfi1_init_ctxt(struct send_context *sc)
12460 {
12461         if (sc) {
12462                 struct hfi1_devdata *dd = sc->dd;
12463                 u64 reg;
12464                 u8 set = (sc->type == SC_USER ?
12465                           HFI1_CAP_IS_USET(STATIC_RATE_CTRL) :
12466                           HFI1_CAP_IS_KSET(STATIC_RATE_CTRL));
12467                 reg = read_kctxt_csr(dd, sc->hw_context,
12468                                      SEND_CTXT_CHECK_ENABLE);
12469                 if (set)
12470                         CLEAR_STATIC_RATE_CONTROL_SMASK(reg);
12471                 else
12472                         SET_STATIC_RATE_CONTROL_SMASK(reg);
12473                 write_kctxt_csr(dd, sc->hw_context,
12474                                 SEND_CTXT_CHECK_ENABLE, reg);
12475         }
12476         return 0;
12477 }
12478
12479 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp)
12480 {
12481         int ret = 0;
12482         u64 reg;
12483
12484         if (dd->icode != ICODE_RTL_SILICON) {
12485                 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
12486                         dd_dev_info(dd, "%s: tempsense not supported by HW\n",
12487                                     __func__);
12488                 return -EINVAL;
12489         }
12490         reg = read_csr(dd, ASIC_STS_THERM);
12491         temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) &
12492                       ASIC_STS_THERM_CURR_TEMP_MASK);
12493         temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) &
12494                         ASIC_STS_THERM_LO_TEMP_MASK);
12495         temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) &
12496                         ASIC_STS_THERM_HI_TEMP_MASK);
12497         temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) &
12498                           ASIC_STS_THERM_CRIT_TEMP_MASK);
12499         /* triggers is a 3-bit value - 1 bit per trigger. */
12500         temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7);
12501
12502         return ret;
12503 }
12504
12505 /* ========================================================================= */
12506
12507 /*
12508  * Enable/disable chip from delivering interrupts.
12509  */
12510 void set_intr_state(struct hfi1_devdata *dd, u32 enable)
12511 {
12512         int i;
12513
12514         /*
12515          * In HFI, the mask needs to be 1 to allow interrupts.
12516          */
12517         if (enable) {
12518                 /* enable all interrupts */
12519                 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12520                         write_csr(dd, CCE_INT_MASK + (8 * i), ~(u64)0);
12521
12522                 init_qsfp_int(dd);
12523         } else {
12524                 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12525                         write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
12526         }
12527 }
12528
12529 /*
12530  * Clear all interrupt sources on the chip.
12531  */
12532 static void clear_all_interrupts(struct hfi1_devdata *dd)
12533 {
12534         int i;
12535
12536         for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12537                 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0);
12538
12539         write_csr(dd, CCE_ERR_CLEAR, ~(u64)0);
12540         write_csr(dd, MISC_ERR_CLEAR, ~(u64)0);
12541         write_csr(dd, RCV_ERR_CLEAR, ~(u64)0);
12542         write_csr(dd, SEND_ERR_CLEAR, ~(u64)0);
12543         write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0);
12544         write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0);
12545         write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0);
12546         for (i = 0; i < dd->chip_send_contexts; i++)
12547                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~(u64)0);
12548         for (i = 0; i < dd->chip_sdma_engines; i++)
12549                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~(u64)0);
12550
12551         write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0);
12552         write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0);
12553         write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0);
12554 }
12555
12556 /* Move to pcie.c? */
12557 static void disable_intx(struct pci_dev *pdev)
12558 {
12559         pci_intx(pdev, 0);
12560 }
12561
12562 static void clean_up_interrupts(struct hfi1_devdata *dd)
12563 {
12564         int i;
12565
12566         /* remove irqs - must happen before disabling/turning off */
12567         if (dd->num_msix_entries) {
12568                 /* MSI-X */
12569                 struct hfi1_msix_entry *me = dd->msix_entries;
12570
12571                 for (i = 0; i < dd->num_msix_entries; i++, me++) {
12572                         if (!me->arg) /* => no irq, no affinity */
12573                                 continue;
12574                         hfi1_put_irq_affinity(dd, &dd->msix_entries[i]);
12575                         free_irq(me->msix.vector, me->arg);
12576                 }
12577         } else {
12578                 /* INTx */
12579                 if (dd->requested_intx_irq) {
12580                         free_irq(dd->pcidev->irq, dd);
12581                         dd->requested_intx_irq = 0;
12582                 }
12583         }
12584
12585         /* turn off interrupts */
12586         if (dd->num_msix_entries) {
12587                 /* MSI-X */
12588                 pci_disable_msix(dd->pcidev);
12589         } else {
12590                 /* INTx */
12591                 disable_intx(dd->pcidev);
12592         }
12593
12594         /* clean structures */
12595         kfree(dd->msix_entries);
12596         dd->msix_entries = NULL;
12597         dd->num_msix_entries = 0;
12598 }
12599
12600 /*
12601  * Remap the interrupt source from the general handler to the given MSI-X
12602  * interrupt.
12603  */
12604 static void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr)
12605 {
12606         u64 reg;
12607         int m, n;
12608
12609         /* clear from the handled mask of the general interrupt */
12610         m = isrc / 64;
12611         n = isrc % 64;
12612         dd->gi_mask[m] &= ~((u64)1 << n);
12613
12614         /* direct the chip source to the given MSI-X interrupt */
12615         m = isrc / 8;
12616         n = isrc % 8;
12617         reg = read_csr(dd, CCE_INT_MAP + (8 * m));
12618         reg &= ~((u64)0xff << (8 * n));
12619         reg |= ((u64)msix_intr & 0xff) << (8 * n);
12620         write_csr(dd, CCE_INT_MAP + (8 * m), reg);
12621 }
12622
12623 static void remap_sdma_interrupts(struct hfi1_devdata *dd,
12624                                   int engine, int msix_intr)
12625 {
12626         /*
12627          * SDMA engine interrupt sources grouped by type, rather than
12628          * engine.  Per-engine interrupts are as follows:
12629          *      SDMA
12630          *      SDMAProgress
12631          *      SDMAIdle
12632          */
12633         remap_intr(dd, IS_SDMA_START + 0 * TXE_NUM_SDMA_ENGINES + engine,
12634                    msix_intr);
12635         remap_intr(dd, IS_SDMA_START + 1 * TXE_NUM_SDMA_ENGINES + engine,
12636                    msix_intr);
12637         remap_intr(dd, IS_SDMA_START + 2 * TXE_NUM_SDMA_ENGINES + engine,
12638                    msix_intr);
12639 }
12640
12641 static int request_intx_irq(struct hfi1_devdata *dd)
12642 {
12643         int ret;
12644
12645         snprintf(dd->intx_name, sizeof(dd->intx_name), DRIVER_NAME "_%d",
12646                  dd->unit);
12647         ret = request_irq(dd->pcidev->irq, general_interrupt,
12648                           IRQF_SHARED, dd->intx_name, dd);
12649         if (ret)
12650                 dd_dev_err(dd, "unable to request INTx interrupt, err %d\n",
12651                            ret);
12652         else
12653                 dd->requested_intx_irq = 1;
12654         return ret;
12655 }
12656
12657 static int request_msix_irqs(struct hfi1_devdata *dd)
12658 {
12659         int first_general, last_general;
12660         int first_sdma, last_sdma;
12661         int first_rx, last_rx;
12662         int i, ret = 0;
12663
12664         /* calculate the ranges we are going to use */
12665         first_general = 0;
12666         last_general = first_general + 1;
12667         first_sdma = last_general;
12668         last_sdma = first_sdma + dd->num_sdma;
12669         first_rx = last_sdma;
12670         last_rx = first_rx + dd->n_krcv_queues;
12671
12672         /*
12673          * Sanity check - the code expects all SDMA chip source
12674          * interrupts to be in the same CSR, starting at bit 0.  Verify
12675          * that this is true by checking the bit location of the start.
12676          */
12677         BUILD_BUG_ON(IS_SDMA_START % 64);
12678
12679         for (i = 0; i < dd->num_msix_entries; i++) {
12680                 struct hfi1_msix_entry *me = &dd->msix_entries[i];
12681                 const char *err_info;
12682                 irq_handler_t handler;
12683                 irq_handler_t thread = NULL;
12684                 void *arg;
12685                 int idx;
12686                 struct hfi1_ctxtdata *rcd = NULL;
12687                 struct sdma_engine *sde = NULL;
12688
12689                 /* obtain the arguments to request_irq */
12690                 if (first_general <= i && i < last_general) {
12691                         idx = i - first_general;
12692                         handler = general_interrupt;
12693                         arg = dd;
12694                         snprintf(me->name, sizeof(me->name),
12695                                  DRIVER_NAME "_%d", dd->unit);
12696                         err_info = "general";
12697                         me->type = IRQ_GENERAL;
12698                 } else if (first_sdma <= i && i < last_sdma) {
12699                         idx = i - first_sdma;
12700                         sde = &dd->per_sdma[idx];
12701                         handler = sdma_interrupt;
12702                         arg = sde;
12703                         snprintf(me->name, sizeof(me->name),
12704                                  DRIVER_NAME "_%d sdma%d", dd->unit, idx);
12705                         err_info = "sdma";
12706                         remap_sdma_interrupts(dd, idx, i);
12707                         me->type = IRQ_SDMA;
12708                 } else if (first_rx <= i && i < last_rx) {
12709                         idx = i - first_rx;
12710                         rcd = dd->rcd[idx];
12711                         /* no interrupt if no rcd */
12712                         if (!rcd)
12713                                 continue;
12714                         /*
12715                          * Set the interrupt register and mask for this
12716                          * context's interrupt.
12717                          */
12718                         rcd->ireg = (IS_RCVAVAIL_START + idx) / 64;
12719                         rcd->imask = ((u64)1) <<
12720                                         ((IS_RCVAVAIL_START + idx) % 64);
12721                         handler = receive_context_interrupt;
12722                         thread = receive_context_thread;
12723                         arg = rcd;
12724                         snprintf(me->name, sizeof(me->name),
12725                                  DRIVER_NAME "_%d kctxt%d", dd->unit, idx);
12726                         err_info = "receive context";
12727                         remap_intr(dd, IS_RCVAVAIL_START + idx, i);
12728                         me->type = IRQ_RCVCTXT;
12729                 } else {
12730                         /* not in our expected range - complain, then
12731                          * ignore it
12732                          */
12733                         dd_dev_err(dd,
12734                                    "Unexpected extra MSI-X interrupt %d\n", i);
12735                         continue;
12736                 }
12737                 /* no argument, no interrupt */
12738                 if (!arg)
12739                         continue;
12740                 /* make sure the name is terminated */
12741                 me->name[sizeof(me->name) - 1] = 0;
12742
12743                 ret = request_threaded_irq(me->msix.vector, handler, thread, 0,
12744                                            me->name, arg);
12745                 if (ret) {
12746                         dd_dev_err(dd,
12747                                    "unable to allocate %s interrupt, vector %d, index %d, err %d\n",
12748                                    err_info, me->msix.vector, idx, ret);
12749                         return ret;
12750                 }
12751                 /*
12752                  * assign arg after request_irq call, so it will be
12753                  * cleaned up
12754                  */
12755                 me->arg = arg;
12756
12757                 ret = hfi1_get_irq_affinity(dd, me);
12758                 if (ret)
12759                         dd_dev_err(dd,
12760                                    "unable to pin IRQ %d\n", ret);
12761         }
12762
12763         return ret;
12764 }
12765
12766 /*
12767  * Set the general handler to accept all interrupts, remap all
12768  * chip interrupts back to MSI-X 0.
12769  */
12770 static void reset_interrupts(struct hfi1_devdata *dd)
12771 {
12772         int i;
12773
12774         /* all interrupts handled by the general handler */
12775         for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12776                 dd->gi_mask[i] = ~(u64)0;
12777
12778         /* all chip interrupts map to MSI-X 0 */
12779         for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
12780                 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
12781 }
12782
12783 static int set_up_interrupts(struct hfi1_devdata *dd)
12784 {
12785         struct hfi1_msix_entry *entries;
12786         u32 total, request;
12787         int i, ret;
12788         int single_interrupt = 0; /* we expect to have all the interrupts */
12789
12790         /*
12791          * Interrupt count:
12792          *      1 general, "slow path" interrupt (includes the SDMA engines
12793          *              slow source, SDMACleanupDone)
12794          *      N interrupts - one per used SDMA engine
12795          *      M interrupt - one per kernel receive context
12796          */
12797         total = 1 + dd->num_sdma + dd->n_krcv_queues;
12798
12799         entries = kcalloc(total, sizeof(*entries), GFP_KERNEL);
12800         if (!entries) {
12801                 ret = -ENOMEM;
12802                 goto fail;
12803         }
12804         /* 1-1 MSI-X entry assignment */
12805         for (i = 0; i < total; i++)
12806                 entries[i].msix.entry = i;
12807
12808         /* ask for MSI-X interrupts */
12809         request = total;
12810         request_msix(dd, &request, entries);
12811
12812         if (request == 0) {
12813                 /* using INTx */
12814                 /* dd->num_msix_entries already zero */
12815                 kfree(entries);
12816                 single_interrupt = 1;
12817                 dd_dev_err(dd, "MSI-X failed, using INTx interrupts\n");
12818         } else {
12819                 /* using MSI-X */
12820                 dd->num_msix_entries = request;
12821                 dd->msix_entries = entries;
12822
12823                 if (request != total) {
12824                         /* using MSI-X, with reduced interrupts */
12825                         dd_dev_err(
12826                                 dd,
12827                                 "cannot handle reduced interrupt case, want %u, got %u\n",
12828                                 total, request);
12829                         ret = -EINVAL;
12830                         goto fail;
12831                 }
12832                 dd_dev_info(dd, "%u MSI-X interrupts allocated\n", total);
12833         }
12834
12835         /* mask all interrupts */
12836         set_intr_state(dd, 0);
12837         /* clear all pending interrupts */
12838         clear_all_interrupts(dd);
12839
12840         /* reset general handler mask, chip MSI-X mappings */
12841         reset_interrupts(dd);
12842
12843         if (single_interrupt)
12844                 ret = request_intx_irq(dd);
12845         else
12846                 ret = request_msix_irqs(dd);
12847         if (ret)
12848                 goto fail;
12849
12850         return 0;
12851
12852 fail:
12853         clean_up_interrupts(dd);
12854         return ret;
12855 }
12856
12857 /*
12858  * Set up context values in dd.  Sets:
12859  *
12860  *      num_rcv_contexts - number of contexts being used
12861  *      n_krcv_queues - number of kernel contexts
12862  *      first_user_ctxt - first non-kernel context in array of contexts
12863  *      freectxts  - number of free user contexts
12864  *      num_send_contexts - number of PIO send contexts being used
12865  */
12866 static int set_up_context_variables(struct hfi1_devdata *dd)
12867 {
12868         int num_kernel_contexts;
12869         int total_contexts;
12870         int ret;
12871         unsigned ngroups;
12872         int qos_rmt_count;
12873         int user_rmt_reduced;
12874
12875         /*
12876          * Kernel receive contexts:
12877          * - Context 0 - control context (VL15/multicast/error)
12878          * - Context 1 - first kernel context
12879          * - Context 2 - second kernel context
12880          * ...
12881          */
12882         if (n_krcvqs)
12883                 /*
12884                  * n_krcvqs is the sum of module parameter kernel receive
12885                  * contexts, krcvqs[].  It does not include the control
12886                  * context, so add that.
12887                  */
12888                 num_kernel_contexts = n_krcvqs + 1;
12889         else
12890                 num_kernel_contexts = DEFAULT_KRCVQS + 1;
12891         /*
12892          * Every kernel receive context needs an ACK send context.
12893          * one send context is allocated for each VL{0-7} and VL15
12894          */
12895         if (num_kernel_contexts > (dd->chip_send_contexts - num_vls - 1)) {
12896                 dd_dev_err(dd,
12897                            "Reducing # kernel rcv contexts to: %d, from %d\n",
12898                            (int)(dd->chip_send_contexts - num_vls - 1),
12899                            (int)num_kernel_contexts);
12900                 num_kernel_contexts = dd->chip_send_contexts - num_vls - 1;
12901         }
12902         /*
12903          * User contexts:
12904          *      - default to 1 user context per real (non-HT) CPU core if
12905          *        num_user_contexts is negative
12906          */
12907         if (num_user_contexts < 0)
12908                 num_user_contexts =
12909                         cpumask_weight(&node_affinity.real_cpu_mask);
12910
12911         total_contexts = num_kernel_contexts + num_user_contexts;
12912
12913         /*
12914          * Adjust the counts given a global max.
12915          */
12916         if (total_contexts > dd->chip_rcv_contexts) {
12917                 dd_dev_err(dd,
12918                            "Reducing # user receive contexts to: %d, from %d\n",
12919                            (int)(dd->chip_rcv_contexts - num_kernel_contexts),
12920                            (int)num_user_contexts);
12921                 num_user_contexts = dd->chip_rcv_contexts - num_kernel_contexts;
12922                 /* recalculate */
12923                 total_contexts = num_kernel_contexts + num_user_contexts;
12924         }
12925
12926         /* each user context requires an entry in the RMT */
12927         qos_rmt_count = qos_rmt_entries(dd, NULL, NULL);
12928         if (qos_rmt_count + num_user_contexts > NUM_MAP_ENTRIES) {
12929                 user_rmt_reduced = NUM_MAP_ENTRIES - qos_rmt_count;
12930                 dd_dev_err(dd,
12931                            "RMT size is reducing the number of user receive contexts from %d to %d\n",
12932                            (int)num_user_contexts,
12933                            user_rmt_reduced);
12934                 /* recalculate */
12935                 num_user_contexts = user_rmt_reduced;
12936                 total_contexts = num_kernel_contexts + num_user_contexts;
12937         }
12938
12939         /* the first N are kernel contexts, the rest are user contexts */
12940         dd->num_rcv_contexts = total_contexts;
12941         dd->n_krcv_queues = num_kernel_contexts;
12942         dd->first_user_ctxt = num_kernel_contexts;
12943         dd->num_user_contexts = num_user_contexts;
12944         dd->freectxts = num_user_contexts;
12945         dd_dev_info(dd,
12946                     "rcv contexts: chip %d, used %d (kernel %d, user %d)\n",
12947                     (int)dd->chip_rcv_contexts,
12948                     (int)dd->num_rcv_contexts,
12949                     (int)dd->n_krcv_queues,
12950                     (int)dd->num_rcv_contexts - dd->n_krcv_queues);
12951
12952         /*
12953          * Receive array allocation:
12954          *   All RcvArray entries are divided into groups of 8. This
12955          *   is required by the hardware and will speed up writes to
12956          *   consecutive entries by using write-combining of the entire
12957          *   cacheline.
12958          *
12959          *   The number of groups are evenly divided among all contexts.
12960          *   any left over groups will be given to the first N user
12961          *   contexts.
12962          */
12963         dd->rcv_entries.group_size = RCV_INCREMENT;
12964         ngroups = dd->chip_rcv_array_count / dd->rcv_entries.group_size;
12965         dd->rcv_entries.ngroups = ngroups / dd->num_rcv_contexts;
12966         dd->rcv_entries.nctxt_extra = ngroups -
12967                 (dd->num_rcv_contexts * dd->rcv_entries.ngroups);
12968         dd_dev_info(dd, "RcvArray groups %u, ctxts extra %u\n",
12969                     dd->rcv_entries.ngroups,
12970                     dd->rcv_entries.nctxt_extra);
12971         if (dd->rcv_entries.ngroups * dd->rcv_entries.group_size >
12972             MAX_EAGER_ENTRIES * 2) {
12973                 dd->rcv_entries.ngroups = (MAX_EAGER_ENTRIES * 2) /
12974                         dd->rcv_entries.group_size;
12975                 dd_dev_info(dd,
12976                             "RcvArray group count too high, change to %u\n",
12977                             dd->rcv_entries.ngroups);
12978                 dd->rcv_entries.nctxt_extra = 0;
12979         }
12980         /*
12981          * PIO send contexts
12982          */
12983         ret = init_sc_pools_and_sizes(dd);
12984         if (ret >= 0) { /* success */
12985                 dd->num_send_contexts = ret;
12986                 dd_dev_info(
12987                         dd,
12988                         "send contexts: chip %d, used %d (kernel %d, ack %d, user %d, vl15 %d)\n",
12989                         dd->chip_send_contexts,
12990                         dd->num_send_contexts,
12991                         dd->sc_sizes[SC_KERNEL].count,
12992                         dd->sc_sizes[SC_ACK].count,
12993                         dd->sc_sizes[SC_USER].count,
12994                         dd->sc_sizes[SC_VL15].count);
12995                 ret = 0;        /* success */
12996         }
12997
12998         return ret;
12999 }
13000
13001 /*
13002  * Set the device/port partition key table. The MAD code
13003  * will ensure that, at least, the partial management
13004  * partition key is present in the table.
13005  */
13006 static void set_partition_keys(struct hfi1_pportdata *ppd)
13007 {
13008         struct hfi1_devdata *dd = ppd->dd;
13009         u64 reg = 0;
13010         int i;
13011
13012         dd_dev_info(dd, "Setting partition keys\n");
13013         for (i = 0; i < hfi1_get_npkeys(dd); i++) {
13014                 reg |= (ppd->pkeys[i] &
13015                         RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) <<
13016                         ((i % 4) *
13017                          RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT);
13018                 /* Each register holds 4 PKey values. */
13019                 if ((i % 4) == 3) {
13020                         write_csr(dd, RCV_PARTITION_KEY +
13021                                   ((i - 3) * 2), reg);
13022                         reg = 0;
13023                 }
13024         }
13025
13026         /* Always enable HW pkeys check when pkeys table is set */
13027         add_rcvctrl(dd, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK);
13028 }
13029
13030 /*
13031  * These CSRs and memories are uninitialized on reset and must be
13032  * written before reading to set the ECC/parity bits.
13033  *
13034  * NOTE: All user context CSRs that are not mmaped write-only
13035  * (e.g. the TID flows) must be initialized even if the driver never
13036  * reads them.
13037  */
13038 static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd)
13039 {
13040         int i, j;
13041
13042         /* CceIntMap */
13043         for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
13044                 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
13045
13046         /* SendCtxtCreditReturnAddr */
13047         for (i = 0; i < dd->chip_send_contexts; i++)
13048                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13049
13050         /* PIO Send buffers */
13051         /* SDMA Send buffers */
13052         /*
13053          * These are not normally read, and (presently) have no method
13054          * to be read, so are not pre-initialized
13055          */
13056
13057         /* RcvHdrAddr */
13058         /* RcvHdrTailAddr */
13059         /* RcvTidFlowTable */
13060         for (i = 0; i < dd->chip_rcv_contexts; i++) {
13061                 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13062                 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13063                 for (j = 0; j < RXE_NUM_TID_FLOWS; j++)
13064                         write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j), 0);
13065         }
13066
13067         /* RcvArray */
13068         for (i = 0; i < dd->chip_rcv_array_count; i++)
13069                 write_csr(dd, RCV_ARRAY + (8 * i),
13070                           RCV_ARRAY_RT_WRITE_ENABLE_SMASK);
13071
13072         /* RcvQPMapTable */
13073         for (i = 0; i < 32; i++)
13074                 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13075 }
13076
13077 /*
13078  * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
13079  */
13080 static void clear_cce_status(struct hfi1_devdata *dd, u64 status_bits,
13081                              u64 ctrl_bits)
13082 {
13083         unsigned long timeout;
13084         u64 reg;
13085
13086         /* is the condition present? */
13087         reg = read_csr(dd, CCE_STATUS);
13088         if ((reg & status_bits) == 0)
13089                 return;
13090
13091         /* clear the condition */
13092         write_csr(dd, CCE_CTRL, ctrl_bits);
13093
13094         /* wait for the condition to clear */
13095         timeout = jiffies + msecs_to_jiffies(CCE_STATUS_TIMEOUT);
13096         while (1) {
13097                 reg = read_csr(dd, CCE_STATUS);
13098                 if ((reg & status_bits) == 0)
13099                         return;
13100                 if (time_after(jiffies, timeout)) {
13101                         dd_dev_err(dd,
13102                                    "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n",
13103                                    status_bits, reg & status_bits);
13104                         return;
13105                 }
13106                 udelay(1);
13107         }
13108 }
13109
13110 /* set CCE CSRs to chip reset defaults */
13111 static void reset_cce_csrs(struct hfi1_devdata *dd)
13112 {
13113         int i;
13114
13115         /* CCE_REVISION read-only */
13116         /* CCE_REVISION2 read-only */
13117         /* CCE_CTRL - bits clear automatically */
13118         /* CCE_STATUS read-only, use CceCtrl to clear */
13119         clear_cce_status(dd, ALL_FROZE, CCE_CTRL_SPC_UNFREEZE_SMASK);
13120         clear_cce_status(dd, ALL_TXE_PAUSE, CCE_CTRL_TXE_RESUME_SMASK);
13121         clear_cce_status(dd, ALL_RXE_PAUSE, CCE_CTRL_RXE_RESUME_SMASK);
13122         for (i = 0; i < CCE_NUM_SCRATCH; i++)
13123                 write_csr(dd, CCE_SCRATCH + (8 * i), 0);
13124         /* CCE_ERR_STATUS read-only */
13125         write_csr(dd, CCE_ERR_MASK, 0);
13126         write_csr(dd, CCE_ERR_CLEAR, ~0ull);
13127         /* CCE_ERR_FORCE leave alone */
13128         for (i = 0; i < CCE_NUM_32_BIT_COUNTERS; i++)
13129                 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0);
13130         write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR);
13131         /* CCE_PCIE_CTRL leave alone */
13132         for (i = 0; i < CCE_NUM_MSIX_VECTORS; i++) {
13133                 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0);
13134                 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i),
13135                           CCE_MSIX_TABLE_UPPER_RESETCSR);
13136         }
13137         for (i = 0; i < CCE_NUM_MSIX_PBAS; i++) {
13138                 /* CCE_MSIX_PBA read-only */
13139                 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull);
13140                 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull);
13141         }
13142         for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
13143                 write_csr(dd, CCE_INT_MAP, 0);
13144         for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
13145                 /* CCE_INT_STATUS read-only */
13146                 write_csr(dd, CCE_INT_MASK + (8 * i), 0);
13147                 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull);
13148                 /* CCE_INT_FORCE leave alone */
13149                 /* CCE_INT_BLOCKED read-only */
13150         }
13151         for (i = 0; i < CCE_NUM_32_BIT_INT_COUNTERS; i++)
13152                 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0);
13153 }
13154
13155 /* set MISC CSRs to chip reset defaults */
13156 static void reset_misc_csrs(struct hfi1_devdata *dd)
13157 {
13158         int i;
13159
13160         for (i = 0; i < 32; i++) {
13161                 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0);
13162                 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0);
13163                 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0);
13164         }
13165         /*
13166          * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
13167          * only be written 128-byte chunks
13168          */
13169         /* init RSA engine to clear lingering errors */
13170         write_csr(dd, MISC_CFG_RSA_CMD, 1);
13171         write_csr(dd, MISC_CFG_RSA_MU, 0);
13172         write_csr(dd, MISC_CFG_FW_CTRL, 0);
13173         /* MISC_STS_8051_DIGEST read-only */
13174         /* MISC_STS_SBM_DIGEST read-only */
13175         /* MISC_STS_PCIE_DIGEST read-only */
13176         /* MISC_STS_FAB_DIGEST read-only */
13177         /* MISC_ERR_STATUS read-only */
13178         write_csr(dd, MISC_ERR_MASK, 0);
13179         write_csr(dd, MISC_ERR_CLEAR, ~0ull);
13180         /* MISC_ERR_FORCE leave alone */
13181 }
13182
13183 /* set TXE CSRs to chip reset defaults */
13184 static void reset_txe_csrs(struct hfi1_devdata *dd)
13185 {
13186         int i;
13187
13188         /*
13189          * TXE Kernel CSRs
13190          */
13191         write_csr(dd, SEND_CTRL, 0);
13192         __cm_reset(dd, 0);      /* reset CM internal state */
13193         /* SEND_CONTEXTS read-only */
13194         /* SEND_DMA_ENGINES read-only */
13195         /* SEND_PIO_MEM_SIZE read-only */
13196         /* SEND_DMA_MEM_SIZE read-only */
13197         write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0);
13198         pio_reset_all(dd);      /* SEND_PIO_INIT_CTXT */
13199         /* SEND_PIO_ERR_STATUS read-only */
13200         write_csr(dd, SEND_PIO_ERR_MASK, 0);
13201         write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull);
13202         /* SEND_PIO_ERR_FORCE leave alone */
13203         /* SEND_DMA_ERR_STATUS read-only */
13204         write_csr(dd, SEND_DMA_ERR_MASK, 0);
13205         write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull);
13206         /* SEND_DMA_ERR_FORCE leave alone */
13207         /* SEND_EGRESS_ERR_STATUS read-only */
13208         write_csr(dd, SEND_EGRESS_ERR_MASK, 0);
13209         write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull);
13210         /* SEND_EGRESS_ERR_FORCE leave alone */
13211         write_csr(dd, SEND_BTH_QP, 0);
13212         write_csr(dd, SEND_STATIC_RATE_CONTROL, 0);
13213         write_csr(dd, SEND_SC2VLT0, 0);
13214         write_csr(dd, SEND_SC2VLT1, 0);
13215         write_csr(dd, SEND_SC2VLT2, 0);
13216         write_csr(dd, SEND_SC2VLT3, 0);
13217         write_csr(dd, SEND_LEN_CHECK0, 0);
13218         write_csr(dd, SEND_LEN_CHECK1, 0);
13219         /* SEND_ERR_STATUS read-only */
13220         write_csr(dd, SEND_ERR_MASK, 0);
13221         write_csr(dd, SEND_ERR_CLEAR, ~0ull);
13222         /* SEND_ERR_FORCE read-only */
13223         for (i = 0; i < VL_ARB_LOW_PRIO_TABLE_SIZE; i++)
13224                 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0);
13225         for (i = 0; i < VL_ARB_HIGH_PRIO_TABLE_SIZE; i++)
13226                 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0);
13227         for (i = 0; i < dd->chip_send_contexts / NUM_CONTEXTS_PER_SET; i++)
13228                 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0);
13229         for (i = 0; i < TXE_NUM_32_BIT_COUNTER; i++)
13230                 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0);
13231         for (i = 0; i < TXE_NUM_64_BIT_COUNTER; i++)
13232                 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0);
13233         write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR);
13234         write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR);
13235         /* SEND_CM_CREDIT_USED_STATUS read-only */
13236         write_csr(dd, SEND_CM_TIMER_CTRL, 0);
13237         write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0);
13238         write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0);
13239         write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0);
13240         write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0);
13241         for (i = 0; i < TXE_NUM_DATA_VL; i++)
13242                 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
13243         write_csr(dd, SEND_CM_CREDIT_VL15, 0);
13244         /* SEND_CM_CREDIT_USED_VL read-only */
13245         /* SEND_CM_CREDIT_USED_VL15 read-only */
13246         /* SEND_EGRESS_CTXT_STATUS read-only */
13247         /* SEND_EGRESS_SEND_DMA_STATUS read-only */
13248         write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull);
13249         /* SEND_EGRESS_ERR_INFO read-only */
13250         /* SEND_EGRESS_ERR_SOURCE read-only */
13251
13252         /*
13253          * TXE Per-Context CSRs
13254          */
13255         for (i = 0; i < dd->chip_send_contexts; i++) {
13256                 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13257                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_CTRL, 0);
13258                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13259                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_FORCE, 0);
13260                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, 0);
13261                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~0ull);
13262                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_ENABLE, 0);
13263                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_VL, 0);
13264                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_JOB_KEY, 0);
13265                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_PARTITION_KEY, 0);
13266                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, 0);
13267                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_OPCODE, 0);
13268         }
13269
13270         /*
13271          * TXE Per-SDMA CSRs
13272          */
13273         for (i = 0; i < dd->chip_sdma_engines; i++) {
13274                 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13275                 /* SEND_DMA_STATUS read-only */
13276                 write_kctxt_csr(dd, i, SEND_DMA_BASE_ADDR, 0);
13277                 write_kctxt_csr(dd, i, SEND_DMA_LEN_GEN, 0);
13278                 write_kctxt_csr(dd, i, SEND_DMA_TAIL, 0);
13279                 /* SEND_DMA_HEAD read-only */
13280                 write_kctxt_csr(dd, i, SEND_DMA_HEAD_ADDR, 0);
13281                 write_kctxt_csr(dd, i, SEND_DMA_PRIORITY_THLD, 0);
13282                 /* SEND_DMA_IDLE_CNT read-only */
13283                 write_kctxt_csr(dd, i, SEND_DMA_RELOAD_CNT, 0);
13284                 write_kctxt_csr(dd, i, SEND_DMA_DESC_CNT, 0);
13285                 /* SEND_DMA_DESC_FETCHED_CNT read-only */
13286                 /* SEND_DMA_ENG_ERR_STATUS read-only */
13287                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, 0);
13288                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~0ull);
13289                 /* SEND_DMA_ENG_ERR_FORCE leave alone */
13290                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_ENABLE, 0);
13291                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_VL, 0);
13292                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_JOB_KEY, 0);
13293                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_PARTITION_KEY, 0);
13294                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_SLID, 0);
13295                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_OPCODE, 0);
13296                 write_kctxt_csr(dd, i, SEND_DMA_MEMORY, 0);
13297         }
13298 }
13299
13300 /*
13301  * Expect on entry:
13302  * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0
13303  */
13304 static void init_rbufs(struct hfi1_devdata *dd)
13305 {
13306         u64 reg;
13307         int count;
13308
13309         /*
13310          * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are
13311          * clear.
13312          */
13313         count = 0;
13314         while (1) {
13315                 reg = read_csr(dd, RCV_STATUS);
13316                 if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK
13317                             | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK)) == 0)
13318                         break;
13319                 /*
13320                  * Give up after 1ms - maximum wait time.
13321                  *
13322                  * RBuf size is 148KiB.  Slowest possible is PCIe Gen1 x1 at
13323                  * 250MB/s bandwidth.  Lower rate to 66% for overhead to get:
13324                  *      148 KB / (66% * 250MB/s) = 920us
13325                  */
13326                 if (count++ > 500) {
13327                         dd_dev_err(dd,
13328                                    "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n",
13329                                    __func__, reg);
13330                         break;
13331                 }
13332                 udelay(2); /* do not busy-wait the CSR */
13333         }
13334
13335         /* start the init - expect RcvCtrl to be 0 */
13336         write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK);
13337
13338         /*
13339          * Read to force the write of Rcvtrl.RxRbufInit.  There is a brief
13340          * period after the write before RcvStatus.RxRbufInitDone is valid.
13341          * The delay in the first run through the loop below is sufficient and
13342          * required before the first read of RcvStatus.RxRbufInintDone.
13343          */
13344         read_csr(dd, RCV_CTRL);
13345
13346         /* wait for the init to finish */
13347         count = 0;
13348         while (1) {
13349                 /* delay is required first time through - see above */
13350                 udelay(2); /* do not busy-wait the CSR */
13351                 reg = read_csr(dd, RCV_STATUS);
13352                 if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK))
13353                         break;
13354
13355                 /* give up after 100us - slowest possible at 33MHz is 73us */
13356                 if (count++ > 50) {
13357                         dd_dev_err(dd,
13358                                    "%s: RcvStatus.RxRbufInit not set, continuing\n",
13359                                    __func__);
13360                         break;
13361                 }
13362         }
13363 }
13364
13365 /* set RXE CSRs to chip reset defaults */
13366 static void reset_rxe_csrs(struct hfi1_devdata *dd)
13367 {
13368         int i, j;
13369
13370         /*
13371          * RXE Kernel CSRs
13372          */
13373         write_csr(dd, RCV_CTRL, 0);
13374         init_rbufs(dd);
13375         /* RCV_STATUS read-only */
13376         /* RCV_CONTEXTS read-only */
13377         /* RCV_ARRAY_CNT read-only */
13378         /* RCV_BUF_SIZE read-only */
13379         write_csr(dd, RCV_BTH_QP, 0);
13380         write_csr(dd, RCV_MULTICAST, 0);
13381         write_csr(dd, RCV_BYPASS, 0);
13382         write_csr(dd, RCV_VL15, 0);
13383         /* this is a clear-down */
13384         write_csr(dd, RCV_ERR_INFO,
13385                   RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK);
13386         /* RCV_ERR_STATUS read-only */
13387         write_csr(dd, RCV_ERR_MASK, 0);
13388         write_csr(dd, RCV_ERR_CLEAR, ~0ull);
13389         /* RCV_ERR_FORCE leave alone */
13390         for (i = 0; i < 32; i++)
13391                 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13392         for (i = 0; i < 4; i++)
13393                 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0);
13394         for (i = 0; i < RXE_NUM_32_BIT_COUNTERS; i++)
13395                 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0);
13396         for (i = 0; i < RXE_NUM_64_BIT_COUNTERS; i++)
13397                 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0);
13398         for (i = 0; i < RXE_NUM_RSM_INSTANCES; i++) {
13399                 write_csr(dd, RCV_RSM_CFG + (8 * i), 0);
13400                 write_csr(dd, RCV_RSM_SELECT + (8 * i), 0);
13401                 write_csr(dd, RCV_RSM_MATCH + (8 * i), 0);
13402         }
13403         for (i = 0; i < 32; i++)
13404                 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0);
13405
13406         /*
13407          * RXE Kernel and User Per-Context CSRs
13408          */
13409         for (i = 0; i < dd->chip_rcv_contexts; i++) {
13410                 /* kernel */
13411                 write_kctxt_csr(dd, i, RCV_CTXT_CTRL, 0);
13412                 /* RCV_CTXT_STATUS read-only */
13413                 write_kctxt_csr(dd, i, RCV_EGR_CTRL, 0);
13414                 write_kctxt_csr(dd, i, RCV_TID_CTRL, 0);
13415                 write_kctxt_csr(dd, i, RCV_KEY_CTRL, 0);
13416                 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13417                 write_kctxt_csr(dd, i, RCV_HDR_CNT, 0);
13418                 write_kctxt_csr(dd, i, RCV_HDR_ENT_SIZE, 0);
13419                 write_kctxt_csr(dd, i, RCV_HDR_SIZE, 0);
13420                 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13421                 write_kctxt_csr(dd, i, RCV_AVAIL_TIME_OUT, 0);
13422                 write_kctxt_csr(dd, i, RCV_HDR_OVFL_CNT, 0);
13423
13424                 /* user */
13425                 /* RCV_HDR_TAIL read-only */
13426                 write_uctxt_csr(dd, i, RCV_HDR_HEAD, 0);
13427                 /* RCV_EGR_INDEX_TAIL read-only */
13428                 write_uctxt_csr(dd, i, RCV_EGR_INDEX_HEAD, 0);
13429                 /* RCV_EGR_OFFSET_TAIL read-only */
13430                 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) {
13431                         write_uctxt_csr(dd, i,
13432                                         RCV_TID_FLOW_TABLE + (8 * j), 0);
13433                 }
13434         }
13435 }
13436
13437 /*
13438  * Set sc2vl tables.
13439  *
13440  * They power on to zeros, so to avoid send context errors
13441  * they need to be set:
13442  *
13443  * SC 0-7 -> VL 0-7 (respectively)
13444  * SC 15  -> VL 15
13445  * otherwise
13446  *        -> VL 0
13447  */
13448 static void init_sc2vl_tables(struct hfi1_devdata *dd)
13449 {
13450         int i;
13451         /* init per architecture spec, constrained by hardware capability */
13452
13453         /* HFI maps sent packets */
13454         write_csr(dd, SEND_SC2VLT0, SC2VL_VAL(
13455                 0,
13456                 0, 0, 1, 1,
13457                 2, 2, 3, 3,
13458                 4, 4, 5, 5,
13459                 6, 6, 7, 7));
13460         write_csr(dd, SEND_SC2VLT1, SC2VL_VAL(
13461                 1,
13462                 8, 0, 9, 0,
13463                 10, 0, 11, 0,
13464                 12, 0, 13, 0,
13465                 14, 0, 15, 15));
13466         write_csr(dd, SEND_SC2VLT2, SC2VL_VAL(
13467                 2,
13468                 16, 0, 17, 0,
13469                 18, 0, 19, 0,
13470                 20, 0, 21, 0,
13471                 22, 0, 23, 0));
13472         write_csr(dd, SEND_SC2VLT3, SC2VL_VAL(
13473                 3,
13474                 24, 0, 25, 0,
13475                 26, 0, 27, 0,
13476                 28, 0, 29, 0,
13477                 30, 0, 31, 0));
13478
13479         /* DC maps received packets */
13480         write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL(
13481                 15_0,
13482                 0, 0, 1, 1,  2, 2,  3, 3,  4, 4,  5, 5,  6, 6,  7,  7,
13483                 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15));
13484         write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL(
13485                 31_16,
13486                 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0,
13487                 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0));
13488
13489         /* initialize the cached sc2vl values consistently with h/w */
13490         for (i = 0; i < 32; i++) {
13491                 if (i < 8 || i == 15)
13492                         *((u8 *)(dd->sc2vl) + i) = (u8)i;
13493                 else
13494                         *((u8 *)(dd->sc2vl) + i) = 0;
13495         }
13496 }
13497
13498 /*
13499  * Read chip sizes and then reset parts to sane, disabled, values.  We cannot
13500  * depend on the chip going through a power-on reset - a driver may be loaded
13501  * and unloaded many times.
13502  *
13503  * Do not write any CSR values to the chip in this routine - there may be
13504  * a reset following the (possible) FLR in this routine.
13505  *
13506  */
13507 static void init_chip(struct hfi1_devdata *dd)
13508 {
13509         int i;
13510
13511         /*
13512          * Put the HFI CSRs in a known state.
13513          * Combine this with a DC reset.
13514          *
13515          * Stop the device from doing anything while we do a
13516          * reset.  We know there are no other active users of
13517          * the device since we are now in charge.  Turn off
13518          * off all outbound and inbound traffic and make sure
13519          * the device does not generate any interrupts.
13520          */
13521
13522         /* disable send contexts and SDMA engines */
13523         write_csr(dd, SEND_CTRL, 0);
13524         for (i = 0; i < dd->chip_send_contexts; i++)
13525                 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13526         for (i = 0; i < dd->chip_sdma_engines; i++)
13527                 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13528         /* disable port (turn off RXE inbound traffic) and contexts */
13529         write_csr(dd, RCV_CTRL, 0);
13530         for (i = 0; i < dd->chip_rcv_contexts; i++)
13531                 write_csr(dd, RCV_CTXT_CTRL, 0);
13532         /* mask all interrupt sources */
13533         for (i = 0; i < CCE_NUM_INT_CSRS; i++)
13534                 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
13535
13536         /*
13537          * DC Reset: do a full DC reset before the register clear.
13538          * A recommended length of time to hold is one CSR read,
13539          * so reread the CceDcCtrl.  Then, hold the DC in reset
13540          * across the clear.
13541          */
13542         write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
13543         (void)read_csr(dd, CCE_DC_CTRL);
13544
13545         if (use_flr) {
13546                 /*
13547                  * A FLR will reset the SPC core and part of the PCIe.
13548                  * The parts that need to be restored have already been
13549                  * saved.
13550                  */
13551                 dd_dev_info(dd, "Resetting CSRs with FLR\n");
13552
13553                 /* do the FLR, the DC reset will remain */
13554                 hfi1_pcie_flr(dd);
13555
13556                 /* restore command and BARs */
13557                 restore_pci_variables(dd);
13558
13559                 if (is_ax(dd)) {
13560                         dd_dev_info(dd, "Resetting CSRs with FLR\n");
13561                         hfi1_pcie_flr(dd);
13562                         restore_pci_variables(dd);
13563                 }
13564         } else {
13565                 dd_dev_info(dd, "Resetting CSRs with writes\n");
13566                 reset_cce_csrs(dd);
13567                 reset_txe_csrs(dd);
13568                 reset_rxe_csrs(dd);
13569                 reset_misc_csrs(dd);
13570         }
13571         /* clear the DC reset */
13572         write_csr(dd, CCE_DC_CTRL, 0);
13573
13574         /* Set the LED off */
13575         setextled(dd, 0);
13576
13577         /*
13578          * Clear the QSFP reset.
13579          * An FLR enforces a 0 on all out pins. The driver does not touch
13580          * ASIC_QSFPn_OUT otherwise.  This leaves RESET_N low and
13581          * anything plugged constantly in reset, if it pays attention
13582          * to RESET_N.
13583          * Prime examples of this are optical cables. Set all pins high.
13584          * I2CCLK and I2CDAT will change per direction, and INT_N and
13585          * MODPRS_N are input only and their value is ignored.
13586          */
13587         write_csr(dd, ASIC_QSFP1_OUT, 0x1f);
13588         write_csr(dd, ASIC_QSFP2_OUT, 0x1f);
13589         init_chip_resources(dd);
13590 }
13591
13592 static void init_early_variables(struct hfi1_devdata *dd)
13593 {
13594         int i;
13595
13596         /* assign link credit variables */
13597         dd->vau = CM_VAU;
13598         dd->link_credits = CM_GLOBAL_CREDITS;
13599         if (is_ax(dd))
13600                 dd->link_credits--;
13601         dd->vcu = cu_to_vcu(hfi1_cu);
13602         /* enough room for 8 MAD packets plus header - 17K */
13603         dd->vl15_init = (8 * (2048 + 128)) / vau_to_au(dd->vau);
13604         if (dd->vl15_init > dd->link_credits)
13605                 dd->vl15_init = dd->link_credits;
13606
13607         write_uninitialized_csrs_and_memories(dd);
13608
13609         if (HFI1_CAP_IS_KSET(PKEY_CHECK))
13610                 for (i = 0; i < dd->num_pports; i++) {
13611                         struct hfi1_pportdata *ppd = &dd->pport[i];
13612
13613                         set_partition_keys(ppd);
13614                 }
13615         init_sc2vl_tables(dd);
13616 }
13617
13618 static void init_kdeth_qp(struct hfi1_devdata *dd)
13619 {
13620         /* user changed the KDETH_QP */
13621         if (kdeth_qp != 0 && kdeth_qp >= 0xff) {
13622                 /* out of range or illegal value */
13623                 dd_dev_err(dd, "Invalid KDETH queue pair prefix, ignoring");
13624                 kdeth_qp = 0;
13625         }
13626         if (kdeth_qp == 0)      /* not set, or failed range check */
13627                 kdeth_qp = DEFAULT_KDETH_QP;
13628
13629         write_csr(dd, SEND_BTH_QP,
13630                   (kdeth_qp & SEND_BTH_QP_KDETH_QP_MASK) <<
13631                   SEND_BTH_QP_KDETH_QP_SHIFT);
13632
13633         write_csr(dd, RCV_BTH_QP,
13634                   (kdeth_qp & RCV_BTH_QP_KDETH_QP_MASK) <<
13635                   RCV_BTH_QP_KDETH_QP_SHIFT);
13636 }
13637
13638 /**
13639  * init_qpmap_table
13640  * @dd - device data
13641  * @first_ctxt - first context
13642  * @last_ctxt - first context
13643  *
13644  * This return sets the qpn mapping table that
13645  * is indexed by qpn[8:1].
13646  *
13647  * The routine will round robin the 256 settings
13648  * from first_ctxt to last_ctxt.
13649  *
13650  * The first/last looks ahead to having specialized
13651  * receive contexts for mgmt and bypass.  Normal
13652  * verbs traffic will assumed to be on a range
13653  * of receive contexts.
13654  */
13655 static void init_qpmap_table(struct hfi1_devdata *dd,
13656                              u32 first_ctxt,
13657                              u32 last_ctxt)
13658 {
13659         u64 reg = 0;
13660         u64 regno = RCV_QP_MAP_TABLE;
13661         int i;
13662         u64 ctxt = first_ctxt;
13663
13664         for (i = 0; i < 256; i++) {
13665                 reg |= ctxt << (8 * (i % 8));
13666                 ctxt++;
13667                 if (ctxt > last_ctxt)
13668                         ctxt = first_ctxt;
13669                 if (i % 8 == 7) {
13670                         write_csr(dd, regno, reg);
13671                         reg = 0;
13672                         regno += 8;
13673                 }
13674         }
13675
13676         add_rcvctrl(dd, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK
13677                         | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK);
13678 }
13679
13680 struct rsm_map_table {
13681         u64 map[NUM_MAP_REGS];
13682         unsigned int used;
13683 };
13684
13685 struct rsm_rule_data {
13686         u8 offset;
13687         u8 pkt_type;
13688         u32 field1_off;
13689         u32 field2_off;
13690         u32 index1_off;
13691         u32 index1_width;
13692         u32 index2_off;
13693         u32 index2_width;
13694         u32 mask1;
13695         u32 value1;
13696         u32 mask2;
13697         u32 value2;
13698 };
13699
13700 /*
13701  * Return an initialized RMT map table for users to fill in.  OK if it
13702  * returns NULL, indicating no table.
13703  */
13704 static struct rsm_map_table *alloc_rsm_map_table(struct hfi1_devdata *dd)
13705 {
13706         struct rsm_map_table *rmt;
13707         u8 rxcontext = is_ax(dd) ? 0 : 0xff;  /* 0 is default if a0 ver. */
13708
13709         rmt = kmalloc(sizeof(*rmt), GFP_KERNEL);
13710         if (rmt) {
13711                 memset(rmt->map, rxcontext, sizeof(rmt->map));
13712                 rmt->used = 0;
13713         }
13714
13715         return rmt;
13716 }
13717
13718 /*
13719  * Write the final RMT map table to the chip and free the table.  OK if
13720  * table is NULL.
13721  */
13722 static void complete_rsm_map_table(struct hfi1_devdata *dd,
13723                                    struct rsm_map_table *rmt)
13724 {
13725         int i;
13726
13727         if (rmt) {
13728                 /* write table to chip */
13729                 for (i = 0; i < NUM_MAP_REGS; i++)
13730                         write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]);
13731
13732                 /* enable RSM */
13733                 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
13734         }
13735 }
13736
13737 /*
13738  * Add a receive side mapping rule.
13739  */
13740 static void add_rsm_rule(struct hfi1_devdata *dd, u8 rule_index,
13741                          struct rsm_rule_data *rrd)
13742 {
13743         write_csr(dd, RCV_RSM_CFG + (8 * rule_index),
13744                   (u64)rrd->offset << RCV_RSM_CFG_OFFSET_SHIFT |
13745                   1ull << rule_index | /* enable bit */
13746                   (u64)rrd->pkt_type << RCV_RSM_CFG_PACKET_TYPE_SHIFT);
13747         write_csr(dd, RCV_RSM_SELECT + (8 * rule_index),
13748                   (u64)rrd->field1_off << RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT |
13749                   (u64)rrd->field2_off << RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT |
13750                   (u64)rrd->index1_off << RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT |
13751                   (u64)rrd->index1_width << RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT |
13752                   (u64)rrd->index2_off << RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT |
13753                   (u64)rrd->index2_width << RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT);
13754         write_csr(dd, RCV_RSM_MATCH + (8 * rule_index),
13755                   (u64)rrd->mask1 << RCV_RSM_MATCH_MASK1_SHIFT |
13756                   (u64)rrd->value1 << RCV_RSM_MATCH_VALUE1_SHIFT |
13757                   (u64)rrd->mask2 << RCV_RSM_MATCH_MASK2_SHIFT |
13758                   (u64)rrd->value2 << RCV_RSM_MATCH_VALUE2_SHIFT);
13759 }
13760
13761 /* return the number of RSM map table entries that will be used for QOS */
13762 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp,
13763                            unsigned int *np)
13764 {
13765         int i;
13766         unsigned int m, n;
13767         u8 max_by_vl = 0;
13768
13769         /* is QOS active at all? */
13770         if (dd->n_krcv_queues <= MIN_KERNEL_KCTXTS ||
13771             num_vls == 1 ||
13772             krcvqsset <= 1)
13773                 goto no_qos;
13774
13775         /* determine bits for qpn */
13776         for (i = 0; i < min_t(unsigned int, num_vls, krcvqsset); i++)
13777                 if (krcvqs[i] > max_by_vl)
13778                         max_by_vl = krcvqs[i];
13779         if (max_by_vl > 32)
13780                 goto no_qos;
13781         m = ilog2(__roundup_pow_of_two(max_by_vl));
13782
13783         /* determine bits for vl */
13784         n = ilog2(__roundup_pow_of_two(num_vls));
13785
13786         /* reject if too much is used */
13787         if ((m + n) > 7)
13788                 goto no_qos;
13789
13790         if (mp)
13791                 *mp = m;
13792         if (np)
13793                 *np = n;
13794
13795         return 1 << (m + n);
13796
13797 no_qos:
13798         if (mp)
13799                 *mp = 0;
13800         if (np)
13801                 *np = 0;
13802         return 0;
13803 }
13804
13805 /**
13806  * init_qos - init RX qos
13807  * @dd - device data
13808  * @rmt - RSM map table
13809  *
13810  * This routine initializes Rule 0 and the RSM map table to implement
13811  * quality of service (qos).
13812  *
13813  * If all of the limit tests succeed, qos is applied based on the array
13814  * interpretation of krcvqs where entry 0 is VL0.
13815  *
13816  * The number of vl bits (n) and the number of qpn bits (m) are computed to
13817  * feed both the RSM map table and the single rule.
13818  */
13819 static void init_qos(struct hfi1_devdata *dd, struct rsm_map_table *rmt)
13820 {
13821         struct rsm_rule_data rrd;
13822         unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m;
13823         unsigned int rmt_entries;
13824         u64 reg;
13825
13826         if (!rmt)
13827                 goto bail;
13828         rmt_entries = qos_rmt_entries(dd, &m, &n);
13829         if (rmt_entries == 0)
13830                 goto bail;
13831         qpns_per_vl = 1 << m;
13832
13833         /* enough room in the map table? */
13834         rmt_entries = 1 << (m + n);
13835         if (rmt->used + rmt_entries >= NUM_MAP_ENTRIES)
13836                 goto bail;
13837
13838         /* add qos entries to the the RSM map table */
13839         for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) {
13840                 unsigned tctxt;
13841
13842                 for (qpn = 0, tctxt = ctxt;
13843                      krcvqs[i] && qpn < qpns_per_vl; qpn++) {
13844                         unsigned idx, regoff, regidx;
13845
13846                         /* generate the index the hardware will produce */
13847                         idx = rmt->used + ((qpn << n) ^ i);
13848                         regoff = (idx % 8) * 8;
13849                         regidx = idx / 8;
13850                         /* replace default with context number */
13851                         reg = rmt->map[regidx];
13852                         reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
13853                                 << regoff);
13854                         reg |= (u64)(tctxt++) << regoff;
13855                         rmt->map[regidx] = reg;
13856                         if (tctxt == ctxt + krcvqs[i])
13857                                 tctxt = ctxt;
13858                 }
13859                 ctxt += krcvqs[i];
13860         }
13861
13862         rrd.offset = rmt->used;
13863         rrd.pkt_type = 2;
13864         rrd.field1_off = LRH_BTH_MATCH_OFFSET;
13865         rrd.field2_off = LRH_SC_MATCH_OFFSET;
13866         rrd.index1_off = LRH_SC_SELECT_OFFSET;
13867         rrd.index1_width = n;
13868         rrd.index2_off = QPN_SELECT_OFFSET;
13869         rrd.index2_width = m + n;
13870         rrd.mask1 = LRH_BTH_MASK;
13871         rrd.value1 = LRH_BTH_VALUE;
13872         rrd.mask2 = LRH_SC_MASK;
13873         rrd.value2 = LRH_SC_VALUE;
13874
13875         /* add rule 0 */
13876         add_rsm_rule(dd, 0, &rrd);
13877
13878         /* mark RSM map entries as used */
13879         rmt->used += rmt_entries;
13880         /* map everything else to the mcast/err/vl15 context */
13881         init_qpmap_table(dd, HFI1_CTRL_CTXT, HFI1_CTRL_CTXT);
13882         dd->qos_shift = n + 1;
13883         return;
13884 bail:
13885         dd->qos_shift = 1;
13886         init_qpmap_table(dd, FIRST_KERNEL_KCTXT, dd->n_krcv_queues - 1);
13887 }
13888
13889 static void init_user_fecn_handling(struct hfi1_devdata *dd,
13890                                     struct rsm_map_table *rmt)
13891 {
13892         struct rsm_rule_data rrd;
13893         u64 reg;
13894         int i, idx, regoff, regidx;
13895         u8 offset;
13896
13897         /* there needs to be enough room in the map table */
13898         if (rmt->used + dd->num_user_contexts >= NUM_MAP_ENTRIES) {
13899                 dd_dev_err(dd, "User FECN handling disabled - too many user contexts allocated\n");
13900                 return;
13901         }
13902
13903         /*
13904          * RSM will extract the destination context as an index into the
13905          * map table.  The destination contexts are a sequential block
13906          * in the range first_user_ctxt...num_rcv_contexts-1 (inclusive).
13907          * Map entries are accessed as offset + extracted value.  Adjust
13908          * the added offset so this sequence can be placed anywhere in
13909          * the table - as long as the entries themselves do not wrap.
13910          * There are only enough bits in offset for the table size, so
13911          * start with that to allow for a "negative" offset.
13912          */
13913         offset = (u8)(NUM_MAP_ENTRIES + (int)rmt->used -
13914                                                 (int)dd->first_user_ctxt);
13915
13916         for (i = dd->first_user_ctxt, idx = rmt->used;
13917                                 i < dd->num_rcv_contexts; i++, idx++) {
13918                 /* replace with identity mapping */
13919                 regoff = (idx % 8) * 8;
13920                 regidx = idx / 8;
13921                 reg = rmt->map[regidx];
13922                 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK << regoff);
13923                 reg |= (u64)i << regoff;
13924                 rmt->map[regidx] = reg;
13925         }
13926
13927         /*
13928          * For RSM intercept of Expected FECN packets:
13929          * o packet type 0 - expected
13930          * o match on F (bit 95), using select/match 1, and
13931          * o match on SH (bit 133), using select/match 2.
13932          *
13933          * Use index 1 to extract the 8-bit receive context from DestQP
13934          * (start at bit 64).  Use that as the RSM map table index.
13935          */
13936         rrd.offset = offset;
13937         rrd.pkt_type = 0;
13938         rrd.field1_off = 95;
13939         rrd.field2_off = 133;
13940         rrd.index1_off = 64;
13941         rrd.index1_width = 8;
13942         rrd.index2_off = 0;
13943         rrd.index2_width = 0;
13944         rrd.mask1 = 1;
13945         rrd.value1 = 1;
13946         rrd.mask2 = 1;
13947         rrd.value2 = 1;
13948
13949         /* add rule 1 */
13950         add_rsm_rule(dd, 1, &rrd);
13951
13952         rmt->used += dd->num_user_contexts;
13953 }
13954
13955 static void init_rxe(struct hfi1_devdata *dd)
13956 {
13957         struct rsm_map_table *rmt;
13958
13959         /* enable all receive errors */
13960         write_csr(dd, RCV_ERR_MASK, ~0ull);
13961
13962         rmt = alloc_rsm_map_table(dd);
13963         /* set up QOS, including the QPN map table */
13964         init_qos(dd, rmt);
13965         init_user_fecn_handling(dd, rmt);
13966         complete_rsm_map_table(dd, rmt);
13967         kfree(rmt);
13968
13969         /*
13970          * make sure RcvCtrl.RcvWcb <= PCIe Device Control
13971          * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config
13972          * space, PciCfgCap2.MaxPayloadSize in HFI).  There is only one
13973          * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
13974          * Max_PayLoad_Size set to its minimum of 128.
13975          *
13976          * Presently, RcvCtrl.RcvWcb is not modified from its default of 0
13977          * (64 bytes).  Max_Payload_Size is possibly modified upward in
13978          * tune_pcie_caps() which is called after this routine.
13979          */
13980 }
13981
13982 static void init_other(struct hfi1_devdata *dd)
13983 {
13984         /* enable all CCE errors */
13985         write_csr(dd, CCE_ERR_MASK, ~0ull);
13986         /* enable *some* Misc errors */
13987         write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK);
13988         /* enable all DC errors, except LCB */
13989         write_csr(dd, DCC_ERR_FLG_EN, ~0ull);
13990         write_csr(dd, DC_DC8051_ERR_EN, ~0ull);
13991 }
13992
13993 /*
13994  * Fill out the given AU table using the given CU.  A CU is defined in terms
13995  * AUs.  The table is a an encoding: given the index, how many AUs does that
13996  * represent?
13997  *
13998  * NOTE: Assumes that the register layout is the same for the
13999  * local and remote tables.
14000  */
14001 static void assign_cm_au_table(struct hfi1_devdata *dd, u32 cu,
14002                                u32 csr0to3, u32 csr4to7)
14003 {
14004         write_csr(dd, csr0to3,
14005                   0ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT |
14006                   1ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT |
14007                   2ull * cu <<
14008                   SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT |
14009                   4ull * cu <<
14010                   SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT);
14011         write_csr(dd, csr4to7,
14012                   8ull * cu <<
14013                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT |
14014                   16ull * cu <<
14015                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT |
14016                   32ull * cu <<
14017                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT |
14018                   64ull * cu <<
14019                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT);
14020 }
14021
14022 static void assign_local_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
14023 {
14024         assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_LOCAL_AU_TABLE0_TO3,
14025                            SEND_CM_LOCAL_AU_TABLE4_TO7);
14026 }
14027
14028 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
14029 {
14030         assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_REMOTE_AU_TABLE0_TO3,
14031                            SEND_CM_REMOTE_AU_TABLE4_TO7);
14032 }
14033
14034 static void init_txe(struct hfi1_devdata *dd)
14035 {
14036         int i;
14037
14038         /* enable all PIO, SDMA, general, and Egress errors */
14039         write_csr(dd, SEND_PIO_ERR_MASK, ~0ull);
14040         write_csr(dd, SEND_DMA_ERR_MASK, ~0ull);
14041         write_csr(dd, SEND_ERR_MASK, ~0ull);
14042         write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull);
14043
14044         /* enable all per-context and per-SDMA engine errors */
14045         for (i = 0; i < dd->chip_send_contexts; i++)
14046                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, ~0ull);
14047         for (i = 0; i < dd->chip_sdma_engines; i++)
14048                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, ~0ull);
14049
14050         /* set the local CU to AU mapping */
14051         assign_local_cm_au_table(dd, dd->vcu);
14052
14053         /*
14054          * Set reasonable default for Credit Return Timer
14055          * Don't set on Simulator - causes it to choke.
14056          */
14057         if (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)
14058                 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE);
14059 }
14060
14061 int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt, u16 jkey)
14062 {
14063         struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
14064         unsigned sctxt;
14065         int ret = 0;
14066         u64 reg;
14067
14068         if (!rcd || !rcd->sc) {
14069                 ret = -EINVAL;
14070                 goto done;
14071         }
14072         sctxt = rcd->sc->hw_context;
14073         reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */
14074                 ((jkey & SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK) <<
14075                  SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT);
14076         /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */
14077         if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY))
14078                 reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK;
14079         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, reg);
14080         /*
14081          * Enable send-side J_KEY integrity check, unless this is A0 h/w
14082          */
14083         if (!is_ax(dd)) {
14084                 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14085                 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
14086                 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14087         }
14088
14089         /* Enable J_KEY check on receive context. */
14090         reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK |
14091                 ((jkey & RCV_KEY_CTRL_JOB_KEY_VALUE_MASK) <<
14092                  RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT);
14093         write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, reg);
14094 done:
14095         return ret;
14096 }
14097
14098 int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt)
14099 {
14100         struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
14101         unsigned sctxt;
14102         int ret = 0;
14103         u64 reg;
14104
14105         if (!rcd || !rcd->sc) {
14106                 ret = -EINVAL;
14107                 goto done;
14108         }
14109         sctxt = rcd->sc->hw_context;
14110         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, 0);
14111         /*
14112          * Disable send-side J_KEY integrity check, unless this is A0 h/w.
14113          * This check would not have been enabled for A0 h/w, see
14114          * set_ctxt_jkey().
14115          */
14116         if (!is_ax(dd)) {
14117                 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14118                 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
14119                 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14120         }
14121         /* Turn off the J_KEY on the receive side */
14122         write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, 0);
14123 done:
14124         return ret;
14125 }
14126
14127 int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt, u16 pkey)
14128 {
14129         struct hfi1_ctxtdata *rcd;
14130         unsigned sctxt;
14131         int ret = 0;
14132         u64 reg;
14133
14134         if (ctxt < dd->num_rcv_contexts) {
14135                 rcd = dd->rcd[ctxt];
14136         } else {
14137                 ret = -EINVAL;
14138                 goto done;
14139         }
14140         if (!rcd || !rcd->sc) {
14141                 ret = -EINVAL;
14142                 goto done;
14143         }
14144         sctxt = rcd->sc->hw_context;
14145         reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) <<
14146                 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT;
14147         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg);
14148         reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14149         reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
14150         reg &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK;
14151         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14152 done:
14153         return ret;
14154 }
14155
14156 int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt)
14157 {
14158         struct hfi1_ctxtdata *rcd;
14159         unsigned sctxt;
14160         int ret = 0;
14161         u64 reg;
14162
14163         if (ctxt < dd->num_rcv_contexts) {
14164                 rcd = dd->rcd[ctxt];
14165         } else {
14166                 ret = -EINVAL;
14167                 goto done;
14168         }
14169         if (!rcd || !rcd->sc) {
14170                 ret = -EINVAL;
14171                 goto done;
14172         }
14173         sctxt = rcd->sc->hw_context;
14174         reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14175         reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
14176         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14177         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_PARTITION_KEY, 0);
14178 done:
14179         return ret;
14180 }
14181
14182 /*
14183  * Start doing the clean up the the chip. Our clean up happens in multiple
14184  * stages and this is just the first.
14185  */
14186 void hfi1_start_cleanup(struct hfi1_devdata *dd)
14187 {
14188         aspm_exit(dd);
14189         free_cntrs(dd);
14190         free_rcverr(dd);
14191         clean_up_interrupts(dd);
14192         finish_chip_resources(dd);
14193 }
14194
14195 #define HFI_BASE_GUID(dev) \
14196         ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT))
14197
14198 /*
14199  * Information can be shared between the two HFIs on the same ASIC
14200  * in the same OS.  This function finds the peer device and sets
14201  * up a shared structure.
14202  */
14203 static int init_asic_data(struct hfi1_devdata *dd)
14204 {
14205         unsigned long flags;
14206         struct hfi1_devdata *tmp, *peer = NULL;
14207         struct hfi1_asic_data *asic_data;
14208         int ret = 0;
14209
14210         /* pre-allocate the asic structure in case we are the first device */
14211         asic_data = kzalloc(sizeof(*dd->asic_data), GFP_KERNEL);
14212         if (!asic_data)
14213                 return -ENOMEM;
14214
14215         spin_lock_irqsave(&hfi1_devs_lock, flags);
14216         /* Find our peer device */
14217         list_for_each_entry(tmp, &hfi1_dev_list, list) {
14218                 if ((HFI_BASE_GUID(dd) == HFI_BASE_GUID(tmp)) &&
14219                     dd->unit != tmp->unit) {
14220                         peer = tmp;
14221                         break;
14222                 }
14223         }
14224
14225         if (peer) {
14226                 /* use already allocated structure */
14227                 dd->asic_data = peer->asic_data;
14228                 kfree(asic_data);
14229         } else {
14230                 dd->asic_data = asic_data;
14231                 mutex_init(&dd->asic_data->asic_resource_mutex);
14232         }
14233         dd->asic_data->dds[dd->hfi1_id] = dd; /* self back-pointer */
14234         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
14235
14236         /* first one through - set up i2c devices */
14237         if (!peer)
14238                 ret = set_up_i2c(dd, dd->asic_data);
14239
14240         return ret;
14241 }
14242
14243 /*
14244  * Set dd->boardname.  Use a generic name if a name is not returned from
14245  * EFI variable space.
14246  *
14247  * Return 0 on success, -ENOMEM if space could not be allocated.
14248  */
14249 static int obtain_boardname(struct hfi1_devdata *dd)
14250 {
14251         /* generic board description */
14252         const char generic[] =
14253                 "Intel Omni-Path Host Fabric Interface Adapter 100 Series";
14254         unsigned long size;
14255         int ret;
14256
14257         ret = read_hfi1_efi_var(dd, "description", &size,
14258                                 (void **)&dd->boardname);
14259         if (ret) {
14260                 dd_dev_info(dd, "Board description not found\n");
14261                 /* use generic description */
14262                 dd->boardname = kstrdup(generic, GFP_KERNEL);
14263                 if (!dd->boardname)
14264                         return -ENOMEM;
14265         }
14266         return 0;
14267 }
14268
14269 /*
14270  * Check the interrupt registers to make sure that they are mapped correctly.
14271  * It is intended to help user identify any mismapping by VMM when the driver
14272  * is running in a VM. This function should only be called before interrupt
14273  * is set up properly.
14274  *
14275  * Return 0 on success, -EINVAL on failure.
14276  */
14277 static int check_int_registers(struct hfi1_devdata *dd)
14278 {
14279         u64 reg;
14280         u64 all_bits = ~(u64)0;
14281         u64 mask;
14282
14283         /* Clear CceIntMask[0] to avoid raising any interrupts */
14284         mask = read_csr(dd, CCE_INT_MASK);
14285         write_csr(dd, CCE_INT_MASK, 0ull);
14286         reg = read_csr(dd, CCE_INT_MASK);
14287         if (reg)
14288                 goto err_exit;
14289
14290         /* Clear all interrupt status bits */
14291         write_csr(dd, CCE_INT_CLEAR, all_bits);
14292         reg = read_csr(dd, CCE_INT_STATUS);
14293         if (reg)
14294                 goto err_exit;
14295
14296         /* Set all interrupt status bits */
14297         write_csr(dd, CCE_INT_FORCE, all_bits);
14298         reg = read_csr(dd, CCE_INT_STATUS);
14299         if (reg != all_bits)
14300                 goto err_exit;
14301
14302         /* Restore the interrupt mask */
14303         write_csr(dd, CCE_INT_CLEAR, all_bits);
14304         write_csr(dd, CCE_INT_MASK, mask);
14305
14306         return 0;
14307 err_exit:
14308         write_csr(dd, CCE_INT_MASK, mask);
14309         dd_dev_err(dd, "Interrupt registers not properly mapped by VMM\n");
14310         return -EINVAL;
14311 }
14312
14313 /**
14314  * Allocate and initialize the device structure for the hfi.
14315  * @dev: the pci_dev for hfi1_ib device
14316  * @ent: pci_device_id struct for this dev
14317  *
14318  * Also allocates, initializes, and returns the devdata struct for this
14319  * device instance
14320  *
14321  * This is global, and is called directly at init to set up the
14322  * chip-specific function pointers for later use.
14323  */
14324 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
14325                                   const struct pci_device_id *ent)
14326 {
14327         struct hfi1_devdata *dd;
14328         struct hfi1_pportdata *ppd;
14329         u64 reg;
14330         int i, ret;
14331         static const char * const inames[] = { /* implementation names */
14332                 "RTL silicon",
14333                 "RTL VCS simulation",
14334                 "RTL FPGA emulation",
14335                 "Functional simulator"
14336         };
14337         struct pci_dev *parent = pdev->bus->self;
14338
14339         dd = hfi1_alloc_devdata(pdev, NUM_IB_PORTS *
14340                                 sizeof(struct hfi1_pportdata));
14341         if (IS_ERR(dd))
14342                 goto bail;
14343         ppd = dd->pport;
14344         for (i = 0; i < dd->num_pports; i++, ppd++) {
14345                 int vl;
14346                 /* init common fields */
14347                 hfi1_init_pportdata(pdev, ppd, dd, 0, 1);
14348                 /* DC supports 4 link widths */
14349                 ppd->link_width_supported =
14350                         OPA_LINK_WIDTH_1X | OPA_LINK_WIDTH_2X |
14351                         OPA_LINK_WIDTH_3X | OPA_LINK_WIDTH_4X;
14352                 ppd->link_width_downgrade_supported =
14353                         ppd->link_width_supported;
14354                 /* start out enabling only 4X */
14355                 ppd->link_width_enabled = OPA_LINK_WIDTH_4X;
14356                 ppd->link_width_downgrade_enabled =
14357                                         ppd->link_width_downgrade_supported;
14358                 /* link width active is 0 when link is down */
14359                 /* link width downgrade active is 0 when link is down */
14360
14361                 if (num_vls < HFI1_MIN_VLS_SUPPORTED ||
14362                     num_vls > HFI1_MAX_VLS_SUPPORTED) {
14363                         hfi1_early_err(&pdev->dev,
14364                                        "Invalid num_vls %u, using %u VLs\n",
14365                                     num_vls, HFI1_MAX_VLS_SUPPORTED);
14366                         num_vls = HFI1_MAX_VLS_SUPPORTED;
14367                 }
14368                 ppd->vls_supported = num_vls;
14369                 ppd->vls_operational = ppd->vls_supported;
14370                 ppd->actual_vls_operational = ppd->vls_supported;
14371                 /* Set the default MTU. */
14372                 for (vl = 0; vl < num_vls; vl++)
14373                         dd->vld[vl].mtu = hfi1_max_mtu;
14374                 dd->vld[15].mtu = MAX_MAD_PACKET;
14375                 /*
14376                  * Set the initial values to reasonable default, will be set
14377                  * for real when link is up.
14378                  */
14379                 ppd->lstate = IB_PORT_DOWN;
14380                 ppd->overrun_threshold = 0x4;
14381                 ppd->phy_error_threshold = 0xf;
14382                 ppd->port_crc_mode_enabled = link_crc_mask;
14383                 /* initialize supported LTP CRC mode */
14384                 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
14385                 /* initialize enabled LTP CRC mode */
14386                 ppd->port_ltp_crc_mode |= cap_to_port_ltp(link_crc_mask) << 4;
14387                 /* start in offline */
14388                 ppd->host_link_state = HLS_DN_OFFLINE;
14389                 init_vl_arb_caches(ppd);
14390                 ppd->last_pstate = 0xff; /* invalid value */
14391         }
14392
14393         dd->link_default = HLS_DN_POLL;
14394
14395         /*
14396          * Do remaining PCIe setup and save PCIe values in dd.
14397          * Any error printing is already done by the init code.
14398          * On return, we have the chip mapped.
14399          */
14400         ret = hfi1_pcie_ddinit(dd, pdev, ent);
14401         if (ret < 0)
14402                 goto bail_free;
14403
14404         /* verify that reads actually work, save revision for reset check */
14405         dd->revision = read_csr(dd, CCE_REVISION);
14406         if (dd->revision == ~(u64)0) {
14407                 dd_dev_err(dd, "cannot read chip CSRs\n");
14408                 ret = -EINVAL;
14409                 goto bail_cleanup;
14410         }
14411         dd->majrev = (dd->revision >> CCE_REVISION_CHIP_REV_MAJOR_SHIFT)
14412                         & CCE_REVISION_CHIP_REV_MAJOR_MASK;
14413         dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT)
14414                         & CCE_REVISION_CHIP_REV_MINOR_MASK;
14415
14416         /*
14417          * Check interrupt registers mapping if the driver has no access to
14418          * the upstream component. In this case, it is likely that the driver
14419          * is running in a VM.
14420          */
14421         if (!parent) {
14422                 ret = check_int_registers(dd);
14423                 if (ret)
14424                         goto bail_cleanup;
14425         }
14426
14427         /*
14428          * obtain the hardware ID - NOT related to unit, which is a
14429          * software enumeration
14430          */
14431         reg = read_csr(dd, CCE_REVISION2);
14432         dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT)
14433                                         & CCE_REVISION2_HFI_ID_MASK;
14434         /* the variable size will remove unwanted bits */
14435         dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT;
14436         dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT;
14437         dd_dev_info(dd, "Implementation: %s, revision 0x%x\n",
14438                     dd->icode < ARRAY_SIZE(inames) ?
14439                     inames[dd->icode] : "unknown", (int)dd->irev);
14440
14441         /* speeds the hardware can support */
14442         dd->pport->link_speed_supported = OPA_LINK_SPEED_25G;
14443         /* speeds allowed to run at */
14444         dd->pport->link_speed_enabled = dd->pport->link_speed_supported;
14445         /* give a reasonable active value, will be set on link up */
14446         dd->pport->link_speed_active = OPA_LINK_SPEED_25G;
14447
14448         dd->chip_rcv_contexts = read_csr(dd, RCV_CONTEXTS);
14449         dd->chip_send_contexts = read_csr(dd, SEND_CONTEXTS);
14450         dd->chip_sdma_engines = read_csr(dd, SEND_DMA_ENGINES);
14451         dd->chip_pio_mem_size = read_csr(dd, SEND_PIO_MEM_SIZE);
14452         dd->chip_sdma_mem_size = read_csr(dd, SEND_DMA_MEM_SIZE);
14453         /* fix up link widths for emulation _p */
14454         ppd = dd->pport;
14455         if (dd->icode == ICODE_FPGA_EMULATION && is_emulator_p(dd)) {
14456                 ppd->link_width_supported =
14457                         ppd->link_width_enabled =
14458                         ppd->link_width_downgrade_supported =
14459                         ppd->link_width_downgrade_enabled =
14460                                 OPA_LINK_WIDTH_1X;
14461         }
14462         /* insure num_vls isn't larger than number of sdma engines */
14463         if (HFI1_CAP_IS_KSET(SDMA) && num_vls > dd->chip_sdma_engines) {
14464                 dd_dev_err(dd, "num_vls %u too large, using %u VLs\n",
14465                            num_vls, dd->chip_sdma_engines);
14466                 num_vls = dd->chip_sdma_engines;
14467                 ppd->vls_supported = dd->chip_sdma_engines;
14468                 ppd->vls_operational = ppd->vls_supported;
14469         }
14470
14471         /*
14472          * Convert the ns parameter to the 64 * cclocks used in the CSR.
14473          * Limit the max if larger than the field holds.  If timeout is
14474          * non-zero, then the calculated field will be at least 1.
14475          *
14476          * Must be after icode is set up - the cclock rate depends
14477          * on knowing the hardware being used.
14478          */
14479         dd->rcv_intr_timeout_csr = ns_to_cclock(dd, rcv_intr_timeout) / 64;
14480         if (dd->rcv_intr_timeout_csr >
14481                         RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK)
14482                 dd->rcv_intr_timeout_csr =
14483                         RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK;
14484         else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout)
14485                 dd->rcv_intr_timeout_csr = 1;
14486
14487         /* needs to be done before we look for the peer device */
14488         read_guid(dd);
14489
14490         /* set up shared ASIC data with peer device */
14491         ret = init_asic_data(dd);
14492         if (ret)
14493                 goto bail_cleanup;
14494
14495         /* obtain chip sizes, reset chip CSRs */
14496         init_chip(dd);
14497
14498         /* read in the PCIe link speed information */
14499         ret = pcie_speeds(dd);
14500         if (ret)
14501                 goto bail_cleanup;
14502
14503         /* Needs to be called before hfi1_firmware_init */
14504         get_platform_config(dd);
14505
14506         /* read in firmware */
14507         ret = hfi1_firmware_init(dd);
14508         if (ret)
14509                 goto bail_cleanup;
14510
14511         /*
14512          * In general, the PCIe Gen3 transition must occur after the
14513          * chip has been idled (so it won't initiate any PCIe transactions
14514          * e.g. an interrupt) and before the driver changes any registers
14515          * (the transition will reset the registers).
14516          *
14517          * In particular, place this call after:
14518          * - init_chip()     - the chip will not initiate any PCIe transactions
14519          * - pcie_speeds()   - reads the current link speed
14520          * - hfi1_firmware_init() - the needed firmware is ready to be
14521          *                          downloaded
14522          */
14523         ret = do_pcie_gen3_transition(dd);
14524         if (ret)
14525                 goto bail_cleanup;
14526
14527         /* start setting dd values and adjusting CSRs */
14528         init_early_variables(dd);
14529
14530         parse_platform_config(dd);
14531
14532         ret = obtain_boardname(dd);
14533         if (ret)
14534                 goto bail_cleanup;
14535
14536         snprintf(dd->boardversion, BOARD_VERS_MAX,
14537                  "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n",
14538                  HFI1_CHIP_VERS_MAJ, HFI1_CHIP_VERS_MIN,
14539                  (u32)dd->majrev,
14540                  (u32)dd->minrev,
14541                  (dd->revision >> CCE_REVISION_SW_SHIFT)
14542                     & CCE_REVISION_SW_MASK);
14543
14544         ret = set_up_context_variables(dd);
14545         if (ret)
14546                 goto bail_cleanup;
14547
14548         /* set initial RXE CSRs */
14549         init_rxe(dd);
14550         /* set initial TXE CSRs */
14551         init_txe(dd);
14552         /* set initial non-RXE, non-TXE CSRs */
14553         init_other(dd);
14554         /* set up KDETH QP prefix in both RX and TX CSRs */
14555         init_kdeth_qp(dd);
14556
14557         ret = hfi1_dev_affinity_init(dd);
14558         if (ret)
14559                 goto bail_cleanup;
14560
14561         /* send contexts must be set up before receive contexts */
14562         ret = init_send_contexts(dd);
14563         if (ret)
14564                 goto bail_cleanup;
14565
14566         ret = hfi1_create_ctxts(dd);
14567         if (ret)
14568                 goto bail_cleanup;
14569
14570         dd->rcvhdrsize = DEFAULT_RCVHDRSIZE;
14571         /*
14572          * rcd[0] is guaranteed to be valid by this point. Also, all
14573          * context are using the same value, as per the module parameter.
14574          */
14575         dd->rhf_offset = dd->rcd[0]->rcvhdrqentsize - sizeof(u64) / sizeof(u32);
14576
14577         ret = init_pervl_scs(dd);
14578         if (ret)
14579                 goto bail_cleanup;
14580
14581         /* sdma init */
14582         for (i = 0; i < dd->num_pports; ++i) {
14583                 ret = sdma_init(dd, i);
14584                 if (ret)
14585                         goto bail_cleanup;
14586         }
14587
14588         /* use contexts created by hfi1_create_ctxts */
14589         ret = set_up_interrupts(dd);
14590         if (ret)
14591                 goto bail_cleanup;
14592
14593         /* set up LCB access - must be after set_up_interrupts() */
14594         init_lcb_access(dd);
14595
14596         /*
14597          * Serial number is created from the base guid:
14598          * [27:24] = base guid [38:35]
14599          * [23: 0] = base guid [23: 0]
14600          */
14601         snprintf(dd->serial, SERIAL_MAX, "0x%08llx\n",
14602                  (dd->base_guid & 0xFFFFFF) |
14603                      ((dd->base_guid >> 11) & 0xF000000));
14604
14605         dd->oui1 = dd->base_guid >> 56 & 0xFF;
14606         dd->oui2 = dd->base_guid >> 48 & 0xFF;
14607         dd->oui3 = dd->base_guid >> 40 & 0xFF;
14608
14609         ret = load_firmware(dd); /* asymmetric with dispose_firmware() */
14610         if (ret)
14611                 goto bail_clear_intr;
14612
14613         thermal_init(dd);
14614
14615         ret = init_cntrs(dd);
14616         if (ret)
14617                 goto bail_clear_intr;
14618
14619         ret = init_rcverr(dd);
14620         if (ret)
14621                 goto bail_free_cntrs;
14622
14623         ret = eprom_init(dd);
14624         if (ret)
14625                 goto bail_free_rcverr;
14626
14627         goto bail;
14628
14629 bail_free_rcverr:
14630         free_rcverr(dd);
14631 bail_free_cntrs:
14632         free_cntrs(dd);
14633 bail_clear_intr:
14634         clean_up_interrupts(dd);
14635 bail_cleanup:
14636         hfi1_pcie_ddcleanup(dd);
14637 bail_free:
14638         hfi1_free_devdata(dd);
14639         dd = ERR_PTR(ret);
14640 bail:
14641         return dd;
14642 }
14643
14644 static u16 delay_cycles(struct hfi1_pportdata *ppd, u32 desired_egress_rate,
14645                         u32 dw_len)
14646 {
14647         u32 delta_cycles;
14648         u32 current_egress_rate = ppd->current_egress_rate;
14649         /* rates here are in units of 10^6 bits/sec */
14650
14651         if (desired_egress_rate == -1)
14652                 return 0; /* shouldn't happen */
14653
14654         if (desired_egress_rate >= current_egress_rate)
14655                 return 0; /* we can't help go faster, only slower */
14656
14657         delta_cycles = egress_cycles(dw_len * 4, desired_egress_rate) -
14658                         egress_cycles(dw_len * 4, current_egress_rate);
14659
14660         return (u16)delta_cycles;
14661 }
14662
14663 /**
14664  * create_pbc - build a pbc for transmission
14665  * @flags: special case flags or-ed in built pbc
14666  * @srate: static rate
14667  * @vl: vl
14668  * @dwlen: dword length (header words + data words + pbc words)
14669  *
14670  * Create a PBC with the given flags, rate, VL, and length.
14671  *
14672  * NOTE: The PBC created will not insert any HCRC - all callers but one are
14673  * for verbs, which does not use this PSM feature.  The lone other caller
14674  * is for the diagnostic interface which calls this if the user does not
14675  * supply their own PBC.
14676  */
14677 u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl,
14678                u32 dw_len)
14679 {
14680         u64 pbc, delay = 0;
14681
14682         if (unlikely(srate_mbs))
14683                 delay = delay_cycles(ppd, srate_mbs, dw_len);
14684
14685         pbc = flags
14686                 | (delay << PBC_STATIC_RATE_CONTROL_COUNT_SHIFT)
14687                 | ((u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT)
14688                 | (vl & PBC_VL_MASK) << PBC_VL_SHIFT
14689                 | (dw_len & PBC_LENGTH_DWS_MASK)
14690                         << PBC_LENGTH_DWS_SHIFT;
14691
14692         return pbc;
14693 }
14694
14695 #define SBUS_THERMAL    0x4f
14696 #define SBUS_THERM_MONITOR_MODE 0x1
14697
14698 #define THERM_FAILURE(dev, ret, reason) \
14699         dd_dev_err((dd),                                                \
14700                    "Thermal sensor initialization failed: %s (%d)\n",   \
14701                    (reason), (ret))
14702
14703 /*
14704  * Initialize the thermal sensor.
14705  *
14706  * After initialization, enable polling of thermal sensor through
14707  * SBus interface. In order for this to work, the SBus Master
14708  * firmware has to be loaded due to the fact that the HW polling
14709  * logic uses SBus interrupts, which are not supported with
14710  * default firmware. Otherwise, no data will be returned through
14711  * the ASIC_STS_THERM CSR.
14712  */
14713 static int thermal_init(struct hfi1_devdata *dd)
14714 {
14715         int ret = 0;
14716
14717         if (dd->icode != ICODE_RTL_SILICON ||
14718             check_chip_resource(dd, CR_THERM_INIT, NULL))
14719                 return ret;
14720
14721         ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
14722         if (ret) {
14723                 THERM_FAILURE(dd, ret, "Acquire SBus");
14724                 return ret;
14725         }
14726
14727         dd_dev_info(dd, "Initializing thermal sensor\n");
14728         /* Disable polling of thermal readings */
14729         write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
14730         msleep(100);
14731         /* Thermal Sensor Initialization */
14732         /*    Step 1: Reset the Thermal SBus Receiver */
14733         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14734                                 RESET_SBUS_RECEIVER, 0);
14735         if (ret) {
14736                 THERM_FAILURE(dd, ret, "Bus Reset");
14737                 goto done;
14738         }
14739         /*    Step 2: Set Reset bit in Thermal block */
14740         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14741                                 WRITE_SBUS_RECEIVER, 0x1);
14742         if (ret) {
14743                 THERM_FAILURE(dd, ret, "Therm Block Reset");
14744                 goto done;
14745         }
14746         /*    Step 3: Write clock divider value (100MHz -> 2MHz) */
14747         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x1,
14748                                 WRITE_SBUS_RECEIVER, 0x32);
14749         if (ret) {
14750                 THERM_FAILURE(dd, ret, "Write Clock Div");
14751                 goto done;
14752         }
14753         /*    Step 4: Select temperature mode */
14754         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x3,
14755                                 WRITE_SBUS_RECEIVER,
14756                                 SBUS_THERM_MONITOR_MODE);
14757         if (ret) {
14758                 THERM_FAILURE(dd, ret, "Write Mode Sel");
14759                 goto done;
14760         }
14761         /*    Step 5: De-assert block reset and start conversion */
14762         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14763                                 WRITE_SBUS_RECEIVER, 0x2);
14764         if (ret) {
14765                 THERM_FAILURE(dd, ret, "Write Reset Deassert");
14766                 goto done;
14767         }
14768         /*    Step 5.1: Wait for first conversion (21.5ms per spec) */
14769         msleep(22);
14770
14771         /* Enable polling of thermal readings */
14772         write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
14773
14774         /* Set initialized flag */
14775         ret = acquire_chip_resource(dd, CR_THERM_INIT, 0);
14776         if (ret)
14777                 THERM_FAILURE(dd, ret, "Unable to set thermal init flag");
14778
14779 done:
14780         release_chip_resource(dd, CR_SBUS);
14781         return ret;
14782 }
14783
14784 static void handle_temp_err(struct hfi1_devdata *dd)
14785 {
14786         struct hfi1_pportdata *ppd = &dd->pport[0];
14787         /*
14788          * Thermal Critical Interrupt
14789          * Put the device into forced freeze mode, take link down to
14790          * offline, and put DC into reset.
14791          */
14792         dd_dev_emerg(dd,
14793                      "Critical temperature reached! Forcing device into freeze mode!\n");
14794         dd->flags |= HFI1_FORCED_FREEZE;
14795         start_freeze_handling(ppd, FREEZE_SELF | FREEZE_ABORT);
14796         /*
14797          * Shut DC down as much and as quickly as possible.
14798          *
14799          * Step 1: Take the link down to OFFLINE. This will cause the
14800          *         8051 to put the Serdes in reset. However, we don't want to
14801          *         go through the entire link state machine since we want to
14802          *         shutdown ASAP. Furthermore, this is not a graceful shutdown
14803          *         but rather an attempt to save the chip.
14804          *         Code below is almost the same as quiet_serdes() but avoids
14805          *         all the extra work and the sleeps.
14806          */
14807         ppd->driver_link_ready = 0;
14808         ppd->link_enabled = 0;
14809         set_physical_link_state(dd, (OPA_LINKDOWN_REASON_SMA_DISABLED << 8) |
14810                                 PLS_OFFLINE);
14811         /*
14812          * Step 2: Shutdown LCB and 8051
14813          *         After shutdown, do not restore DC_CFG_RESET value.
14814          */
14815         dc_shutdown(dd);
14816 }