2 * Broadcom NetXtreme-E RoCE driver.
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Description: Slow Path Operators
39 #define dev_fmt(fmt) "QPLIB: " fmt
41 #include <linux/interrupt.h>
42 #include <linux/spinlock.h>
43 #include <linux/sched.h>
44 #include <linux/pci.h>
48 #include "qplib_res.h"
49 #include "qplib_rcfw.h"
51 #include "qplib_tlv.h"
53 const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0,
54 0, 0, 0, 0, 0, 0, 0, 0 } };
58 static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw)
62 if (!bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx))
65 pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2);
66 return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ);
69 static void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw,
72 struct creq_query_version_resp resp = {};
73 struct bnxt_qplib_cmdqmsg msg = {};
74 struct cmdq_query_version req = {};
77 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
78 CMDQ_BASE_OPCODE_QUERY_VERSION,
81 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0);
82 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
85 fw_ver[0] = resp.fw_maj;
86 fw_ver[1] = resp.fw_minor;
87 fw_ver[2] = resp.fw_bld;
88 fw_ver[3] = resp.fw_rsvd;
91 int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw,
92 struct bnxt_qplib_dev_attr *attr, bool vf)
94 struct creq_query_func_resp resp = {};
95 struct bnxt_qplib_cmdqmsg msg = {};
96 struct creq_query_func_resp_sb *sb;
97 struct bnxt_qplib_rcfw_sbuf *sbuf;
98 struct cmdq_query_func req = {};
103 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
104 CMDQ_BASE_OPCODE_QUERY_FUNC,
107 sbuf = bnxt_qplib_rcfw_alloc_sbuf(rcfw, sizeof(*sb));
109 dev_err(&rcfw->pdev->dev,
110 "SP: QUERY_FUNC alloc side buffer failed\n");
115 req.resp_size = sizeof(*sb) / BNXT_QPLIB_CMDQE_UNITS;
116 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, sbuf, sizeof(req),
118 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
122 /* Extract the context from the side buffer */
123 attr->max_qp = le32_to_cpu(sb->max_qp);
124 /* max_qp value reported by FW for PF doesn't include the QP1 for PF */
127 attr->max_qp_rd_atom =
128 sb->max_qp_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ?
129 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_rd_atom;
130 attr->max_qp_init_rd_atom =
131 sb->max_qp_init_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ?
132 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_init_rd_atom;
133 attr->max_qp_wqes = le16_to_cpu(sb->max_qp_wr);
135 * 128 WQEs needs to be reserved for the HW (8916). Prevent
136 * reporting the max number
138 attr->max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS + 1;
139 attr->max_qp_sges = bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx) ?
141 attr->max_cq = le32_to_cpu(sb->max_cq);
142 attr->max_cq_wqes = le32_to_cpu(sb->max_cqe);
143 attr->max_cq_sges = attr->max_qp_sges;
144 attr->max_mr = le32_to_cpu(sb->max_mr);
145 attr->max_mw = le32_to_cpu(sb->max_mw);
147 attr->max_mr_size = le64_to_cpu(sb->max_mr_size);
148 attr->max_pd = 64 * 1024;
149 attr->max_raw_ethy_qp = le32_to_cpu(sb->max_raw_eth_qp);
150 attr->max_ah = le32_to_cpu(sb->max_ah);
152 attr->max_srq = le16_to_cpu(sb->max_srq);
153 attr->max_srq_wqes = le32_to_cpu(sb->max_srq_wr) - 1;
154 attr->max_srq_sges = sb->max_srq_sge;
156 attr->max_inline_data = le32_to_cpu(sb->max_inline_data);
157 attr->l2_db_size = (sb->l2_db_space_size + 1) *
158 (0x01 << RCFW_DBR_BASE_PAGE_SHIFT);
159 attr->max_sgid = BNXT_QPLIB_NUM_GIDS_SUPPORTED;
160 attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags);
162 bnxt_qplib_query_version(rcfw, attr->fw_ver);
164 for (i = 0; i < MAX_TQM_ALLOC_REQ / 4; i++) {
165 temp = le32_to_cpu(sb->tqm_alloc_reqs[i]);
166 tqm_alloc = (u8 *)&temp;
167 attr->tqm_alloc_reqs[i * 4] = *tqm_alloc;
168 attr->tqm_alloc_reqs[i * 4 + 1] = *(++tqm_alloc);
169 attr->tqm_alloc_reqs[i * 4 + 2] = *(++tqm_alloc);
170 attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc);
173 attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw);
175 bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf);
179 int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res,
180 struct bnxt_qplib_rcfw *rcfw,
181 struct bnxt_qplib_ctx *ctx)
183 struct creq_set_func_resources_resp resp = {};
184 struct cmdq_set_func_resources req = {};
185 struct bnxt_qplib_cmdqmsg msg = {};
188 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
189 CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES,
192 req.number_of_qp = cpu_to_le32(ctx->qpc_count);
193 req.number_of_mrw = cpu_to_le32(ctx->mrw_count);
194 req.number_of_srq = cpu_to_le32(ctx->srqc_count);
195 req.number_of_cq = cpu_to_le32(ctx->cq_count);
197 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf);
198 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf);
199 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf);
200 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf);
201 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf);
203 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
205 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
207 dev_err(&res->pdev->dev, "Failed to set function resources\n");
213 int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res,
214 struct bnxt_qplib_sgid_tbl *sgid_tbl, int index,
215 struct bnxt_qplib_gid *gid)
217 if (index >= sgid_tbl->max) {
218 dev_err(&res->pdev->dev,
219 "Index %d exceeded SGID table max (%d)\n",
220 index, sgid_tbl->max);
223 memcpy(gid, &sgid_tbl->tbl[index].gid, sizeof(*gid));
227 int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl,
228 struct bnxt_qplib_gid *gid, u16 vlan_id, bool update)
230 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl,
231 struct bnxt_qplib_res,
233 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
237 dev_err(&res->pdev->dev, "SGID table not allocated\n");
240 /* Do we need a sgid_lock here? */
241 if (!sgid_tbl->active) {
242 dev_err(&res->pdev->dev, "SGID table has no active entries\n");
245 for (index = 0; index < sgid_tbl->max; index++) {
246 if (!memcmp(&sgid_tbl->tbl[index].gid, gid, sizeof(*gid)) &&
247 vlan_id == sgid_tbl->tbl[index].vlan_id)
250 if (index == sgid_tbl->max) {
251 dev_warn(&res->pdev->dev, "GID not found in the SGID table\n");
254 /* Remove GID from the SGID table */
256 struct creq_delete_gid_resp resp = {};
257 struct bnxt_qplib_cmdqmsg msg = {};
258 struct cmdq_delete_gid req = {};
261 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
262 CMDQ_BASE_OPCODE_DELETE_GID,
264 if (sgid_tbl->hw_id[index] == 0xFFFF) {
265 dev_err(&res->pdev->dev,
266 "GID entry contains an invalid HW id\n");
269 req.gid_index = cpu_to_le16(sgid_tbl->hw_id[index]);
270 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
272 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
276 memcpy(&sgid_tbl->tbl[index].gid, &bnxt_qplib_gid_zero,
277 sizeof(bnxt_qplib_gid_zero));
278 sgid_tbl->tbl[index].vlan_id = 0xFFFF;
279 sgid_tbl->vlan[index] = 0;
281 dev_dbg(&res->pdev->dev,
282 "SGID deleted hw_id[0x%x] = 0x%x active = 0x%x\n",
283 index, sgid_tbl->hw_id[index], sgid_tbl->active);
284 sgid_tbl->hw_id[index] = (u16)-1;
290 int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl,
291 struct bnxt_qplib_gid *gid, const u8 *smac,
292 u16 vlan_id, bool update, u32 *index)
294 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl,
295 struct bnxt_qplib_res,
297 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
301 dev_err(&res->pdev->dev, "SGID table not allocated\n");
304 /* Do we need a sgid_lock here? */
305 if (sgid_tbl->active == sgid_tbl->max) {
306 dev_err(&res->pdev->dev, "SGID table is full\n");
309 free_idx = sgid_tbl->max;
310 for (i = 0; i < sgid_tbl->max; i++) {
311 if (!memcmp(&sgid_tbl->tbl[i], gid, sizeof(*gid)) &&
312 sgid_tbl->tbl[i].vlan_id == vlan_id) {
313 dev_dbg(&res->pdev->dev,
314 "SGID entry already exist in entry %d!\n", i);
317 } else if (!memcmp(&sgid_tbl->tbl[i], &bnxt_qplib_gid_zero,
318 sizeof(bnxt_qplib_gid_zero)) &&
319 free_idx == sgid_tbl->max) {
323 if (free_idx == sgid_tbl->max) {
324 dev_err(&res->pdev->dev,
325 "SGID table is FULL but count is not MAX??\n");
329 struct creq_add_gid_resp resp = {};
330 struct bnxt_qplib_cmdqmsg msg = {};
331 struct cmdq_add_gid req = {};
334 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
335 CMDQ_BASE_OPCODE_ADD_GID,
338 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]);
339 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]);
340 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]);
341 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]);
343 * driver should ensure that all RoCE traffic is always VLAN
344 * tagged if RoCE traffic is running on non-zero VLAN ID or
345 * RoCE traffic is running on non-zero Priority.
347 if ((vlan_id != 0xFFFF) || res->prio) {
348 if (vlan_id != 0xFFFF)
349 req.vlan = cpu_to_le16
350 (vlan_id & CMDQ_ADD_GID_VLAN_VLAN_ID_MASK);
351 req.vlan |= cpu_to_le16
352 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 |
353 CMDQ_ADD_GID_VLAN_VLAN_EN);
356 /* MAC in network format */
357 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]);
358 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]);
359 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]);
361 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
363 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
366 sgid_tbl->hw_id[free_idx] = le32_to_cpu(resp.xid);
368 /* Add GID to the sgid_tbl */
369 memcpy(&sgid_tbl->tbl[free_idx], gid, sizeof(*gid));
370 sgid_tbl->tbl[free_idx].vlan_id = vlan_id;
372 if (vlan_id != 0xFFFF)
373 sgid_tbl->vlan[free_idx] = 1;
375 dev_dbg(&res->pdev->dev,
376 "SGID added hw_id[0x%x] = 0x%x active = 0x%x\n",
377 free_idx, sgid_tbl->hw_id[free_idx], sgid_tbl->active);
384 int bnxt_qplib_update_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl,
385 struct bnxt_qplib_gid *gid, u16 gid_idx,
388 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl,
389 struct bnxt_qplib_res,
391 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
392 struct creq_modify_gid_resp resp = {};
393 struct bnxt_qplib_cmdqmsg msg = {};
394 struct cmdq_modify_gid req = {};
397 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
398 CMDQ_BASE_OPCODE_MODIFY_GID,
401 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]);
402 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]);
403 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]);
404 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]);
406 req.vlan |= cpu_to_le16
407 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 |
408 CMDQ_ADD_GID_VLAN_VLAN_EN);
411 /* MAC in network format */
412 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]);
413 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]);
414 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]);
416 req.gid_index = cpu_to_le16(gid_idx);
418 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
420 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
425 int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah,
428 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
429 struct creq_create_ah_resp resp = {};
430 struct bnxt_qplib_cmdqmsg msg = {};
431 struct cmdq_create_ah req = {};
436 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
437 CMDQ_BASE_OPCODE_CREATE_AH,
440 memcpy(temp32, ah->dgid.data, sizeof(struct bnxt_qplib_gid));
441 req.dgid[0] = cpu_to_le32(temp32[0]);
442 req.dgid[1] = cpu_to_le32(temp32[1]);
443 req.dgid[2] = cpu_to_le32(temp32[2]);
444 req.dgid[3] = cpu_to_le32(temp32[3]);
446 req.type = ah->nw_type;
447 req.hop_limit = ah->hop_limit;
448 req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id[ah->sgid_index]);
449 req.dest_vlan_id_flow_label = cpu_to_le32((ah->flow_label &
450 CMDQ_CREATE_AH_FLOW_LABEL_MASK) |
451 CMDQ_CREATE_AH_DEST_VLAN_ID_MASK);
452 req.pd_id = cpu_to_le32(ah->pd->id);
453 req.traffic_class = ah->traffic_class;
455 /* MAC in network format */
456 memcpy(temp16, ah->dmac, 6);
457 req.dest_mac[0] = cpu_to_le16(temp16[0]);
458 req.dest_mac[1] = cpu_to_le16(temp16[1]);
459 req.dest_mac[2] = cpu_to_le16(temp16[2]);
461 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
462 sizeof(resp), block);
463 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
467 ah->id = le32_to_cpu(resp.xid);
471 void bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah,
474 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
475 struct creq_destroy_ah_resp resp = {};
476 struct bnxt_qplib_cmdqmsg msg = {};
477 struct cmdq_destroy_ah req = {};
479 /* Clean up the AH table in the device */
480 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
481 CMDQ_BASE_OPCODE_DESTROY_AH,
484 req.ah_cid = cpu_to_le32(ah->id);
486 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
487 sizeof(resp), block);
488 bnxt_qplib_rcfw_send_message(rcfw, &msg);
492 int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw)
494 struct creq_deallocate_key_resp resp = {};
495 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
496 struct cmdq_deallocate_key req = {};
497 struct bnxt_qplib_cmdqmsg msg = {};
500 if (mrw->lkey == 0xFFFFFFFF) {
501 dev_info(&res->pdev->dev, "SP: Free a reserved lkey MRW\n");
505 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
506 CMDQ_BASE_OPCODE_DEALLOCATE_KEY,
509 req.mrw_flags = mrw->type;
511 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) ||
512 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) ||
513 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B))
514 req.key = cpu_to_le32(mrw->rkey);
516 req.key = cpu_to_le32(mrw->lkey);
518 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
520 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
524 /* Free the qplib's MRW memory */
525 if (mrw->hwq.max_elements)
526 bnxt_qplib_free_hwq(res, &mrw->hwq);
531 int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw)
533 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
534 struct creq_allocate_mrw_resp resp = {};
535 struct bnxt_qplib_cmdqmsg msg = {};
536 struct cmdq_allocate_mrw req = {};
540 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
541 CMDQ_BASE_OPCODE_ALLOCATE_MRW,
544 req.pd_id = cpu_to_le32(mrw->pd->id);
545 req.mrw_flags = mrw->type;
546 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR &&
547 mrw->flags & BNXT_QPLIB_FR_PMR) ||
548 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A ||
549 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)
550 req.access = CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY;
551 tmp = (unsigned long)mrw;
552 req.mrw_handle = cpu_to_le64(tmp);
554 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
556 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
560 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) ||
561 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) ||
562 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B))
563 mrw->rkey = le32_to_cpu(resp.xid);
565 mrw->lkey = le32_to_cpu(resp.xid);
569 int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw,
572 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
573 struct creq_deregister_mr_resp resp = {};
574 struct bnxt_qplib_cmdqmsg msg = {};
575 struct cmdq_deregister_mr req = {};
578 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
579 CMDQ_BASE_OPCODE_DEREGISTER_MR,
582 req.lkey = cpu_to_le32(mrw->lkey);
583 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
584 sizeof(resp), block);
585 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
589 /* Free the qplib's MR memory */
590 if (mrw->hwq.max_elements) {
593 bnxt_qplib_free_hwq(res, &mrw->hwq);
599 int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr,
600 struct ib_umem *umem, int num_pbls, u32 buf_pg_size)
602 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
603 struct bnxt_qplib_hwq_attr hwq_attr = {};
604 struct bnxt_qplib_sg_info sginfo = {};
605 struct creq_register_mr_resp resp = {};
606 struct bnxt_qplib_cmdqmsg msg = {};
607 struct cmdq_register_mr req = {};
613 pages = roundup_pow_of_two(num_pbls);
614 /* Allocate memory for the non-leaf pages to store buf ptrs.
615 * Non-leaf pages always uses system PAGE_SIZE
617 /* Free the hwq if it already exist, must be a rereg */
618 if (mr->hwq.max_elements)
619 bnxt_qplib_free_hwq(res, &mr->hwq);
620 /* Use system PAGE_SIZE */
622 hwq_attr.depth = pages;
623 hwq_attr.stride = buf_pg_size;
624 hwq_attr.type = HWQ_TYPE_MR;
625 hwq_attr.sginfo = &sginfo;
626 hwq_attr.sginfo->umem = umem;
627 hwq_attr.sginfo->npages = pages;
628 hwq_attr.sginfo->pgsize = PAGE_SIZE;
629 hwq_attr.sginfo->pgshft = PAGE_SHIFT;
630 rc = bnxt_qplib_alloc_init_hwq(&mr->hwq, &hwq_attr);
632 dev_err(&res->pdev->dev,
633 "SP: Reg MR memory allocation failed\n");
638 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
639 CMDQ_BASE_OPCODE_REGISTER_MR,
642 /* Configure the request */
643 if (mr->hwq.level == PBL_LVL_MAX) {
644 /* No PBL provided, just use system PAGE_SIZE */
649 level = mr->hwq.level;
650 req.pbl = cpu_to_le64(mr->hwq.pbl[PBL_LVL_0].pg_map_arr[0]);
652 pg_size = buf_pg_size ? buf_pg_size : PAGE_SIZE;
653 req.log2_pg_size_lvl = (level << CMDQ_REGISTER_MR_LVL_SFT) |
655 CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT) &
656 CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK);
657 req.log2_pbl_pg_size = cpu_to_le16(((ilog2(PAGE_SIZE) <<
658 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT) &
659 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK));
660 req.access = (mr->flags & 0xFFFF);
661 req.va = cpu_to_le64(mr->va);
662 req.key = cpu_to_le32(mr->lkey);
663 req.mr_size = cpu_to_le64(mr->total_size);
665 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
667 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
674 if (mr->hwq.max_elements)
675 bnxt_qplib_free_hwq(res, &mr->hwq);
679 int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res,
680 struct bnxt_qplib_frpl *frpl,
683 struct bnxt_qplib_hwq_attr hwq_attr = {};
684 struct bnxt_qplib_sg_info sginfo = {};
685 int pg_ptrs, pages, rc;
687 /* Re-calculate the max to fit the HWQ allocation model */
688 pg_ptrs = roundup_pow_of_two(max_pg_ptrs);
689 pages = pg_ptrs >> MAX_PBL_LVL_1_PGS_SHIFT;
693 if (pages > MAX_PBL_LVL_1_PGS)
696 sginfo.pgsize = PAGE_SIZE;
700 hwq_attr.depth = pg_ptrs;
701 hwq_attr.stride = PAGE_SIZE;
702 hwq_attr.sginfo = &sginfo;
703 hwq_attr.type = HWQ_TYPE_CTX;
704 rc = bnxt_qplib_alloc_init_hwq(&frpl->hwq, &hwq_attr);
706 frpl->max_pg_ptrs = pg_ptrs;
711 int bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res,
712 struct bnxt_qplib_frpl *frpl)
714 bnxt_qplib_free_hwq(res, &frpl->hwq);
718 int bnxt_qplib_get_roce_stats(struct bnxt_qplib_rcfw *rcfw,
719 struct bnxt_qplib_roce_stats *stats)
721 struct creq_query_roce_stats_resp resp = {};
722 struct creq_query_roce_stats_resp_sb *sb;
723 struct cmdq_query_roce_stats req = {};
724 struct bnxt_qplib_cmdqmsg msg = {};
725 struct bnxt_qplib_rcfw_sbuf *sbuf;
728 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
729 CMDQ_BASE_OPCODE_QUERY_ROCE_STATS,
732 sbuf = bnxt_qplib_rcfw_alloc_sbuf(rcfw, sizeof(*sb));
734 dev_err(&rcfw->pdev->dev,
735 "SP: QUERY_ROCE_STATS alloc side buffer failed\n");
740 req.resp_size = sizeof(*sb) / BNXT_QPLIB_CMDQE_UNITS;
741 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, sbuf, sizeof(req),
743 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
746 /* Extract the context from the side buffer */
747 stats->to_retransmits = le64_to_cpu(sb->to_retransmits);
748 stats->seq_err_naks_rcvd = le64_to_cpu(sb->seq_err_naks_rcvd);
749 stats->max_retry_exceeded = le64_to_cpu(sb->max_retry_exceeded);
750 stats->rnr_naks_rcvd = le64_to_cpu(sb->rnr_naks_rcvd);
751 stats->missing_resp = le64_to_cpu(sb->missing_resp);
752 stats->unrecoverable_err = le64_to_cpu(sb->unrecoverable_err);
753 stats->bad_resp_err = le64_to_cpu(sb->bad_resp_err);
754 stats->local_qp_op_err = le64_to_cpu(sb->local_qp_op_err);
755 stats->local_protection_err = le64_to_cpu(sb->local_protection_err);
756 stats->mem_mgmt_op_err = le64_to_cpu(sb->mem_mgmt_op_err);
757 stats->remote_invalid_req_err = le64_to_cpu(sb->remote_invalid_req_err);
758 stats->remote_access_err = le64_to_cpu(sb->remote_access_err);
759 stats->remote_op_err = le64_to_cpu(sb->remote_op_err);
760 stats->dup_req = le64_to_cpu(sb->dup_req);
761 stats->res_exceed_max = le64_to_cpu(sb->res_exceed_max);
762 stats->res_length_mismatch = le64_to_cpu(sb->res_length_mismatch);
763 stats->res_exceeds_wqe = le64_to_cpu(sb->res_exceeds_wqe);
764 stats->res_opcode_err = le64_to_cpu(sb->res_opcode_err);
765 stats->res_rx_invalid_rkey = le64_to_cpu(sb->res_rx_invalid_rkey);
766 stats->res_rx_domain_err = le64_to_cpu(sb->res_rx_domain_err);
767 stats->res_rx_no_perm = le64_to_cpu(sb->res_rx_no_perm);
768 stats->res_rx_range_err = le64_to_cpu(sb->res_rx_range_err);
769 stats->res_tx_invalid_rkey = le64_to_cpu(sb->res_tx_invalid_rkey);
770 stats->res_tx_domain_err = le64_to_cpu(sb->res_tx_domain_err);
771 stats->res_tx_no_perm = le64_to_cpu(sb->res_tx_no_perm);
772 stats->res_tx_range_err = le64_to_cpu(sb->res_tx_range_err);
773 stats->res_irrq_oflow = le64_to_cpu(sb->res_irrq_oflow);
774 stats->res_unsup_opcode = le64_to_cpu(sb->res_unsup_opcode);
775 stats->res_unaligned_atomic = le64_to_cpu(sb->res_unaligned_atomic);
776 stats->res_rem_inv_err = le64_to_cpu(sb->res_rem_inv_err);
777 stats->res_mem_error = le64_to_cpu(sb->res_mem_error);
778 stats->res_srq_err = le64_to_cpu(sb->res_srq_err);
779 stats->res_cmp_err = le64_to_cpu(sb->res_cmp_err);
780 stats->res_invalid_dup_rkey = le64_to_cpu(sb->res_invalid_dup_rkey);
781 stats->res_wqe_format_err = le64_to_cpu(sb->res_wqe_format_err);
782 stats->res_cq_load_err = le64_to_cpu(sb->res_cq_load_err);
783 stats->res_srq_load_err = le64_to_cpu(sb->res_srq_load_err);
784 stats->res_tx_pci_err = le64_to_cpu(sb->res_tx_pci_err);
785 stats->res_rx_pci_err = le64_to_cpu(sb->res_rx_pci_err);
786 if (!rcfw->init_oos_stats) {
787 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count);
788 rcfw->init_oos_stats = 1;
790 stats->res_oos_drop_count +=
791 (le64_to_cpu(sb->res_oos_drop_count) -
792 rcfw->oos_prev) & BNXT_QPLIB_OOS_COUNT_MASK;
793 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count);
797 bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf);
801 int bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw *rcfw, u32 fid,
802 struct bnxt_qplib_ext_stat *estat)
804 struct creq_query_roce_stats_ext_resp resp = {};
805 struct creq_query_roce_stats_ext_resp_sb *sb;
806 struct cmdq_query_roce_stats_ext req = {};
807 struct bnxt_qplib_cmdqmsg msg = {};
808 struct bnxt_qplib_rcfw_sbuf *sbuf;
811 sbuf = bnxt_qplib_rcfw_alloc_sbuf(rcfw, sizeof(*sb));
813 dev_err(&rcfw->pdev->dev,
814 "SP: QUERY_ROCE_STATS_EXT alloc sb failed");
818 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
819 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS,
822 req.resp_size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS);
823 req.resp_addr = cpu_to_le64(sbuf->dma_addr);
824 req.function_id = cpu_to_le32(fid);
825 req.flags = cpu_to_le16(CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID);
827 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, sbuf, sizeof(req),
829 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
834 estat->tx_atomic_req = le64_to_cpu(sb->tx_atomic_req_pkts);
835 estat->tx_read_req = le64_to_cpu(sb->tx_read_req_pkts);
836 estat->tx_read_res = le64_to_cpu(sb->tx_read_res_pkts);
837 estat->tx_write_req = le64_to_cpu(sb->tx_write_req_pkts);
838 estat->tx_send_req = le64_to_cpu(sb->tx_send_req_pkts);
839 estat->rx_atomic_req = le64_to_cpu(sb->rx_atomic_req_pkts);
840 estat->rx_read_req = le64_to_cpu(sb->rx_read_req_pkts);
841 estat->rx_read_res = le64_to_cpu(sb->rx_read_res_pkts);
842 estat->rx_write_req = le64_to_cpu(sb->rx_write_req_pkts);
843 estat->rx_send_req = le64_to_cpu(sb->rx_send_req_pkts);
844 estat->rx_roce_good_pkts = le64_to_cpu(sb->rx_roce_good_pkts);
845 estat->rx_roce_good_bytes = le64_to_cpu(sb->rx_roce_good_bytes);
846 estat->rx_out_of_buffer = le64_to_cpu(sb->rx_out_of_buffer_pkts);
847 estat->rx_out_of_sequence = le64_to_cpu(sb->rx_out_of_sequence_pkts);
850 bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf);
854 static void bnxt_qplib_fill_cc_gen1(struct cmdq_modify_roce_cc_gen1_tlv *ext_req,
855 struct bnxt_qplib_cc_param_ext *cc_ext)
857 ext_req->modify_mask = cpu_to_le64(cc_ext->ext_mask);
858 cc_ext->ext_mask = 0;
859 ext_req->inactivity_th_hi = cpu_to_le16(cc_ext->inact_th_hi);
860 ext_req->min_time_between_cnps = cpu_to_le16(cc_ext->min_delta_cnp);
861 ext_req->init_cp = cpu_to_le16(cc_ext->init_cp);
862 ext_req->tr_update_mode = cc_ext->tr_update_mode;
863 ext_req->tr_update_cycles = cc_ext->tr_update_cyls;
864 ext_req->fr_num_rtts = cc_ext->fr_rtt;
865 ext_req->ai_rate_increase = cc_ext->ai_rate_incr;
866 ext_req->reduction_relax_rtts_th = cpu_to_le16(cc_ext->rr_rtt_th);
867 ext_req->additional_relax_cr_th = cpu_to_le16(cc_ext->ar_cr_th);
868 ext_req->cr_min_th = cpu_to_le16(cc_ext->cr_min_th);
869 ext_req->bw_avg_weight = cc_ext->bw_avg_weight;
870 ext_req->actual_cr_factor = cc_ext->cr_factor;
871 ext_req->max_cp_cr_th = cpu_to_le16(cc_ext->cr_th_max_cp);
872 ext_req->cp_bias_en = cc_ext->cp_bias_en;
873 ext_req->cp_bias = cc_ext->cp_bias;
874 ext_req->cnp_ecn = cc_ext->cnp_ecn;
875 ext_req->rtt_jitter_en = cc_ext->rtt_jitter_en;
876 ext_req->link_bytes_per_usec = cpu_to_le16(cc_ext->bytes_per_usec);
877 ext_req->reset_cc_cr_th = cpu_to_le16(cc_ext->cc_cr_reset_th);
878 ext_req->cr_width = cc_ext->cr_width;
879 ext_req->quota_period_min = cc_ext->min_quota;
880 ext_req->quota_period_max = cc_ext->max_quota;
881 ext_req->quota_period_abs_max = cc_ext->abs_max_quota;
882 ext_req->tr_lower_bound = cpu_to_le16(cc_ext->tr_lb);
883 ext_req->cr_prob_factor = cc_ext->cr_prob_fac;
884 ext_req->tr_prob_factor = cc_ext->tr_prob_fac;
885 ext_req->fairness_cr_th = cpu_to_le16(cc_ext->fair_cr_th);
886 ext_req->red_div = cc_ext->red_div;
887 ext_req->cnp_ratio_th = cc_ext->cnp_ratio_th;
888 ext_req->exp_ai_rtts = cpu_to_le16(cc_ext->ai_ext_rtt);
889 ext_req->exp_ai_cr_cp_ratio = cc_ext->exp_crcp_ratio;
890 ext_req->use_rate_table = cc_ext->low_rate_en;
891 ext_req->cp_exp_update_th = cpu_to_le16(cc_ext->cpcr_update_th);
892 ext_req->high_exp_ai_rtts_th1 = cpu_to_le16(cc_ext->ai_rtt_th1);
893 ext_req->high_exp_ai_rtts_th2 = cpu_to_le16(cc_ext->ai_rtt_th2);
894 ext_req->actual_cr_cong_free_rtts_th = cpu_to_le16(cc_ext->cf_rtt_th);
895 ext_req->severe_cong_cr_th1 = cpu_to_le16(cc_ext->sc_cr_th1);
896 ext_req->severe_cong_cr_th2 = cpu_to_le16(cc_ext->sc_cr_th2);
897 ext_req->link64B_per_rtt = cpu_to_le32(cc_ext->l64B_per_rtt);
898 ext_req->cc_ack_bytes = cc_ext->cc_ack_bytes;
901 int bnxt_qplib_modify_cc(struct bnxt_qplib_res *res,
902 struct bnxt_qplib_cc_param *cc_param)
904 struct bnxt_qplib_tlv_modify_cc_req tlv_req = {};
905 struct creq_modify_roce_cc_resp resp = {};
906 struct bnxt_qplib_cmdqmsg msg = {};
907 struct cmdq_modify_roce_cc *req;
912 /* Prepare the older base command */
913 req = &tlv_req.base_req;
915 req_size = sizeof(*req);
916 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)req, CMDQ_BASE_OPCODE_MODIFY_ROCE_CC,
918 req->modify_mask = cpu_to_le32(cc_param->mask);
919 req->enable_cc = cc_param->enable;
920 req->g = cc_param->g;
921 req->num_phases_per_state = cc_param->nph_per_state;
922 req->time_per_phase = cc_param->time_pph;
923 req->pkts_per_phase = cc_param->pkts_pph;
924 req->init_cr = cpu_to_le16(cc_param->init_cr);
925 req->init_tr = cpu_to_le16(cc_param->init_tr);
926 req->tos_dscp_tos_ecn = (cc_param->tos_dscp << CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT) |
927 (cc_param->tos_ecn & CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK);
928 req->alt_vlan_pcp = cc_param->alt_vlan_pcp;
929 req->alt_tos_dscp = cpu_to_le16(cc_param->alt_tos_dscp);
930 req->rtt = cpu_to_le16(cc_param->rtt);
931 req->tcp_cp = cpu_to_le16(cc_param->tcp_cp);
932 req->cc_mode = cc_param->cc_mode;
933 req->inactivity_th = cpu_to_le16(cc_param->inact_th);
935 /* For chip gen P5 onwards fill extended cmd and header */
936 if (bnxt_qplib_is_chip_gen_p5(res->cctx)) {
937 struct roce_tlv *hdr;
942 req_size = sizeof(tlv_req);
943 /* Prepare primary tlv header */
944 hdr = &tlv_req.tlv_hdr;
945 chunks = CHUNKS(sizeof(struct bnxt_qplib_tlv_modify_cc_req));
946 payload = sizeof(struct cmdq_modify_roce_cc);
947 __roce_1st_tlv_prep(hdr, chunks, payload, true);
948 /* Prepare secondary tlv header */
949 hdr = (struct roce_tlv *)&tlv_req.ext_req;
950 payload = sizeof(struct cmdq_modify_roce_cc_gen1_tlv) -
951 sizeof(struct roce_tlv);
952 __roce_ext_tlv_prep(hdr, TLV_TYPE_MODIFY_ROCE_CC_GEN1, payload, false, true);
953 bnxt_qplib_fill_cc_gen1(&tlv_req.ext_req, &cc_param->cc_ext);
956 bnxt_qplib_fill_cmdqmsg(&msg, cmd, &resp, NULL, req_size,
958 rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg);