2 * Broadcom NetXtreme-E RoCE driver.
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Description: RDMA Controller HW interface
39 #define dev_fmt(fmt) "QPLIB: " fmt
41 #include <linux/interrupt.h>
42 #include <linux/spinlock.h>
43 #include <linux/pci.h>
44 #include <linux/prefetch.h>
45 #include <linux/delay.h>
48 #include "qplib_res.h"
49 #include "qplib_rcfw.h"
52 #include "qplib_tlv.h"
54 static void bnxt_qplib_service_creq(struct tasklet_struct *t);
57 * bnxt_qplib_map_rc - map return type based on opcode
58 * @opcode - roce slow path opcode
61 * Firmware initiated error recovery is a safe state machine and
62 * driver can consider all the underlying rdma resources are free.
63 * In this state, it is safe to return success for opcodes related to
64 * destroying rdma resources (like destroy qp, destroy cq etc.).
67 * If driver detect potential firmware stall, it is not safe state machine
68 * and the driver can not consider all the underlying rdma resources are
70 * In this state, it is not safe to return success for opcodes related to
71 * destroying rdma resources (like destroy qp, destroy cq etc.).
73 * Scope of this helper function is only for case #1.
76 * 0 to communicate success to caller.
77 * Non zero error code to communicate failure to caller.
79 static int bnxt_qplib_map_rc(u8 opcode)
82 case CMDQ_BASE_OPCODE_DESTROY_QP:
83 case CMDQ_BASE_OPCODE_DESTROY_SRQ:
84 case CMDQ_BASE_OPCODE_DESTROY_CQ:
85 case CMDQ_BASE_OPCODE_DEALLOCATE_KEY:
86 case CMDQ_BASE_OPCODE_DEREGISTER_MR:
87 case CMDQ_BASE_OPCODE_DELETE_GID:
88 case CMDQ_BASE_OPCODE_DESTROY_QP1:
89 case CMDQ_BASE_OPCODE_DESTROY_AH:
90 case CMDQ_BASE_OPCODE_DEINITIALIZE_FW:
91 case CMDQ_BASE_OPCODE_MODIFY_ROCE_CC:
92 case CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE:
100 * bnxt_re_is_fw_stalled - Check firmware health
101 * @rcfw - rcfw channel instance of rdev
102 * @cookie - cookie to track the command
104 * If firmware has not responded any rcfw command within
105 * rcfw->max_timeout, consider firmware as stalled.
108 * 0 if firmware is responding
109 * -ENODEV if firmware is not responding
111 static int bnxt_re_is_fw_stalled(struct bnxt_qplib_rcfw *rcfw,
114 struct bnxt_qplib_cmdq_ctx *cmdq;
115 struct bnxt_qplib_crsqe *crsqe;
117 crsqe = &rcfw->crsqe_tbl[cookie];
120 if (time_after(jiffies, cmdq->last_seen +
121 (rcfw->max_timeout * HZ))) {
122 dev_warn_ratelimited(&rcfw->pdev->dev,
123 "%s: FW STALL Detected. cmdq[%#x]=%#x waited (%d > %d) msec active %d ",
124 __func__, cookie, crsqe->opcode,
125 jiffies_to_msecs(jiffies - cmdq->last_seen),
126 rcfw->max_timeout * 1000,
135 * __wait_for_resp - Don't hold the cpu context and wait for response
136 * @rcfw - rcfw channel instance of rdev
137 * @cookie - cookie to track the command
139 * Wait for command completion in sleepable context.
142 * 0 if command is completed by firmware.
143 * Non zero error code for rest of the case.
145 static int __wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
147 struct bnxt_qplib_cmdq_ctx *cmdq;
148 struct bnxt_qplib_crsqe *crsqe;
152 crsqe = &rcfw->crsqe_tbl[cookie];
155 if (test_bit(ERR_DEVICE_DETACHED, &cmdq->flags))
156 return bnxt_qplib_map_rc(crsqe->opcode);
157 if (test_bit(FIRMWARE_STALL_DETECTED, &cmdq->flags))
160 wait_event_timeout(cmdq->waitq,
161 !crsqe->is_in_used ||
162 test_bit(ERR_DEVICE_DETACHED, &cmdq->flags),
163 msecs_to_jiffies(rcfw->max_timeout * 1000));
165 if (!crsqe->is_in_used)
168 bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet);
170 if (!crsqe->is_in_used)
173 ret = bnxt_re_is_fw_stalled(rcfw, cookie);
181 * __block_for_resp - hold the cpu context and wait for response
182 * @rcfw - rcfw channel instance of rdev
183 * @cookie - cookie to track the command
185 * This function will hold the cpu (non-sleepable context) and
186 * wait for command completion. Maximum holding interval is 8 second.
189 * -ETIMEOUT if command is not completed in specific time interval.
190 * 0 if command is completed by firmware.
192 static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
194 struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq;
195 struct bnxt_qplib_crsqe *crsqe;
196 unsigned long issue_time = 0;
198 issue_time = jiffies;
199 crsqe = &rcfw->crsqe_tbl[cookie];
202 if (test_bit(ERR_DEVICE_DETACHED, &cmdq->flags))
203 return bnxt_qplib_map_rc(crsqe->opcode);
204 if (test_bit(FIRMWARE_STALL_DETECTED, &cmdq->flags))
209 bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet);
210 if (!crsqe->is_in_used)
213 } while (time_before(jiffies, issue_time + (8 * HZ)));
218 /* __send_message_no_waiter - get cookie and post the message.
219 * @rcfw - rcfw channel instance of rdev
220 * @msg - qplib message internal
222 * This function will just post and don't bother about completion.
223 * Current design of this function is -
224 * user must hold the completion queue hwq->lock.
225 * user must have used existing completion and free the resources.
226 * this function will not check queue full condition.
227 * this function will explicitly set is_waiter_alive=false.
228 * current use case is - send destroy_ah if create_ah is return
229 * after waiter of create_ah is lost. It can be extended for other
235 static void __send_message_no_waiter(struct bnxt_qplib_rcfw *rcfw,
236 struct bnxt_qplib_cmdqmsg *msg)
238 struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq;
239 struct bnxt_qplib_hwq *hwq = &cmdq->hwq;
240 struct bnxt_qplib_crsqe *crsqe;
241 struct bnxt_qplib_cmdqe *cmdqe;
242 u32 sw_prod, cmdq_prod;
247 cookie = cmdq->seq_num & RCFW_MAX_COOKIE_VALUE;
248 __set_cmdq_base_cookie(msg->req, msg->req_sz, cpu_to_le16(cookie));
249 crsqe = &rcfw->crsqe_tbl[cookie];
251 /* Set cmd_size in terms of 16B slots in req. */
252 bsize = bnxt_qplib_set_cmd_slots(msg->req);
253 /* GET_CMD_SIZE would return number of slots in either case of tlv
254 * and non-tlv commands after call to bnxt_qplib_set_cmd_slots()
256 crsqe->is_internal_cmd = true;
257 crsqe->is_waiter_alive = false;
258 crsqe->is_in_used = true;
259 crsqe->req_size = __get_cmdq_base_cmd_size(msg->req, msg->req_sz);
261 preq = (u8 *)msg->req;
263 /* Locate the next cmdq slot */
264 sw_prod = HWQ_CMP(hwq->prod, hwq);
265 cmdqe = bnxt_qplib_get_qe(hwq, sw_prod, NULL);
266 /* Copy a segment of the req cmd to the cmdq */
267 memset(cmdqe, 0, sizeof(*cmdqe));
268 memcpy(cmdqe, preq, min_t(u32, bsize, sizeof(*cmdqe)));
269 preq += min_t(u32, bsize, sizeof(*cmdqe));
270 bsize -= min_t(u32, bsize, sizeof(*cmdqe));
275 cmdq_prod = hwq->prod;
276 atomic_inc(&rcfw->timeout_send);
279 writel(cmdq_prod, cmdq->cmdq_mbox.prod);
280 writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db);
283 static int __send_message(struct bnxt_qplib_rcfw *rcfw,
284 struct bnxt_qplib_cmdqmsg *msg, u8 opcode)
286 u32 bsize, free_slots, required_slots;
287 struct bnxt_qplib_cmdq_ctx *cmdq;
288 struct bnxt_qplib_crsqe *crsqe;
289 struct bnxt_qplib_cmdqe *cmdqe;
290 struct bnxt_qplib_hwq *hwq;
291 u32 sw_prod, cmdq_prod;
292 struct pci_dev *pdev;
301 /* Cmdq are in 16-byte units, each request can consume 1 or more
304 spin_lock_irqsave(&hwq->lock, flags);
305 required_slots = bnxt_qplib_get_cmd_slots(msg->req);
306 free_slots = HWQ_FREE_SLOTS(hwq);
307 cookie = cmdq->seq_num & RCFW_MAX_COOKIE_VALUE;
308 crsqe = &rcfw->crsqe_tbl[cookie];
310 if (required_slots >= free_slots) {
311 dev_info_ratelimited(&pdev->dev,
312 "CMDQ is full req/free %d/%d!",
313 required_slots, free_slots);
314 spin_unlock_irqrestore(&hwq->lock, flags);
318 cookie |= RCFW_CMD_IS_BLOCKING;
319 __set_cmdq_base_cookie(msg->req, msg->req_sz, cpu_to_le16(cookie));
321 bsize = bnxt_qplib_set_cmd_slots(msg->req);
322 crsqe->free_slots = free_slots;
323 crsqe->resp = (struct creq_qp_event *)msg->resp;
324 crsqe->resp->cookie = cpu_to_le16(cookie);
325 crsqe->is_internal_cmd = false;
326 crsqe->is_waiter_alive = true;
327 crsqe->is_in_used = true;
328 crsqe->opcode = opcode;
330 crsqe->req_size = __get_cmdq_base_cmd_size(msg->req, msg->req_sz);
331 if (__get_cmdq_base_resp_size(msg->req, msg->req_sz) && msg->sb) {
332 struct bnxt_qplib_rcfw_sbuf *sbuf = msg->sb;
334 __set_cmdq_base_resp_addr(msg->req, msg->req_sz,
335 cpu_to_le64(sbuf->dma_addr));
336 __set_cmdq_base_resp_size(msg->req, msg->req_sz,
338 BNXT_QPLIB_CMDQE_UNITS));
341 preq = (u8 *)msg->req;
343 /* Locate the next cmdq slot */
344 sw_prod = HWQ_CMP(hwq->prod, hwq);
345 cmdqe = bnxt_qplib_get_qe(hwq, sw_prod, NULL);
346 /* Copy a segment of the req cmd to the cmdq */
347 memset(cmdqe, 0, sizeof(*cmdqe));
348 memcpy(cmdqe, preq, min_t(u32, bsize, sizeof(*cmdqe)));
349 preq += min_t(u32, bsize, sizeof(*cmdqe));
350 bsize -= min_t(u32, bsize, sizeof(*cmdqe));
355 cmdq_prod = hwq->prod & 0xFFFF;
356 if (test_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags)) {
357 /* The very first doorbell write
358 * is required to set this flag
359 * which prompts the FW to reset
360 * its internal pointers
362 cmdq_prod |= BIT(FIRMWARE_FIRST_FLAG);
363 clear_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags);
367 writel(cmdq_prod, cmdq->cmdq_mbox.prod);
368 writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db);
369 spin_unlock_irqrestore(&hwq->lock, flags);
370 /* Return the CREQ response pointer */
375 * __poll_for_resp - self poll completion for rcfw command
376 * @rcfw - rcfw channel instance of rdev
377 * @cookie - cookie to track the command
379 * It works same as __wait_for_resp except this function will
380 * do self polling in sort interval since interrupt is disabled.
381 * This function can not be called from non-sleepable context.
384 * -ETIMEOUT if command is not completed in specific time interval.
385 * 0 if command is completed by firmware.
387 static int __poll_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
389 struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq;
390 struct bnxt_qplib_crsqe *crsqe;
391 unsigned long issue_time;
394 issue_time = jiffies;
395 crsqe = &rcfw->crsqe_tbl[cookie];
398 if (test_bit(ERR_DEVICE_DETACHED, &cmdq->flags))
399 return bnxt_qplib_map_rc(crsqe->opcode);
400 if (test_bit(FIRMWARE_STALL_DETECTED, &cmdq->flags))
403 usleep_range(1000, 1001);
405 bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet);
406 if (!crsqe->is_in_used)
408 if (jiffies_to_msecs(jiffies - issue_time) >
409 (rcfw->max_timeout * 1000)) {
410 ret = bnxt_re_is_fw_stalled(rcfw, cookie);
417 static int __send_message_basic_sanity(struct bnxt_qplib_rcfw *rcfw,
418 struct bnxt_qplib_cmdqmsg *msg,
421 struct bnxt_qplib_cmdq_ctx *cmdq;
425 /* Prevent posting if f/w is not in a state to process */
426 if (test_bit(ERR_DEVICE_DETACHED, &rcfw->cmdq.flags))
427 return bnxt_qplib_map_rc(opcode);
428 if (test_bit(FIRMWARE_STALL_DETECTED, &cmdq->flags))
431 if (test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) &&
432 opcode == CMDQ_BASE_OPCODE_INITIALIZE_FW) {
433 dev_err(&rcfw->pdev->dev, "QPLIB: RCFW already initialized!");
437 if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) &&
438 (opcode != CMDQ_BASE_OPCODE_QUERY_FUNC &&
439 opcode != CMDQ_BASE_OPCODE_INITIALIZE_FW &&
440 opcode != CMDQ_BASE_OPCODE_QUERY_VERSION)) {
441 dev_err(&rcfw->pdev->dev,
442 "QPLIB: RCFW not initialized, reject opcode 0x%x",
450 /* This function will just post and do not bother about completion */
451 static void __destroy_timedout_ah(struct bnxt_qplib_rcfw *rcfw,
452 struct creq_create_ah_resp *create_ah_resp)
454 struct bnxt_qplib_cmdqmsg msg = {};
455 struct cmdq_destroy_ah req = {};
457 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
458 CMDQ_BASE_OPCODE_DESTROY_AH,
460 req.ah_cid = create_ah_resp->xid;
461 msg.req = (struct cmdq_base *)&req;
462 msg.req_sz = sizeof(req);
463 __send_message_no_waiter(rcfw, &msg);
464 dev_info_ratelimited(&rcfw->pdev->dev,
465 "From %s: ah_cid = %d timeout_send %d\n",
466 __func__, req.ah_cid,
467 atomic_read(&rcfw->timeout_send));
471 * __bnxt_qplib_rcfw_send_message - qplib interface to send
472 * and complete rcfw command.
473 * @rcfw - rcfw channel instance of rdev
474 * @msg - qplib message internal
476 * This function does not account shadow queue depth. It will send
477 * all the command unconditionally as long as send queue is not full.
480 * 0 if command completed by firmware.
481 * Non zero if the command is not completed by firmware.
483 static int __bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
484 struct bnxt_qplib_cmdqmsg *msg)
486 struct creq_qp_event *evnt = (struct creq_qp_event *)msg->resp;
487 struct bnxt_qplib_crsqe *crsqe;
493 opcode = __get_cmdq_base_opcode(msg->req, msg->req_sz);
495 rc = __send_message_basic_sanity(rcfw, msg, opcode);
499 rc = __send_message(rcfw, msg, opcode);
503 cookie = le16_to_cpu(__get_cmdq_base_cookie(msg->req, msg->req_sz))
504 & RCFW_MAX_COOKIE_VALUE;
507 rc = __block_for_resp(rcfw, cookie);
508 else if (atomic_read(&rcfw->rcfw_intr_enabled))
509 rc = __wait_for_resp(rcfw, cookie);
511 rc = __poll_for_resp(rcfw, cookie);
514 spin_lock_irqsave(&rcfw->cmdq.hwq.lock, flags);
515 crsqe = &rcfw->crsqe_tbl[cookie];
516 crsqe->is_waiter_alive = false;
518 set_bit(FIRMWARE_STALL_DETECTED, &rcfw->cmdq.flags);
519 spin_unlock_irqrestore(&rcfw->cmdq.hwq.lock, flags);
524 /* failed with status */
525 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x status %#x\n",
526 cookie, opcode, evnt->status);
534 * bnxt_qplib_rcfw_send_message - qplib interface to send
535 * and complete rcfw command.
536 * @rcfw - rcfw channel instance of rdev
537 * @msg - qplib message internal
539 * Driver interact with Firmware through rcfw channel/slow path in two ways.
540 * a. Blocking rcfw command send. In this path, driver cannot hold
541 * the context for longer period since it is holding cpu until
542 * command is not completed.
543 * b. Non-blocking rcfw command send. In this path, driver can hold the
544 * context for longer period. There may be many pending command waiting
545 * for completion because of non-blocking nature.
547 * Driver will use shadow queue depth. Current queue depth of 8K
548 * (due to size of rcfw message there can be actual ~4K rcfw outstanding)
549 * is not optimal for rcfw command processing in firmware.
551 * Restrict at max #RCFW_CMD_NON_BLOCKING_SHADOW_QD Non-Blocking rcfw commands.
552 * Allow all blocking commands until there is no queue full.
555 * 0 if command completed by firmware.
556 * Non zero if the command is not completed by firmware.
558 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
559 struct bnxt_qplib_cmdqmsg *msg)
564 down(&rcfw->rcfw_inflight);
565 ret = __bnxt_qplib_rcfw_send_message(rcfw, msg);
566 up(&rcfw->rcfw_inflight);
568 ret = __bnxt_qplib_rcfw_send_message(rcfw, msg);
575 static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw,
576 struct creq_func_event *func_event)
580 switch (func_event->event) {
581 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
583 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR:
585 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR:
587 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR:
589 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR:
591 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR:
593 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR:
595 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR:
596 /* SRQ ctx error, call srq_handler??
597 * But there's no SRQ handle!
600 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR:
602 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR:
604 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR:
606 case CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST:
608 case CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED:
614 rc = rcfw->creq.aeq_handler(rcfw, (void *)func_event, NULL);
618 static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw,
619 struct creq_qp_event *qp_event,
622 struct creq_qp_error_notification *err_event;
623 struct bnxt_qplib_hwq *hwq = &rcfw->cmdq.hwq;
624 struct bnxt_qplib_crsqe *crsqe;
625 u32 qp_id, tbl_indx, req_size;
626 struct bnxt_qplib_qp *qp;
627 u16 cookie, blocked = 0;
628 bool is_waiter_alive;
629 struct pci_dev *pdev;
635 switch (qp_event->event) {
636 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:
637 err_event = (struct creq_qp_error_notification *)qp_event;
638 qp_id = le32_to_cpu(err_event->xid);
639 tbl_indx = map_qp_id_to_tbl_indx(qp_id, rcfw);
640 qp = rcfw->qp_tbl[tbl_indx].qp_handle;
641 dev_dbg(&pdev->dev, "Received QP error notification\n");
643 "qpid 0x%x, req_err=0x%x, resp_err=0x%x\n",
644 qp_id, err_event->req_err_state_reason,
645 err_event->res_err_state_reason);
648 bnxt_qplib_mark_qp_error(qp);
649 rc = rcfw->creq.aeq_handler(rcfw, qp_event, qp);
654 * cmdq->lock needs to be acquired to synchronie
655 * the command send and completion reaping. This function
656 * is always called with creq->lock held. Using
657 * the nested variant of spin_lock.
661 spin_lock_irqsave_nested(&hwq->lock, flags,
662 SINGLE_DEPTH_NESTING);
663 cookie = le16_to_cpu(qp_event->cookie);
664 blocked = cookie & RCFW_CMD_IS_BLOCKING;
665 cookie &= RCFW_MAX_COOKIE_VALUE;
666 crsqe = &rcfw->crsqe_tbl[cookie];
667 crsqe->is_in_used = false;
669 if (WARN_ONCE(test_bit(FIRMWARE_STALL_DETECTED,
671 "QPLIB: Unreponsive rcfw channel detected.!!")) {
673 "rcfw timedout: cookie = %#x, free_slots = %d",
674 cookie, crsqe->free_slots);
675 spin_unlock_irqrestore(&hwq->lock, flags);
679 if (crsqe->is_internal_cmd && !qp_event->status)
680 atomic_dec(&rcfw->timeout_send);
682 if (crsqe->is_waiter_alive) {
684 memcpy(crsqe->resp, qp_event, sizeof(*qp_event));
689 req_size = crsqe->req_size;
690 is_waiter_alive = crsqe->is_waiter_alive;
693 if (!is_waiter_alive)
696 hwq->cons += req_size;
698 /* This is a case to handle below scenario -
699 * Create AH is completed successfully by firmware,
700 * but completion took more time and driver already lost
701 * the context of create_ah from caller.
702 * We have already return failure for create_ah verbs,
703 * so let's destroy the same address vector since it is
704 * no more used in stack. We don't care about completion
705 * in __send_message_no_waiter.
706 * If destroy_ah is failued by firmware, there will be AH
707 * resource leak and relatively not critical + unlikely
708 * scenario. Current design is not to handle such case.
710 if (!is_waiter_alive && !qp_event->status &&
711 qp_event->event == CREQ_QP_EVENT_EVENT_CREATE_AH)
712 __destroy_timedout_ah(rcfw,
713 (struct creq_create_ah_resp *)
715 spin_unlock_irqrestore(&hwq->lock, flags);
717 *num_wait += wait_cmds;
721 /* SP - CREQ Completion handlers */
722 static void bnxt_qplib_service_creq(struct tasklet_struct *t)
724 struct bnxt_qplib_rcfw *rcfw = from_tasklet(rcfw, t, creq.creq_tasklet);
725 struct bnxt_qplib_creq_ctx *creq = &rcfw->creq;
726 u32 type, budget = CREQ_ENTRY_POLL_BUDGET;
727 struct bnxt_qplib_hwq *hwq = &creq->hwq;
728 struct creq_base *creqe;
729 u32 sw_cons, raw_cons;
733 /* Service the CREQ until budget is over */
734 spin_lock_irqsave(&hwq->lock, flags);
735 raw_cons = hwq->cons;
737 sw_cons = HWQ_CMP(raw_cons, hwq);
738 creqe = bnxt_qplib_get_qe(hwq, sw_cons, NULL);
739 if (!CREQ_CMP_VALID(creqe, raw_cons, hwq->max_elements))
741 /* The valid test of the entry must be done first before
742 * reading any further.
745 rcfw->cmdq.last_seen = jiffies;
747 type = creqe->type & CREQ_BASE_TYPE_MASK;
749 case CREQ_BASE_TYPE_QP_EVENT:
750 bnxt_qplib_process_qp_event
751 (rcfw, (struct creq_qp_event *)creqe,
753 creq->stats.creq_qp_event_processed++;
755 case CREQ_BASE_TYPE_FUNC_EVENT:
756 if (!bnxt_qplib_process_func_event
757 (rcfw, (struct creq_func_event *)creqe))
758 creq->stats.creq_func_event_processed++;
760 dev_warn(&rcfw->pdev->dev,
761 "aeqe:%#x Not handled\n", type);
764 if (type != ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT)
765 dev_warn(&rcfw->pdev->dev,
766 "creqe with event 0x%x not handled\n",
774 if (hwq->cons != raw_cons) {
775 hwq->cons = raw_cons;
776 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo,
777 rcfw->res->cctx, true);
779 spin_unlock_irqrestore(&hwq->lock, flags);
781 wake_up_nr(&rcfw->cmdq.waitq, num_wakeup);
784 static irqreturn_t bnxt_qplib_creq_irq(int irq, void *dev_instance)
786 struct bnxt_qplib_rcfw *rcfw = dev_instance;
787 struct bnxt_qplib_creq_ctx *creq;
788 struct bnxt_qplib_hwq *hwq;
793 /* Prefetch the CREQ element */
794 sw_cons = HWQ_CMP(hwq->cons, hwq);
795 prefetch(bnxt_qplib_get_qe(hwq, sw_cons, NULL));
797 tasklet_schedule(&creq->creq_tasklet);
803 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw)
805 struct creq_deinitialize_fw_resp resp = {};
806 struct cmdq_deinitialize_fw req = {};
807 struct bnxt_qplib_cmdqmsg msg = {};
810 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
811 CMDQ_BASE_OPCODE_DEINITIALIZE_FW,
813 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL,
814 sizeof(req), sizeof(resp), 0);
815 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
819 clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags);
823 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
824 struct bnxt_qplib_ctx *ctx, int is_virtfn)
826 struct creq_initialize_fw_resp resp = {};
827 struct cmdq_initialize_fw req = {};
828 struct bnxt_qplib_cmdqmsg msg = {};
832 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
833 CMDQ_BASE_OPCODE_INITIALIZE_FW,
835 /* Supply (log-base-2-of-host-page-size - base-page-shift)
836 * to bono to adjust the doorbell page sizes.
838 req.log2_dbr_pg_size = cpu_to_le16(PAGE_SHIFT -
839 RCFW_DBR_BASE_PAGE_SHIFT);
841 * Gen P5 devices doesn't require this allocation
842 * as the L2 driver does the same for RoCE also.
843 * Also, VFs need not setup the HW context area, PF
844 * shall setup this area for VF. Skipping the
849 if (bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx))
852 lvl = ctx->qpc_tbl.level;
853 pgsz = bnxt_qplib_base_pg_size(&ctx->qpc_tbl);
854 req.qpc_pg_size_qpc_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
856 lvl = ctx->mrw_tbl.level;
857 pgsz = bnxt_qplib_base_pg_size(&ctx->mrw_tbl);
858 req.mrw_pg_size_mrw_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
860 lvl = ctx->srqc_tbl.level;
861 pgsz = bnxt_qplib_base_pg_size(&ctx->srqc_tbl);
862 req.srq_pg_size_srq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
864 lvl = ctx->cq_tbl.level;
865 pgsz = bnxt_qplib_base_pg_size(&ctx->cq_tbl);
866 req.cq_pg_size_cq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
868 lvl = ctx->tim_tbl.level;
869 pgsz = bnxt_qplib_base_pg_size(&ctx->tim_tbl);
870 req.tim_pg_size_tim_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
872 lvl = ctx->tqm_ctx.pde.level;
873 pgsz = bnxt_qplib_base_pg_size(&ctx->tqm_ctx.pde);
874 req.tqm_pg_size_tqm_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
877 cpu_to_le64(ctx->qpc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
879 cpu_to_le64(ctx->mrw_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
881 cpu_to_le64(ctx->srqc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
883 cpu_to_le64(ctx->cq_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
885 cpu_to_le64(ctx->tim_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
887 cpu_to_le64(ctx->tqm_ctx.pde.pbl[PBL_LVL_0].pg_map_arr[0]);
889 req.number_of_qp = cpu_to_le32(ctx->qpc_tbl.max_elements);
890 req.number_of_mrw = cpu_to_le32(ctx->mrw_tbl.max_elements);
891 req.number_of_srq = cpu_to_le32(ctx->srqc_tbl.max_elements);
892 req.number_of_cq = cpu_to_le32(ctx->cq_tbl.max_elements);
895 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf);
896 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf);
897 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf);
898 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf);
899 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf);
902 req.stat_ctx_id = cpu_to_le32(ctx->stats.fw_id);
903 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0);
904 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
907 set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags);
911 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)
914 kfree(rcfw->crsqe_tbl);
915 bnxt_qplib_free_hwq(rcfw->res, &rcfw->cmdq.hwq);
916 bnxt_qplib_free_hwq(rcfw->res, &rcfw->creq.hwq);
920 int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res,
921 struct bnxt_qplib_rcfw *rcfw,
922 struct bnxt_qplib_ctx *ctx,
925 struct bnxt_qplib_hwq_attr hwq_attr = {};
926 struct bnxt_qplib_sg_info sginfo = {};
927 struct bnxt_qplib_cmdq_ctx *cmdq;
928 struct bnxt_qplib_creq_ctx *creq;
930 rcfw->pdev = res->pdev;
935 sginfo.pgsize = PAGE_SIZE;
936 sginfo.pgshft = PAGE_SHIFT;
938 hwq_attr.sginfo = &sginfo;
939 hwq_attr.res = rcfw->res;
940 hwq_attr.depth = BNXT_QPLIB_CREQE_MAX_CNT;
941 hwq_attr.stride = BNXT_QPLIB_CREQE_UNITS;
942 hwq_attr.type = bnxt_qplib_get_hwq_type(res);
944 if (bnxt_qplib_alloc_init_hwq(&creq->hwq, &hwq_attr)) {
945 dev_err(&rcfw->pdev->dev,
946 "HW channel CREQ allocation failed\n");
950 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT;
952 sginfo.pgsize = bnxt_qplib_cmdqe_page_size(rcfw->cmdq_depth);
953 hwq_attr.depth = rcfw->cmdq_depth & 0x7FFFFFFF;
954 hwq_attr.stride = BNXT_QPLIB_CMDQE_UNITS;
955 hwq_attr.type = HWQ_TYPE_CTX;
956 if (bnxt_qplib_alloc_init_hwq(&cmdq->hwq, &hwq_attr)) {
957 dev_err(&rcfw->pdev->dev,
958 "HW channel CMDQ allocation failed\n");
962 rcfw->crsqe_tbl = kcalloc(cmdq->hwq.max_elements,
963 sizeof(*rcfw->crsqe_tbl), GFP_KERNEL);
964 if (!rcfw->crsqe_tbl)
967 /* Allocate one extra to hold the QP1 entries */
968 rcfw->qp_tbl_size = qp_tbl_sz + 1;
969 rcfw->qp_tbl = kcalloc(rcfw->qp_tbl_size, sizeof(struct bnxt_qplib_qp_node),
974 rcfw->max_timeout = res->cctx->hwrm_cmd_max_timeout;
979 bnxt_qplib_free_rcfw_channel(rcfw);
983 void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill)
985 struct bnxt_qplib_creq_ctx *creq;
989 if (!creq->requested)
992 tasklet_disable(&creq->creq_tasklet);
993 /* Mask h/w interrupts */
994 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, false);
995 /* Sync with last running IRQ-handler */
996 synchronize_irq(creq->msix_vec);
998 tasklet_kill(&creq->creq_tasklet);
1000 free_irq(creq->msix_vec, rcfw);
1001 kfree(creq->irq_name);
1002 creq->irq_name = NULL;
1003 creq->requested = false;
1004 atomic_set(&rcfw->rcfw_intr_enabled, 0);
1007 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)
1009 struct bnxt_qplib_creq_ctx *creq;
1010 struct bnxt_qplib_cmdq_ctx *cmdq;
1014 /* Make sure the HW channel is stopped! */
1015 bnxt_qplib_rcfw_stop_irq(rcfw, true);
1017 iounmap(cmdq->cmdq_mbox.reg.bar_reg);
1018 iounmap(creq->creq_db.reg.bar_reg);
1020 cmdq->cmdq_mbox.reg.bar_reg = NULL;
1021 creq->creq_db.reg.bar_reg = NULL;
1022 creq->aeq_handler = NULL;
1026 int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
1029 struct bnxt_qplib_creq_ctx *creq;
1030 struct bnxt_qplib_res *res;
1036 if (creq->requested)
1039 creq->msix_vec = msix_vector;
1041 tasklet_setup(&creq->creq_tasklet, bnxt_qplib_service_creq);
1043 tasklet_enable(&creq->creq_tasklet);
1045 creq->irq_name = kasprintf(GFP_KERNEL, "bnxt_re-creq@pci:%s",
1046 pci_name(res->pdev));
1047 if (!creq->irq_name)
1049 rc = request_irq(creq->msix_vec, bnxt_qplib_creq_irq, 0,
1050 creq->irq_name, rcfw);
1052 kfree(creq->irq_name);
1053 creq->irq_name = NULL;
1054 tasklet_disable(&creq->creq_tasklet);
1057 creq->requested = true;
1059 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, res->cctx, true);
1060 atomic_inc(&rcfw->rcfw_intr_enabled);
1065 static int bnxt_qplib_map_cmdq_mbox(struct bnxt_qplib_rcfw *rcfw)
1067 struct bnxt_qplib_cmdq_mbox *mbox;
1068 resource_size_t bar_reg;
1069 struct pci_dev *pdev;
1072 mbox = &rcfw->cmdq.cmdq_mbox;
1074 mbox->reg.bar_id = RCFW_COMM_PCI_BAR_REGION;
1075 mbox->reg.len = RCFW_COMM_SIZE;
1076 mbox->reg.bar_base = pci_resource_start(pdev, mbox->reg.bar_id);
1077 if (!mbox->reg.bar_base) {
1079 "QPLIB: CMDQ BAR region %d resc start is 0!\n",
1084 bar_reg = mbox->reg.bar_base + RCFW_COMM_BASE_OFFSET;
1085 mbox->reg.len = RCFW_COMM_SIZE;
1086 mbox->reg.bar_reg = ioremap(bar_reg, mbox->reg.len);
1087 if (!mbox->reg.bar_reg) {
1089 "QPLIB: CMDQ BAR region %d mapping failed\n",
1094 mbox->prod = (void __iomem *)(mbox->reg.bar_reg +
1095 RCFW_PF_VF_COMM_PROD_OFFSET);
1096 mbox->db = (void __iomem *)(mbox->reg.bar_reg + RCFW_COMM_TRIG_OFFSET);
1100 static int bnxt_qplib_map_creq_db(struct bnxt_qplib_rcfw *rcfw, u32 reg_offt)
1102 struct bnxt_qplib_creq_db *creq_db;
1103 resource_size_t bar_reg;
1104 struct pci_dev *pdev;
1107 creq_db = &rcfw->creq.creq_db;
1109 creq_db->reg.bar_id = RCFW_COMM_CONS_PCI_BAR_REGION;
1110 creq_db->reg.bar_base = pci_resource_start(pdev, creq_db->reg.bar_id);
1111 if (!creq_db->reg.bar_id)
1113 "QPLIB: CREQ BAR region %d resc start is 0!",
1114 creq_db->reg.bar_id);
1116 bar_reg = creq_db->reg.bar_base + reg_offt;
1117 /* Unconditionally map 8 bytes to support 57500 series */
1118 creq_db->reg.len = 8;
1119 creq_db->reg.bar_reg = ioremap(bar_reg, creq_db->reg.len);
1120 if (!creq_db->reg.bar_reg) {
1122 "QPLIB: CREQ BAR region %d mapping failed",
1123 creq_db->reg.bar_id);
1126 creq_db->dbinfo.db = creq_db->reg.bar_reg;
1127 creq_db->dbinfo.hwq = &rcfw->creq.hwq;
1128 creq_db->dbinfo.xid = rcfw->creq.ring_id;
1132 static void bnxt_qplib_start_rcfw(struct bnxt_qplib_rcfw *rcfw)
1134 struct bnxt_qplib_cmdq_ctx *cmdq;
1135 struct bnxt_qplib_creq_ctx *creq;
1136 struct bnxt_qplib_cmdq_mbox *mbox;
1137 struct cmdq_init init = {0};
1141 mbox = &cmdq->cmdq_mbox;
1143 init.cmdq_pbl = cpu_to_le64(cmdq->hwq.pbl[PBL_LVL_0].pg_map_arr[0]);
1144 init.cmdq_size_cmdq_lvl =
1145 cpu_to_le16(((rcfw->cmdq_depth <<
1146 CMDQ_INIT_CMDQ_SIZE_SFT) &
1147 CMDQ_INIT_CMDQ_SIZE_MASK) |
1148 ((cmdq->hwq.level <<
1149 CMDQ_INIT_CMDQ_LVL_SFT) &
1150 CMDQ_INIT_CMDQ_LVL_MASK));
1151 init.creq_ring_id = cpu_to_le16(creq->ring_id);
1152 /* Write to the Bono mailbox register */
1153 __iowrite32_copy(mbox->reg.bar_reg, &init, sizeof(init) / 4);
1156 int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw,
1159 aeq_handler_t aeq_handler)
1161 struct bnxt_qplib_cmdq_ctx *cmdq;
1162 struct bnxt_qplib_creq_ctx *creq;
1168 /* Clear to defaults */
1171 set_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags);
1172 init_waitqueue_head(&cmdq->waitq);
1174 creq->stats.creq_qp_event_processed = 0;
1175 creq->stats.creq_func_event_processed = 0;
1176 creq->aeq_handler = aeq_handler;
1178 rc = bnxt_qplib_map_cmdq_mbox(rcfw);
1182 rc = bnxt_qplib_map_creq_db(rcfw, cp_bar_reg_off);
1186 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_vector, true);
1188 dev_err(&rcfw->pdev->dev,
1189 "Failed to request IRQ for CREQ rc = 0x%x\n", rc);
1190 bnxt_qplib_disable_rcfw_channel(rcfw);
1194 sema_init(&rcfw->rcfw_inflight, RCFW_CMD_NON_BLOCKING_SHADOW_QD);
1195 bnxt_qplib_start_rcfw(rcfw);
1200 struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
1201 struct bnxt_qplib_rcfw *rcfw,
1204 struct bnxt_qplib_rcfw_sbuf *sbuf;
1206 sbuf = kzalloc(sizeof(*sbuf), GFP_KERNEL);
1211 sbuf->sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf->size,
1212 &sbuf->dma_addr, GFP_KERNEL);
1222 void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
1223 struct bnxt_qplib_rcfw_sbuf *sbuf)
1226 dma_free_coherent(&rcfw->pdev->dev, sbuf->size,
1227 sbuf->sb, sbuf->dma_addr);