2 * Broadcom NetXtreme-E RoCE driver.
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Description: Fast Path Operators
39 #define dev_fmt(fmt) "QPLIB: " fmt
41 #include <linux/interrupt.h>
42 #include <linux/spinlock.h>
43 #include <linux/sched.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/delay.h>
47 #include <linux/prefetch.h>
48 #include <linux/if_ether.h>
49 #include <rdma/ib_mad.h>
53 #include "qplib_res.h"
54 #include "qplib_rcfw.h"
58 static void __clean_cq(struct bnxt_qplib_cq *cq, u64 qp);
60 static void bnxt_qplib_cancel_phantom_processing(struct bnxt_qplib_qp *qp)
62 qp->sq.condition = false;
63 qp->sq.send_phantom = false;
64 qp->sq.single = false;
68 static void __bnxt_qplib_add_flush_qp(struct bnxt_qplib_qp *qp)
70 struct bnxt_qplib_cq *scq, *rcq;
75 if (!qp->sq.flushed) {
76 dev_dbg(&scq->hwq.pdev->dev,
77 "FP: Adding to SQ Flush list = %p\n", qp);
78 bnxt_qplib_cancel_phantom_processing(qp);
79 list_add_tail(&qp->sq_flush, &scq->sqf_head);
80 qp->sq.flushed = true;
83 if (!qp->rq.flushed) {
84 dev_dbg(&rcq->hwq.pdev->dev,
85 "FP: Adding to RQ Flush list = %p\n", qp);
86 list_add_tail(&qp->rq_flush, &rcq->rqf_head);
87 qp->rq.flushed = true;
92 static void bnxt_qplib_acquire_cq_flush_locks(struct bnxt_qplib_qp *qp,
94 __acquires(&qp->scq->flush_lock) __acquires(&qp->rcq->flush_lock)
96 spin_lock_irqsave(&qp->scq->flush_lock, *flags);
97 if (qp->scq == qp->rcq)
98 __acquire(&qp->rcq->flush_lock);
100 spin_lock(&qp->rcq->flush_lock);
103 static void bnxt_qplib_release_cq_flush_locks(struct bnxt_qplib_qp *qp,
104 unsigned long *flags)
105 __releases(&qp->scq->flush_lock) __releases(&qp->rcq->flush_lock)
107 if (qp->scq == qp->rcq)
108 __release(&qp->rcq->flush_lock);
110 spin_unlock(&qp->rcq->flush_lock);
111 spin_unlock_irqrestore(&qp->scq->flush_lock, *flags);
114 void bnxt_qplib_add_flush_qp(struct bnxt_qplib_qp *qp)
118 bnxt_qplib_acquire_cq_flush_locks(qp, &flags);
119 __bnxt_qplib_add_flush_qp(qp);
120 bnxt_qplib_release_cq_flush_locks(qp, &flags);
123 static void __bnxt_qplib_del_flush_qp(struct bnxt_qplib_qp *qp)
125 if (qp->sq.flushed) {
126 qp->sq.flushed = false;
127 list_del(&qp->sq_flush);
130 if (qp->rq.flushed) {
131 qp->rq.flushed = false;
132 list_del(&qp->rq_flush);
137 void bnxt_qplib_clean_qp(struct bnxt_qplib_qp *qp)
141 bnxt_qplib_acquire_cq_flush_locks(qp, &flags);
142 __clean_cq(qp->scq, (u64)(unsigned long)qp);
145 __clean_cq(qp->rcq, (u64)(unsigned long)qp);
149 __bnxt_qplib_del_flush_qp(qp);
150 bnxt_qplib_release_cq_flush_locks(qp, &flags);
153 static void bnxt_qpn_cqn_sched_task(struct work_struct *work)
155 struct bnxt_qplib_nq_work *nq_work =
156 container_of(work, struct bnxt_qplib_nq_work, work);
158 struct bnxt_qplib_cq *cq = nq_work->cq;
159 struct bnxt_qplib_nq *nq = nq_work->nq;
162 spin_lock_bh(&cq->compl_lock);
163 if (atomic_read(&cq->arm_state) && nq->cqn_handler) {
164 dev_dbg(&nq->pdev->dev,
165 "%s:Trigger cq = %p event nq = %p\n",
167 nq->cqn_handler(nq, cq);
169 spin_unlock_bh(&cq->compl_lock);
174 static void bnxt_qplib_free_qp_hdr_buf(struct bnxt_qplib_res *res,
175 struct bnxt_qplib_qp *qp)
177 struct bnxt_qplib_q *rq = &qp->rq;
178 struct bnxt_qplib_q *sq = &qp->sq;
181 dma_free_coherent(&res->pdev->dev,
182 rq->max_wqe * qp->rq_hdr_buf_size,
183 qp->rq_hdr_buf, qp->rq_hdr_buf_map);
185 dma_free_coherent(&res->pdev->dev,
186 sq->max_wqe * qp->sq_hdr_buf_size,
187 qp->sq_hdr_buf, qp->sq_hdr_buf_map);
188 qp->rq_hdr_buf = NULL;
189 qp->sq_hdr_buf = NULL;
190 qp->rq_hdr_buf_map = 0;
191 qp->sq_hdr_buf_map = 0;
192 qp->sq_hdr_buf_size = 0;
193 qp->rq_hdr_buf_size = 0;
196 static int bnxt_qplib_alloc_qp_hdr_buf(struct bnxt_qplib_res *res,
197 struct bnxt_qplib_qp *qp)
199 struct bnxt_qplib_q *rq = &qp->rq;
200 struct bnxt_qplib_q *sq = &qp->sq;
203 if (qp->sq_hdr_buf_size && sq->max_wqe) {
204 qp->sq_hdr_buf = dma_alloc_coherent(&res->pdev->dev,
205 sq->max_wqe * qp->sq_hdr_buf_size,
206 &qp->sq_hdr_buf_map, GFP_KERNEL);
207 if (!qp->sq_hdr_buf) {
209 dev_err(&res->pdev->dev,
210 "Failed to create sq_hdr_buf\n");
215 if (qp->rq_hdr_buf_size && rq->max_wqe) {
216 qp->rq_hdr_buf = dma_alloc_coherent(&res->pdev->dev,
221 if (!qp->rq_hdr_buf) {
223 dev_err(&res->pdev->dev,
224 "Failed to create rq_hdr_buf\n");
231 bnxt_qplib_free_qp_hdr_buf(res, qp);
235 static void clean_nq(struct bnxt_qplib_nq *nq, struct bnxt_qplib_cq *cq)
237 struct bnxt_qplib_hwq *hwq = &nq->hwq;
238 struct nq_base *nqe, **nq_ptr;
239 int budget = nq->budget;
240 u32 sw_cons, raw_cons;
244 spin_lock_bh(&hwq->lock);
245 /* Service the NQ until empty */
246 raw_cons = hwq->cons;
248 sw_cons = HWQ_CMP(raw_cons, hwq);
249 nq_ptr = (struct nq_base **)hwq->pbl_ptr;
250 nqe = &nq_ptr[NQE_PG(sw_cons)][NQE_IDX(sw_cons)];
251 if (!NQE_CMP_VALID(nqe, raw_cons, hwq->max_elements))
255 * The valid test of the entry must be done first before
256 * reading any further.
260 type = le16_to_cpu(nqe->info10_type) & NQ_BASE_TYPE_MASK;
262 case NQ_BASE_TYPE_CQ_NOTIFICATION:
264 struct nq_cn *nqcne = (struct nq_cn *)nqe;
266 q_handle = le32_to_cpu(nqcne->cq_handle_low);
267 q_handle |= (u64)le32_to_cpu(nqcne->cq_handle_high)
269 if ((unsigned long)cq == q_handle) {
270 nqcne->cq_handle_low = 0;
271 nqcne->cq_handle_high = 0;
281 spin_unlock_bh(&hwq->lock);
284 /* Wait for receiving all NQEs for this CQ and clean the NQEs associated with
287 static void __wait_for_all_nqes(struct bnxt_qplib_cq *cq, u16 cnq_events)
291 while (retry_cnt--) {
292 if (cnq_events == cq->cnq_events)
294 usleep_range(50, 100);
295 clean_nq(cq->nq, cq);
299 static void bnxt_qplib_service_nq(struct tasklet_struct *t)
301 struct bnxt_qplib_nq *nq = from_tasklet(nq, t, nq_tasklet);
302 struct bnxt_qplib_hwq *hwq = &nq->hwq;
303 struct bnxt_qplib_cq *cq;
304 int budget = nq->budget;
305 u32 sw_cons, raw_cons;
310 spin_lock_bh(&hwq->lock);
311 /* Service the NQ until empty */
312 raw_cons = hwq->cons;
314 sw_cons = HWQ_CMP(raw_cons, hwq);
315 nqe = bnxt_qplib_get_qe(hwq, sw_cons, NULL);
316 if (!NQE_CMP_VALID(nqe, raw_cons, hwq->max_elements))
320 * The valid test of the entry must be done first before
321 * reading any further.
325 type = le16_to_cpu(nqe->info10_type) & NQ_BASE_TYPE_MASK;
327 case NQ_BASE_TYPE_CQ_NOTIFICATION:
329 struct nq_cn *nqcne = (struct nq_cn *)nqe;
331 q_handle = le32_to_cpu(nqcne->cq_handle_low);
332 q_handle |= (u64)le32_to_cpu(nqcne->cq_handle_high)
334 cq = (struct bnxt_qplib_cq *)(unsigned long)q_handle;
337 bnxt_qplib_armen_db(&cq->dbinfo,
338 DBC_DBC_TYPE_CQ_ARMENA);
339 spin_lock_bh(&cq->compl_lock);
340 atomic_set(&cq->arm_state, 0);
341 if (nq->cqn_handler(nq, (cq)))
342 dev_warn(&nq->pdev->dev,
343 "cqn - type 0x%x not handled\n", type);
345 spin_unlock_bh(&cq->compl_lock);
348 case NQ_BASE_TYPE_SRQ_EVENT:
350 struct bnxt_qplib_srq *srq;
351 struct nq_srq_event *nqsrqe =
352 (struct nq_srq_event *)nqe;
354 q_handle = le32_to_cpu(nqsrqe->srq_handle_low);
355 q_handle |= (u64)le32_to_cpu(nqsrqe->srq_handle_high)
357 srq = (struct bnxt_qplib_srq *)q_handle;
358 bnxt_qplib_armen_db(&srq->dbinfo,
359 DBC_DBC_TYPE_SRQ_ARMENA);
360 if (nq->srqn_handler(nq,
361 (struct bnxt_qplib_srq *)q_handle,
363 dev_warn(&nq->pdev->dev,
364 "SRQ event 0x%x not handled\n",
368 case NQ_BASE_TYPE_DBQ_EVENT:
371 dev_warn(&nq->pdev->dev,
372 "nqe with type = 0x%x not handled\n", type);
377 if (hwq->cons != raw_cons) {
378 hwq->cons = raw_cons;
379 bnxt_qplib_ring_nq_db(&nq->nq_db.dbinfo, nq->res->cctx, true);
381 spin_unlock_bh(&hwq->lock);
384 static irqreturn_t bnxt_qplib_nq_irq(int irq, void *dev_instance)
386 struct bnxt_qplib_nq *nq = dev_instance;
387 struct bnxt_qplib_hwq *hwq = &nq->hwq;
390 /* Prefetch the NQ element */
391 sw_cons = HWQ_CMP(hwq->cons, hwq);
392 prefetch(bnxt_qplib_get_qe(hwq, sw_cons, NULL));
394 /* Fan out to CPU affinitized kthreads? */
395 tasklet_schedule(&nq->nq_tasklet);
400 void bnxt_qplib_nq_stop_irq(struct bnxt_qplib_nq *nq, bool kill)
402 tasklet_disable(&nq->nq_tasklet);
403 /* Mask h/w interrupt */
404 bnxt_qplib_ring_nq_db(&nq->nq_db.dbinfo, nq->res->cctx, false);
405 /* Sync with last running IRQ handler */
406 synchronize_irq(nq->msix_vec);
408 tasklet_kill(&nq->nq_tasklet);
410 irq_set_affinity_hint(nq->msix_vec, NULL);
411 free_irq(nq->msix_vec, nq);
412 nq->requested = false;
416 void bnxt_qplib_disable_nq(struct bnxt_qplib_nq *nq)
419 destroy_workqueue(nq->cqn_wq);
423 /* Make sure the HW is stopped! */
424 bnxt_qplib_nq_stop_irq(nq, true);
426 if (nq->nq_db.reg.bar_reg) {
427 iounmap(nq->nq_db.reg.bar_reg);
428 nq->nq_db.reg.bar_reg = NULL;
431 nq->cqn_handler = NULL;
432 nq->srqn_handler = NULL;
436 int bnxt_qplib_nq_start_irq(struct bnxt_qplib_nq *nq, int nq_indx,
437 int msix_vector, bool need_init)
444 nq->msix_vec = msix_vector;
446 tasklet_setup(&nq->nq_tasklet, bnxt_qplib_service_nq);
448 tasklet_enable(&nq->nq_tasklet);
450 snprintf(nq->name, sizeof(nq->name), "bnxt_qplib_nq-%d", nq_indx);
451 rc = request_irq(nq->msix_vec, bnxt_qplib_nq_irq, 0, nq->name, nq);
455 cpumask_clear(&nq->mask);
456 cpumask_set_cpu(nq_indx, &nq->mask);
457 rc = irq_set_affinity_hint(nq->msix_vec, &nq->mask);
459 dev_warn(&nq->pdev->dev,
460 "set affinity failed; vector: %d nq_idx: %d\n",
461 nq->msix_vec, nq_indx);
463 nq->requested = true;
464 bnxt_qplib_ring_nq_db(&nq->nq_db.dbinfo, nq->res->cctx, true);
469 static int bnxt_qplib_map_nq_db(struct bnxt_qplib_nq *nq, u32 reg_offt)
471 resource_size_t reg_base;
472 struct bnxt_qplib_nq_db *nq_db;
473 struct pci_dev *pdev;
479 nq_db->reg.bar_id = NQ_CONS_PCI_BAR_REGION;
480 nq_db->reg.bar_base = pci_resource_start(pdev, nq_db->reg.bar_id);
481 if (!nq_db->reg.bar_base) {
482 dev_err(&pdev->dev, "QPLIB: NQ BAR region %d resc start is 0!",
488 reg_base = nq_db->reg.bar_base + reg_offt;
489 /* Unconditionally map 8 bytes to support 57500 series */
491 nq_db->reg.bar_reg = ioremap(reg_base, nq_db->reg.len);
492 if (!nq_db->reg.bar_reg) {
493 dev_err(&pdev->dev, "QPLIB: NQ BAR region %d mapping failed",
499 nq_db->dbinfo.db = nq_db->reg.bar_reg;
500 nq_db->dbinfo.hwq = &nq->hwq;
501 nq_db->dbinfo.xid = nq->ring_id;
506 int bnxt_qplib_enable_nq(struct pci_dev *pdev, struct bnxt_qplib_nq *nq,
507 int nq_idx, int msix_vector, int bar_reg_offset,
508 cqn_handler_t cqn_handler,
509 srqn_handler_t srqn_handler)
514 nq->cqn_handler = cqn_handler;
515 nq->srqn_handler = srqn_handler;
517 /* Have a task to schedule CQ notifiers in post send case */
518 nq->cqn_wq = create_singlethread_workqueue("bnxt_qplib_nq");
522 rc = bnxt_qplib_map_nq_db(nq, bar_reg_offset);
526 rc = bnxt_qplib_nq_start_irq(nq, nq_idx, msix_vector, true);
528 dev_err(&nq->pdev->dev,
529 "Failed to request irq for nq-idx %d\n", nq_idx);
535 bnxt_qplib_disable_nq(nq);
539 void bnxt_qplib_free_nq(struct bnxt_qplib_nq *nq)
541 if (nq->hwq.max_elements) {
542 bnxt_qplib_free_hwq(nq->res, &nq->hwq);
543 nq->hwq.max_elements = 0;
547 int bnxt_qplib_alloc_nq(struct bnxt_qplib_res *res, struct bnxt_qplib_nq *nq)
549 struct bnxt_qplib_hwq_attr hwq_attr = {};
550 struct bnxt_qplib_sg_info sginfo = {};
552 nq->pdev = res->pdev;
554 if (!nq->hwq.max_elements ||
555 nq->hwq.max_elements > BNXT_QPLIB_NQE_MAX_CNT)
556 nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT;
558 sginfo.pgsize = PAGE_SIZE;
559 sginfo.pgshft = PAGE_SHIFT;
561 hwq_attr.sginfo = &sginfo;
562 hwq_attr.depth = nq->hwq.max_elements;
563 hwq_attr.stride = sizeof(struct nq_base);
564 hwq_attr.type = bnxt_qplib_get_hwq_type(nq->res);
565 if (bnxt_qplib_alloc_init_hwq(&nq->hwq, &hwq_attr)) {
566 dev_err(&nq->pdev->dev, "FP NQ allocation failed");
574 void bnxt_qplib_destroy_srq(struct bnxt_qplib_res *res,
575 struct bnxt_qplib_srq *srq)
577 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
578 struct creq_destroy_srq_resp resp = {};
579 struct bnxt_qplib_cmdqmsg msg = {};
580 struct cmdq_destroy_srq req = {};
583 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
584 CMDQ_BASE_OPCODE_DESTROY_SRQ,
587 /* Configure the request */
588 req.srq_cid = cpu_to_le32(srq->id);
590 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0);
591 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
595 bnxt_qplib_free_hwq(res, &srq->hwq);
598 int bnxt_qplib_create_srq(struct bnxt_qplib_res *res,
599 struct bnxt_qplib_srq *srq)
601 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
602 struct bnxt_qplib_hwq_attr hwq_attr = {};
603 struct creq_create_srq_resp resp = {};
604 struct bnxt_qplib_cmdqmsg msg = {};
605 struct cmdq_create_srq req = {};
606 struct bnxt_qplib_pbl *pbl;
611 hwq_attr.sginfo = &srq->sg_info;
612 hwq_attr.depth = srq->max_wqe;
613 hwq_attr.stride = srq->wqe_size;
614 hwq_attr.type = HWQ_TYPE_QUEUE;
615 rc = bnxt_qplib_alloc_init_hwq(&srq->hwq, &hwq_attr);
619 srq->swq = kcalloc(srq->hwq.max_elements, sizeof(*srq->swq),
626 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
627 CMDQ_BASE_OPCODE_CREATE_SRQ,
630 /* Configure the request */
631 req.dpi = cpu_to_le32(srq->dpi->dpi);
632 req.srq_handle = cpu_to_le64((uintptr_t)srq);
634 req.srq_size = cpu_to_le16((u16)srq->hwq.max_elements);
635 pbl = &srq->hwq.pbl[PBL_LVL_0];
636 pg_sz_lvl = ((u16)bnxt_qplib_base_pg_size(&srq->hwq) <<
637 CMDQ_CREATE_SRQ_PG_SIZE_SFT);
638 pg_sz_lvl |= (srq->hwq.level & CMDQ_CREATE_SRQ_LVL_MASK) <<
639 CMDQ_CREATE_SRQ_LVL_SFT;
640 req.pg_size_lvl = cpu_to_le16(pg_sz_lvl);
641 req.pbl = cpu_to_le64(pbl->pg_map_arr[0]);
642 req.pd_id = cpu_to_le32(srq->pd->id);
643 req.eventq_id = cpu_to_le16(srq->eventq_hw_ring_id);
645 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0);
646 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
650 spin_lock_init(&srq->lock);
652 srq->last_idx = srq->hwq.max_elements - 1;
653 for (idx = 0; idx < srq->hwq.max_elements; idx++)
654 srq->swq[idx].next_idx = idx + 1;
655 srq->swq[srq->last_idx].next_idx = -1;
657 srq->id = le32_to_cpu(resp.xid);
658 srq->dbinfo.hwq = &srq->hwq;
659 srq->dbinfo.xid = srq->id;
660 srq->dbinfo.db = srq->dpi->dbr;
661 srq->dbinfo.max_slot = 1;
662 srq->dbinfo.priv_db = res->dpi_tbl.dbr_bar_reg_iomem;
664 bnxt_qplib_armen_db(&srq->dbinfo, DBC_DBC_TYPE_SRQ_ARMENA);
665 srq->arm_req = false;
669 bnxt_qplib_free_hwq(res, &srq->hwq);
675 int bnxt_qplib_modify_srq(struct bnxt_qplib_res *res,
676 struct bnxt_qplib_srq *srq)
678 struct bnxt_qplib_hwq *srq_hwq = &srq->hwq;
679 u32 sw_prod, sw_cons, count = 0;
681 sw_prod = HWQ_CMP(srq_hwq->prod, srq_hwq);
682 sw_cons = HWQ_CMP(srq_hwq->cons, srq_hwq);
684 count = sw_prod > sw_cons ? sw_prod - sw_cons :
685 srq_hwq->max_elements - sw_cons + sw_prod;
686 if (count > srq->threshold) {
687 srq->arm_req = false;
688 bnxt_qplib_srq_arm_db(&srq->dbinfo, srq->threshold);
690 /* Deferred arming */
697 int bnxt_qplib_query_srq(struct bnxt_qplib_res *res,
698 struct bnxt_qplib_srq *srq)
700 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
701 struct creq_query_srq_resp resp = {};
702 struct bnxt_qplib_cmdqmsg msg = {};
703 struct bnxt_qplib_rcfw_sbuf *sbuf;
704 struct creq_query_srq_resp_sb *sb;
705 struct cmdq_query_srq req = {};
708 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
709 CMDQ_BASE_OPCODE_QUERY_SRQ,
712 /* Configure the request */
713 sbuf = bnxt_qplib_rcfw_alloc_sbuf(rcfw, sizeof(*sb));
716 req.resp_size = sizeof(*sb) / BNXT_QPLIB_CMDQE_UNITS;
717 req.srq_cid = cpu_to_le32(srq->id);
719 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, sbuf, sizeof(req),
721 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
722 srq->threshold = le16_to_cpu(sb->srq_limit);
723 bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf);
728 int bnxt_qplib_post_srq_recv(struct bnxt_qplib_srq *srq,
729 struct bnxt_qplib_swqe *wqe)
731 struct bnxt_qplib_hwq *srq_hwq = &srq->hwq;
733 struct sq_sge *hw_sge;
734 u32 sw_prod, sw_cons, count = 0;
737 spin_lock(&srq_hwq->lock);
738 if (srq->start_idx == srq->last_idx) {
739 dev_err(&srq_hwq->pdev->dev,
740 "FP: SRQ (0x%x) is full!\n", srq->id);
742 spin_unlock(&srq_hwq->lock);
745 next = srq->start_idx;
746 srq->start_idx = srq->swq[next].next_idx;
747 spin_unlock(&srq_hwq->lock);
749 sw_prod = HWQ_CMP(srq_hwq->prod, srq_hwq);
750 srqe = bnxt_qplib_get_qe(srq_hwq, sw_prod, NULL);
751 memset(srqe, 0, srq->wqe_size);
752 /* Calculate wqe_size16 and data_len */
753 for (i = 0, hw_sge = (struct sq_sge *)srqe->data;
754 i < wqe->num_sge; i++, hw_sge++) {
755 hw_sge->va_or_pa = cpu_to_le64(wqe->sg_list[i].addr);
756 hw_sge->l_key = cpu_to_le32(wqe->sg_list[i].lkey);
757 hw_sge->size = cpu_to_le32(wqe->sg_list[i].size);
759 srqe->wqe_type = wqe->type;
760 srqe->flags = wqe->flags;
761 srqe->wqe_size = wqe->num_sge +
762 ((offsetof(typeof(*srqe), data) + 15) >> 4);
763 srqe->wr_id[0] = cpu_to_le32((u32)next);
764 srq->swq[next].wr_id = wqe->wr_id;
768 spin_lock(&srq_hwq->lock);
769 sw_prod = HWQ_CMP(srq_hwq->prod, srq_hwq);
770 /* retaining srq_hwq->cons for this logic
771 * actually the lock is only required to
772 * read srq_hwq->cons.
774 sw_cons = HWQ_CMP(srq_hwq->cons, srq_hwq);
775 count = sw_prod > sw_cons ? sw_prod - sw_cons :
776 srq_hwq->max_elements - sw_cons + sw_prod;
777 spin_unlock(&srq_hwq->lock);
779 bnxt_qplib_ring_prod_db(&srq->dbinfo, DBC_DBC_TYPE_SRQ);
780 if (srq->arm_req == true && count > srq->threshold) {
781 srq->arm_req = false;
782 bnxt_qplib_srq_arm_db(&srq->dbinfo, srq->threshold);
790 static int bnxt_qplib_alloc_init_swq(struct bnxt_qplib_q *que)
795 que->swq = kcalloc(que->max_wqe, sizeof(*que->swq), GFP_KERNEL);
802 que->swq_last = que->max_wqe - 1;
803 for (indx = 0; indx < que->max_wqe; indx++)
804 que->swq[indx].next_idx = indx + 1;
805 que->swq[que->swq_last].next_idx = 0; /* Make it circular */
811 int bnxt_qplib_create_qp1(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp)
813 struct bnxt_qplib_hwq_attr hwq_attr = {};
814 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
815 struct creq_create_qp1_resp resp = {};
816 struct bnxt_qplib_cmdqmsg msg = {};
817 struct bnxt_qplib_q *sq = &qp->sq;
818 struct bnxt_qplib_q *rq = &qp->rq;
819 struct cmdq_create_qp1 req = {};
820 struct bnxt_qplib_pbl *pbl;
826 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
827 CMDQ_BASE_OPCODE_CREATE_QP1,
831 req.dpi = cpu_to_le32(qp->dpi->dpi);
832 req.qp_handle = cpu_to_le64(qp->qp_handle);
836 hwq_attr.sginfo = &sq->sg_info;
837 hwq_attr.stride = sizeof(struct sq_sge);
838 hwq_attr.depth = bnxt_qplib_get_depth(sq);
839 hwq_attr.type = HWQ_TYPE_QUEUE;
840 rc = bnxt_qplib_alloc_init_hwq(&sq->hwq, &hwq_attr);
844 rc = bnxt_qplib_alloc_init_swq(sq);
848 req.sq_size = cpu_to_le32(bnxt_qplib_set_sq_size(sq, qp->wqe_mode));
849 pbl = &sq->hwq.pbl[PBL_LVL_0];
850 req.sq_pbl = cpu_to_le64(pbl->pg_map_arr[0]);
851 pg_sz_lvl = (bnxt_qplib_base_pg_size(&sq->hwq) <<
852 CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT);
853 pg_sz_lvl |= (sq->hwq.level & CMDQ_CREATE_QP1_SQ_LVL_MASK);
854 req.sq_pg_size_sq_lvl = pg_sz_lvl;
856 cpu_to_le16((sq->max_sge & CMDQ_CREATE_QP1_SQ_SGE_MASK) <<
857 CMDQ_CREATE_QP1_SQ_SGE_SFT);
858 req.scq_cid = cpu_to_le32(qp->scq->id);
863 hwq_attr.sginfo = &rq->sg_info;
864 hwq_attr.stride = sizeof(struct sq_sge);
865 hwq_attr.depth = bnxt_qplib_get_depth(rq);
866 hwq_attr.type = HWQ_TYPE_QUEUE;
867 rc = bnxt_qplib_alloc_init_hwq(&rq->hwq, &hwq_attr);
870 rc = bnxt_qplib_alloc_init_swq(rq);
873 req.rq_size = cpu_to_le32(rq->max_wqe);
874 pbl = &rq->hwq.pbl[PBL_LVL_0];
875 req.rq_pbl = cpu_to_le64(pbl->pg_map_arr[0]);
876 pg_sz_lvl = (bnxt_qplib_base_pg_size(&rq->hwq) <<
877 CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT);
878 pg_sz_lvl |= (rq->hwq.level & CMDQ_CREATE_QP1_RQ_LVL_MASK);
879 req.rq_pg_size_rq_lvl = pg_sz_lvl;
881 cpu_to_le16((rq->max_sge &
882 CMDQ_CREATE_QP1_RQ_SGE_MASK) <<
883 CMDQ_CREATE_QP1_RQ_SGE_SFT);
885 req.rcq_cid = cpu_to_le32(qp->rcq->id);
886 /* Header buffer - allow hdr_buf pass in */
887 rc = bnxt_qplib_alloc_qp_hdr_buf(res, qp);
892 qp_flags |= CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE;
893 req.qp_flags = cpu_to_le32(qp_flags);
894 req.pd_id = cpu_to_le32(qp->pd->id);
896 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0);
897 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
901 qp->id = le32_to_cpu(resp.xid);
902 qp->cur_qp_state = CMDQ_MODIFY_QP_NEW_STATE_RESET;
903 qp->cctx = res->cctx;
904 sq->dbinfo.hwq = &sq->hwq;
905 sq->dbinfo.xid = qp->id;
906 sq->dbinfo.db = qp->dpi->dbr;
907 sq->dbinfo.max_slot = bnxt_qplib_set_sq_max_slot(qp->wqe_mode);
909 rq->dbinfo.hwq = &rq->hwq;
910 rq->dbinfo.xid = qp->id;
911 rq->dbinfo.db = qp->dpi->dbr;
912 rq->dbinfo.max_slot = bnxt_qplib_set_rq_max_slot(rq->wqe_size);
914 tbl_indx = map_qp_id_to_tbl_indx(qp->id, rcfw);
915 rcfw->qp_tbl[tbl_indx].qp_id = qp->id;
916 rcfw->qp_tbl[tbl_indx].qp_handle = (void *)qp;
921 bnxt_qplib_free_qp_hdr_buf(res, qp);
925 bnxt_qplib_free_hwq(res, &rq->hwq);
929 bnxt_qplib_free_hwq(res, &sq->hwq);
934 static void bnxt_qplib_init_psn_ptr(struct bnxt_qplib_qp *qp, int size)
936 struct bnxt_qplib_hwq *hwq;
937 struct bnxt_qplib_q *sq;
943 /* First psn entry */
944 fpsne = (u64)bnxt_qplib_get_qe(hwq, hwq->depth, &psn_pg);
945 if (!IS_ALIGNED(fpsne, PAGE_SIZE))
946 indx_pad = (fpsne & ~PAGE_MASK) / size;
947 hwq->pad_pgofft = indx_pad;
948 hwq->pad_pg = (u64 *)psn_pg;
949 hwq->pad_stride = size;
952 int bnxt_qplib_create_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp)
954 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
955 struct bnxt_qplib_hwq_attr hwq_attr = {};
956 struct bnxt_qplib_sg_info sginfo = {};
957 struct creq_create_qp_resp resp = {};
958 struct bnxt_qplib_cmdqmsg msg = {};
959 struct bnxt_qplib_q *sq = &qp->sq;
960 struct bnxt_qplib_q *rq = &qp->rq;
961 struct cmdq_create_qp req = {};
962 int rc, req_size, psn_sz = 0;
963 struct bnxt_qplib_hwq *xrrq;
964 struct bnxt_qplib_pbl *pbl;
970 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
971 CMDQ_BASE_OPCODE_CREATE_QP,
976 req.dpi = cpu_to_le32(qp->dpi->dpi);
977 req.qp_handle = cpu_to_le64(qp->qp_handle);
980 if (qp->type == CMDQ_CREATE_QP_TYPE_RC) {
981 psn_sz = bnxt_qplib_is_chip_gen_p5(res->cctx) ?
982 sizeof(struct sq_psn_search_ext) :
983 sizeof(struct sq_psn_search);
987 hwq_attr.sginfo = &sq->sg_info;
988 hwq_attr.stride = sizeof(struct sq_sge);
989 hwq_attr.depth = bnxt_qplib_get_depth(sq);
990 hwq_attr.aux_stride = psn_sz;
991 hwq_attr.aux_depth = bnxt_qplib_set_sq_size(sq, qp->wqe_mode);
992 hwq_attr.type = HWQ_TYPE_QUEUE;
993 rc = bnxt_qplib_alloc_init_hwq(&sq->hwq, &hwq_attr);
997 rc = bnxt_qplib_alloc_init_swq(sq);
1002 bnxt_qplib_init_psn_ptr(qp, psn_sz);
1004 req.sq_size = cpu_to_le32(bnxt_qplib_set_sq_size(sq, qp->wqe_mode));
1005 pbl = &sq->hwq.pbl[PBL_LVL_0];
1006 req.sq_pbl = cpu_to_le64(pbl->pg_map_arr[0]);
1007 pg_sz_lvl = (bnxt_qplib_base_pg_size(&sq->hwq) <<
1008 CMDQ_CREATE_QP_SQ_PG_SIZE_SFT);
1009 pg_sz_lvl |= (sq->hwq.level & CMDQ_CREATE_QP_SQ_LVL_MASK);
1010 req.sq_pg_size_sq_lvl = pg_sz_lvl;
1012 cpu_to_le16(((sq->max_sge & CMDQ_CREATE_QP_SQ_SGE_MASK) <<
1013 CMDQ_CREATE_QP_SQ_SGE_SFT) | 0);
1014 req.scq_cid = cpu_to_le32(qp->scq->id);
1019 hwq_attr.sginfo = &rq->sg_info;
1020 hwq_attr.stride = sizeof(struct sq_sge);
1021 hwq_attr.depth = bnxt_qplib_get_depth(rq);
1022 hwq_attr.aux_stride = 0;
1023 hwq_attr.aux_depth = 0;
1024 hwq_attr.type = HWQ_TYPE_QUEUE;
1025 rc = bnxt_qplib_alloc_init_hwq(&rq->hwq, &hwq_attr);
1028 rc = bnxt_qplib_alloc_init_swq(rq);
1032 req.rq_size = cpu_to_le32(rq->max_wqe);
1033 pbl = &rq->hwq.pbl[PBL_LVL_0];
1034 req.rq_pbl = cpu_to_le64(pbl->pg_map_arr[0]);
1035 pg_sz_lvl = (bnxt_qplib_base_pg_size(&rq->hwq) <<
1036 CMDQ_CREATE_QP_RQ_PG_SIZE_SFT);
1037 pg_sz_lvl |= (rq->hwq.level & CMDQ_CREATE_QP_RQ_LVL_MASK);
1038 req.rq_pg_size_rq_lvl = pg_sz_lvl;
1039 nsge = (qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
1042 cpu_to_le16(((nsge &
1043 CMDQ_CREATE_QP_RQ_SGE_MASK) <<
1044 CMDQ_CREATE_QP_RQ_SGE_SFT) | 0);
1047 qp_flags |= CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED;
1048 req.srq_cid = cpu_to_le32(qp->srq->id);
1050 req.rcq_cid = cpu_to_le32(qp->rcq->id);
1052 qp_flags |= CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE;
1053 qp_flags |= CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED;
1055 qp_flags |= CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION;
1056 if (qp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE)
1057 qp_flags |= CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED;
1058 if (_is_ext_stats_supported(res->dattr->dev_cap_flags) && !res->is_vf)
1059 qp_flags |= CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED;
1061 req.qp_flags = cpu_to_le32(qp_flags);
1066 xrrq->max_elements =
1067 ORD_LIMIT_TO_ORRQ_SLOTS(qp->max_rd_atomic);
1068 req_size = xrrq->max_elements *
1069 BNXT_QPLIB_MAX_ORRQE_ENTRY_SIZE + PAGE_SIZE - 1;
1070 req_size &= ~(PAGE_SIZE - 1);
1071 sginfo.pgsize = req_size;
1072 sginfo.pgshft = PAGE_SHIFT;
1075 hwq_attr.sginfo = &sginfo;
1076 hwq_attr.depth = xrrq->max_elements;
1077 hwq_attr.stride = BNXT_QPLIB_MAX_ORRQE_ENTRY_SIZE;
1078 hwq_attr.aux_stride = 0;
1079 hwq_attr.aux_depth = 0;
1080 hwq_attr.type = HWQ_TYPE_CTX;
1081 rc = bnxt_qplib_alloc_init_hwq(xrrq, &hwq_attr);
1084 pbl = &xrrq->pbl[PBL_LVL_0];
1085 req.orrq_addr = cpu_to_le64(pbl->pg_map_arr[0]);
1088 xrrq->max_elements = IRD_LIMIT_TO_IRRQ_SLOTS(
1089 qp->max_dest_rd_atomic);
1090 req_size = xrrq->max_elements *
1091 BNXT_QPLIB_MAX_IRRQE_ENTRY_SIZE + PAGE_SIZE - 1;
1092 req_size &= ~(PAGE_SIZE - 1);
1093 sginfo.pgsize = req_size;
1094 hwq_attr.depth = xrrq->max_elements;
1095 hwq_attr.stride = BNXT_QPLIB_MAX_IRRQE_ENTRY_SIZE;
1096 rc = bnxt_qplib_alloc_init_hwq(xrrq, &hwq_attr);
1100 pbl = &xrrq->pbl[PBL_LVL_0];
1101 req.irrq_addr = cpu_to_le64(pbl->pg_map_arr[0]);
1103 req.pd_id = cpu_to_le32(qp->pd->id);
1105 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
1107 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
1111 qp->id = le32_to_cpu(resp.xid);
1112 qp->cur_qp_state = CMDQ_MODIFY_QP_NEW_STATE_RESET;
1113 INIT_LIST_HEAD(&qp->sq_flush);
1114 INIT_LIST_HEAD(&qp->rq_flush);
1115 qp->cctx = res->cctx;
1116 sq->dbinfo.hwq = &sq->hwq;
1117 sq->dbinfo.xid = qp->id;
1118 sq->dbinfo.db = qp->dpi->dbr;
1119 sq->dbinfo.max_slot = bnxt_qplib_set_sq_max_slot(qp->wqe_mode);
1121 rq->dbinfo.hwq = &rq->hwq;
1122 rq->dbinfo.xid = qp->id;
1123 rq->dbinfo.db = qp->dpi->dbr;
1124 rq->dbinfo.max_slot = bnxt_qplib_set_rq_max_slot(rq->wqe_size);
1126 tbl_indx = map_qp_id_to_tbl_indx(qp->id, rcfw);
1127 rcfw->qp_tbl[tbl_indx].qp_id = qp->id;
1128 rcfw->qp_tbl[tbl_indx].qp_handle = (void *)qp;
1132 bnxt_qplib_free_hwq(res, &qp->irrq);
1134 bnxt_qplib_free_hwq(res, &qp->orrq);
1138 bnxt_qplib_free_hwq(res, &rq->hwq);
1142 bnxt_qplib_free_hwq(res, &sq->hwq);
1147 static void __modify_flags_from_init_state(struct bnxt_qplib_qp *qp)
1149 switch (qp->state) {
1150 case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1151 /* INIT->RTR, configure the path_mtu to the default
1152 * 2048 if not being requested
1154 if (!(qp->modify_flags &
1155 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU)) {
1157 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1159 CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1162 ~CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
1163 /* Bono FW require the max_dest_rd_atomic to be >= 1 */
1164 if (qp->max_dest_rd_atomic < 1)
1165 qp->max_dest_rd_atomic = 1;
1166 qp->modify_flags &= ~CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC;
1167 /* Bono FW 20.6.5 requires SGID_INDEX configuration */
1168 if (!(qp->modify_flags &
1169 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX)) {
1171 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX;
1172 qp->ah.sgid_index = 0;
1180 static void __modify_flags_from_rtr_state(struct bnxt_qplib_qp *qp)
1182 switch (qp->state) {
1183 case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1184 /* Bono FW requires the max_rd_atomic to be >= 1 */
1185 if (qp->max_rd_atomic < 1)
1186 qp->max_rd_atomic = 1;
1187 /* Bono FW does not allow PKEY_INDEX,
1188 * DGID, FLOW_LABEL, SGID_INDEX, HOP_LIMIT,
1189 * TRAFFIC_CLASS, DEST_MAC, PATH_MTU, RQ_PSN,
1190 * MIN_RNR_TIMER, MAX_DEST_RD_ATOMIC, DEST_QP_ID
1194 ~(CMDQ_MODIFY_QP_MODIFY_MASK_PKEY |
1195 CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
1196 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
1197 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
1198 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
1199 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
1200 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
1201 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU |
1202 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN |
1203 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER |
1204 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC |
1205 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID);
1212 static void __filter_modify_flags(struct bnxt_qplib_qp *qp)
1214 switch (qp->cur_qp_state) {
1215 case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1217 case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1218 __modify_flags_from_init_state(qp);
1220 case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1221 __modify_flags_from_rtr_state(qp);
1223 case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1225 case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1227 case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1229 case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1236 int bnxt_qplib_modify_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp)
1238 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
1239 struct creq_modify_qp_resp resp = {};
1240 struct bnxt_qplib_cmdqmsg msg = {};
1241 struct cmdq_modify_qp req = {};
1246 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
1247 CMDQ_BASE_OPCODE_MODIFY_QP,
1250 /* Filter out the qp_attr_mask based on the state->new transition */
1251 __filter_modify_flags(qp);
1252 bmask = qp->modify_flags;
1253 req.modify_mask = cpu_to_le32(qp->modify_flags);
1254 req.qp_cid = cpu_to_le32(qp->id);
1255 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_STATE) {
1256 req.network_type_en_sqd_async_notify_new_state =
1257 (qp->state & CMDQ_MODIFY_QP_NEW_STATE_MASK) |
1258 (qp->en_sqd_async_notify ?
1259 CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY : 0);
1261 req.network_type_en_sqd_async_notify_new_state |= qp->nw_type;
1263 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS)
1264 req.access = qp->access;
1266 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_PKEY)
1267 req.pkey = cpu_to_le16(IB_DEFAULT_PKEY_FULL);
1269 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_QKEY)
1270 req.qkey = cpu_to_le32(qp->qkey);
1272 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_DGID) {
1273 memcpy(temp32, qp->ah.dgid.data, sizeof(struct bnxt_qplib_gid));
1274 req.dgid[0] = cpu_to_le32(temp32[0]);
1275 req.dgid[1] = cpu_to_le32(temp32[1]);
1276 req.dgid[2] = cpu_to_le32(temp32[2]);
1277 req.dgid[3] = cpu_to_le32(temp32[3]);
1279 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL)
1280 req.flow_label = cpu_to_le32(qp->ah.flow_label);
1282 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX)
1283 req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id
1284 [qp->ah.sgid_index]);
1286 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT)
1287 req.hop_limit = qp->ah.hop_limit;
1289 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS)
1290 req.traffic_class = qp->ah.traffic_class;
1292 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC)
1293 memcpy(req.dest_mac, qp->ah.dmac, 6);
1295 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU)
1296 req.path_mtu_pingpong_push_enable |= qp->path_mtu;
1298 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT)
1299 req.timeout = qp->timeout;
1301 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT)
1302 req.retry_cnt = qp->retry_cnt;
1304 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY)
1305 req.rnr_retry = qp->rnr_retry;
1307 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER)
1308 req.min_rnr_timer = qp->min_rnr_timer;
1310 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN)
1311 req.rq_psn = cpu_to_le32(qp->rq.psn);
1313 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN)
1314 req.sq_psn = cpu_to_le32(qp->sq.psn);
1316 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC)
1318 ORD_LIMIT_TO_ORRQ_SLOTS(qp->max_rd_atomic);
1320 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC)
1321 req.max_dest_rd_atomic =
1322 IRD_LIMIT_TO_IRRQ_SLOTS(qp->max_dest_rd_atomic);
1324 req.sq_size = cpu_to_le32(qp->sq.hwq.max_elements);
1325 req.rq_size = cpu_to_le32(qp->rq.hwq.max_elements);
1326 req.sq_sge = cpu_to_le16(qp->sq.max_sge);
1327 req.rq_sge = cpu_to_le16(qp->rq.max_sge);
1328 req.max_inline_data = cpu_to_le32(qp->max_inline_data);
1329 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID)
1330 req.dest_qp_id = cpu_to_le32(qp->dest_qpn);
1332 req.vlan_pcp_vlan_dei_vlan_id = cpu_to_le16(qp->vlan_id);
1334 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0);
1335 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
1338 qp->cur_qp_state = qp->state;
1342 int bnxt_qplib_query_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp)
1344 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
1345 struct creq_query_qp_resp resp = {};
1346 struct bnxt_qplib_cmdqmsg msg = {};
1347 struct bnxt_qplib_rcfw_sbuf *sbuf;
1348 struct creq_query_qp_resp_sb *sb;
1349 struct cmdq_query_qp req = {};
1353 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
1354 CMDQ_BASE_OPCODE_QUERY_QP,
1357 sbuf = bnxt_qplib_rcfw_alloc_sbuf(rcfw, sizeof(*sb));
1362 req.qp_cid = cpu_to_le32(qp->id);
1363 req.resp_size = sizeof(*sb) / BNXT_QPLIB_CMDQE_UNITS;
1364 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, sbuf, sizeof(req),
1366 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
1369 /* Extract the context from the side buffer */
1370 qp->state = sb->en_sqd_async_notify_state &
1371 CREQ_QUERY_QP_RESP_SB_STATE_MASK;
1372 qp->en_sqd_async_notify = sb->en_sqd_async_notify_state &
1373 CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY ?
1375 qp->access = sb->access;
1376 qp->pkey_index = le16_to_cpu(sb->pkey);
1377 qp->qkey = le32_to_cpu(sb->qkey);
1379 temp32[0] = le32_to_cpu(sb->dgid[0]);
1380 temp32[1] = le32_to_cpu(sb->dgid[1]);
1381 temp32[2] = le32_to_cpu(sb->dgid[2]);
1382 temp32[3] = le32_to_cpu(sb->dgid[3]);
1383 memcpy(qp->ah.dgid.data, temp32, sizeof(qp->ah.dgid.data));
1385 qp->ah.flow_label = le32_to_cpu(sb->flow_label);
1387 qp->ah.sgid_index = 0;
1388 for (i = 0; i < res->sgid_tbl.max; i++) {
1389 if (res->sgid_tbl.hw_id[i] == le16_to_cpu(sb->sgid_index)) {
1390 qp->ah.sgid_index = i;
1394 if (i == res->sgid_tbl.max)
1395 dev_warn(&res->pdev->dev, "SGID not found??\n");
1397 qp->ah.hop_limit = sb->hop_limit;
1398 qp->ah.traffic_class = sb->traffic_class;
1399 memcpy(qp->ah.dmac, sb->dest_mac, 6);
1400 qp->ah.vlan_id = (le16_to_cpu(sb->path_mtu_dest_vlan_id) &
1401 CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK) >>
1402 CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT;
1403 qp->path_mtu = (le16_to_cpu(sb->path_mtu_dest_vlan_id) &
1404 CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) >>
1405 CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT;
1406 qp->timeout = sb->timeout;
1407 qp->retry_cnt = sb->retry_cnt;
1408 qp->rnr_retry = sb->rnr_retry;
1409 qp->min_rnr_timer = sb->min_rnr_timer;
1410 qp->rq.psn = le32_to_cpu(sb->rq_psn);
1411 qp->max_rd_atomic = ORRQ_SLOTS_TO_ORD_LIMIT(sb->max_rd_atomic);
1412 qp->sq.psn = le32_to_cpu(sb->sq_psn);
1413 qp->max_dest_rd_atomic =
1414 IRRQ_SLOTS_TO_IRD_LIMIT(sb->max_dest_rd_atomic);
1415 qp->sq.max_wqe = qp->sq.hwq.max_elements;
1416 qp->rq.max_wqe = qp->rq.hwq.max_elements;
1417 qp->sq.max_sge = le16_to_cpu(sb->sq_sge);
1418 qp->rq.max_sge = le16_to_cpu(sb->rq_sge);
1419 qp->max_inline_data = le32_to_cpu(sb->max_inline_data);
1420 qp->dest_qpn = le32_to_cpu(sb->dest_qp_id);
1421 memcpy(qp->smac, sb->src_mac, 6);
1422 qp->vlan_id = le16_to_cpu(sb->vlan_pcp_vlan_dei_vlan_id);
1424 bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf);
1428 static void __clean_cq(struct bnxt_qplib_cq *cq, u64 qp)
1430 struct bnxt_qplib_hwq *cq_hwq = &cq->hwq;
1431 struct cq_base *hw_cqe;
1434 for (i = 0; i < cq_hwq->max_elements; i++) {
1435 hw_cqe = bnxt_qplib_get_qe(cq_hwq, i, NULL);
1436 if (!CQE_CMP_VALID(hw_cqe, i, cq_hwq->max_elements))
1439 * The valid test of the entry must be done first before
1440 * reading any further.
1443 switch (hw_cqe->cqe_type_toggle & CQ_BASE_CQE_TYPE_MASK) {
1444 case CQ_BASE_CQE_TYPE_REQ:
1445 case CQ_BASE_CQE_TYPE_TERMINAL:
1447 struct cq_req *cqe = (struct cq_req *)hw_cqe;
1449 if (qp == le64_to_cpu(cqe->qp_handle))
1453 case CQ_BASE_CQE_TYPE_RES_RC:
1454 case CQ_BASE_CQE_TYPE_RES_UD:
1455 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
1457 struct cq_res_rc *cqe = (struct cq_res_rc *)hw_cqe;
1459 if (qp == le64_to_cpu(cqe->qp_handle))
1469 int bnxt_qplib_destroy_qp(struct bnxt_qplib_res *res,
1470 struct bnxt_qplib_qp *qp)
1472 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
1473 struct creq_destroy_qp_resp resp = {};
1474 struct bnxt_qplib_cmdqmsg msg = {};
1475 struct cmdq_destroy_qp req = {};
1479 tbl_indx = map_qp_id_to_tbl_indx(qp->id, rcfw);
1480 rcfw->qp_tbl[tbl_indx].qp_id = BNXT_QPLIB_QP_ID_INVALID;
1481 rcfw->qp_tbl[tbl_indx].qp_handle = NULL;
1483 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
1484 CMDQ_BASE_OPCODE_DESTROY_QP,
1487 req.qp_cid = cpu_to_le32(qp->id);
1488 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
1490 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
1492 rcfw->qp_tbl[tbl_indx].qp_id = qp->id;
1493 rcfw->qp_tbl[tbl_indx].qp_handle = qp;
1500 void bnxt_qplib_free_qp_res(struct bnxt_qplib_res *res,
1501 struct bnxt_qplib_qp *qp)
1503 bnxt_qplib_free_qp_hdr_buf(res, qp);
1504 bnxt_qplib_free_hwq(res, &qp->sq.hwq);
1507 bnxt_qplib_free_hwq(res, &qp->rq.hwq);
1510 if (qp->irrq.max_elements)
1511 bnxt_qplib_free_hwq(res, &qp->irrq);
1512 if (qp->orrq.max_elements)
1513 bnxt_qplib_free_hwq(res, &qp->orrq);
1517 void *bnxt_qplib_get_qp1_sq_buf(struct bnxt_qplib_qp *qp,
1518 struct bnxt_qplib_sge *sge)
1520 struct bnxt_qplib_q *sq = &qp->sq;
1523 memset(sge, 0, sizeof(*sge));
1525 if (qp->sq_hdr_buf) {
1526 sw_prod = sq->swq_start;
1527 sge->addr = (dma_addr_t)(qp->sq_hdr_buf_map +
1528 sw_prod * qp->sq_hdr_buf_size);
1529 sge->lkey = 0xFFFFFFFF;
1530 sge->size = qp->sq_hdr_buf_size;
1531 return qp->sq_hdr_buf + sw_prod * sge->size;
1536 u32 bnxt_qplib_get_rq_prod_index(struct bnxt_qplib_qp *qp)
1538 struct bnxt_qplib_q *rq = &qp->rq;
1540 return rq->swq_start;
1543 dma_addr_t bnxt_qplib_get_qp_buf_from_index(struct bnxt_qplib_qp *qp, u32 index)
1545 return (qp->rq_hdr_buf_map + index * qp->rq_hdr_buf_size);
1548 void *bnxt_qplib_get_qp1_rq_buf(struct bnxt_qplib_qp *qp,
1549 struct bnxt_qplib_sge *sge)
1551 struct bnxt_qplib_q *rq = &qp->rq;
1554 memset(sge, 0, sizeof(*sge));
1556 if (qp->rq_hdr_buf) {
1557 sw_prod = rq->swq_start;
1558 sge->addr = (dma_addr_t)(qp->rq_hdr_buf_map +
1559 sw_prod * qp->rq_hdr_buf_size);
1560 sge->lkey = 0xFFFFFFFF;
1561 sge->size = qp->rq_hdr_buf_size;
1562 return qp->rq_hdr_buf + sw_prod * sge->size;
1567 static void bnxt_qplib_fill_psn_search(struct bnxt_qplib_qp *qp,
1568 struct bnxt_qplib_swqe *wqe,
1569 struct bnxt_qplib_swq *swq)
1571 struct sq_psn_search_ext *psns_ext;
1572 struct sq_psn_search *psns;
1576 if (!swq->psn_search)
1578 psns = swq->psn_search;
1579 psns_ext = swq->psn_ext;
1581 op_spsn = ((swq->start_psn << SQ_PSN_SEARCH_START_PSN_SFT) &
1582 SQ_PSN_SEARCH_START_PSN_MASK);
1583 op_spsn |= ((wqe->type << SQ_PSN_SEARCH_OPCODE_SFT) &
1584 SQ_PSN_SEARCH_OPCODE_MASK);
1585 flg_npsn = ((swq->next_psn << SQ_PSN_SEARCH_NEXT_PSN_SFT) &
1586 SQ_PSN_SEARCH_NEXT_PSN_MASK);
1588 if (bnxt_qplib_is_chip_gen_p5(qp->cctx)) {
1589 psns_ext->opcode_start_psn = cpu_to_le32(op_spsn);
1590 psns_ext->flags_next_psn = cpu_to_le32(flg_npsn);
1591 psns_ext->start_slot_idx = cpu_to_le16(swq->slot_idx);
1593 psns->opcode_start_psn = cpu_to_le32(op_spsn);
1594 psns->flags_next_psn = cpu_to_le32(flg_npsn);
1598 static int bnxt_qplib_put_inline(struct bnxt_qplib_qp *qp,
1599 struct bnxt_qplib_swqe *wqe,
1602 struct bnxt_qplib_hwq *hwq;
1603 int len, t_len, offt;
1604 bool pull_dst = true;
1605 void *il_dst = NULL;
1606 void *il_src = NULL;
1612 for (indx = 0; indx < wqe->num_sge; indx++) {
1613 len = wqe->sg_list[indx].size;
1614 il_src = (void *)wqe->sg_list[indx].addr;
1616 if (t_len > qp->max_inline_data)
1621 il_dst = bnxt_qplib_get_prod_qe(hwq, *idx);
1626 cplen = min_t(int, len, sizeof(struct sq_sge));
1627 cplen = min_t(int, cplen,
1628 (sizeof(struct sq_sge) - offt));
1629 memcpy(il_dst, il_src, cplen);
1635 if (t_cplen == sizeof(struct sq_sge))
1645 static u32 bnxt_qplib_put_sges(struct bnxt_qplib_hwq *hwq,
1646 struct bnxt_qplib_sge *ssge,
1649 struct sq_sge *dsge;
1652 for (indx = 0; indx < nsge; indx++, (*idx)++) {
1653 dsge = bnxt_qplib_get_prod_qe(hwq, *idx);
1654 dsge->va_or_pa = cpu_to_le64(ssge[indx].addr);
1655 dsge->l_key = cpu_to_le32(ssge[indx].lkey);
1656 dsge->size = cpu_to_le32(ssge[indx].size);
1657 len += ssge[indx].size;
1663 static u16 bnxt_qplib_required_slots(struct bnxt_qplib_qp *qp,
1664 struct bnxt_qplib_swqe *wqe,
1665 u16 *wqe_sz, u16 *qdf, u8 mode)
1671 nsge = wqe->num_sge;
1672 /* Adding sq_send_hdr is a misnomer, for rq also hdr size is same. */
1673 bytes = sizeof(struct sq_send_hdr) + nsge * sizeof(struct sq_sge);
1674 if (wqe->flags & BNXT_QPLIB_SWQE_FLAGS_INLINE) {
1675 ilsize = bnxt_qplib_calc_ilsize(wqe, qp->max_inline_data);
1676 bytes = ALIGN(ilsize, sizeof(struct sq_sge));
1677 bytes += sizeof(struct sq_send_hdr);
1680 *qdf = __xlate_qfd(qp->sq.q_full_delta, bytes);
1683 if (mode == BNXT_QPLIB_WQE_MODE_STATIC)
1688 static void bnxt_qplib_pull_psn_buff(struct bnxt_qplib_q *sq,
1689 struct bnxt_qplib_swq *swq)
1691 struct bnxt_qplib_hwq *hwq;
1692 u32 pg_num, pg_indx;
1699 tail = swq->slot_idx / sq->dbinfo.max_slot;
1700 pg_num = (tail + hwq->pad_pgofft) / (PAGE_SIZE / hwq->pad_stride);
1701 pg_indx = (tail + hwq->pad_pgofft) % (PAGE_SIZE / hwq->pad_stride);
1702 buff = (void *)(hwq->pad_pg[pg_num] + pg_indx * hwq->pad_stride);
1703 swq->psn_ext = buff;
1704 swq->psn_search = buff;
1707 void bnxt_qplib_post_send_db(struct bnxt_qplib_qp *qp)
1709 struct bnxt_qplib_q *sq = &qp->sq;
1711 bnxt_qplib_ring_prod_db(&sq->dbinfo, DBC_DBC_TYPE_SQ);
1714 int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp,
1715 struct bnxt_qplib_swqe *wqe)
1717 struct bnxt_qplib_nq_work *nq_work = NULL;
1718 int i, rc = 0, data_len = 0, pkt_num = 0;
1719 struct bnxt_qplib_q *sq = &qp->sq;
1720 struct bnxt_qplib_hwq *hwq;
1721 struct bnxt_qplib_swq *swq;
1722 bool sch_handler = false;
1723 u16 wqe_sz, qdf = 0;
1732 if (qp->state != CMDQ_MODIFY_QP_NEW_STATE_RTS &&
1733 qp->state != CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1734 dev_err(&hwq->pdev->dev,
1735 "QPLIB: FP: QP (0x%x) is in the 0x%x state",
1741 slots = bnxt_qplib_required_slots(qp, wqe, &wqe_sz, &qdf, qp->wqe_mode);
1742 if (bnxt_qplib_queue_full(sq, slots + qdf)) {
1743 dev_err(&hwq->pdev->dev,
1744 "prod = %#x cons = %#x qdepth = %#x delta = %#x\n",
1745 hwq->prod, hwq->cons, hwq->depth, sq->q_full_delta);
1750 swq = bnxt_qplib_get_swqe(sq, &wqe_idx);
1751 bnxt_qplib_pull_psn_buff(sq, swq);
1754 swq->slot_idx = hwq->prod;
1756 swq->wr_id = wqe->wr_id;
1757 swq->type = wqe->type;
1758 swq->flags = wqe->flags;
1759 swq->start_psn = sq->psn & BTH_PSN_MASK;
1761 swq->flags |= SQ_SEND_FLAGS_SIGNAL_COMP;
1763 if (qp->state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1765 dev_dbg(&hwq->pdev->dev,
1766 "%s Error QP. Scheduling for poll_cq\n", __func__);
1770 base_hdr = bnxt_qplib_get_prod_qe(hwq, idx++);
1771 ext_hdr = bnxt_qplib_get_prod_qe(hwq, idx++);
1772 memset(base_hdr, 0, sizeof(struct sq_sge));
1773 memset(ext_hdr, 0, sizeof(struct sq_sge));
1775 if (wqe->flags & BNXT_QPLIB_SWQE_FLAGS_INLINE)
1776 /* Copy the inline data */
1777 data_len = bnxt_qplib_put_inline(qp, wqe, &idx);
1779 data_len = bnxt_qplib_put_sges(hwq, wqe->sg_list, wqe->num_sge,
1784 switch (wqe->type) {
1785 case BNXT_QPLIB_SWQE_TYPE_SEND:
1786 if (qp->type == CMDQ_CREATE_QP1_TYPE_GSI) {
1787 struct sq_send_raweth_qp1_hdr *sqe = base_hdr;
1788 struct sq_raw_ext_hdr *ext_sqe = ext_hdr;
1789 /* Assemble info for Raw Ethertype QPs */
1791 sqe->wqe_type = wqe->type;
1792 sqe->flags = wqe->flags;
1793 sqe->wqe_size = wqe_sz;
1794 sqe->cfa_action = cpu_to_le16(wqe->rawqp1.cfa_action);
1795 sqe->lflags = cpu_to_le16(wqe->rawqp1.lflags);
1796 sqe->length = cpu_to_le32(data_len);
1797 ext_sqe->cfa_meta = cpu_to_le32((wqe->rawqp1.cfa_meta &
1798 SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK) <<
1799 SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT);
1804 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
1805 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
1807 struct sq_ud_ext_hdr *ext_sqe = ext_hdr;
1808 struct sq_send_hdr *sqe = base_hdr;
1810 sqe->wqe_type = wqe->type;
1811 sqe->flags = wqe->flags;
1812 sqe->wqe_size = wqe_sz;
1813 sqe->inv_key_or_imm_data = cpu_to_le32(wqe->send.inv_key);
1814 if (qp->type == CMDQ_CREATE_QP_TYPE_UD ||
1815 qp->type == CMDQ_CREATE_QP_TYPE_GSI) {
1816 sqe->q_key = cpu_to_le32(wqe->send.q_key);
1817 sqe->length = cpu_to_le32(data_len);
1818 sq->psn = (sq->psn + 1) & BTH_PSN_MASK;
1819 ext_sqe->dst_qp = cpu_to_le32(wqe->send.dst_qp &
1820 SQ_SEND_DST_QP_MASK);
1821 ext_sqe->avid = cpu_to_le32(wqe->send.avid &
1824 sqe->length = cpu_to_le32(data_len);
1826 pkt_num = (data_len + qp->mtu - 1) / qp->mtu;
1829 sq->psn = (sq->psn + pkt_num) & BTH_PSN_MASK;
1833 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
1834 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
1835 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
1837 struct sq_rdma_ext_hdr *ext_sqe = ext_hdr;
1838 struct sq_rdma_hdr *sqe = base_hdr;
1840 sqe->wqe_type = wqe->type;
1841 sqe->flags = wqe->flags;
1842 sqe->wqe_size = wqe_sz;
1843 sqe->imm_data = cpu_to_le32(wqe->rdma.inv_key);
1844 sqe->length = cpu_to_le32((u32)data_len);
1845 ext_sqe->remote_va = cpu_to_le64(wqe->rdma.remote_va);
1846 ext_sqe->remote_key = cpu_to_le32(wqe->rdma.r_key);
1848 pkt_num = (data_len + qp->mtu - 1) / qp->mtu;
1851 sq->psn = (sq->psn + pkt_num) & BTH_PSN_MASK;
1854 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
1855 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
1857 struct sq_atomic_ext_hdr *ext_sqe = ext_hdr;
1858 struct sq_atomic_hdr *sqe = base_hdr;
1860 sqe->wqe_type = wqe->type;
1861 sqe->flags = wqe->flags;
1862 sqe->remote_key = cpu_to_le32(wqe->atomic.r_key);
1863 sqe->remote_va = cpu_to_le64(wqe->atomic.remote_va);
1864 ext_sqe->swap_data = cpu_to_le64(wqe->atomic.swap_data);
1865 ext_sqe->cmp_data = cpu_to_le64(wqe->atomic.cmp_data);
1867 pkt_num = (data_len + qp->mtu - 1) / qp->mtu;
1870 sq->psn = (sq->psn + pkt_num) & BTH_PSN_MASK;
1873 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
1875 struct sq_localinvalidate *sqe = base_hdr;
1877 sqe->wqe_type = wqe->type;
1878 sqe->flags = wqe->flags;
1879 sqe->inv_l_key = cpu_to_le32(wqe->local_inv.inv_l_key);
1883 case BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR:
1885 struct sq_fr_pmr_ext_hdr *ext_sqe = ext_hdr;
1886 struct sq_fr_pmr_hdr *sqe = base_hdr;
1888 sqe->wqe_type = wqe->type;
1889 sqe->flags = wqe->flags;
1890 sqe->access_cntl = wqe->frmr.access_cntl |
1891 SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
1892 sqe->zero_based_page_size_log =
1893 (wqe->frmr.pg_sz_log & SQ_FR_PMR_PAGE_SIZE_LOG_MASK) <<
1894 SQ_FR_PMR_PAGE_SIZE_LOG_SFT |
1895 (wqe->frmr.zero_based ? SQ_FR_PMR_ZERO_BASED : 0);
1896 sqe->l_key = cpu_to_le32(wqe->frmr.l_key);
1897 temp32 = cpu_to_le32(wqe->frmr.length);
1898 memcpy(sqe->length, &temp32, sizeof(wqe->frmr.length));
1899 sqe->numlevels_pbl_page_size_log =
1900 ((wqe->frmr.pbl_pg_sz_log <<
1901 SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT) &
1902 SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK) |
1903 ((wqe->frmr.levels << SQ_FR_PMR_NUMLEVELS_SFT) &
1904 SQ_FR_PMR_NUMLEVELS_MASK);
1906 for (i = 0; i < wqe->frmr.page_list_len; i++)
1907 wqe->frmr.pbl_ptr[i] = cpu_to_le64(
1908 wqe->frmr.page_list[i] |
1910 ext_sqe->pblptr = cpu_to_le64(wqe->frmr.pbl_dma_ptr);
1911 ext_sqe->va = cpu_to_le64(wqe->frmr.va);
1915 case BNXT_QPLIB_SWQE_TYPE_BIND_MW:
1917 struct sq_bind_ext_hdr *ext_sqe = ext_hdr;
1918 struct sq_bind_hdr *sqe = base_hdr;
1920 sqe->wqe_type = wqe->type;
1921 sqe->flags = wqe->flags;
1922 sqe->access_cntl = wqe->bind.access_cntl;
1923 sqe->mw_type_zero_based = wqe->bind.mw_type |
1924 (wqe->bind.zero_based ? SQ_BIND_ZERO_BASED : 0);
1925 sqe->parent_l_key = cpu_to_le32(wqe->bind.parent_l_key);
1926 sqe->l_key = cpu_to_le32(wqe->bind.r_key);
1927 ext_sqe->va = cpu_to_le64(wqe->bind.va);
1928 ext_sqe->length_lo = cpu_to_le32(wqe->bind.length);
1932 /* Bad wqe, return error */
1936 swq->next_psn = sq->psn & BTH_PSN_MASK;
1937 bnxt_qplib_fill_psn_search(qp, wqe, swq);
1939 bnxt_qplib_swq_mod_start(sq, wqe_idx);
1940 bnxt_qplib_hwq_incr_prod(hwq, swq->slots);
1944 nq_work = kzalloc(sizeof(*nq_work), GFP_ATOMIC);
1946 nq_work->cq = qp->scq;
1947 nq_work->nq = qp->scq->nq;
1948 INIT_WORK(&nq_work->work, bnxt_qpn_cqn_sched_task);
1949 queue_work(qp->scq->nq->cqn_wq, &nq_work->work);
1951 dev_err(&hwq->pdev->dev,
1952 "FP: Failed to allocate SQ nq_work!\n");
1959 void bnxt_qplib_post_recv_db(struct bnxt_qplib_qp *qp)
1961 struct bnxt_qplib_q *rq = &qp->rq;
1963 bnxt_qplib_ring_prod_db(&rq->dbinfo, DBC_DBC_TYPE_RQ);
1966 int bnxt_qplib_post_recv(struct bnxt_qplib_qp *qp,
1967 struct bnxt_qplib_swqe *wqe)
1969 struct bnxt_qplib_nq_work *nq_work = NULL;
1970 struct bnxt_qplib_q *rq = &qp->rq;
1971 struct rq_wqe_hdr *base_hdr;
1972 struct rq_ext_hdr *ext_hdr;
1973 struct bnxt_qplib_hwq *hwq;
1974 struct bnxt_qplib_swq *swq;
1975 bool sch_handler = false;
1981 if (qp->state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
1982 dev_err(&hwq->pdev->dev,
1983 "QPLIB: FP: QP (0x%x) is in the 0x%x state",
1989 if (bnxt_qplib_queue_full(rq, rq->dbinfo.max_slot)) {
1990 dev_err(&hwq->pdev->dev,
1991 "FP: QP (0x%x) RQ is full!\n", qp->id);
1996 swq = bnxt_qplib_get_swqe(rq, &wqe_idx);
1997 swq->wr_id = wqe->wr_id;
1998 swq->slots = rq->dbinfo.max_slot;
2000 if (qp->state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
2002 dev_dbg(&hwq->pdev->dev,
2003 "%s: Error QP. Scheduling for poll_cq\n", __func__);
2008 base_hdr = bnxt_qplib_get_prod_qe(hwq, idx++);
2009 ext_hdr = bnxt_qplib_get_prod_qe(hwq, idx++);
2010 memset(base_hdr, 0, sizeof(struct sq_sge));
2011 memset(ext_hdr, 0, sizeof(struct sq_sge));
2012 wqe_sz = (sizeof(struct rq_wqe_hdr) +
2013 wqe->num_sge * sizeof(struct sq_sge)) >> 4;
2014 bnxt_qplib_put_sges(hwq, wqe->sg_list, wqe->num_sge, &idx);
2015 if (!wqe->num_sge) {
2018 sge = bnxt_qplib_get_prod_qe(hwq, idx++);
2022 base_hdr->wqe_type = wqe->type;
2023 base_hdr->flags = wqe->flags;
2024 base_hdr->wqe_size = wqe_sz;
2025 base_hdr->wr_id[0] = cpu_to_le32(wqe_idx);
2027 bnxt_qplib_swq_mod_start(rq, wqe_idx);
2028 bnxt_qplib_hwq_incr_prod(hwq, swq->slots);
2031 nq_work = kzalloc(sizeof(*nq_work), GFP_ATOMIC);
2033 nq_work->cq = qp->rcq;
2034 nq_work->nq = qp->rcq->nq;
2035 INIT_WORK(&nq_work->work, bnxt_qpn_cqn_sched_task);
2036 queue_work(qp->rcq->nq->cqn_wq, &nq_work->work);
2038 dev_err(&hwq->pdev->dev,
2039 "FP: Failed to allocate RQ nq_work!\n");
2048 int bnxt_qplib_create_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq)
2050 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
2051 struct bnxt_qplib_hwq_attr hwq_attr = {};
2052 struct creq_create_cq_resp resp = {};
2053 struct bnxt_qplib_cmdqmsg msg = {};
2054 struct cmdq_create_cq req = {};
2055 struct bnxt_qplib_pbl *pbl;
2060 hwq_attr.depth = cq->max_wqe;
2061 hwq_attr.stride = sizeof(struct cq_base);
2062 hwq_attr.type = HWQ_TYPE_QUEUE;
2063 hwq_attr.sginfo = &cq->sg_info;
2064 rc = bnxt_qplib_alloc_init_hwq(&cq->hwq, &hwq_attr);
2068 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
2069 CMDQ_BASE_OPCODE_CREATE_CQ,
2073 dev_err(&rcfw->pdev->dev,
2074 "FP: CREATE_CQ failed due to NULL DPI\n");
2077 req.dpi = cpu_to_le32(cq->dpi->dpi);
2078 req.cq_handle = cpu_to_le64(cq->cq_handle);
2079 req.cq_size = cpu_to_le32(cq->hwq.max_elements);
2080 pbl = &cq->hwq.pbl[PBL_LVL_0];
2081 pg_sz_lvl = (bnxt_qplib_base_pg_size(&cq->hwq) <<
2082 CMDQ_CREATE_CQ_PG_SIZE_SFT);
2083 pg_sz_lvl |= (cq->hwq.level & CMDQ_CREATE_CQ_LVL_MASK);
2084 req.pg_size_lvl = cpu_to_le32(pg_sz_lvl);
2085 req.pbl = cpu_to_le64(pbl->pg_map_arr[0]);
2086 req.cq_fco_cnq_id = cpu_to_le32(
2087 (cq->cnq_hw_ring_id & CMDQ_CREATE_CQ_CNQ_ID_MASK) <<
2088 CMDQ_CREATE_CQ_CNQ_ID_SFT);
2089 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
2091 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
2095 cq->id = le32_to_cpu(resp.xid);
2096 cq->period = BNXT_QPLIB_QUEUE_START_PERIOD;
2097 init_waitqueue_head(&cq->waitq);
2098 INIT_LIST_HEAD(&cq->sqf_head);
2099 INIT_LIST_HEAD(&cq->rqf_head);
2100 spin_lock_init(&cq->compl_lock);
2101 spin_lock_init(&cq->flush_lock);
2103 cq->dbinfo.hwq = &cq->hwq;
2104 cq->dbinfo.xid = cq->id;
2105 cq->dbinfo.db = cq->dpi->dbr;
2106 cq->dbinfo.priv_db = res->dpi_tbl.dbr_bar_reg_iomem;
2108 bnxt_qplib_armen_db(&cq->dbinfo, DBC_DBC_TYPE_CQ_ARMENA);
2113 bnxt_qplib_free_hwq(res, &cq->hwq);
2118 void bnxt_qplib_resize_cq_complete(struct bnxt_qplib_res *res,
2119 struct bnxt_qplib_cq *cq)
2121 bnxt_qplib_free_hwq(res, &cq->hwq);
2122 memcpy(&cq->hwq, &cq->resize_hwq, sizeof(cq->hwq));
2125 int bnxt_qplib_resize_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq,
2128 struct bnxt_qplib_hwq_attr hwq_attr = {};
2129 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
2130 struct creq_resize_cq_resp resp = {};
2131 struct bnxt_qplib_cmdqmsg msg = {};
2132 struct cmdq_resize_cq req = {};
2133 struct bnxt_qplib_pbl *pbl;
2134 u32 pg_sz, lvl, new_sz;
2137 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
2138 CMDQ_BASE_OPCODE_RESIZE_CQ,
2140 hwq_attr.sginfo = &cq->sg_info;
2142 hwq_attr.depth = new_cqes;
2143 hwq_attr.stride = sizeof(struct cq_base);
2144 hwq_attr.type = HWQ_TYPE_QUEUE;
2145 rc = bnxt_qplib_alloc_init_hwq(&cq->resize_hwq, &hwq_attr);
2149 req.cq_cid = cpu_to_le32(cq->id);
2150 pbl = &cq->resize_hwq.pbl[PBL_LVL_0];
2151 pg_sz = bnxt_qplib_base_pg_size(&cq->resize_hwq);
2152 lvl = (cq->resize_hwq.level << CMDQ_RESIZE_CQ_LVL_SFT) &
2153 CMDQ_RESIZE_CQ_LVL_MASK;
2154 new_sz = (new_cqes << CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT) &
2155 CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK;
2156 req.new_cq_size_pg_size_lvl = cpu_to_le32(new_sz | pg_sz | lvl);
2157 req.new_pbl = cpu_to_le64(pbl->pg_map_arr[0]);
2159 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
2161 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
2165 int bnxt_qplib_destroy_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq)
2167 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
2168 struct creq_destroy_cq_resp resp = {};
2169 struct bnxt_qplib_cmdqmsg msg = {};
2170 struct cmdq_destroy_cq req = {};
2171 u16 total_cnq_events;
2174 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
2175 CMDQ_BASE_OPCODE_DESTROY_CQ,
2178 req.cq_cid = cpu_to_le32(cq->id);
2179 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
2181 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
2184 total_cnq_events = le16_to_cpu(resp.total_cnq_events);
2185 __wait_for_all_nqes(cq, total_cnq_events);
2186 bnxt_qplib_free_hwq(res, &cq->hwq);
2190 static int __flush_sq(struct bnxt_qplib_q *sq, struct bnxt_qplib_qp *qp,
2191 struct bnxt_qplib_cqe **pcqe, int *budget)
2193 struct bnxt_qplib_cqe *cqe;
2197 /* Now complete all outstanding SQEs with FLUSHED_ERR */
2198 start = sq->swq_start;
2201 last = sq->swq_last;
2204 /* Skip the FENCE WQE completions */
2205 if (sq->swq[last].wr_id == BNXT_QPLIB_FENCE_WRID) {
2206 bnxt_qplib_cancel_phantom_processing(qp);
2209 memset(cqe, 0, sizeof(*cqe));
2210 cqe->status = CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR;
2211 cqe->opcode = CQ_BASE_CQE_TYPE_REQ;
2212 cqe->qp_handle = (u64)(unsigned long)qp;
2213 cqe->wr_id = sq->swq[last].wr_id;
2214 cqe->src_qp = qp->id;
2215 cqe->type = sq->swq[last].type;
2219 bnxt_qplib_hwq_incr_cons(&sq->hwq, sq->swq[last].slots);
2220 sq->swq_last = sq->swq[last].next_idx;
2223 if (!(*budget) && sq->swq_last != start)
2230 static int __flush_rq(struct bnxt_qplib_q *rq, struct bnxt_qplib_qp *qp,
2231 struct bnxt_qplib_cqe **pcqe, int *budget)
2233 struct bnxt_qplib_cqe *cqe;
2239 case CMDQ_CREATE_QP1_TYPE_GSI:
2240 opcode = CQ_BASE_CQE_TYPE_RES_RAWETH_QP1;
2242 case CMDQ_CREATE_QP_TYPE_RC:
2243 opcode = CQ_BASE_CQE_TYPE_RES_RC;
2245 case CMDQ_CREATE_QP_TYPE_UD:
2246 case CMDQ_CREATE_QP_TYPE_GSI:
2247 opcode = CQ_BASE_CQE_TYPE_RES_UD;
2251 /* Flush the rest of the RQ */
2252 start = rq->swq_start;
2255 last = rq->swq_last;
2258 memset(cqe, 0, sizeof(*cqe));
2260 CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR;
2261 cqe->opcode = opcode;
2262 cqe->qp_handle = (unsigned long)qp;
2263 cqe->wr_id = rq->swq[last].wr_id;
2266 bnxt_qplib_hwq_incr_cons(&rq->hwq, rq->swq[last].slots);
2267 rq->swq_last = rq->swq[last].next_idx;
2270 if (!*budget && rq->swq_last != start)
2277 void bnxt_qplib_mark_qp_error(void *qp_handle)
2279 struct bnxt_qplib_qp *qp = qp_handle;
2284 /* Must block new posting of SQ and RQ */
2285 qp->state = CMDQ_MODIFY_QP_NEW_STATE_ERR;
2286 bnxt_qplib_cancel_phantom_processing(qp);
2289 /* Note: SQE is valid from sw_sq_cons up to cqe_sq_cons (exclusive)
2290 * CQE is track from sw_cq_cons to max_element but valid only if VALID=1
2292 static int do_wa9060(struct bnxt_qplib_qp *qp, struct bnxt_qplib_cq *cq,
2293 u32 cq_cons, u32 swq_last, u32 cqe_sq_cons)
2295 u32 peek_sw_cq_cons, peek_raw_cq_cons, peek_sq_cons_idx;
2296 struct bnxt_qplib_q *sq = &qp->sq;
2297 struct cq_req *peek_req_hwcqe;
2298 struct bnxt_qplib_qp *peek_qp;
2299 struct bnxt_qplib_q *peek_sq;
2300 struct bnxt_qplib_swq *swq;
2301 struct cq_base *peek_hwcqe;
2305 /* Check for the psn_search marking before completing */
2306 swq = &sq->swq[swq_last];
2307 if (swq->psn_search &&
2308 le32_to_cpu(swq->psn_search->flags_next_psn) & 0x80000000) {
2310 swq->psn_search->flags_next_psn = cpu_to_le32
2311 (le32_to_cpu(swq->psn_search->flags_next_psn)
2313 dev_dbg(&cq->hwq.pdev->dev,
2314 "FP: Process Req cq_cons=0x%x qp=0x%x sq cons sw=0x%x cqe=0x%x marked!\n",
2315 cq_cons, qp->id, swq_last, cqe_sq_cons);
2316 sq->condition = true;
2317 sq->send_phantom = true;
2319 /* TODO: Only ARM if the previous SQE is ARMALL */
2320 bnxt_qplib_ring_db(&cq->dbinfo, DBC_DBC_TYPE_CQ_ARMALL);
2324 if (sq->condition) {
2325 /* Peek at the completions */
2326 peek_raw_cq_cons = cq->hwq.cons;
2327 peek_sw_cq_cons = cq_cons;
2328 i = cq->hwq.max_elements;
2330 peek_sw_cq_cons = HWQ_CMP((peek_sw_cq_cons), &cq->hwq);
2331 peek_hwcqe = bnxt_qplib_get_qe(&cq->hwq,
2332 peek_sw_cq_cons, NULL);
2333 /* If the next hwcqe is VALID */
2334 if (CQE_CMP_VALID(peek_hwcqe, peek_raw_cq_cons,
2335 cq->hwq.max_elements)) {
2337 * The valid test of the entry must be done first before
2338 * reading any further.
2341 /* If the next hwcqe is a REQ */
2342 if ((peek_hwcqe->cqe_type_toggle &
2343 CQ_BASE_CQE_TYPE_MASK) ==
2344 CQ_BASE_CQE_TYPE_REQ) {
2345 peek_req_hwcqe = (struct cq_req *)
2347 peek_qp = (struct bnxt_qplib_qp *)
2350 (peek_req_hwcqe->qp_handle));
2351 peek_sq = &peek_qp->sq;
2354 peek_req_hwcqe->sq_cons_idx)
2355 - 1) % sq->max_wqe);
2356 /* If the hwcqe's sq's wr_id matches */
2357 if (peek_sq == sq &&
2358 sq->swq[peek_sq_cons_idx].wr_id ==
2359 BNXT_QPLIB_FENCE_WRID) {
2361 * Unbreak only if the phantom
2364 dev_dbg(&cq->hwq.pdev->dev,
2365 "FP: Got Phantom CQE\n");
2366 sq->condition = false;
2372 /* Valid but not the phantom, so keep looping */
2374 /* Not valid yet, just exit and wait */
2381 dev_err(&cq->hwq.pdev->dev,
2382 "Should not have come here! cq_cons=0x%x qp=0x%x sq cons sw=0x%x hw=0x%x\n",
2383 cq_cons, qp->id, swq_last, cqe_sq_cons);
2390 static int bnxt_qplib_cq_process_req(struct bnxt_qplib_cq *cq,
2391 struct cq_req *hwcqe,
2392 struct bnxt_qplib_cqe **pcqe, int *budget,
2393 u32 cq_cons, struct bnxt_qplib_qp **lib_qp)
2395 struct bnxt_qplib_swq *swq;
2396 struct bnxt_qplib_cqe *cqe;
2397 struct bnxt_qplib_qp *qp;
2398 struct bnxt_qplib_q *sq;
2402 qp = (struct bnxt_qplib_qp *)((unsigned long)
2403 le64_to_cpu(hwcqe->qp_handle));
2405 dev_err(&cq->hwq.pdev->dev,
2406 "FP: Process Req qp is NULL\n");
2411 cqe_sq_cons = le16_to_cpu(hwcqe->sq_cons_idx) % sq->max_wqe;
2412 if (qp->sq.flushed) {
2413 dev_dbg(&cq->hwq.pdev->dev,
2414 "%s: QP in Flush QP = %p\n", __func__, qp);
2417 /* Require to walk the sq's swq to fabricate CQEs for all previously
2418 * signaled SWQEs due to CQE aggregation from the current sq cons
2419 * to the cqe_sq_cons
2423 if (sq->swq_last == cqe_sq_cons)
2427 swq = &sq->swq[sq->swq_last];
2428 memset(cqe, 0, sizeof(*cqe));
2429 cqe->opcode = CQ_BASE_CQE_TYPE_REQ;
2430 cqe->qp_handle = (u64)(unsigned long)qp;
2431 cqe->src_qp = qp->id;
2432 cqe->wr_id = swq->wr_id;
2433 if (cqe->wr_id == BNXT_QPLIB_FENCE_WRID)
2435 cqe->type = swq->type;
2437 /* For the last CQE, check for status. For errors, regardless
2438 * of the request being signaled or not, it must complete with
2439 * the hwcqe error status
2441 if (swq->next_idx == cqe_sq_cons &&
2442 hwcqe->status != CQ_REQ_STATUS_OK) {
2443 cqe->status = hwcqe->status;
2444 dev_err(&cq->hwq.pdev->dev,
2445 "FP: CQ Processed Req wr_id[%d] = 0x%llx with status 0x%x\n",
2446 sq->swq_last, cqe->wr_id, cqe->status);
2449 bnxt_qplib_mark_qp_error(qp);
2450 /* Add qp to flush list of the CQ */
2451 bnxt_qplib_add_flush_qp(qp);
2453 /* Before we complete, do WA 9060 */
2454 if (do_wa9060(qp, cq, cq_cons, sq->swq_last,
2459 if (swq->flags & SQ_SEND_FLAGS_SIGNAL_COMP) {
2460 cqe->status = CQ_REQ_STATUS_OK;
2466 bnxt_qplib_hwq_incr_cons(&sq->hwq, swq->slots);
2467 sq->swq_last = swq->next_idx;
2473 if (sq->swq_last != cqe_sq_cons) {
2479 * Back to normal completion mode only after it has completed all of
2480 * the WC for this CQE
2487 static void bnxt_qplib_release_srqe(struct bnxt_qplib_srq *srq, u32 tag)
2489 spin_lock(&srq->hwq.lock);
2490 srq->swq[srq->last_idx].next_idx = (int)tag;
2491 srq->last_idx = (int)tag;
2492 srq->swq[srq->last_idx].next_idx = -1;
2493 srq->hwq.cons++; /* Support for SRQE counter */
2494 spin_unlock(&srq->hwq.lock);
2497 static int bnxt_qplib_cq_process_res_rc(struct bnxt_qplib_cq *cq,
2498 struct cq_res_rc *hwcqe,
2499 struct bnxt_qplib_cqe **pcqe,
2502 struct bnxt_qplib_srq *srq;
2503 struct bnxt_qplib_cqe *cqe;
2504 struct bnxt_qplib_qp *qp;
2505 struct bnxt_qplib_q *rq;
2509 qp = (struct bnxt_qplib_qp *)((unsigned long)
2510 le64_to_cpu(hwcqe->qp_handle));
2512 dev_err(&cq->hwq.pdev->dev, "process_cq RC qp is NULL\n");
2515 if (qp->rq.flushed) {
2516 dev_dbg(&cq->hwq.pdev->dev,
2517 "%s: QP in Flush QP = %p\n", __func__, qp);
2522 cqe->opcode = hwcqe->cqe_type_toggle & CQ_BASE_CQE_TYPE_MASK;
2523 cqe->length = le32_to_cpu(hwcqe->length);
2524 cqe->invrkey = le32_to_cpu(hwcqe->imm_data_or_inv_r_key);
2525 cqe->mr_handle = le64_to_cpu(hwcqe->mr_handle);
2526 cqe->flags = le16_to_cpu(hwcqe->flags);
2527 cqe->status = hwcqe->status;
2528 cqe->qp_handle = (u64)(unsigned long)qp;
2530 wr_id_idx = le32_to_cpu(hwcqe->srq_or_rq_wr_id) &
2531 CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK;
2532 if (cqe->flags & CQ_RES_RC_FLAGS_SRQ_SRQ) {
2536 if (wr_id_idx >= srq->hwq.max_elements) {
2537 dev_err(&cq->hwq.pdev->dev,
2538 "FP: CQ Process RC wr_id idx 0x%x exceeded SRQ max 0x%x\n",
2539 wr_id_idx, srq->hwq.max_elements);
2542 cqe->wr_id = srq->swq[wr_id_idx].wr_id;
2543 bnxt_qplib_release_srqe(srq, wr_id_idx);
2548 struct bnxt_qplib_swq *swq;
2551 if (wr_id_idx > (rq->max_wqe - 1)) {
2552 dev_err(&cq->hwq.pdev->dev,
2553 "FP: CQ Process RC wr_id idx 0x%x exceeded RQ max 0x%x\n",
2554 wr_id_idx, rq->max_wqe);
2557 if (wr_id_idx != rq->swq_last)
2559 swq = &rq->swq[rq->swq_last];
2560 cqe->wr_id = swq->wr_id;
2563 bnxt_qplib_hwq_incr_cons(&rq->hwq, swq->slots);
2564 rq->swq_last = swq->next_idx;
2567 if (hwcqe->status != CQ_RES_RC_STATUS_OK) {
2568 qp->state = CMDQ_MODIFY_QP_NEW_STATE_ERR;
2569 /* Add qp to flush list of the CQ */
2570 bnxt_qplib_add_flush_qp(qp);
2578 static int bnxt_qplib_cq_process_res_ud(struct bnxt_qplib_cq *cq,
2579 struct cq_res_ud *hwcqe,
2580 struct bnxt_qplib_cqe **pcqe,
2583 struct bnxt_qplib_srq *srq;
2584 struct bnxt_qplib_cqe *cqe;
2585 struct bnxt_qplib_qp *qp;
2586 struct bnxt_qplib_q *rq;
2590 qp = (struct bnxt_qplib_qp *)((unsigned long)
2591 le64_to_cpu(hwcqe->qp_handle));
2593 dev_err(&cq->hwq.pdev->dev, "process_cq UD qp is NULL\n");
2596 if (qp->rq.flushed) {
2597 dev_dbg(&cq->hwq.pdev->dev,
2598 "%s: QP in Flush QP = %p\n", __func__, qp);
2602 cqe->opcode = hwcqe->cqe_type_toggle & CQ_BASE_CQE_TYPE_MASK;
2603 cqe->length = le16_to_cpu(hwcqe->length) & CQ_RES_UD_LENGTH_MASK;
2604 cqe->cfa_meta = le16_to_cpu(hwcqe->cfa_metadata);
2605 cqe->invrkey = le32_to_cpu(hwcqe->imm_data);
2606 cqe->flags = le16_to_cpu(hwcqe->flags);
2607 cqe->status = hwcqe->status;
2608 cqe->qp_handle = (u64)(unsigned long)qp;
2609 /*FIXME: Endianness fix needed for smace */
2610 memcpy(cqe->smac, hwcqe->src_mac, ETH_ALEN);
2611 wr_id_idx = le32_to_cpu(hwcqe->src_qp_high_srq_or_rq_wr_id)
2612 & CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK;
2613 cqe->src_qp = le16_to_cpu(hwcqe->src_qp_low) |
2615 hwcqe->src_qp_high_srq_or_rq_wr_id) &
2616 CQ_RES_UD_SRC_QP_HIGH_MASK) >> 8);
2618 if (cqe->flags & CQ_RES_RC_FLAGS_SRQ_SRQ) {
2623 if (wr_id_idx >= srq->hwq.max_elements) {
2624 dev_err(&cq->hwq.pdev->dev,
2625 "FP: CQ Process UD wr_id idx 0x%x exceeded SRQ max 0x%x\n",
2626 wr_id_idx, srq->hwq.max_elements);
2629 cqe->wr_id = srq->swq[wr_id_idx].wr_id;
2630 bnxt_qplib_release_srqe(srq, wr_id_idx);
2635 struct bnxt_qplib_swq *swq;
2638 if (wr_id_idx > (rq->max_wqe - 1)) {
2639 dev_err(&cq->hwq.pdev->dev,
2640 "FP: CQ Process UD wr_id idx 0x%x exceeded RQ max 0x%x\n",
2641 wr_id_idx, rq->max_wqe);
2645 if (rq->swq_last != wr_id_idx)
2647 swq = &rq->swq[rq->swq_last];
2648 cqe->wr_id = swq->wr_id;
2651 bnxt_qplib_hwq_incr_cons(&rq->hwq, swq->slots);
2652 rq->swq_last = swq->next_idx;
2655 if (hwcqe->status != CQ_RES_RC_STATUS_OK) {
2656 qp->state = CMDQ_MODIFY_QP_NEW_STATE_ERR;
2657 /* Add qp to flush list of the CQ */
2658 bnxt_qplib_add_flush_qp(qp);
2665 bool bnxt_qplib_is_cq_empty(struct bnxt_qplib_cq *cq)
2667 struct cq_base *hw_cqe;
2668 u32 sw_cons, raw_cons;
2671 raw_cons = cq->hwq.cons;
2672 sw_cons = HWQ_CMP(raw_cons, &cq->hwq);
2673 hw_cqe = bnxt_qplib_get_qe(&cq->hwq, sw_cons, NULL);
2674 /* Check for Valid bit. If the CQE is valid, return false */
2675 rc = !CQE_CMP_VALID(hw_cqe, raw_cons, cq->hwq.max_elements);
2679 static int bnxt_qplib_cq_process_res_raweth_qp1(struct bnxt_qplib_cq *cq,
2680 struct cq_res_raweth_qp1 *hwcqe,
2681 struct bnxt_qplib_cqe **pcqe,
2684 struct bnxt_qplib_qp *qp;
2685 struct bnxt_qplib_q *rq;
2686 struct bnxt_qplib_srq *srq;
2687 struct bnxt_qplib_cqe *cqe;
2691 qp = (struct bnxt_qplib_qp *)((unsigned long)
2692 le64_to_cpu(hwcqe->qp_handle));
2694 dev_err(&cq->hwq.pdev->dev, "process_cq Raw/QP1 qp is NULL\n");
2697 if (qp->rq.flushed) {
2698 dev_dbg(&cq->hwq.pdev->dev,
2699 "%s: QP in Flush QP = %p\n", __func__, qp);
2703 cqe->opcode = hwcqe->cqe_type_toggle & CQ_BASE_CQE_TYPE_MASK;
2704 cqe->flags = le16_to_cpu(hwcqe->flags);
2705 cqe->qp_handle = (u64)(unsigned long)qp;
2708 le32_to_cpu(hwcqe->raweth_qp1_payload_offset_srq_or_rq_wr_id)
2709 & CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK;
2710 cqe->src_qp = qp->id;
2711 if (qp->id == 1 && !cqe->length) {
2712 /* Add workaround for the length misdetection */
2715 cqe->length = le16_to_cpu(hwcqe->length);
2717 cqe->pkey_index = qp->pkey_index;
2718 memcpy(cqe->smac, qp->smac, 6);
2720 cqe->raweth_qp1_flags = le16_to_cpu(hwcqe->raweth_qp1_flags);
2721 cqe->raweth_qp1_flags2 = le32_to_cpu(hwcqe->raweth_qp1_flags2);
2722 cqe->raweth_qp1_metadata = le32_to_cpu(hwcqe->raweth_qp1_metadata);
2724 if (cqe->flags & CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ) {
2727 dev_err(&cq->hwq.pdev->dev,
2728 "FP: SRQ used but not defined??\n");
2731 if (wr_id_idx >= srq->hwq.max_elements) {
2732 dev_err(&cq->hwq.pdev->dev,
2733 "FP: CQ Process Raw/QP1 wr_id idx 0x%x exceeded SRQ max 0x%x\n",
2734 wr_id_idx, srq->hwq.max_elements);
2737 cqe->wr_id = srq->swq[wr_id_idx].wr_id;
2738 bnxt_qplib_release_srqe(srq, wr_id_idx);
2743 struct bnxt_qplib_swq *swq;
2746 if (wr_id_idx > (rq->max_wqe - 1)) {
2747 dev_err(&cq->hwq.pdev->dev,
2748 "FP: CQ Process Raw/QP1 RQ wr_id idx 0x%x exceeded RQ max 0x%x\n",
2749 wr_id_idx, rq->max_wqe);
2752 if (rq->swq_last != wr_id_idx)
2754 swq = &rq->swq[rq->swq_last];
2755 cqe->wr_id = swq->wr_id;
2758 bnxt_qplib_hwq_incr_cons(&rq->hwq, swq->slots);
2759 rq->swq_last = swq->next_idx;
2762 if (hwcqe->status != CQ_RES_RC_STATUS_OK) {
2763 qp->state = CMDQ_MODIFY_QP_NEW_STATE_ERR;
2764 /* Add qp to flush list of the CQ */
2765 bnxt_qplib_add_flush_qp(qp);
2773 static int bnxt_qplib_cq_process_terminal(struct bnxt_qplib_cq *cq,
2774 struct cq_terminal *hwcqe,
2775 struct bnxt_qplib_cqe **pcqe,
2778 struct bnxt_qplib_qp *qp;
2779 struct bnxt_qplib_q *sq, *rq;
2780 struct bnxt_qplib_cqe *cqe;
2781 u32 swq_last = 0, cqe_cons;
2784 /* Check the Status */
2785 if (hwcqe->status != CQ_TERMINAL_STATUS_OK)
2786 dev_warn(&cq->hwq.pdev->dev,
2787 "FP: CQ Process Terminal Error status = 0x%x\n",
2790 qp = (struct bnxt_qplib_qp *)((unsigned long)
2791 le64_to_cpu(hwcqe->qp_handle));
2793 dev_err(&cq->hwq.pdev->dev,
2794 "FP: CQ Process terminal qp is NULL\n");
2798 /* Must block new posting of SQ and RQ */
2799 qp->state = CMDQ_MODIFY_QP_NEW_STATE_ERR;
2804 cqe_cons = le16_to_cpu(hwcqe->sq_cons_idx);
2805 if (cqe_cons == 0xFFFF)
2807 cqe_cons %= sq->max_wqe;
2809 if (qp->sq.flushed) {
2810 dev_dbg(&cq->hwq.pdev->dev,
2811 "%s: QP in Flush QP = %p\n", __func__, qp);
2815 /* Terminal CQE can also include aggregated successful CQEs prior.
2816 * So we must complete all CQEs from the current sq's cons to the
2817 * cq_cons with status OK
2821 swq_last = sq->swq_last;
2822 if (swq_last == cqe_cons)
2824 if (sq->swq[swq_last].flags & SQ_SEND_FLAGS_SIGNAL_COMP) {
2825 memset(cqe, 0, sizeof(*cqe));
2826 cqe->status = CQ_REQ_STATUS_OK;
2827 cqe->opcode = CQ_BASE_CQE_TYPE_REQ;
2828 cqe->qp_handle = (u64)(unsigned long)qp;
2829 cqe->src_qp = qp->id;
2830 cqe->wr_id = sq->swq[swq_last].wr_id;
2831 cqe->type = sq->swq[swq_last].type;
2835 bnxt_qplib_hwq_incr_cons(&sq->hwq, sq->swq[swq_last].slots);
2836 sq->swq_last = sq->swq[swq_last].next_idx;
2839 if (!(*budget) && swq_last != cqe_cons) {
2848 cqe_cons = le16_to_cpu(hwcqe->rq_cons_idx);
2849 if (cqe_cons == 0xFFFF) {
2851 } else if (cqe_cons > rq->max_wqe - 1) {
2852 dev_err(&cq->hwq.pdev->dev,
2853 "FP: CQ Processed terminal reported rq_cons_idx 0x%x exceeds max 0x%x\n",
2854 cqe_cons, rq->max_wqe);
2859 if (qp->rq.flushed) {
2860 dev_dbg(&cq->hwq.pdev->dev,
2861 "%s: QP in Flush QP = %p\n", __func__, qp);
2866 /* Terminal CQE requires all posted RQEs to complete with FLUSHED_ERR
2867 * from the current rq->cons to the rq->prod regardless what the
2868 * rq->cons the terminal CQE indicates
2871 /* Add qp to flush list of the CQ */
2872 bnxt_qplib_add_flush_qp(qp);
2877 static int bnxt_qplib_cq_process_cutoff(struct bnxt_qplib_cq *cq,
2878 struct cq_cutoff *hwcqe)
2880 /* Check the Status */
2881 if (hwcqe->status != CQ_CUTOFF_STATUS_OK) {
2882 dev_err(&cq->hwq.pdev->dev,
2883 "FP: CQ Process Cutoff Error status = 0x%x\n",
2887 clear_bit(CQ_FLAGS_RESIZE_IN_PROG, &cq->flags);
2888 wake_up_interruptible(&cq->waitq);
2893 int bnxt_qplib_process_flush_list(struct bnxt_qplib_cq *cq,
2894 struct bnxt_qplib_cqe *cqe,
2897 struct bnxt_qplib_qp *qp = NULL;
2898 u32 budget = num_cqes;
2899 unsigned long flags;
2901 spin_lock_irqsave(&cq->flush_lock, flags);
2902 list_for_each_entry(qp, &cq->sqf_head, sq_flush) {
2903 dev_dbg(&cq->hwq.pdev->dev, "FP: Flushing SQ QP= %p\n", qp);
2904 __flush_sq(&qp->sq, qp, &cqe, &budget);
2907 list_for_each_entry(qp, &cq->rqf_head, rq_flush) {
2908 dev_dbg(&cq->hwq.pdev->dev, "FP: Flushing RQ QP= %p\n", qp);
2909 __flush_rq(&qp->rq, qp, &cqe, &budget);
2911 spin_unlock_irqrestore(&cq->flush_lock, flags);
2913 return num_cqes - budget;
2916 int bnxt_qplib_poll_cq(struct bnxt_qplib_cq *cq, struct bnxt_qplib_cqe *cqe,
2917 int num_cqes, struct bnxt_qplib_qp **lib_qp)
2919 struct cq_base *hw_cqe;
2920 u32 sw_cons, raw_cons;
2924 raw_cons = cq->hwq.cons;
2928 sw_cons = HWQ_CMP(raw_cons, &cq->hwq);
2929 hw_cqe = bnxt_qplib_get_qe(&cq->hwq, sw_cons, NULL);
2931 /* Check for Valid bit */
2932 if (!CQE_CMP_VALID(hw_cqe, raw_cons, cq->hwq.max_elements))
2936 * The valid test of the entry must be done first before
2937 * reading any further.
2940 /* From the device's respective CQE format to qplib_wc*/
2941 type = hw_cqe->cqe_type_toggle & CQ_BASE_CQE_TYPE_MASK;
2943 case CQ_BASE_CQE_TYPE_REQ:
2944 rc = bnxt_qplib_cq_process_req(cq,
2945 (struct cq_req *)hw_cqe,
2949 case CQ_BASE_CQE_TYPE_RES_RC:
2950 rc = bnxt_qplib_cq_process_res_rc(cq,
2951 (struct cq_res_rc *)
2955 case CQ_BASE_CQE_TYPE_RES_UD:
2956 rc = bnxt_qplib_cq_process_res_ud
2957 (cq, (struct cq_res_ud *)hw_cqe, &cqe,
2960 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
2961 rc = bnxt_qplib_cq_process_res_raweth_qp1
2962 (cq, (struct cq_res_raweth_qp1 *)
2963 hw_cqe, &cqe, &budget);
2965 case CQ_BASE_CQE_TYPE_TERMINAL:
2966 rc = bnxt_qplib_cq_process_terminal
2967 (cq, (struct cq_terminal *)hw_cqe,
2970 case CQ_BASE_CQE_TYPE_CUT_OFF:
2971 bnxt_qplib_cq_process_cutoff
2972 (cq, (struct cq_cutoff *)hw_cqe);
2973 /* Done processing this CQ */
2976 dev_err(&cq->hwq.pdev->dev,
2977 "process_cq unknown type 0x%lx\n",
2978 hw_cqe->cqe_type_toggle &
2979 CQ_BASE_CQE_TYPE_MASK);
2986 /* Error while processing the CQE, just skip to the
2989 if (type != CQ_BASE_CQE_TYPE_TERMINAL)
2990 dev_err(&cq->hwq.pdev->dev,
2991 "process_cqe error rc = 0x%x\n", rc);
2995 if (cq->hwq.cons != raw_cons) {
2996 cq->hwq.cons = raw_cons;
2997 bnxt_qplib_ring_db(&cq->dbinfo, DBC_DBC_TYPE_CQ);
3000 return num_cqes - budget;
3003 void bnxt_qplib_req_notify_cq(struct bnxt_qplib_cq *cq, u32 arm_type)
3006 bnxt_qplib_ring_db(&cq->dbinfo, arm_type);
3007 /* Using cq->arm_state variable to track whether to issue cq handler */
3008 atomic_set(&cq->arm_state, 1);
3011 void bnxt_qplib_flush_cqn_wq(struct bnxt_qplib_qp *qp)
3013 flush_workqueue(qp->scq->nq->cqn_wq);
3014 if (qp->scq != qp->rcq)
3015 flush_workqueue(qp->rcq->nq->cqn_wq);