2 * INCA-IP internal switch ethernet driver.
4 * (C) Copyright 2003-2004
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
30 && defined(CONFIG_INCA_IP_SWITCH)
34 #include <asm/inca-ip.h>
35 #include <asm/addrspace.h>
38 #define NUM_RX_DESC PKTBUFSRX
40 #define TOUT_LOOP 1000000
43 #define DELAY udelay(10000)
45 #define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value;
46 #define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
47 #define SW_WRITE_REG(reg, value) \
48 *((volatile u32*)reg) = (u32)value;\
50 *((volatile u32*)reg) = (u32)value;
52 #define SW_READ_REG(reg, value) \
53 value = (u32)*((volatile u32*)reg);\
55 value = (u32)*((volatile u32*)reg);
57 #define INCA_DMA_TX_POLLING_TIME 0x07
58 #define INCA_DMA_RX_POLLING_TIME 0x07
60 #define INCA_DMA_TX_HOLD 0x80000000
61 #define INCA_DMA_TX_EOP 0x40000000
62 #define INCA_DMA_TX_SOP 0x20000000
63 #define INCA_DMA_TX_ICPT 0x10000000
64 #define INCA_DMA_TX_IEOP 0x08000000
66 #define INCA_DMA_RX_C 0x80000000
67 #define INCA_DMA_RX_SOP 0x40000000
68 #define INCA_DMA_RX_EOP 0x20000000
70 #define INCA_SWITCH_PHY_SPEED_10H 0x1
71 #define INCA_SWITCH_PHY_SPEED_10F 0x5
72 #define INCA_SWITCH_PHY_SPEED_100H 0x2
73 #define INCA_SWITCH_PHY_SPEED_100F 0x6
75 /************************ Auto MDIX settings ************************/
76 #define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR
77 #define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL
78 #define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT
79 #define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16
81 #define WAIT_SIGNAL_RETRIES 100
82 #define WAIT_LINK_RETRIES 100
83 #define LINK_RETRY_DELAY 2000 /* ms */
84 /********************************************************************/
93 volatile u32 offset :3;
94 volatile u32 reserved0 :4;
101 volatile u32 nextRxDescPtr;
103 volatile u32 RxDataPtr;
110 volatile u32 reserved3 :12;
111 volatile u32 NBT :17;
117 } inca_rx_descriptor_t;
124 volatile u32 HOLD :1;
127 volatile u32 ICpt :1;
128 volatile u32 IEop :1;
129 volatile u32 reserved0 :5;
130 volatile u32 NBA :22;
136 volatile u32 nextTxDescPtr;
138 volatile u32 TxDataPtr;
141 volatile u32 reserved3 :31;
143 } inca_tx_descriptor_t;
146 static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16)));
147 static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16)));
149 static int tx_new, rx_new, tx_hold, rx_hold;
150 static int tx_old_hold = -1;
151 static int initialized = 0;
154 static int inca_switch_init(struct eth_device *dev, bd_t * bis);
155 static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length);
156 static int inca_switch_recv(struct eth_device *dev);
157 static void inca_switch_halt(struct eth_device *dev);
158 static void inca_init_switch_chip(void);
159 static void inca_dma_init(void);
160 static int inca_amdix(void);
163 int inca_switch_initialize(bd_t * bis)
165 struct eth_device *dev;
168 printf("Entered inca_switch_initialize()\n");
171 if (!(dev = (struct eth_device *) malloc (sizeof *dev))) {
172 printf("Failed to allocate memory\n");
175 memset(dev, 0, sizeof(*dev));
179 inca_init_switch_chip();
181 #if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
185 sprintf(dev->name, "INCA-IP Switch");
186 dev->init = inca_switch_init;
187 dev->halt = inca_switch_halt;
188 dev->send = inca_switch_send;
189 dev->recv = inca_switch_recv;
194 printf("Leaving inca_switch_initialize()\n");
201 static int inca_switch_init(struct eth_device *dev, bd_t * bis)
208 printf("Entering inca_switch_init()\n");
213 wTmp = (u16)dev->enetaddr[0];
214 regValue = (wTmp << 8) | dev->enetaddr[1];
216 SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue);
218 wTmp = (u16)dev->enetaddr[2];
219 regValue = (wTmp << 8) | dev->enetaddr[3];
220 regValue = regValue << 16;
221 wTmp = (u16)dev->enetaddr[4];
222 regValue |= (wTmp<<8) | dev->enetaddr[5];
224 SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue);
226 /* Initialize the descriptor rings.
228 for (i = 0; i < NUM_RX_DESC; i++) {
229 inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]);
230 memset(rx_desc, 0, sizeof(rx_ring[i]));
232 /* Set maximum size of receive buffer.
234 rx_desc->params.field.NFB = PKTSIZE_ALIGN;
236 /* Set the offset of the receive buffer. Zero means
237 * that the offset mechanism is not used.
239 rx_desc->params.field.offset = 0;
241 /* Check if it is the last descriptor.
243 if (i == (NUM_RX_DESC - 1)) {
244 /* Let the last descriptor point to the first
247 rx_desc->nextRxDescPtr = KSEG1ADDR((u32)rx_ring);
249 /* Set the address of the next descriptor.
251 rx_desc->nextRxDescPtr = (u32)KSEG1ADDR(&rx_ring[i+1]);
254 rx_desc->RxDataPtr = (u32)KSEG1ADDR(NetRxPackets[i]);
258 printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]);
259 printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]);
262 for (i = 0; i < NUM_TX_DESC; i++) {
263 inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[i]);
265 memset(tx_desc, 0, sizeof(tx_ring[i]));
267 tx_desc->params.word = 0;
268 tx_desc->params.field.HOLD = 1;
271 /* Check if it is the last descriptor.
273 if (i == (NUM_TX_DESC - 1)) {
274 /* Let the last descriptor point to the
277 tx_desc->nextTxDescPtr = KSEG1ADDR((u32)tx_ring);
279 /* Set the address of the next descriptor.
281 tx_desc->nextTxDescPtr = (u32)KSEG1ADDR(&tx_ring[i+1]);
287 DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v);
289 printf("RX status = 0x%08X\n", v);
292 /* Writing to the FRDA of CHANNEL.
294 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring);
296 /* Writing to the COMMAND REG.
298 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT);
302 DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v);
304 printf("TX status = 0x%08X\n", v);
307 /* Writing to the FRDA of CHANNEL.
309 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring);
313 tx_hold = NUM_TX_DESC - 1;
314 rx_hold = NUM_RX_DESC - 1;
317 rx_ring[rx_hold].params.field.HOLD = 1;
319 /* enable spanning tree forwarding, enable the CPU port */
321 * CPS (CPU port status) 0x3 (forwarding)
322 * LPS (LAN port status) 0x3 (forwarding)
323 * PPS (PC port status) 0x3 (forwarding)
325 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f);
328 printf("Leaving inca_switch_init()\n");
335 static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length)
341 inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[tx_new]);
344 printf("Entered inca_switch_send()\n");
348 printf ("%s: bad packet size: %d\n", dev->name, length);
352 for(i = 0; tx_desc->C == 0; i++) {
353 if (i >= TOUT_LOOP) {
354 printf("%s: tx error buffer not ready\n", dev->name);
359 if (tx_old_hold >= 0) {
360 KSEG1ADDR(&tx_ring[tx_old_hold])->params.field.HOLD = 1;
362 tx_old_hold = tx_hold;
364 tx_desc->params.word =
365 (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD);
368 tx_desc->TxDataPtr = (u32)packet;
369 tx_desc->params.field.NBA = length;
371 KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0;
374 tx_new = (tx_new + 1) % NUM_TX_DESC;
378 command = INCA_IP_DMA_DMA_TXCCR0_INIT;
381 command = INCA_IP_DMA_DMA_TXCCR0_HR;
384 DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
387 printf("regValue = 0x%x\n", regValue);
389 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
392 for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++) {
393 if (i >= TOUT_LOOP) {
394 printf("%s: tx buffer not ready\n", dev->name);
402 printf("Leaving inca_switch_send()\n");
408 static int inca_switch_recv(struct eth_device *dev)
411 inca_rx_descriptor_t * rx_desc;
414 printf("Entered inca_switch_recv()\n");
418 rx_desc = KSEG1ADDR(&rx_ring[rx_new]);
420 if (rx_desc->status.field.C == 0) {
425 rx_ring[rx_new].params.field.HOLD = 1;
428 if (! rx_desc->status.field.Eop) {
429 printf("Partly received packet!!!\n");
433 length = rx_desc->status.field.NBT;
434 rx_desc->status.word &=
435 ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C);
439 for (i=0;i<length - 4;i++) {
440 if (i % 16 == 0) printf("\n%04x: ", i);
441 printf("%02X ", NetRxPackets[rx_new][i]);
449 printf("Received %d bytes\n", length);
451 NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]), length - 4);
454 printf("Zero length!!!\n");
459 KSEG1ADDR(&rx_ring[rx_hold])->params.field.HOLD = 0;
463 rx_new = (rx_new + 1) % NUM_RX_DESC;
467 printf("Leaving inca_switch_recv()\n");
474 static void inca_switch_halt(struct eth_device *dev)
477 printf("Entered inca_switch_halt()\n");
484 /* Disable forwarding to the CPU port.
486 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
488 /* Close RxDMA channel.
490 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
492 /* Close TxDMA channel.
494 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF);
499 printf("Leaving inca_switch_halt()\n");
504 static void inca_init_switch_chip(void)
508 /* To workaround a problem with collision counter
509 * (see Errata sheet).
511 SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001);
512 SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001);
515 /* init MDIO configuration:
516 * MDS (Poll speed): 0x01 (4ms)
519 * UEP (Use External PHY): 0x00 (Internal PHY is used)
520 * PS (Port Select): 0x00 (PT/UMM for LAN)
521 * PT (PHY Test): 0x00 (no test mode)
522 * UMM (Use MDIO Mode): 0x00 (state machine is disabled)
524 SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
527 * SL (Auto Neg. Speed for LAN)
528 * SP (Auto Neg. Speed for PC)
529 * LL (Link Status for LAN)
530 * LP (Link Status for PC)
531 * DL (Duplex Status for LAN)
532 * DP (Duplex Status for PC)
533 * PL (Auto Neg. Pause Status for LAN)
534 * PP (Auto Neg. Pause Status for PC)
536 SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff);
539 * RA (Request/Ack) 0x01 (Request)
540 * RW (Read/Write) 0x01 (Write)
542 * REG_ADDR 0x00 (PHY_BCR: basic control register)
544 * Reset - software reset
545 * LB (loop back) - normal
546 * SS (speed select) - 10 Mbit/s
547 * ANE (auto neg. enable) - enable
548 * PD (power down) - normal
549 * ISO (isolate) - normal
550 * RAN (restart auto neg.) - normal
551 * DM (duplex mode) - half duplex
552 * CT (collision test) - enable
554 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
557 * RA (Request/Ack) 0x01 (Request)
558 * RW (Read/Write) 0x01 (Write)
559 * PHY_ADDR 0x06 (LAN)
560 * REG_ADDR 0x00 (PHY_BCR: basic control register)
562 * Reset - software reset
563 * LB (loop back) - normal
564 * SS (speed select) - 10 Mbit/s
565 * ANE (auto neg. enable) - enable
566 * PD (power down) - normal
567 * ISO (isolate) - normal
568 * RAN (restart auto neg.) - normal
569 * DM (duplex mode) - half duplex
570 * CT (collision test) - enable
572 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
576 /* Make sure the CPU port is disabled for now. We
577 * don't want packets to get stacked for us until
578 * we enable DMA and are prepared to receive them.
580 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
582 SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue);
584 /* CRC GEN is enabled.
586 regValue |= 0x00000200;
587 SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue);
589 /* ADD TAG is disabled.
591 SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
592 regValue &= ~0x00000002;
593 SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
597 static void inca_dma_init(void)
599 /* Switch off all DMA channels.
601 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
602 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF);
604 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
605 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF);
606 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF);
608 /* Setup TX channel polling time.
610 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME);
612 /* Setup RX channel polling time.
614 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME);
616 /* ERRATA: write reset value into the DMA RX IMR register.
618 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF);
620 /* Just in case: disable all transmit interrupts also.
622 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF);
624 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF);
625 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF);
628 #if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
629 static int inca_amdix(void)
642 *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
643 *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
648 retries = WAIT_SIGNAL_RETRIES;
650 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
651 (0x1 << 31) | /* RA */
652 (0x0 << 30) | /* Read */
653 (0x6 << 21) | /* LAN */
654 (17 << 16)); /* PHY_MCSR */
656 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
657 } while (phyReg1 & (1 << 31));
659 if (phyReg1 & (1 << 1)) {
660 /* Signal detected */
671 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
676 retries = WAIT_LINK_RETRIES;
678 udelay(LINK_RETRY_DELAY * 1000);
679 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
680 (0x1 << 31) | /* RA */
681 (0x0 << 30) | /* Read */
682 (0x6 << 21) | /* LAN */
683 (1 << 16)); /* PHY_BSR */
685 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
686 } while (phyReg1 & (1 << 31));
688 if (phyReg1 & (1 << 2)) {
691 } else if (mdi_flag) {
693 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
697 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
705 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
706 (0x1 << 31) | /* RA */
707 (0x0 << 30) | /* Read */
708 (0x6 << 21) | /* LAN */
709 (1 << 16)); /* PHY_BSR */
711 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
712 } while (phyReg1 & (1 << 31));
714 /* Auto-negotiation / Parallel detection complete
716 if (phyReg1 & (1 << 5)) {
717 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
718 (0x1 << 31) | /* RA */
719 (0x0 << 30) | /* Read */
720 (0x6 << 21) | /* LAN */
721 (31 << 16)); /* PHY_SCSR */
723 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31);
724 } while (phyReg31 & (1 << 31));
726 switch ((phyReg31 >> 2) & 0x7) {
727 case INCA_SWITCH_PHY_SPEED_10H:
728 /* 10Base-T Half-duplex */
731 case INCA_SWITCH_PHY_SPEED_10F:
732 /* 10Base-T Full-duplex */
733 regEphy = INCA_IP_Switch_EPHY_DL;
735 case INCA_SWITCH_PHY_SPEED_100H:
736 /* 100Base-TX Half-duplex */
737 regEphy = INCA_IP_Switch_EPHY_SL;
739 case INCA_SWITCH_PHY_SPEED_100F:
740 /* 100Base-TX Full-duplex */
741 regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL;
745 /* In case of Auto-negotiation,
746 * update the negotiated PAUSE support status
748 if (phyReg1 & (1 << 3)) {
749 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
750 (0x1 << 31) | /* RA */
751 (0x0 << 30) | /* Read */
752 (0x6 << 21) | /* LAN */
753 (6 << 16)); /* PHY_ANER */
755 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
756 } while (phyReg6 & (1 << 31));
758 /* We are Autoneg-able.
759 * Is Link partner also able to autoneg?
761 if (phyReg6 & (1 << 0)) {
762 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
763 (0x1 << 31) | /* RA */
764 (0x0 << 30) | /* Read */
765 (0x6 << 21) | /* LAN */
766 (4 << 16)); /* PHY_ANAR */
768 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
769 } while (phyReg4 & (1 << 31));
771 /* We advertise PAUSE capab.
772 * Does link partner also advertise it?
774 if (phyReg4 & (1 << 10)) {
775 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
776 (0x1 << 31) | /* RA */
777 (0x0 << 30) | /* Read */
778 (0x6 << 21) | /* LAN */
779 (5 << 16)); /* PHY_ANLPAR */
781 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
782 } while (phyReg5 & (1 << 31));
784 /* Link partner is PAUSE capab.
786 if (phyReg5 & (1 << 10)) {
787 regEphy |= INCA_IP_Switch_EPHY_PL;
795 regEphy |= INCA_IP_Switch_EPHY_LL;
797 SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy);
804 printf("No Link on LAN port\n");
807 #endif /* CONFIG_INCA_IP_SWITCH_AMDIX */