2 * Copyright (C) 2012 Invensense, Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 #include <linux/i2c.h>
14 #include <linux/i2c-mux.h>
15 #include <linux/mutex.h>
16 #include <linux/iio/iio.h>
17 #include <linux/iio/buffer.h>
18 #include <linux/regmap.h>
19 #include <linux/iio/sysfs.h>
20 #include <linux/iio/kfifo_buf.h>
21 #include <linux/iio/trigger.h>
22 #include <linux/iio/triggered_buffer.h>
23 #include <linux/iio/trigger_consumer.h>
24 #include <linux/platform_data/invensense_mpu6050.h>
27 * struct inv_mpu6050_reg_map - Notable registers.
28 * @sample_rate_div: Divider applied to gyro output rate.
29 * @lpf: Configures internal low pass filter.
30 * @accel_lpf: Configures accelerometer low pass filter.
31 * @user_ctrl: Enables/resets the FIFO.
32 * @fifo_en: Determines which data will appear in FIFO.
33 * @gyro_config: gyro config register.
34 * @accl_config: accel config register
35 * @fifo_count_h: Upper byte of FIFO count.
36 * @fifo_r_w: FIFO register.
37 * @raw_gyro: Address of first gyro register.
38 * @raw_accl: Address of first accel register.
39 * @temperature: temperature register
40 * @int_enable: Interrupt enable register.
41 * @int_status: Interrupt status register.
42 * @pwr_mgmt_1: Controls chip's power state and clock source.
43 * @pwr_mgmt_2: Controls power state of individual sensors.
44 * @int_pin_cfg; Controls interrupt pin configuration.
45 * @accl_offset: Controls the accelerometer calibration offset.
46 * @gyro_offset: Controls the gyroscope calibration offset.
47 * @i2c_if: Controls the i2c interface
49 struct inv_mpu6050_reg_map {
87 * struct inv_mpu6050_chip_config - Cached chip configuration data.
88 * @fsr: Full scale range.
89 * @lpf: Digital low pass filter frequency.
90 * @accl_fs: accel full scale range.
91 * @accl_fifo_enable: enable accel data output
92 * @gyro_fifo_enable: enable gyro data output
93 * @divider: chip sample rate divider (sample rate divider - 1)
95 struct inv_mpu6050_chip_config {
98 unsigned int accl_fs:2;
99 unsigned int accl_fifo_enable:1;
100 unsigned int gyro_fifo_enable:1;
106 * struct inv_mpu6050_hw - Other important hardware information.
107 * @whoami: Self identification byte from WHO_AM_I register
108 * @name: name of the chip.
109 * @reg: register map of the chip.
110 * @config: configuration of the chip.
111 * @fifo_size: size of the FIFO in bytes.
113 struct inv_mpu6050_hw {
116 const struct inv_mpu6050_reg_map *reg;
117 const struct inv_mpu6050_chip_config *config;
122 * struct inv_mpu6050_state - Driver state variables.
123 * @lock: Chip access lock.
124 * @trig: IIO trigger.
125 * @chip_config: Cached attribute information.
126 * @reg: Map of important registers.
127 * @hw: Other hardware-specific information.
128 * @chip_type: chip type.
129 * @plat_data: platform data (deprecated in favor of @orientation).
130 * @orientation: sensor chip orientation relative to main hardware.
131 * @map regmap pointer.
132 * @irq interrupt number.
133 * @irq_mask the int_pin_cfg mask to configure interrupt type.
134 * @chip_period: chip internal period estimation (~1kHz).
135 * @it_timestamp: timestamp from previous interrupt.
136 * @data_timestamp: timestamp for next data sample.
138 struct inv_mpu6050_state {
140 struct iio_trigger *trig;
141 struct inv_mpu6050_chip_config chip_config;
142 const struct inv_mpu6050_reg_map *reg;
143 const struct inv_mpu6050_hw *hw;
144 enum inv_devices chip_type;
145 struct i2c_mux_core *muxc;
146 struct i2c_client *mux_client;
147 unsigned int powerup_count;
148 struct inv_mpu6050_platform_data plat_data;
149 struct iio_mount_matrix orientation;
153 unsigned skip_samples;
159 /*register and associated bit definition*/
160 #define INV_MPU6050_REG_ACCEL_OFFSET 0x06
161 #define INV_MPU6050_REG_GYRO_OFFSET 0x13
163 #define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19
164 #define INV_MPU6050_REG_CONFIG 0x1A
165 #define INV_MPU6050_REG_GYRO_CONFIG 0x1B
166 #define INV_MPU6050_REG_ACCEL_CONFIG 0x1C
168 #define INV_MPU6050_REG_FIFO_EN 0x23
169 #define INV_MPU6050_BIT_ACCEL_OUT 0x08
170 #define INV_MPU6050_BITS_GYRO_OUT 0x70
172 #define INV_MPU6050_REG_INT_ENABLE 0x38
173 #define INV_MPU6050_BIT_DATA_RDY_EN 0x01
174 #define INV_MPU6050_BIT_DMP_INT_EN 0x02
176 #define INV_MPU6050_REG_RAW_ACCEL 0x3B
177 #define INV_MPU6050_REG_TEMPERATURE 0x41
178 #define INV_MPU6050_REG_RAW_GYRO 0x43
180 #define INV_MPU6050_REG_INT_STATUS 0x3A
181 #define INV_MPU6050_BIT_FIFO_OVERFLOW_INT 0x10
182 #define INV_MPU6050_BIT_RAW_DATA_RDY_INT 0x01
184 #define INV_MPU6050_REG_USER_CTRL 0x6A
185 #define INV_MPU6050_BIT_FIFO_RST 0x04
186 #define INV_MPU6050_BIT_DMP_RST 0x08
187 #define INV_MPU6050_BIT_I2C_MST_EN 0x20
188 #define INV_MPU6050_BIT_FIFO_EN 0x40
189 #define INV_MPU6050_BIT_DMP_EN 0x80
190 #define INV_MPU6050_BIT_I2C_IF_DIS 0x10
192 #define INV_MPU6050_REG_PWR_MGMT_1 0x6B
193 #define INV_MPU6050_BIT_H_RESET 0x80
194 #define INV_MPU6050_BIT_SLEEP 0x40
195 #define INV_MPU6050_BIT_CLK_MASK 0x7
197 #define INV_MPU6050_REG_PWR_MGMT_2 0x6C
198 #define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38
199 #define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07
201 /* ICM20602 register */
202 #define INV_ICM20602_REG_I2C_IF 0x70
203 #define INV_ICM20602_BIT_I2C_IF_DIS 0x40
205 #define INV_MPU6050_REG_FIFO_COUNT_H 0x72
206 #define INV_MPU6050_REG_FIFO_R_W 0x74
208 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6
209 #define INV_MPU6050_FIFO_COUNT_BYTE 2
211 /* ICM20602 FIFO samples include temperature readings */
212 #define INV_ICM20602_BYTES_PER_TEMP_SENSOR 2
214 /* mpu6500 registers */
215 #define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D
216 #define INV_MPU6500_REG_ACCEL_OFFSET 0x77
218 /* delay time in milliseconds */
219 #define INV_MPU6050_POWER_UP_TIME 100
220 #define INV_MPU6050_TEMP_UP_TIME 100
221 #define INV_MPU6050_SENSOR_UP_TIME 30
223 /* delay time in microseconds */
224 #define INV_MPU6050_REG_UP_TIME_MIN 5000
225 #define INV_MPU6050_REG_UP_TIME_MAX 10000
227 #define INV_MPU6050_TEMP_OFFSET 12421
228 #define INV_MPU6050_TEMP_SCALE 2941
229 #define INV_MPU6050_MAX_GYRO_FS_PARAM 3
230 #define INV_MPU6050_MAX_ACCL_FS_PARAM 3
231 #define INV_MPU6050_THREE_AXIS 3
232 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3
233 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3
235 #define INV_ICM20602_TEMP_OFFSET 8170
236 #define INV_ICM20602_TEMP_SCALE 3060
238 /* 6 + 6 round up and plus 8 */
239 #define INV_MPU6050_OUTPUT_DATA_SIZE 24
241 #define INV_MPU6050_REG_INT_PIN_CFG 0x37
242 #define INV_MPU6050_ACTIVE_HIGH 0x00
243 #define INV_MPU6050_ACTIVE_LOW 0x80
244 /* enable level triggering */
245 #define INV_MPU6050_LATCH_INT_EN 0x20
246 #define INV_MPU6050_BIT_BYPASS_EN 0x2
248 /* Allowed timestamp period jitter in percent */
249 #define INV_MPU6050_TS_PERIOD_JITTER 4
251 /* init parameters */
252 #define INV_MPU6050_INIT_FIFO_RATE 50
253 #define INV_MPU6050_MAX_FIFO_RATE 1000
254 #define INV_MPU6050_MIN_FIFO_RATE 4
256 /* chip internal frequency: 1KHz */
257 #define INV_MPU6050_INTERNAL_FREQ_HZ 1000
258 /* return the frequency divider (chip sample rate divider + 1) */
259 #define INV_MPU6050_FREQ_DIVIDER(st) \
260 ((st)->chip_config.divider + 1)
261 /* chip sample rate divider to fifo rate */
262 #define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate) \
263 ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1)
264 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \
265 (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1))
267 #define INV_MPU6050_REG_WHOAMI 117
269 #define INV_MPU6000_WHOAMI_VALUE 0x68
270 #define INV_MPU6050_WHOAMI_VALUE 0x68
271 #define INV_MPU6500_WHOAMI_VALUE 0x70
272 #define INV_MPU9150_WHOAMI_VALUE 0x68
273 #define INV_MPU9250_WHOAMI_VALUE 0x71
274 #define INV_MPU9255_WHOAMI_VALUE 0x73
275 #define INV_MPU6515_WHOAMI_VALUE 0x74
276 #define INV_ICM20608_WHOAMI_VALUE 0xAF
277 #define INV_ICM20602_WHOAMI_VALUE 0x12
279 /* scan element definition for generic MPU6xxx devices */
280 enum inv_mpu6050_scan {
281 INV_MPU6050_SCAN_ACCL_X,
282 INV_MPU6050_SCAN_ACCL_Y,
283 INV_MPU6050_SCAN_ACCL_Z,
284 INV_MPU6050_SCAN_GYRO_X,
285 INV_MPU6050_SCAN_GYRO_Y,
286 INV_MPU6050_SCAN_GYRO_Z,
287 INV_MPU6050_SCAN_TIMESTAMP,
290 /* scan element definition for ICM20602, which includes temperature */
291 enum inv_icm20602_scan {
292 INV_ICM20602_SCAN_ACCL_X,
293 INV_ICM20602_SCAN_ACCL_Y,
294 INV_ICM20602_SCAN_ACCL_Z,
295 INV_ICM20602_SCAN_TEMP,
296 INV_ICM20602_SCAN_GYRO_X,
297 INV_ICM20602_SCAN_GYRO_Y,
298 INV_ICM20602_SCAN_GYRO_Z,
299 INV_ICM20602_SCAN_TIMESTAMP,
302 enum inv_mpu6050_filter_e {
303 INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
304 INV_MPU6050_FILTER_188HZ,
305 INV_MPU6050_FILTER_98HZ,
306 INV_MPU6050_FILTER_42HZ,
307 INV_MPU6050_FILTER_20HZ,
308 INV_MPU6050_FILTER_10HZ,
309 INV_MPU6050_FILTER_5HZ,
310 INV_MPU6050_FILTER_2100HZ_NOLPF,
314 /* IIO attribute address */
315 enum INV_MPU6050_IIO_ATTR_ADDR {
320 enum inv_mpu6050_accl_fs_e {
321 INV_MPU6050_FS_02G = 0,
328 enum inv_mpu6050_fsr_e {
329 INV_MPU6050_FSR_250DPS = 0,
330 INV_MPU6050_FSR_500DPS,
331 INV_MPU6050_FSR_1000DPS,
332 INV_MPU6050_FSR_2000DPS,
336 enum inv_mpu6050_clock_sel_e {
337 INV_CLK_INTERNAL = 0,
342 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
343 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type);
344 int inv_reset_fifo(struct iio_dev *indio_dev);
345 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
346 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
347 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
348 int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
349 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
350 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
351 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
352 extern const struct dev_pm_ops inv_mpu_pmops;