drivers/iio/frequency/admv1013.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ADMV1013 driver
   4  *
   5  * Copyright 2021 Analog Devices Inc.
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/bits.h>
  10 #include <linux/clk.h>
  11 #include <linux/device.h>
  12 #include <linux/iio/iio.h>
  13 #include <linux/module.h>
  14 #include <linux/mod_devicetable.h>
  15 #include <linux/notifier.h>
  16 #include <linux/property.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/spi/spi.h>
  19 #include <linux/units.h>
  20
  21 #include <asm/unaligned.h>
  22
  23 /* ADMV1013 Register Map */
  24 #define ADMV1013_REG_SPI_CONTROL                0x00
  25 #define ADMV1013_REG_ALARM                      0x01
  26 #define ADMV1013_REG_ALARM_MASKS                0x02
  27 #define ADMV1013_REG_ENABLE                     0x03
  28 #define ADMV1013_REG_LO_AMP_I                   0x05
  29 #define ADMV1013_REG_LO_AMP_Q                   0x06
  30 #define ADMV1013_REG_OFFSET_ADJUST_I            0x07
  31 #define ADMV1013_REG_OFFSET_ADJUST_Q            0x08
  32 #define ADMV1013_REG_QUAD                       0x09
  33 #define ADMV1013_REG_VVA_TEMP_COMP              0x0A
  34
  35 /* ADMV1013_REG_SPI_CONTROL Map */
  36 #define ADMV1013_PARITY_EN_MSK                  BIT(15)
  37 #define ADMV1013_SPI_SOFT_RESET_MSK             BIT(14)
  38 #define ADMV1013_CHIP_ID_MSK                    GENMASK(11, 4)
  39 #define ADMV1013_CHIP_ID                        0xA
  40 #define ADMV1013_REVISION_ID_MSK                GENMASK(3, 0)
  41
  42 /* ADMV1013_REG_ALARM Map */
  43 #define ADMV1013_PARITY_ERROR_MSK               BIT(15)
  44 #define ADMV1013_TOO_FEW_ERRORS_MSK             BIT(14)
  45 #define ADMV1013_TOO_MANY_ERRORS_MSK            BIT(13)
  46 #define ADMV1013_ADDRESS_RANGE_ERROR_MSK        BIT(12)
  47
  48 /* ADMV1013_REG_ENABLE Map */
  49 #define ADMV1013_VGA_PD_MSK                     BIT(15)
  50 #define ADMV1013_MIXER_PD_MSK                   BIT(14)
  51 #define ADMV1013_QUAD_PD_MSK                    GENMASK(13, 11)
  52 #define ADMV1013_BG_PD_MSK                      BIT(10)
  53 #define ADMV1013_MIXER_IF_EN_MSK                BIT(7)
  54 #define ADMV1013_DET_EN_MSK                     BIT(5)
  55
  56 /* ADMV1013_REG_LO_AMP Map */
  57 #define ADMV1013_LOAMP_PH_ADJ_FINE_MSK          GENMASK(13, 7)
  58 #define ADMV1013_MIXER_VGATE_MSK                GENMASK(6, 0)
  59
  60 /* ADMV1013_REG_OFFSET_ADJUST Map */
  61 #define ADMV1013_MIXER_OFF_ADJ_P_MSK            GENMASK(15, 9)
  62 #define ADMV1013_MIXER_OFF_ADJ_N_MSK            GENMASK(8, 2)
  63
  64 /* ADMV1013_REG_QUAD Map */
  65 #define ADMV1013_QUAD_SE_MODE_MSK               GENMASK(9, 6)
  66 #define ADMV1013_QUAD_FILTERS_MSK               GENMASK(3, 0)
  67
  68 /* ADMV1013_REG_VVA_TEMP_COMP Map */
  69 #define ADMV1013_VVA_TEMP_COMP_MSK              GENMASK(15, 0)
  70
  71 /* ADMV1013 Miscellaneous Defines */
  72 #define ADMV1013_READ                           BIT(7)
  73 #define ADMV1013_REG_ADDR_READ_MSK              GENMASK(6, 1)
  74 #define ADMV1013_REG_ADDR_WRITE_MSK             GENMASK(22, 17)
  75 #define ADMV1013_REG_DATA_MSK                   GENMASK(16, 1)
  76
  77 enum {
  78         ADMV1013_IQ_MODE,
  79         ADMV1013_IF_MODE
  80 };
  81
  82 enum {
  83         ADMV1013_RFMOD_I_CALIBPHASE,
  84         ADMV1013_RFMOD_Q_CALIBPHASE,
  85 };
  86
  87 enum {
  88         ADMV1013_SE_MODE_POS = 6,
  89         ADMV1013_SE_MODE_NEG = 9,
  90         ADMV1013_SE_MODE_DIFF = 12
  91 };
  92
  93 struct admv1013_state {
  94         struct spi_device       *spi;
  95         struct clk              *clkin;
  96         /* Protect against concurrent accesses to the device and to data */
  97         struct mutex            lock;
  98         struct regulator        *reg;
  99         struct notifier_block   nb;
 100         unsigned int            input_mode;
 101         unsigned int            quad_se_mode;
 102         bool                    det_en;
 103         u8                      data[3] __aligned(IIO_DMA_MINALIGN);
 104 };
 105
 106 static int __admv1013_spi_read(struct admv1013_state *st, unsigned int reg,
 107                                unsigned int *val)
 108 {
 109         int ret;
 110         struct spi_transfer t = {0};
 111
 112         st->data[0] = ADMV1013_READ | FIELD_PREP(ADMV1013_REG_ADDR_READ_MSK, reg);
 113         st->data[1] = 0x0;
 114         st->data[2] = 0x0;
 115
 116         t.rx_buf = &st->data[0];
 117         t.tx_buf = &st->data[0];
 118         t.len = 3;
 119
 120         ret = spi_sync_transfer(st->spi, &t, 1);
 121         if (ret)
 122                 return ret;
 123
 124         *val = FIELD_GET(ADMV1013_REG_DATA_MSK, get_unaligned_be24(&st->data[0]));
 125
 126         return ret;
 127 }
 128
 129 static int admv1013_spi_read(struct admv1013_state *st, unsigned int reg,
 130                              unsigned int *val)
 131 {
 132         int ret;
 133
 134         mutex_lock(&st->lock);
 135         ret = __admv1013_spi_read(st, reg, val);
 136         mutex_unlock(&st->lock);
 137
 138         return ret;
 139 }
 140
 141 static int __admv1013_spi_write(struct admv1013_state *st,
 142                                 unsigned int reg,
 143                                 unsigned int val)
 144 {
 145         put_unaligned_be24(FIELD_PREP(ADMV1013_REG_DATA_MSK, val) |
 146                            FIELD_PREP(ADMV1013_REG_ADDR_WRITE_MSK, reg), &st->data[0]);
 147
 148         return spi_write(st->spi, &st->data[0], 3);
 149 }
 150
 151 static int admv1013_spi_write(struct admv1013_state *st, unsigned int reg,
 152                               unsigned int val)
 153 {
 154         int ret;
 155
 156         mutex_lock(&st->lock);
 157         ret = __admv1013_spi_write(st, reg, val);
 158         mutex_unlock(&st->lock);
 159
 160         return ret;
 161 }
 162
 163 static int __admv1013_spi_update_bits(struct admv1013_state *st, unsigned int reg,
 164                                       unsigned int mask, unsigned int val)
 165 {
 166         int ret;
 167         unsigned int data, temp;
 168
 169         ret = __admv1013_spi_read(st, reg, &data);
 170         if (ret)
 171                 return ret;
 172
 173         temp = (data & ~mask) | (val & mask);
 174
 175         return __admv1013_spi_write(st, reg, temp);
 176 }
 177
 178 static int admv1013_spi_update_bits(struct admv1013_state *st, unsigned int reg,
 179                                     unsigned int mask, unsigned int val)
 180 {
 181         int ret;
 182
 183         mutex_lock(&st->lock);
 184         ret = __admv1013_spi_update_bits(st, reg, mask, val);
 185         mutex_unlock(&st->lock);
 186
 187         return ret;
 188 }
 189
 190 static int admv1013_read_raw(struct iio_dev *indio_dev,
 191                              struct iio_chan_spec const *chan,
 192                              int *val, int *val2, long info)
 193 {
 194         struct admv1013_state *st = iio_priv(indio_dev);
 195         unsigned int data, addr;
 196         int ret;
 197
 198         switch (info) {
 199         case IIO_CHAN_INFO_CALIBBIAS:
 200                 switch (chan->channel) {
 201                 case IIO_MOD_I:
 202                         addr = ADMV1013_REG_OFFSET_ADJUST_I;
 203                         break;
 204                 case IIO_MOD_Q:
 205                         addr = ADMV1013_REG_OFFSET_ADJUST_Q;
 206                         break;
 207                 default:
 208                         return -EINVAL;
 209                 }
 210
 211                 ret = admv1013_spi_read(st, addr, &data);
 212                 if (ret)
 213                         return ret;
 214
 215                 if (!chan->channel)
 216                         *val = FIELD_GET(ADMV1013_MIXER_OFF_ADJ_P_MSK, data);
 217                 else
 218                         *val = FIELD_GET(ADMV1013_MIXER_OFF_ADJ_N_MSK, data);
 219
 220                 return IIO_VAL_INT;
 221         default:
 222                 return -EINVAL;
 223         }
 224 }
 225
 226 static int admv1013_write_raw(struct iio_dev *indio_dev,
 227                               struct iio_chan_spec const *chan,
 228                               int val, int val2, long info)
 229 {
 230         struct admv1013_state *st = iio_priv(indio_dev);
 231         unsigned int addr, data, msk;
 232
 233         switch (info) {
 234         case IIO_CHAN_INFO_CALIBBIAS:
 235                 switch (chan->channel2) {
 236                 case IIO_MOD_I:
 237                         addr = ADMV1013_REG_OFFSET_ADJUST_I;
 238                         break;
 239                 case IIO_MOD_Q:
 240                         addr = ADMV1013_REG_OFFSET_ADJUST_Q;
 241                         break;
 242                 default:
 243                         return -EINVAL;
 244                 }
 245
 246                 if (!chan->channel) {
 247                         msk = ADMV1013_MIXER_OFF_ADJ_P_MSK;
 248                         data = FIELD_PREP(ADMV1013_MIXER_OFF_ADJ_P_MSK, val);
 249                 } else {
 250                         msk = ADMV1013_MIXER_OFF_ADJ_N_MSK;
 251                         data = FIELD_PREP(ADMV1013_MIXER_OFF_ADJ_N_MSK, val);
 252                 }
 253
 254                 return admv1013_spi_update_bits(st, addr, msk, data);
 255         default:
 256                 return -EINVAL;
 257         }
 258 }
 259
 260 static ssize_t admv1013_read(struct iio_dev *indio_dev,
 261                              uintptr_t private,
 262                              const struct iio_chan_spec *chan,
 263                              char *buf)
 264 {
 265         struct admv1013_state *st = iio_priv(indio_dev);
 266         unsigned int data, addr;
 267         int ret;
 268
 269         switch ((u32)private) {
 270         case ADMV1013_RFMOD_I_CALIBPHASE:
 271                 addr = ADMV1013_REG_LO_AMP_I;
 272                 break;
 273         case ADMV1013_RFMOD_Q_CALIBPHASE:
 274                 addr = ADMV1013_REG_LO_AMP_Q;
 275                 break;
 276         default:
 277                 return -EINVAL;
 278         }
 279
 280         ret = admv1013_spi_read(st, addr, &data);
 281         if (ret)
 282                 return ret;
 283
 284         data = FIELD_GET(ADMV1013_LOAMP_PH_ADJ_FINE_MSK, data);
 285
 286         return sysfs_emit(buf, "%u\n", data);
 287 }
 288
 289 static ssize_t admv1013_write(struct iio_dev *indio_dev,
 290                               uintptr_t private,
 291                               const struct iio_chan_spec *chan,
 292                               const char *buf, size_t len)
 293 {
 294         struct admv1013_state *st = iio_priv(indio_dev);
 295         unsigned int data;
 296         int ret;
 297
 298         ret = kstrtou32(buf, 10, &data);
 299         if (ret)
 300                 return ret;
 301
 302         data = FIELD_PREP(ADMV1013_LOAMP_PH_ADJ_FINE_MSK, data);
 303
 304         switch ((u32)private) {
 305         case ADMV1013_RFMOD_I_CALIBPHASE:
 306                 ret = admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_I,
 307                                                ADMV1013_LOAMP_PH_ADJ_FINE_MSK,
 308                                                data);
 309                 if (ret)
 310                         return ret;
 311                 break;
 312         case ADMV1013_RFMOD_Q_CALIBPHASE:
 313                 ret = admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_Q,
 314                                                ADMV1013_LOAMP_PH_ADJ_FINE_MSK,
 315                                                data);
 316                 if (ret)
 317                         return ret;
 318                 break;
 319         default:
 320                 return -EINVAL;
 321         }
 322
 323         return ret ? ret : len;
 324 }
 325
 326 static int admv1013_update_quad_filters(struct admv1013_state *st)
 327 {
 328         unsigned int filt_raw;
 329         u64 rate = clk_get_rate(st->clkin);
 330
 331         if (rate >= (5400 * HZ_PER_MHZ) && rate <= (7000 * HZ_PER_MHZ))
 332                 filt_raw = 15;
 333         else if (rate >= (5400 * HZ_PER_MHZ) && rate <= (8000 * HZ_PER_MHZ))
 334                 filt_raw = 10;
 335         else if (rate >= (6600 * HZ_PER_MHZ) && rate <= (9200 * HZ_PER_MHZ))
 336                 filt_raw = 5;
 337         else
 338                 filt_raw = 0;
 339
 340         return __admv1013_spi_update_bits(st, ADMV1013_REG_QUAD,
 341                                         ADMV1013_QUAD_FILTERS_MSK,
 342                                         FIELD_PREP(ADMV1013_QUAD_FILTERS_MSK, filt_raw));
 343 }
 344
 345 static int admv1013_update_mixer_vgate(struct admv1013_state *st)
 346 {
 347         unsigned int mixer_vgate;
 348         int vcm;
 349
 350         vcm = regulator_get_voltage(st->reg);
 351         if (vcm < 0)
 352                 return vcm;
 353
 354         if (vcm < 1800000)
 355                 mixer_vgate = (2389 * vcm / 1000000 + 8100) / 100;
 356         else if (vcm > 1800000 && vcm < 2600000)
 357                 mixer_vgate = (2375 * vcm / 1000000 + 125) / 100;
 358         else
 359                 return -EINVAL;
 360
 361         return __admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_I,
 362                                  ADMV1013_MIXER_VGATE_MSK,
 363                                  FIELD_PREP(ADMV1013_MIXER_VGATE_MSK, mixer_vgate));
 364 }
 365
 366 static int admv1013_reg_access(struct iio_dev *indio_dev,
 367                                unsigned int reg,
 368                                unsigned int write_val,
 369                                unsigned int *read_val)
 370 {
 371         struct admv1013_state *st = iio_priv(indio_dev);
 372
 373         if (read_val)
 374                 return admv1013_spi_read(st, reg, read_val);
 375         else
 376                 return admv1013_spi_write(st, reg, write_val);
 377 }
 378
 379 static const struct iio_info admv1013_info = {
 380         .read_raw = admv1013_read_raw,
 381         .write_raw = admv1013_write_raw,
 382         .debugfs_reg_access = &admv1013_reg_access,
 383 };
 384
 385 static int admv1013_freq_change(struct notifier_block *nb, unsigned long action, void *data)
 386 {
 387         struct admv1013_state *st = container_of(nb, struct admv1013_state, nb);
 388         int ret;
 389
 390         if (action == POST_RATE_CHANGE) {
 391                 mutex_lock(&st->lock);
 392                 ret = notifier_from_errno(admv1013_update_quad_filters(st));
 393                 mutex_unlock(&st->lock);
 394                 return ret;
 395         }
 396
 397         return NOTIFY_OK;
 398 }
 399
 400 #define _ADMV1013_EXT_INFO(_name, _shared, _ident) { \
 401                 .name = _name, \
 402                 .read = admv1013_read, \
 403                 .write = admv1013_write, \
 404                 .private = _ident, \
 405                 .shared = _shared, \
 406 }
 407
 408 static const struct iio_chan_spec_ext_info admv1013_ext_info[] = {
 409         _ADMV1013_EXT_INFO("i_calibphase", IIO_SEPARATE, ADMV1013_RFMOD_I_CALIBPHASE),
 410         _ADMV1013_EXT_INFO("q_calibphase", IIO_SEPARATE, ADMV1013_RFMOD_Q_CALIBPHASE),
 411         { },
 412 };
 413
 414 #define ADMV1013_CHAN_PHASE(_channel, _channel2, _admv1013_ext_info) {          \
 415         .type = IIO_ALTVOLTAGE,                                 \
 416         .output = 0,                                            \
 417         .indexed = 1,                                           \
 418         .channel2 = _channel2,                                  \
 419         .channel = _channel,                                    \
 420         .differential = 1,                                      \
 421         .ext_info = _admv1013_ext_info,                         \
 422         }
 423
 424 #define ADMV1013_CHAN_CALIB(_channel, rf_comp) {        \
 425         .type = IIO_ALTVOLTAGE,                                 \
 426         .output = 0,                                            \
 427         .indexed = 1,                                           \
 428         .channel = _channel,                                    \
 429         .channel2 = IIO_MOD_##rf_comp,                          \
 430         .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBBIAS),     \
 431         }
 432
 433 static const struct iio_chan_spec admv1013_channels[] = {
 434         ADMV1013_CHAN_PHASE(0, 1, admv1013_ext_info),
 435         ADMV1013_CHAN_CALIB(0, I),
 436         ADMV1013_CHAN_CALIB(0, Q),
 437         ADMV1013_CHAN_CALIB(1, I),
 438         ADMV1013_CHAN_CALIB(1, Q),
 439 };
 440
 441 static int admv1013_init(struct admv1013_state *st)
 442 {
 443         int ret;
 444         unsigned int data;
 445         struct spi_device *spi = st->spi;
 446
 447         /* Perform a software reset */
 448         ret = __admv1013_spi_update_bits(st, ADMV1013_REG_SPI_CONTROL,
 449                                          ADMV1013_SPI_SOFT_RESET_MSK,
 450                                          FIELD_PREP(ADMV1013_SPI_SOFT_RESET_MSK, 1));
 451         if (ret)
 452                 return ret;
 453
 454         ret = __admv1013_spi_update_bits(st, ADMV1013_REG_SPI_CONTROL,
 455                                          ADMV1013_SPI_SOFT_RESET_MSK,
 456                                          FIELD_PREP(ADMV1013_SPI_SOFT_RESET_MSK, 0));
 457         if (ret)
 458                 return ret;
 459
 460         ret = __admv1013_spi_read(st, ADMV1013_REG_SPI_CONTROL, &data);
 461         if (ret)
 462                 return ret;
 463
 464         data = FIELD_GET(ADMV1013_CHIP_ID_MSK, data);
 465         if (data != ADMV1013_CHIP_ID) {
 466                 dev_err(&spi->dev, "Invalid Chip ID.\n");
 467                 return -EINVAL;
 468         }
 469
 470         ret = __admv1013_spi_write(st, ADMV1013_REG_VVA_TEMP_COMP, 0xE700);
 471         if (ret)
 472                 return ret;
 473
 474         data = FIELD_PREP(ADMV1013_QUAD_SE_MODE_MSK, st->quad_se_mode);
 475
 476         ret = __admv1013_spi_update_bits(st, ADMV1013_REG_QUAD,
 477                                          ADMV1013_QUAD_SE_MODE_MSK, data);
 478         if (ret)
 479                 return ret;
 480
 481         ret = admv1013_update_mixer_vgate(st);
 482         if (ret)
 483                 return ret;
 484
 485         ret = admv1013_update_quad_filters(st);
 486         if (ret)
 487                 return ret;
 488
 489         return __admv1013_spi_update_bits(st, ADMV1013_REG_ENABLE,
 490                                           ADMV1013_DET_EN_MSK |
 491                                           ADMV1013_MIXER_IF_EN_MSK,
 492                                           st->det_en |
 493                                           st->input_mode);
 494 }
 495
 496 static void admv1013_reg_disable(void *data)
 497 {
 498         regulator_disable(data);
 499 }
 500
 501 static void admv1013_powerdown(void *data)
 502 {
 503         unsigned int enable_reg, enable_reg_msk;
 504
 505         /* Disable all components in the Enable Register */
 506         enable_reg_msk = ADMV1013_VGA_PD_MSK |
 507                         ADMV1013_MIXER_PD_MSK |
 508                         ADMV1013_QUAD_PD_MSK |
 509                         ADMV1013_BG_PD_MSK |
 510                         ADMV1013_MIXER_IF_EN_MSK |
 511                         ADMV1013_DET_EN_MSK;
 512
 513         enable_reg = FIELD_PREP(ADMV1013_VGA_PD_MSK, 1) |
 514                         FIELD_PREP(ADMV1013_MIXER_PD_MSK, 1) |
 515                         FIELD_PREP(ADMV1013_QUAD_PD_MSK, 7) |
 516                         FIELD_PREP(ADMV1013_BG_PD_MSK, 1) |
 517                         FIELD_PREP(ADMV1013_MIXER_IF_EN_MSK, 0) |
 518                         FIELD_PREP(ADMV1013_DET_EN_MSK, 0);
 519
 520         admv1013_spi_update_bits(data, ADMV1013_REG_ENABLE, enable_reg_msk, enable_reg);
 521 }
 522
 523 static int admv1013_properties_parse(struct admv1013_state *st)
 524 {
 525         int ret;
 526         const char *str;
 527         struct spi_device *spi = st->spi;
 528
 529         st->det_en = device_property_read_bool(&spi->dev, "adi,detector-enable");
 530
 531         ret = device_property_read_string(&spi->dev, "adi,input-mode", &str);
 532         if (ret)
 533                 st->input_mode = ADMV1013_IQ_MODE;
 534
 535         if (!strcmp(str, "iq"))
 536                 st->input_mode = ADMV1013_IQ_MODE;
 537         else if (!strcmp(str, "if"))
 538                 st->input_mode = ADMV1013_IF_MODE;
 539         else
 540                 return -EINVAL;
 541
 542         ret = device_property_read_string(&spi->dev, "adi,quad-se-mode", &str);
 543         if (ret)
 544                 st->quad_se_mode = ADMV1013_SE_MODE_DIFF;
 545
 546         if (!strcmp(str, "diff"))
 547                 st->quad_se_mode = ADMV1013_SE_MODE_DIFF;
 548         else if (!strcmp(str, "se-pos"))
 549                 st->quad_se_mode = ADMV1013_SE_MODE_POS;
 550         else if (!strcmp(str, "se-neg"))
 551                 st->quad_se_mode = ADMV1013_SE_MODE_NEG;
 552         else
 553                 return -EINVAL;
 554
 555         st->reg = devm_regulator_get(&spi->dev, "vcm");
 556         if (IS_ERR(st->reg))
 557                 return dev_err_probe(&spi->dev, PTR_ERR(st->reg),
 558                                      "failed to get the common-mode voltage\n");
 559
 560         return 0;
 561 }
 562
 563 static int admv1013_probe(struct spi_device *spi)
 564 {
 565         struct iio_dev *indio_dev;
 566         struct admv1013_state *st;
 567         int ret;
 568
 569         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 570         if (!indio_dev)
 571                 return -ENOMEM;
 572
 573         st = iio_priv(indio_dev);
 574
 575         indio_dev->info = &admv1013_info;
 576         indio_dev->name = "admv1013";
 577         indio_dev->channels = admv1013_channels;
 578         indio_dev->num_channels = ARRAY_SIZE(admv1013_channels);
 579
 580         st->spi = spi;
 581
 582         ret = admv1013_properties_parse(st);
 583         if (ret)
 584                 return ret;
 585
 586         ret = regulator_enable(st->reg);
 587         if (ret) {
 588                 dev_err(&spi->dev, "Failed to enable specified Common-Mode Voltage!\n");
 589                 return ret;
 590         }
 591
 592         ret = devm_add_action_or_reset(&spi->dev, admv1013_reg_disable,
 593                                        st->reg);
 594         if (ret)
 595                 return ret;
 596
 597         st->clkin = devm_clk_get_enabled(&spi->dev, "lo_in");
 598         if (IS_ERR(st->clkin))
 599                 return dev_err_probe(&spi->dev, PTR_ERR(st->clkin),
 600                                      "failed to get the LO input clock\n");
 601
 602         st->nb.notifier_call = admv1013_freq_change;
 603         ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb);
 604         if (ret)
 605                 return ret;
 606
 607         mutex_init(&st->lock);
 608
 609         ret = admv1013_init(st);
 610         if (ret) {
 611                 dev_err(&spi->dev, "admv1013 init failed\n");
 612                 return ret;
 613         }
 614
 615         ret = devm_add_action_or_reset(&spi->dev, admv1013_powerdown, st);
 616         if (ret)
 617                 return ret;
 618
 619         return devm_iio_device_register(&spi->dev, indio_dev);
 620 }
 621
 622 static const struct spi_device_id admv1013_id[] = {
 623         { "admv1013", 0 },
 624         {}
 625 };
 626 MODULE_DEVICE_TABLE(spi, admv1013_id);
 627
 628 static const struct of_device_id admv1013_of_match[] = {
 629         { .compatible = "adi,admv1013" },
 630         {},
 631 };
 632 MODULE_DEVICE_TABLE(of, admv1013_of_match);
 633
 634 static struct spi_driver admv1013_driver = {
 635         .driver = {
 636                 .name = "admv1013",
 637                 .of_match_table = admv1013_of_match,
 638         },
 639         .probe = admv1013_probe,
 640         .id_table = admv1013_id,
 641 };
 642 module_spi_driver(admv1013_driver);
 643
 644 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com");
 645 MODULE_DESCRIPTION("Analog Devices ADMV1013");
 646 MODULE_LICENSE("GPL v2");