1 // SPDX-License-Identifier: GPL-2.0
3 * This file is part the core part STM32 DFSDM driver
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com> for STMicroelectronics.
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/iio/iio.h>
12 #include <linux/iio/sysfs.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
16 #include <linux/of_platform.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
23 #include "stm32-dfsdm.h"
26 * struct stm32_dfsdm_dev_data - DFSDM compatible configuration data
27 * @ipid: DFSDM identification number. Used only if hardware provides identification registers
28 * @num_filters: DFSDM number of filters. Unused if identification registers are available
29 * @num_channels: DFSDM number of channels. Unused if identification registers are available
30 * @regmap_cfg: SAI register map configuration pointer
32 struct stm32_dfsdm_dev_data {
34 unsigned int num_filters;
35 unsigned int num_channels;
36 const struct regmap_config *regmap_cfg;
39 #define STM32H7_DFSDM_NUM_FILTERS 4
40 #define STM32H7_DFSDM_NUM_CHANNELS 8
42 static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg)
44 if (reg < DFSDM_FILTER_BASE_ADR)
48 * Mask is done on register to avoid to list registers of all
51 switch (reg & DFSDM_FILTER_REG_MASK) {
52 case DFSDM_CR1(0) & DFSDM_FILTER_REG_MASK:
53 case DFSDM_ISR(0) & DFSDM_FILTER_REG_MASK:
54 case DFSDM_JDATAR(0) & DFSDM_FILTER_REG_MASK:
55 case DFSDM_RDATAR(0) & DFSDM_FILTER_REG_MASK:
62 static const struct regmap_config stm32h7_dfsdm_regmap_cfg = {
65 .reg_stride = sizeof(u32),
66 .max_register = 0x2B8,
67 .volatile_reg = stm32_dfsdm_volatile_reg,
71 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_data = {
72 .num_filters = STM32H7_DFSDM_NUM_FILTERS,
73 .num_channels = STM32H7_DFSDM_NUM_CHANNELS,
74 .regmap_cfg = &stm32h7_dfsdm_regmap_cfg,
77 static const struct regmap_config stm32mp1_dfsdm_regmap_cfg = {
80 .reg_stride = sizeof(u32),
81 .max_register = 0x7fc,
82 .volatile_reg = stm32_dfsdm_volatile_reg,
86 static const struct stm32_dfsdm_dev_data stm32mp1_dfsdm_data = {
87 .ipid = STM32MP15_IPIDR_NUMBER,
88 .regmap_cfg = &stm32mp1_dfsdm_regmap_cfg,
92 struct platform_device *pdev; /* platform device */
94 struct stm32_dfsdm dfsdm; /* common data exported for all instances */
96 unsigned int spi_clk_out_div; /* SPI clkout divider value */
97 atomic_t n_active_ch; /* number of current active channels */
99 struct clk *clk; /* DFSDM clock */
100 struct clk *aclk; /* audio clock */
103 static inline struct dfsdm_priv *to_stm32_dfsdm_priv(struct stm32_dfsdm *dfsdm)
105 return container_of(dfsdm, struct dfsdm_priv, dfsdm);
108 static int stm32_dfsdm_clk_prepare_enable(struct stm32_dfsdm *dfsdm)
110 struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
113 ret = clk_prepare_enable(priv->clk);
114 if (ret || !priv->aclk)
117 ret = clk_prepare_enable(priv->aclk);
119 clk_disable_unprepare(priv->clk);
124 static void stm32_dfsdm_clk_disable_unprepare(struct stm32_dfsdm *dfsdm)
126 struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
128 clk_disable_unprepare(priv->aclk);
129 clk_disable_unprepare(priv->clk);
133 * stm32_dfsdm_start_dfsdm - start global dfsdm interface.
135 * Enable interface if n_active_ch is not null.
136 * @dfsdm: Handle used to retrieve dfsdm context.
138 int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm)
140 struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
141 struct device *dev = &priv->pdev->dev;
142 unsigned int clk_div = priv->spi_clk_out_div, clk_src;
145 if (atomic_inc_return(&priv->n_active_ch) == 1) {
146 ret = pm_runtime_resume_and_get(dev);
150 /* select clock source, e.g. 0 for "dfsdm" or 1 for "audio" */
151 clk_src = priv->aclk ? 1 : 0;
152 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
153 DFSDM_CHCFGR1_CKOUTSRC_MASK,
154 DFSDM_CHCFGR1_CKOUTSRC(clk_src));
158 /* Output the SPI CLKOUT (if clk_div == 0 clock if OFF) */
159 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
160 DFSDM_CHCFGR1_CKOUTDIV_MASK,
161 DFSDM_CHCFGR1_CKOUTDIV(clk_div));
165 /* Global enable of DFSDM interface */
166 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
167 DFSDM_CHCFGR1_DFSDMEN_MASK,
168 DFSDM_CHCFGR1_DFSDMEN(1));
173 dev_dbg(dev, "%s: n_active_ch %d\n", __func__,
174 atomic_read(&priv->n_active_ch));
179 pm_runtime_put_sync(dev);
181 atomic_dec(&priv->n_active_ch);
185 EXPORT_SYMBOL_GPL(stm32_dfsdm_start_dfsdm);
188 * stm32_dfsdm_stop_dfsdm - stop global DFSDM interface.
190 * Disable interface if n_active_ch is null
191 * @dfsdm: Handle used to retrieve dfsdm context.
193 int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm)
195 struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
198 if (atomic_dec_and_test(&priv->n_active_ch)) {
199 /* Global disable of DFSDM interface */
200 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
201 DFSDM_CHCFGR1_DFSDMEN_MASK,
202 DFSDM_CHCFGR1_DFSDMEN(0));
206 /* Stop SPI CLKOUT */
207 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
208 DFSDM_CHCFGR1_CKOUTDIV_MASK,
209 DFSDM_CHCFGR1_CKOUTDIV(0));
213 pm_runtime_put_sync(&priv->pdev->dev);
215 dev_dbg(&priv->pdev->dev, "%s: n_active_ch %d\n", __func__,
216 atomic_read(&priv->n_active_ch));
220 EXPORT_SYMBOL_GPL(stm32_dfsdm_stop_dfsdm);
222 static int stm32_dfsdm_parse_of(struct platform_device *pdev,
223 struct dfsdm_priv *priv)
225 struct device_node *node = pdev->dev.of_node;
226 struct resource *res;
227 unsigned long clk_freq, divider;
228 unsigned int spi_freq, rem;
234 priv->dfsdm.base = devm_platform_get_and_ioremap_resource(pdev, 0,
236 if (IS_ERR(priv->dfsdm.base))
237 return PTR_ERR(priv->dfsdm.base);
239 priv->dfsdm.phys_base = res->start;
242 * "dfsdm" clock is mandatory for DFSDM peripheral clocking.
243 * "dfsdm" or "audio" clocks can be used as source clock for
244 * the SPI clock out signal and internal processing, depending
247 priv->clk = devm_clk_get(&pdev->dev, "dfsdm");
248 if (IS_ERR(priv->clk))
249 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk),
250 "Failed to get clock\n");
252 priv->aclk = devm_clk_get(&pdev->dev, "audio");
253 if (IS_ERR(priv->aclk))
257 clk_freq = clk_get_rate(priv->aclk);
259 clk_freq = clk_get_rate(priv->clk);
261 /* SPI clock out frequency */
262 ret = of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
265 /* No SPI master mode */
269 divider = div_u64_rem(clk_freq, spi_freq, &rem);
270 /* Round up divider when ckout isn't precise, not to exceed spi_freq */
274 /* programmable divider is in range of [2:256] */
275 if (divider < 2 || divider > 256) {
276 dev_err(&pdev->dev, "spi-max-frequency not achievable\n");
280 /* SPI clock output divider is: divider = CKOUTDIV + 1 */
281 priv->spi_clk_out_div = divider - 1;
282 priv->dfsdm.spi_master_freq = clk_freq / (priv->spi_clk_out_div + 1);
285 dev_warn(&pdev->dev, "SPI clock not accurate\n");
286 dev_warn(&pdev->dev, "%ld = %d * %d + %d\n",
287 clk_freq, spi_freq, priv->spi_clk_out_div + 1, rem);
293 static const struct of_device_id stm32_dfsdm_of_match[] = {
295 .compatible = "st,stm32h7-dfsdm",
296 .data = &stm32h7_dfsdm_data,
299 .compatible = "st,stm32mp1-dfsdm",
300 .data = &stm32mp1_dfsdm_data,
304 MODULE_DEVICE_TABLE(of, stm32_dfsdm_of_match);
306 static int stm32_dfsdm_probe_identification(struct platform_device *pdev,
307 struct dfsdm_priv *priv,
308 const struct stm32_dfsdm_dev_data *dev_data)
310 struct device_node *np = pdev->dev.of_node;
311 struct device_node *child;
312 struct stm32_dfsdm *dfsdm = &priv->dfsdm;
317 if (!dev_data->ipid) {
318 dfsdm->num_fls = dev_data->num_filters;
319 dfsdm->num_chs = dev_data->num_channels;
323 ret = regmap_read(dfsdm->regmap, DFSDM_IPIDR, &id);
327 if (id != dev_data->ipid) {
328 dev_err(&pdev->dev, "Unexpected IP version: 0x%x", id);
332 for_each_child_of_node(np, child) {
333 ret = of_property_read_string(child, "compatible", &compat);
336 /* Count only child nodes with dfsdm compatible */
337 if (strstr(compat, "dfsdm"))
341 ret = regmap_read(dfsdm->regmap, DFSDM_HWCFGR, &val);
345 dfsdm->num_fls = FIELD_GET(DFSDM_HWCFGR_NBF_MASK, val);
346 dfsdm->num_chs = FIELD_GET(DFSDM_HWCFGR_NBT_MASK, val);
348 if (count > dfsdm->num_fls) {
349 dev_err(&pdev->dev, "Unexpected child number: %d", count);
353 ret = regmap_read(dfsdm->regmap, DFSDM_VERR, &val);
357 dev_dbg(&pdev->dev, "DFSDM version: %lu.%lu. %d channels/%d filters\n",
358 FIELD_GET(DFSDM_VERR_MAJREV_MASK, val),
359 FIELD_GET(DFSDM_VERR_MINREV_MASK, val),
360 dfsdm->num_chs, dfsdm->num_fls);
365 static int stm32_dfsdm_probe(struct platform_device *pdev)
367 struct dfsdm_priv *priv;
368 const struct stm32_dfsdm_dev_data *dev_data;
369 struct stm32_dfsdm *dfsdm;
372 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
378 dev_data = of_device_get_match_data(&pdev->dev);
380 dfsdm = &priv->dfsdm;
382 ret = stm32_dfsdm_parse_of(pdev, priv);
386 dfsdm->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dfsdm",
388 dev_data->regmap_cfg);
389 if (IS_ERR(dfsdm->regmap)) {
390 ret = PTR_ERR(dfsdm->regmap);
391 dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
396 ret = stm32_dfsdm_probe_identification(pdev, priv, dev_data);
400 dfsdm->fl_list = devm_kcalloc(&pdev->dev, dfsdm->num_fls,
401 sizeof(*dfsdm->fl_list), GFP_KERNEL);
405 dfsdm->ch_list = devm_kcalloc(&pdev->dev, dfsdm->num_chs,
406 sizeof(*dfsdm->ch_list), GFP_KERNEL);
410 platform_set_drvdata(pdev, dfsdm);
412 ret = stm32_dfsdm_clk_prepare_enable(dfsdm);
414 dev_err(&pdev->dev, "Failed to start clock\n");
418 pm_runtime_get_noresume(&pdev->dev);
419 pm_runtime_set_active(&pdev->dev);
420 pm_runtime_enable(&pdev->dev);
422 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
426 pm_runtime_put(&pdev->dev);
431 pm_runtime_disable(&pdev->dev);
432 pm_runtime_set_suspended(&pdev->dev);
433 pm_runtime_put_noidle(&pdev->dev);
434 stm32_dfsdm_clk_disable_unprepare(dfsdm);
439 static int stm32_dfsdm_core_remove(struct platform_device *pdev)
441 struct stm32_dfsdm *dfsdm = platform_get_drvdata(pdev);
443 pm_runtime_get_sync(&pdev->dev);
444 of_platform_depopulate(&pdev->dev);
445 pm_runtime_disable(&pdev->dev);
446 pm_runtime_set_suspended(&pdev->dev);
447 pm_runtime_put_noidle(&pdev->dev);
448 stm32_dfsdm_clk_disable_unprepare(dfsdm);
453 static int stm32_dfsdm_core_suspend(struct device *dev)
455 struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
456 struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
459 ret = pm_runtime_force_suspend(dev);
463 /* Balance devm_regmap_init_mmio_clk() clk_prepare() */
464 clk_unprepare(priv->clk);
466 return pinctrl_pm_select_sleep_state(dev);
469 static int stm32_dfsdm_core_resume(struct device *dev)
471 struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
472 struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
475 ret = pinctrl_pm_select_default_state(dev);
479 ret = clk_prepare(priv->clk);
483 return pm_runtime_force_resume(dev);
486 static int stm32_dfsdm_core_runtime_suspend(struct device *dev)
488 struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
490 stm32_dfsdm_clk_disable_unprepare(dfsdm);
495 static int stm32_dfsdm_core_runtime_resume(struct device *dev)
497 struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
499 return stm32_dfsdm_clk_prepare_enable(dfsdm);
502 static const struct dev_pm_ops stm32_dfsdm_core_pm_ops = {
503 SYSTEM_SLEEP_PM_OPS(stm32_dfsdm_core_suspend, stm32_dfsdm_core_resume)
504 RUNTIME_PM_OPS(stm32_dfsdm_core_runtime_suspend,
505 stm32_dfsdm_core_runtime_resume,
509 static struct platform_driver stm32_dfsdm_driver = {
510 .probe = stm32_dfsdm_probe,
511 .remove = stm32_dfsdm_core_remove,
513 .name = "stm32-dfsdm",
514 .of_match_table = stm32_dfsdm_of_match,
515 .pm = pm_ptr(&stm32_dfsdm_core_pm_ops),
519 module_platform_driver(stm32_dfsdm_driver);
521 MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
522 MODULE_DESCRIPTION("STMicroelectronics STM32 dfsdm driver");
523 MODULE_LICENSE("GPL v2");