1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
6 #include <linux/bitops.h>
7 #include <linux/completion.h>
8 #include <linux/delay.h>
10 #include <linux/iio/iio.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/log2.h>
14 #include <linux/math64.h>
15 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
21 #include <dt-bindings/iio/qcom,spmi-vadc.h>
22 #include "qcom-vadc-common.h"
24 #define ADC5_USR_REVISION1 0x0
25 #define ADC5_USR_STATUS1 0x8
26 #define ADC5_USR_STATUS1_CONV_FAULT BIT(7)
27 #define ADC5_USR_STATUS1_REQ_STS BIT(1)
28 #define ADC5_USR_STATUS1_EOC BIT(0)
29 #define ADC5_USR_STATUS1_REQ_STS_EOC_MASK 0x3
31 #define ADC5_USR_STATUS2 0x9
32 #define ADC5_USR_STATUS2_CONV_SEQ_MASK 0x70
33 #define ADC5_USR_STATUS2_CONV_SEQ_MASK_SHIFT 0x5
35 #define ADC5_USR_IBAT_MEAS 0xf
36 #define ADC5_USR_IBAT_MEAS_SUPPORTED BIT(0)
38 #define ADC5_USR_DIG_PARAM 0x42
39 #define ADC5_USR_DIG_PARAM_CAL_VAL BIT(6)
40 #define ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT 6
41 #define ADC5_USR_DIG_PARAM_CAL_SEL 0x30
42 #define ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT 4
43 #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL 0xc
44 #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT 2
46 #define ADC5_USR_FAST_AVG_CTL 0x43
47 #define ADC5_USR_FAST_AVG_CTL_EN BIT(7)
48 #define ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK 0x7
50 #define ADC5_USR_CH_SEL_CTL 0x44
52 #define ADC5_USR_DELAY_CTL 0x45
53 #define ADC5_USR_HW_SETTLE_DELAY_MASK 0xf
55 #define ADC5_USR_EN_CTL1 0x46
56 #define ADC5_USR_EN_CTL1_ADC_EN BIT(7)
58 #define ADC5_USR_CONV_REQ 0x47
59 #define ADC5_USR_CONV_REQ_REQ BIT(7)
61 #define ADC5_USR_DATA0 0x50
63 #define ADC5_USR_DATA1 0x51
65 #define ADC5_USR_IBAT_DATA0 0x52
67 #define ADC5_USR_IBAT_DATA1 0x53
69 #define ADC_CHANNEL_OFFSET 0x8
70 #define ADC_CHANNEL_MASK GENMASK(7, 0)
73 * Conversion time varies based on the decimation, clock rate, fast average
74 * samples and measurements queued across different VADC peripherals.
75 * Set the timeout to a max of 100ms.
77 #define ADC5_CONV_TIME_MIN_US 263
78 #define ADC5_CONV_TIME_MAX_US 264
79 #define ADC5_CONV_TIME_RETRY 400
80 #define ADC5_CONV_TIMEOUT msecs_to_jiffies(100)
82 /* Digital version >= 5.3 supports hw_settle_2 */
83 #define ADC5_HW_SETTLE_DIFF_MINOR 3
84 #define ADC5_HW_SETTLE_DIFF_MAJOR 5
87 #define ADC_APP_SID 0x40
88 #define ADC_APP_SID_MASK GENMASK(3, 0)
89 #define ADC7_CONV_TIMEOUT msecs_to_jiffies(10)
91 enum adc5_cal_method {
103 * struct adc5_channel_prop - ADC channel property.
104 * @channel: channel number, refer to the channel list.
105 * @cal_method: calibration method.
106 * @cal_val: calibration value
107 * @decimation: sampling rate supported for the channel.
108 * @sid: slave id of PMIC owning the channel, for PMIC7.
109 * @prescale: channel scaling performed on the input signal.
110 * @hw_settle_time: the time between AMUX being configured and the
111 * start of conversion.
112 * @avg_samples: ability to provide single result from the ADC
113 * that is an average of multiple measurements.
114 * @scale_fn_type: Represents the scaling function to convert voltage
115 * physical units desired by the client for the channel.
116 * @datasheet_name: Channel name used in device tree.
118 struct adc5_channel_prop {
119 unsigned int channel;
120 enum adc5_cal_method cal_method;
121 enum adc5_cal_val cal_val;
122 unsigned int decimation;
124 unsigned int prescale;
125 unsigned int hw_settle_time;
126 unsigned int avg_samples;
127 enum vadc_scale_fn_type scale_fn_type;
128 const char *datasheet_name;
132 * struct adc5_chip - ADC private structure.
133 * @regmap: SPMI ADC5 peripheral register map field.
134 * @dev: SPMI ADC5 device.
135 * @base: base address for the ADC peripheral.
136 * @nchannels: number of ADC channels.
137 * @chan_props: array of ADC channel properties.
138 * @iio_chans: array of IIO channels specification.
139 * @poll_eoc: use polling instead of interrupt.
140 * @complete: ADC result notification after interrupt is received.
141 * @lock: ADC lock for access to the peripheral.
142 * @data: software configuration data.
145 struct regmap *regmap;
148 unsigned int nchannels;
149 struct adc5_channel_prop *chan_props;
150 struct iio_chan_spec *iio_chans;
152 struct completion complete;
154 const struct adc5_data *data;
157 static const struct vadc_prescale_ratio adc5_prescale_ratios[] = {
158 {.num = 1, .den = 1},
159 {.num = 1, .den = 3},
160 {.num = 1, .den = 4},
161 {.num = 1, .den = 6},
162 {.num = 1, .den = 20},
163 {.num = 1, .den = 8},
164 {.num = 10, .den = 81},
165 {.num = 1, .den = 10},
166 {.num = 1, .den = 16}
169 static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len)
171 return regmap_bulk_read(adc->regmap, adc->base + offset, data, len);
174 static int adc5_write(struct adc5_chip *adc, u16 offset, u8 *data, int len)
176 return regmap_bulk_write(adc->regmap, adc->base + offset, data, len);
179 static int adc5_masked_write(struct adc5_chip *adc, u16 offset, u8 mask, u8 val)
181 return regmap_update_bits(adc->regmap, adc->base + offset, mask, val);
184 static int adc5_prescaling_from_dt(u32 num, u32 den)
188 for (pre = 0; pre < ARRAY_SIZE(adc5_prescale_ratios); pre++)
189 if (adc5_prescale_ratios[pre].num == num &&
190 adc5_prescale_ratios[pre].den == den)
193 if (pre == ARRAY_SIZE(adc5_prescale_ratios))
199 static int adc5_hw_settle_time_from_dt(u32 value,
200 const unsigned int *hw_settle)
204 for (i = 0; i < VADC_HW_SETTLE_SAMPLES_MAX; i++) {
205 if (value == hw_settle[i])
212 static int adc5_avg_samples_from_dt(u32 value)
214 if (!is_power_of_2(value) || value > ADC5_AVG_SAMPLES_MAX)
220 static int adc5_decimation_from_dt(u32 value,
221 const unsigned int *decimation)
225 for (i = 0; i < ADC5_DECIMATION_SAMPLES_MAX; i++) {
226 if (value == decimation[i])
233 static int adc5_read_voltage_data(struct adc5_chip *adc, u16 *data)
236 u8 rslt_lsb, rslt_msb;
238 ret = adc5_read(adc, ADC5_USR_DATA0, &rslt_lsb, sizeof(rslt_lsb));
242 ret = adc5_read(adc, ADC5_USR_DATA1, &rslt_msb, sizeof(rslt_lsb));
246 *data = (rslt_msb << 8) | rslt_lsb;
248 if (*data == ADC5_USR_DATA_CHECK) {
249 dev_err(adc->dev, "Invalid data:0x%x\n", *data);
253 dev_dbg(adc->dev, "voltage raw code:0x%x\n", *data);
258 static int adc5_poll_wait_eoc(struct adc5_chip *adc)
260 unsigned int count, retry = ADC5_CONV_TIME_RETRY;
264 for (count = 0; count < retry; count++) {
265 ret = adc5_read(adc, ADC5_USR_STATUS1, &status1,
270 status1 &= ADC5_USR_STATUS1_REQ_STS_EOC_MASK;
271 if (status1 == ADC5_USR_STATUS1_EOC)
274 usleep_range(ADC5_CONV_TIME_MIN_US, ADC5_CONV_TIME_MAX_US);
280 static void adc5_update_dig_param(struct adc5_chip *adc,
281 struct adc5_channel_prop *prop, u8 *data)
283 /* Update calibration value */
284 *data &= ~ADC5_USR_DIG_PARAM_CAL_VAL;
285 *data |= (prop->cal_val << ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT);
287 /* Update calibration select */
288 *data &= ~ADC5_USR_DIG_PARAM_CAL_SEL;
289 *data |= (prop->cal_method << ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT);
291 /* Update decimation ratio select */
292 *data &= ~ADC5_USR_DIG_PARAM_DEC_RATIO_SEL;
293 *data |= (prop->decimation << ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT);
296 static int adc5_configure(struct adc5_chip *adc,
297 struct adc5_channel_prop *prop)
302 /* Read registers 0x42 through 0x46 */
303 ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
307 /* Digital param selection */
308 adc5_update_dig_param(adc, prop, &buf[0]);
310 /* Update fast average sample value */
311 buf[1] &= (u8) ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK;
312 buf[1] |= prop->avg_samples;
314 /* Select ADC channel */
315 buf[2] = prop->channel;
317 /* Select HW settle delay for channel */
318 buf[3] &= (u8) ~ADC5_USR_HW_SETTLE_DELAY_MASK;
319 buf[3] |= prop->hw_settle_time;
321 /* Select ADC enable */
322 buf[4] |= ADC5_USR_EN_CTL1_ADC_EN;
324 /* Select CONV request */
325 buf[5] |= ADC5_USR_CONV_REQ_REQ;
328 reinit_completion(&adc->complete);
330 return adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
333 static int adc7_configure(struct adc5_chip *adc,
334 struct adc5_channel_prop *prop)
337 u8 conv_req = 0, buf[4];
339 ret = adc5_masked_write(adc, ADC_APP_SID, ADC_APP_SID_MASK, prop->sid);
343 ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
347 /* Digital param selection */
348 adc5_update_dig_param(adc, prop, &buf[0]);
350 /* Update fast average sample value */
351 buf[1] &= ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK;
352 buf[1] |= prop->avg_samples;
354 /* Select ADC channel */
355 buf[2] = prop->channel;
357 /* Select HW settle delay for channel */
358 buf[3] &= ~ADC5_USR_HW_SETTLE_DELAY_MASK;
359 buf[3] |= prop->hw_settle_time;
361 /* Select CONV request */
362 conv_req = ADC5_USR_CONV_REQ_REQ;
365 reinit_completion(&adc->complete);
367 ret = adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
371 return adc5_write(adc, ADC5_USR_CONV_REQ, &conv_req, 1);
374 static int adc5_do_conversion(struct adc5_chip *adc,
375 struct adc5_channel_prop *prop,
376 struct iio_chan_spec const *chan,
377 u16 *data_volt, u16 *data_cur)
381 mutex_lock(&adc->lock);
383 ret = adc5_configure(adc, prop);
385 dev_err(adc->dev, "ADC configure failed with %d\n", ret);
390 ret = adc5_poll_wait_eoc(adc);
392 dev_err(adc->dev, "EOC bit not set\n");
396 ret = wait_for_completion_timeout(&adc->complete,
399 dev_dbg(adc->dev, "Did not get completion timeout.\n");
400 ret = adc5_poll_wait_eoc(adc);
402 dev_err(adc->dev, "EOC bit not set\n");
408 ret = adc5_read_voltage_data(adc, data_volt);
410 mutex_unlock(&adc->lock);
415 static int adc7_do_conversion(struct adc5_chip *adc,
416 struct adc5_channel_prop *prop,
417 struct iio_chan_spec const *chan,
418 u16 *data_volt, u16 *data_cur)
423 mutex_lock(&adc->lock);
425 ret = adc7_configure(adc, prop);
427 dev_err(adc->dev, "ADC configure failed with %d\n", ret);
431 /* No support for polling mode at present */
432 wait_for_completion_timeout(&adc->complete, ADC7_CONV_TIMEOUT);
434 ret = adc5_read(adc, ADC5_USR_STATUS1, &status, 1);
438 if (status & ADC5_USR_STATUS1_CONV_FAULT) {
439 dev_err(adc->dev, "Unexpected conversion fault\n");
444 ret = adc5_read_voltage_data(adc, data_volt);
447 mutex_unlock(&adc->lock);
452 static irqreturn_t adc5_isr(int irq, void *dev_id)
454 struct adc5_chip *adc = dev_id;
456 complete(&adc->complete);
461 static int adc5_of_xlate(struct iio_dev *indio_dev,
462 const struct of_phandle_args *iiospec)
464 struct adc5_chip *adc = iio_priv(indio_dev);
467 for (i = 0; i < adc->nchannels; i++)
468 if (adc->chan_props[i].channel == iiospec->args[0])
474 static int adc7_of_xlate(struct iio_dev *indio_dev,
475 const struct of_phandle_args *iiospec)
477 struct adc5_chip *adc = iio_priv(indio_dev);
480 for (i = 0; i < adc->nchannels; i++) {
481 v_channel = (adc->chan_props[i].sid << ADC_CHANNEL_OFFSET) |
482 adc->chan_props[i].channel;
483 if (v_channel == iiospec->args[0])
490 static int adc5_read_raw(struct iio_dev *indio_dev,
491 struct iio_chan_spec const *chan, int *val, int *val2,
494 struct adc5_chip *adc = iio_priv(indio_dev);
495 struct adc5_channel_prop *prop;
496 u16 adc_code_volt, adc_code_cur;
499 prop = &adc->chan_props[chan->address];
502 case IIO_CHAN_INFO_PROCESSED:
503 ret = adc5_do_conversion(adc, prop, chan,
504 &adc_code_volt, &adc_code_cur);
508 ret = qcom_adc5_hw_scale(prop->scale_fn_type,
509 &adc5_prescale_ratios[prop->prescale],
521 static int adc7_read_raw(struct iio_dev *indio_dev,
522 struct iio_chan_spec const *chan, int *val, int *val2,
525 struct adc5_chip *adc = iio_priv(indio_dev);
526 struct adc5_channel_prop *prop;
527 u16 adc_code_volt, adc_code_cur;
530 prop = &adc->chan_props[chan->address];
533 case IIO_CHAN_INFO_PROCESSED:
534 ret = adc7_do_conversion(adc, prop, chan,
535 &adc_code_volt, &adc_code_cur);
539 ret = qcom_adc5_hw_scale(prop->scale_fn_type,
540 &adc5_prescale_ratios[prop->prescale],
553 static const struct iio_info adc5_info = {
554 .read_raw = adc5_read_raw,
555 .of_xlate = adc5_of_xlate,
558 static const struct iio_info adc7_info = {
559 .read_raw = adc7_read_raw,
560 .of_xlate = adc7_of_xlate,
563 struct adc5_channels {
564 const char *datasheet_name;
565 unsigned int prescale_index;
566 enum iio_chan_type type;
568 enum vadc_scale_fn_type scale_fn_type;
571 /* In these definitions, _pre refers to an index into adc5_prescale_ratios. */
572 #define ADC5_CHAN(_dname, _type, _mask, _pre, _scale) \
574 .datasheet_name = _dname, \
575 .prescale_index = _pre, \
577 .info_mask = _mask, \
578 .scale_fn_type = _scale, \
581 #define ADC5_CHAN_TEMP(_dname, _pre, _scale) \
582 ADC5_CHAN(_dname, IIO_TEMP, \
583 BIT(IIO_CHAN_INFO_PROCESSED), \
586 #define ADC5_CHAN_VOLT(_dname, _pre, _scale) \
587 ADC5_CHAN(_dname, IIO_VOLTAGE, \
588 BIT(IIO_CHAN_INFO_PROCESSED), \
591 static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = {
592 [ADC5_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
593 SCALE_HW_CALIB_DEFAULT)
594 [ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
595 SCALE_HW_CALIB_DEFAULT)
596 [ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
597 SCALE_HW_CALIB_DEFAULT)
598 [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1,
599 SCALE_HW_CALIB_DEFAULT)
600 [ADC5_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
601 SCALE_HW_CALIB_PMIC_THERM)
602 [ADC5_USB_IN_I] = ADC5_CHAN_VOLT("usb_in_i_uv", 0,
603 SCALE_HW_CALIB_DEFAULT)
604 [ADC5_USB_IN_V_16] = ADC5_CHAN_VOLT("usb_in_v_div_16", 8,
605 SCALE_HW_CALIB_DEFAULT)
606 [ADC5_CHG_TEMP] = ADC5_CHAN_TEMP("chg_temp", 0,
607 SCALE_HW_CALIB_PM5_CHG_TEMP)
608 /* Charger prescales SBUx and MID_CHG to fit within 1.8V upper unit */
609 [ADC5_SBUx] = ADC5_CHAN_VOLT("chg_sbux", 1,
610 SCALE_HW_CALIB_DEFAULT)
611 [ADC5_MID_CHG_DIV6] = ADC5_CHAN_VOLT("chg_mid_chg", 3,
612 SCALE_HW_CALIB_DEFAULT)
613 [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm", 0,
614 SCALE_HW_CALIB_XOTHERM)
615 [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0,
616 SCALE_HW_CALIB_THERM_100K_PULLUP)
617 [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0,
618 SCALE_HW_CALIB_THERM_100K_PULLUP)
619 [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0,
620 SCALE_HW_CALIB_THERM_100K_PULLUP)
621 [ADC5_AMUX_THM2] = ADC5_CHAN_TEMP("amux_thm2", 0,
622 SCALE_HW_CALIB_PM5_SMB_TEMP)
625 static const struct adc5_channels adc7_chans_pmic[ADC5_MAX_CHANNEL] = {
626 [ADC7_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
627 SCALE_HW_CALIB_DEFAULT)
628 [ADC7_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
629 SCALE_HW_CALIB_DEFAULT)
630 [ADC7_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
631 SCALE_HW_CALIB_DEFAULT)
632 [ADC7_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 3,
633 SCALE_HW_CALIB_DEFAULT)
634 [ADC7_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
635 SCALE_HW_CALIB_PMIC_THERM_PM7)
636 [ADC7_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_pu2", 0,
637 SCALE_HW_CALIB_THERM_100K_PU_PM7)
638 [ADC7_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_pu2", 0,
639 SCALE_HW_CALIB_THERM_100K_PU_PM7)
640 [ADC7_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_pu2", 0,
641 SCALE_HW_CALIB_THERM_100K_PU_PM7)
642 [ADC7_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_pu2", 0,
643 SCALE_HW_CALIB_THERM_100K_PU_PM7)
644 [ADC7_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_pu2", 0,
645 SCALE_HW_CALIB_THERM_100K_PU_PM7)
646 [ADC7_AMUX_THM6_100K_PU] = ADC5_CHAN_TEMP("amux_thm6_pu2", 0,
647 SCALE_HW_CALIB_THERM_100K_PU_PM7)
648 [ADC7_GPIO1_100K_PU] = ADC5_CHAN_TEMP("gpio1_pu2", 0,
649 SCALE_HW_CALIB_THERM_100K_PU_PM7)
650 [ADC7_GPIO2_100K_PU] = ADC5_CHAN_TEMP("gpio2_pu2", 0,
651 SCALE_HW_CALIB_THERM_100K_PU_PM7)
652 [ADC7_GPIO3_100K_PU] = ADC5_CHAN_TEMP("gpio3_pu2", 0,
653 SCALE_HW_CALIB_THERM_100K_PU_PM7)
654 [ADC7_GPIO4_100K_PU] = ADC5_CHAN_TEMP("gpio4_pu2", 0,
655 SCALE_HW_CALIB_THERM_100K_PU_PM7)
658 static const struct adc5_channels adc5_chans_rev2[ADC5_MAX_CHANNEL] = {
659 [ADC5_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
660 SCALE_HW_CALIB_DEFAULT)
661 [ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
662 SCALE_HW_CALIB_DEFAULT)
663 [ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
664 SCALE_HW_CALIB_DEFAULT)
665 [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1,
666 SCALE_HW_CALIB_DEFAULT)
667 [ADC5_VCOIN] = ADC5_CHAN_VOLT("vcoin", 1,
668 SCALE_HW_CALIB_DEFAULT)
669 [ADC5_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
670 SCALE_HW_CALIB_PMIC_THERM)
671 [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0,
672 SCALE_HW_CALIB_THERM_100K_PULLUP)
673 [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0,
674 SCALE_HW_CALIB_THERM_100K_PULLUP)
675 [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0,
676 SCALE_HW_CALIB_THERM_100K_PULLUP)
677 [ADC5_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_100k_pu", 0,
678 SCALE_HW_CALIB_THERM_100K_PULLUP)
679 [ADC5_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_100k_pu", 0,
680 SCALE_HW_CALIB_THERM_100K_PULLUP)
681 [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm_100k_pu", 0,
682 SCALE_HW_CALIB_THERM_100K_PULLUP)
685 static int adc5_get_dt_channel_data(struct adc5_chip *adc,
686 struct adc5_channel_prop *prop,
687 struct device_node *node,
688 const struct adc5_data *data)
690 const char *name = node->name, *channel_name;
691 u32 chan, value, varr[2];
694 struct device *dev = adc->dev;
696 ret = of_property_read_u32(node, "reg", &chan);
698 dev_err(dev, "invalid channel number %s\n", name);
702 /* Value read from "reg" is virtual channel number */
704 /* virtual channel number = sid << 8 | channel number */
706 if (adc->data->info == &adc7_info) {
707 sid = chan >> ADC_CHANNEL_OFFSET;
708 chan = chan & ADC_CHANNEL_MASK;
711 if (chan > ADC5_PARALLEL_ISENSE_VBAT_IDATA ||
712 !data->adc_chans[chan].datasheet_name) {
713 dev_err(dev, "%s invalid channel number %d\n", name, chan);
717 /* the channel has DT description */
718 prop->channel = chan;
721 channel_name = of_get_property(node,
722 "label", NULL) ? : node->name;
724 dev_err(dev, "Invalid channel name\n");
727 prop->datasheet_name = channel_name;
729 ret = of_property_read_u32(node, "qcom,decimation", &value);
731 ret = adc5_decimation_from_dt(value, data->decimation);
733 dev_err(dev, "%02x invalid decimation %d\n",
737 prop->decimation = ret;
739 prop->decimation = ADC5_DECIMATION_DEFAULT;
742 ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2);
744 ret = adc5_prescaling_from_dt(varr[0], varr[1]);
746 dev_err(dev, "%02x invalid pre-scaling <%d %d>\n",
747 chan, varr[0], varr[1]);
750 prop->prescale = ret;
753 adc->data->adc_chans[prop->channel].prescale_index;
756 ret = of_property_read_u32(node, "qcom,hw-settle-time", &value);
760 ret = adc5_read(adc, ADC5_USR_REVISION1, dig_version,
761 sizeof(dig_version));
763 dev_err(dev, "Invalid dig version read %d\n", ret);
767 dev_dbg(dev, "dig_ver:minor:%d, major:%d\n", dig_version[0],
769 /* Digital controller >= 5.3 have hw_settle_2 option */
770 if ((dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR &&
771 dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR) ||
772 adc->data->info == &adc7_info)
773 ret = adc5_hw_settle_time_from_dt(value,
776 ret = adc5_hw_settle_time_from_dt(value,
780 dev_err(dev, "%02x invalid hw-settle-time %d us\n",
784 prop->hw_settle_time = ret;
786 prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
789 ret = of_property_read_u32(node, "qcom,avg-samples", &value);
791 ret = adc5_avg_samples_from_dt(value);
793 dev_err(dev, "%02x invalid avg-samples %d\n",
797 prop->avg_samples = ret;
799 prop->avg_samples = VADC_DEF_AVG_SAMPLES;
802 if (of_property_read_bool(node, "qcom,ratiometric"))
803 prop->cal_method = ADC5_RATIOMETRIC_CAL;
805 prop->cal_method = ADC5_ABSOLUTE_CAL;
808 * Default to using timer calibration. Using a fresh calibration value
809 * for every conversion will increase the overall time for a request.
811 prop->cal_val = ADC5_TIMER_CAL;
813 dev_dbg(dev, "%02x name %s\n", chan, name);
818 static const struct adc5_data adc5_data_pmic = {
819 .full_scale_code_volt = 0x70e4,
820 .full_scale_code_cur = 0x2710,
821 .adc_chans = adc5_chans_pmic,
823 .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
825 .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
826 {15, 100, 200, 300, 400, 500, 600, 700,
827 800, 900, 1, 2, 4, 6, 8, 10},
828 .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
829 {15, 100, 200, 300, 400, 500, 600, 700,
830 1, 2, 4, 8, 16, 32, 64, 128},
833 static const struct adc5_data adc7_data_pmic = {
834 .full_scale_code_volt = 0x70e4,
835 .adc_chans = adc7_chans_pmic,
837 .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
839 .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
840 {15, 100, 200, 300, 400, 500, 600, 700,
841 1000, 2000, 4000, 8000, 16000, 32000,
845 static const struct adc5_data adc5_data_pmic_rev2 = {
846 .full_scale_code_volt = 0x4000,
847 .full_scale_code_cur = 0x1800,
848 .adc_chans = adc5_chans_rev2,
850 .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
852 .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
853 {0, 100, 200, 300, 400, 500, 600, 700,
854 800, 900, 1, 2, 4, 6, 8, 10},
855 .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
856 {15, 100, 200, 300, 400, 500, 600, 700,
857 1, 2, 4, 8, 16, 32, 64, 128},
860 static const struct of_device_id adc5_match_table[] = {
862 .compatible = "qcom,spmi-adc5",
863 .data = &adc5_data_pmic,
866 .compatible = "qcom,spmi-adc7",
867 .data = &adc7_data_pmic,
870 .compatible = "qcom,spmi-adc-rev2",
871 .data = &adc5_data_pmic_rev2,
875 MODULE_DEVICE_TABLE(of, adc5_match_table);
877 static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node)
879 const struct adc5_channels *adc_chan;
880 struct iio_chan_spec *iio_chan;
881 struct adc5_channel_prop prop, *chan_props;
882 struct device_node *child;
883 unsigned int index = 0;
884 const struct of_device_id *id;
885 const struct adc5_data *data;
888 adc->nchannels = of_get_available_child_count(node);
892 adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels,
893 sizeof(*adc->iio_chans), GFP_KERNEL);
897 adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels,
898 sizeof(*adc->chan_props), GFP_KERNEL);
899 if (!adc->chan_props)
902 chan_props = adc->chan_props;
903 iio_chan = adc->iio_chans;
904 id = of_match_node(adc5_match_table, node);
908 data = &adc5_data_pmic;
911 for_each_available_child_of_node(node, child) {
912 ret = adc5_get_dt_channel_data(adc, &prop, child, data);
919 data->adc_chans[prop.channel].scale_fn_type;
921 adc_chan = &data->adc_chans[prop.channel];
923 iio_chan->channel = prop.channel;
924 iio_chan->datasheet_name = prop.datasheet_name;
925 iio_chan->extend_name = prop.datasheet_name;
926 iio_chan->info_mask_separate = adc_chan->info_mask;
927 iio_chan->type = adc_chan->type;
928 iio_chan->address = index;
937 static int adc5_probe(struct platform_device *pdev)
939 struct device_node *node = pdev->dev.of_node;
940 struct device *dev = &pdev->dev;
941 struct iio_dev *indio_dev;
942 struct adc5_chip *adc;
943 struct regmap *regmap;
947 regmap = dev_get_regmap(dev->parent, NULL);
951 ret = of_property_read_u32(node, "reg", ®);
955 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
959 adc = iio_priv(indio_dev);
960 adc->regmap = regmap;
964 init_completion(&adc->complete);
965 mutex_init(&adc->lock);
967 ret = adc5_get_dt_data(adc, node);
969 dev_err(dev, "adc get dt data failed\n");
973 irq_eoc = platform_get_irq(pdev, 0);
975 if (irq_eoc == -EPROBE_DEFER || irq_eoc == -EINVAL)
977 adc->poll_eoc = true;
979 ret = devm_request_irq(dev, irq_eoc, adc5_isr, 0,
985 indio_dev->name = pdev->name;
986 indio_dev->modes = INDIO_DIRECT_MODE;
987 indio_dev->info = adc->data->info;
988 indio_dev->channels = adc->iio_chans;
989 indio_dev->num_channels = adc->nchannels;
991 return devm_iio_device_register(dev, indio_dev);
994 static struct platform_driver adc5_driver = {
996 .name = "qcom-spmi-adc5.c",
997 .of_match_table = adc5_match_table,
1001 module_platform_driver(adc5_driver);
1003 MODULE_ALIAS("platform:qcom-spmi-adc5");
1004 MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 ADC driver");
1005 MODULE_LICENSE("GPL v2");