drivers/iio/adc/ingenic-adc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ADC driver for the Ingenic JZ47xx SoCs
   4  * Copyright (c) 2019 Artur Rojek <contact@artur-rojek.eu>
   5  *
   6  * based on drivers/mfd/jz4740-adc.c
   7  */
   8
   9 #include <dt-bindings/iio/adc/ingenic,adc.h>
  10 #include <linux/clk.h>
  11 #include <linux/iio/buffer.h>
  12 #include <linux/iio/iio.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/mod_devicetable.h>
  19 #include <linux/mutex.h>
  20 #include <linux/platform_device.h>
  21
  22 #define JZ_ADC_REG_ENABLE               0x00
  23 #define JZ_ADC_REG_CFG                  0x04
  24 #define JZ_ADC_REG_CTRL                 0x08
  25 #define JZ_ADC_REG_STATUS               0x0c
  26 #define JZ_ADC_REG_ADSAME               0x10
  27 #define JZ_ADC_REG_ADWAIT               0x14
  28 #define JZ_ADC_REG_ADTCH                0x18
  29 #define JZ_ADC_REG_ADBDAT               0x1c
  30 #define JZ_ADC_REG_ADSDAT               0x20
  31 #define JZ_ADC_REG_ADCMD                0x24
  32 #define JZ_ADC_REG_ADCLK                0x28
  33
  34 #define JZ_ADC_REG_ENABLE_PD            BIT(7)
  35 #define JZ_ADC_REG_CFG_AUX_MD           (BIT(0) | BIT(1))
  36 #define JZ_ADC_REG_CFG_BAT_MD           BIT(4)
  37 #define JZ_ADC_REG_CFG_SAMPLE_NUM(n)    ((n) << 10)
  38 #define JZ_ADC_REG_CFG_PULL_UP(n)       ((n) << 16)
  39 #define JZ_ADC_REG_CFG_CMD_SEL          BIT(22)
  40 #define JZ_ADC_REG_CFG_TOUCH_OPS_MASK   (BIT(31) | GENMASK(23, 10))
  41 #define JZ_ADC_REG_ADCLK_CLKDIV_LSB     0
  42 #define JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB    16
  43 #define JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB     8
  44 #define JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB       16
  45
  46 #define JZ_ADC_REG_ADCMD_YNADC          BIT(7)
  47 #define JZ_ADC_REG_ADCMD_YPADC          BIT(8)
  48 #define JZ_ADC_REG_ADCMD_XNADC          BIT(9)
  49 #define JZ_ADC_REG_ADCMD_XPADC          BIT(10)
  50 #define JZ_ADC_REG_ADCMD_VREFPYP        BIT(11)
  51 #define JZ_ADC_REG_ADCMD_VREFPXP        BIT(12)
  52 #define JZ_ADC_REG_ADCMD_VREFPXN        BIT(13)
  53 #define JZ_ADC_REG_ADCMD_VREFPAUX       BIT(14)
  54 #define JZ_ADC_REG_ADCMD_VREFPVDD33     BIT(15)
  55 #define JZ_ADC_REG_ADCMD_VREFNYN        BIT(16)
  56 #define JZ_ADC_REG_ADCMD_VREFNXP        BIT(17)
  57 #define JZ_ADC_REG_ADCMD_VREFNXN        BIT(18)
  58 #define JZ_ADC_REG_ADCMD_VREFAUX        BIT(19)
  59 #define JZ_ADC_REG_ADCMD_YNGRU          BIT(20)
  60 #define JZ_ADC_REG_ADCMD_XNGRU          BIT(21)
  61 #define JZ_ADC_REG_ADCMD_XPGRU          BIT(22)
  62 #define JZ_ADC_REG_ADCMD_YPSUP          BIT(23)
  63 #define JZ_ADC_REG_ADCMD_XNSUP          BIT(24)
  64 #define JZ_ADC_REG_ADCMD_XPSUP          BIT(25)
  65
  66 #define JZ_ADC_AUX_VREF                         3300
  67 #define JZ_ADC_AUX_VREF_BITS                    12
  68 #define JZ_ADC_BATTERY_LOW_VREF                 2500
  69 #define JZ_ADC_BATTERY_LOW_VREF_BITS            12
  70 #define JZ4725B_ADC_BATTERY_HIGH_VREF           7500
  71 #define JZ4725B_ADC_BATTERY_HIGH_VREF_BITS      10
  72 #define JZ4740_ADC_BATTERY_HIGH_VREF            (7500 * 0.986)
  73 #define JZ4740_ADC_BATTERY_HIGH_VREF_BITS       12
  74 #define JZ4770_ADC_BATTERY_VREF                 6600
  75 #define JZ4770_ADC_BATTERY_VREF_BITS            12
  76
  77 #define JZ_ADC_IRQ_AUX                  BIT(0)
  78 #define JZ_ADC_IRQ_BATTERY              BIT(1)
  79 #define JZ_ADC_IRQ_TOUCH                BIT(2)
  80 #define JZ_ADC_IRQ_PEN_DOWN             BIT(3)
  81 #define JZ_ADC_IRQ_PEN_UP               BIT(4)
  82 #define JZ_ADC_IRQ_PEN_DOWN_SLEEP       BIT(5)
  83 #define JZ_ADC_IRQ_SLEEP                BIT(7)
  84
  85 struct ingenic_adc;
  86
  87 struct ingenic_adc_soc_data {
  88         unsigned int battery_high_vref;
  89         unsigned int battery_high_vref_bits;
  90         const int *battery_raw_avail;
  91         size_t battery_raw_avail_size;
  92         const int *battery_scale_avail;
  93         size_t battery_scale_avail_size;
  94         unsigned int battery_vref_mode: 1;
  95         unsigned int has_aux2: 1;
  96         const struct iio_chan_spec *channels;
  97         unsigned int num_channels;
  98         int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
  99 };
 100
 101 struct ingenic_adc {
 102         void __iomem *base;
 103         struct clk *clk;
 104         struct mutex lock;
 105         struct mutex aux_lock;
 106         const struct ingenic_adc_soc_data *soc_data;
 107         bool low_vref_mode;
 108 };
 109
 110 static void ingenic_adc_set_adcmd(struct iio_dev *iio_dev, unsigned long mask)
 111 {
 112         struct ingenic_adc *adc = iio_priv(iio_dev);
 113
 114         mutex_lock(&adc->lock);
 115
 116         /* Init ADCMD */
 117         readl(adc->base + JZ_ADC_REG_ADCMD);
 118
 119         if (mask & 0x3) {
 120                 /* Second channel (INGENIC_ADC_TOUCH_YP): sample YP vs. GND */
 121                 writel(JZ_ADC_REG_ADCMD_XNGRU
 122                        | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
 123                        | JZ_ADC_REG_ADCMD_YPADC,
 124                        adc->base + JZ_ADC_REG_ADCMD);
 125
 126                 /* First channel (INGENIC_ADC_TOUCH_XP): sample XP vs. GND */
 127                 writel(JZ_ADC_REG_ADCMD_YNGRU
 128                        | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
 129                        | JZ_ADC_REG_ADCMD_XPADC,
 130                        adc->base + JZ_ADC_REG_ADCMD);
 131         }
 132
 133         if (mask & 0xc) {
 134                 /* Fourth channel (INGENIC_ADC_TOUCH_YN): sample YN vs. GND */
 135                 writel(JZ_ADC_REG_ADCMD_XNGRU
 136                        | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
 137                        | JZ_ADC_REG_ADCMD_YNADC,
 138                        adc->base + JZ_ADC_REG_ADCMD);
 139
 140                 /* Third channel (INGENIC_ADC_TOUCH_XN): sample XN vs. GND */
 141                 writel(JZ_ADC_REG_ADCMD_YNGRU
 142                        | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
 143                        | JZ_ADC_REG_ADCMD_XNADC,
 144                        adc->base + JZ_ADC_REG_ADCMD);
 145         }
 146
 147         if (mask & 0x30) {
 148                 /* Sixth channel (INGENIC_ADC_TOUCH_YD): sample YP vs. YN */
 149                 writel(JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
 150                        | JZ_ADC_REG_ADCMD_YPADC,
 151                        adc->base + JZ_ADC_REG_ADCMD);
 152
 153                 /* Fifth channel (INGENIC_ADC_TOUCH_XD): sample XP vs. XN */
 154                 writel(JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
 155                        | JZ_ADC_REG_ADCMD_XPADC,
 156                        adc->base + JZ_ADC_REG_ADCMD);
 157         }
 158
 159         /* We're done */
 160         writel(0, adc->base + JZ_ADC_REG_ADCMD);
 161
 162         mutex_unlock(&adc->lock);
 163 }
 164
 165 static void ingenic_adc_set_config(struct ingenic_adc *adc,
 166                                    uint32_t mask,
 167                                    uint32_t val)
 168 {
 169         uint32_t cfg;
 170
 171         mutex_lock(&adc->lock);
 172
 173         cfg = readl(adc->base + JZ_ADC_REG_CFG) & ~mask;
 174         cfg |= val;
 175         writel(cfg, adc->base + JZ_ADC_REG_CFG);
 176
 177         mutex_unlock(&adc->lock);
 178 }
 179
 180 static void ingenic_adc_enable(struct ingenic_adc *adc,
 181                                int engine,
 182                                bool enabled)
 183 {
 184         u8 val;
 185
 186         mutex_lock(&adc->lock);
 187         val = readb(adc->base + JZ_ADC_REG_ENABLE);
 188
 189         if (enabled)
 190                 val |= BIT(engine);
 191         else
 192                 val &= ~BIT(engine);
 193
 194         writeb(val, adc->base + JZ_ADC_REG_ENABLE);
 195         mutex_unlock(&adc->lock);
 196 }
 197
 198 static int ingenic_adc_capture(struct ingenic_adc *adc,
 199                                int engine)
 200 {
 201         u8 val;
 202         int ret;
 203
 204         ingenic_adc_enable(adc, engine, true);
 205         ret = readb_poll_timeout(adc->base + JZ_ADC_REG_ENABLE, val,
 206                                  !(val & BIT(engine)), 250, 1000);
 207         if (ret)
 208                 ingenic_adc_enable(adc, engine, false);
 209
 210         return ret;
 211 }
 212
 213 static int ingenic_adc_write_raw(struct iio_dev *iio_dev,
 214                                  struct iio_chan_spec const *chan,
 215                                  int val,
 216                                  int val2,
 217                                  long m)
 218 {
 219         struct ingenic_adc *adc = iio_priv(iio_dev);
 220         struct device *dev = iio_dev->dev.parent;
 221         int ret;
 222
 223         switch (m) {
 224         case IIO_CHAN_INFO_SCALE:
 225                 switch (chan->channel) {
 226                 case INGENIC_ADC_BATTERY:
 227                         if (!adc->soc_data->battery_vref_mode)
 228                                 return -EINVAL;
 229
 230                         ret = clk_enable(adc->clk);
 231                         if (ret) {
 232                                 dev_err(dev, "Failed to enable clock: %d\n",
 233                                         ret);
 234                                 return ret;
 235                         }
 236
 237                         if (val > JZ_ADC_BATTERY_LOW_VREF) {
 238                                 ingenic_adc_set_config(adc,
 239                                                        JZ_ADC_REG_CFG_BAT_MD,
 240                                                        0);
 241                                 adc->low_vref_mode = false;
 242                         } else {
 243                                 ingenic_adc_set_config(adc,
 244                                                        JZ_ADC_REG_CFG_BAT_MD,
 245                                                        JZ_ADC_REG_CFG_BAT_MD);
 246                                 adc->low_vref_mode = true;
 247                         }
 248
 249                         clk_disable(adc->clk);
 250
 251                         return 0;
 252                 default:
 253                         return -EINVAL;
 254                 }
 255         default:
 256                 return -EINVAL;
 257         }
 258 }
 259
 260 static const int jz4725b_adc_battery_raw_avail[] = {
 261         0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
 262 };
 263
 264 static const int jz4725b_adc_battery_scale_avail[] = {
 265         JZ4725B_ADC_BATTERY_HIGH_VREF, JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
 266         JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
 267 };
 268
 269 static const int jz4740_adc_battery_raw_avail[] = {
 270         0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
 271 };
 272
 273 static const int jz4740_adc_battery_scale_avail[] = {
 274         JZ4740_ADC_BATTERY_HIGH_VREF, JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
 275         JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
 276 };
 277
 278 static const int jz4770_adc_battery_raw_avail[] = {
 279         0, 1, (1 << JZ4770_ADC_BATTERY_VREF_BITS) - 1,
 280 };
 281
 282 static const int jz4770_adc_battery_scale_avail[] = {
 283         JZ4770_ADC_BATTERY_VREF, JZ4770_ADC_BATTERY_VREF_BITS,
 284 };
 285
 286 static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
 287 {
 288         struct clk *parent_clk;
 289         unsigned long parent_rate, rate;
 290         unsigned int div_main, div_10us;
 291
 292         parent_clk = clk_get_parent(adc->clk);
 293         if (!parent_clk) {
 294                 dev_err(dev, "ADC clock has no parent\n");
 295                 return -ENODEV;
 296         }
 297         parent_rate = clk_get_rate(parent_clk);
 298
 299         /*
 300          * The JZ4725B ADC works at 500 kHz to 8 MHz.
 301          * We pick the highest rate possible.
 302          * In practice we typically get 6 MHz, half of the 12 MHz EXT clock.
 303          */
 304         div_main = DIV_ROUND_UP(parent_rate, 8000000);
 305         div_main = clamp(div_main, 1u, 64u);
 306         rate = parent_rate / div_main;
 307         if (rate < 500000 || rate > 8000000) {
 308                 dev_err(dev, "No valid divider for ADC main clock\n");
 309                 return -EINVAL;
 310         }
 311
 312         /* We also need a divider that produces a 10us clock. */
 313         div_10us = DIV_ROUND_UP(rate, 100000);
 314
 315         writel(((div_10us - 1) << JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB) |
 316                (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
 317                adc->base + JZ_ADC_REG_ADCLK);
 318
 319         return 0;
 320 }
 321
 322 static int jz4770_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
 323 {
 324         struct clk *parent_clk;
 325         unsigned long parent_rate, rate;
 326         unsigned int div_main, div_ms, div_10us;
 327
 328         parent_clk = clk_get_parent(adc->clk);
 329         if (!parent_clk) {
 330                 dev_err(dev, "ADC clock has no parent\n");
 331                 return -ENODEV;
 332         }
 333         parent_rate = clk_get_rate(parent_clk);
 334
 335         /*
 336          * The JZ4770 ADC works at 20 kHz to 200 kHz.
 337          * We pick the highest rate possible.
 338          */
 339         div_main = DIV_ROUND_UP(parent_rate, 200000);
 340         div_main = clamp(div_main, 1u, 256u);
 341         rate = parent_rate / div_main;
 342         if (rate < 20000 || rate > 200000) {
 343                 dev_err(dev, "No valid divider for ADC main clock\n");
 344                 return -EINVAL;
 345         }
 346
 347         /* We also need a divider that produces a 10us clock. */
 348         div_10us = DIV_ROUND_UP(rate, 10000);
 349         /* And another, which produces a 1ms clock. */
 350         div_ms = DIV_ROUND_UP(rate, 1000);
 351
 352         writel(((div_ms - 1) << JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB) |
 353                ((div_10us - 1) << JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB) |
 354                (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
 355                adc->base + JZ_ADC_REG_ADCLK);
 356
 357         return 0;
 358 }
 359
 360 static const struct iio_chan_spec jz4740_channels[] = {
 361         {
 362                 .extend_name = "aux",
 363                 .type = IIO_VOLTAGE,
 364                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 365                                       BIT(IIO_CHAN_INFO_SCALE),
 366                 .indexed = 1,
 367                 .channel = INGENIC_ADC_AUX,
 368                 .scan_index = -1,
 369         },
 370         {
 371                 .extend_name = "battery",
 372                 .type = IIO_VOLTAGE,
 373                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 374                                       BIT(IIO_CHAN_INFO_SCALE),
 375                 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
 376                                                 BIT(IIO_CHAN_INFO_SCALE),
 377                 .indexed = 1,
 378                 .channel = INGENIC_ADC_BATTERY,
 379                 .scan_index = -1,
 380         },
 381 };
 382
 383 static const struct iio_chan_spec jz4770_channels[] = {
 384         {
 385                 .type = IIO_VOLTAGE,
 386                 .indexed = 1,
 387                 .channel = INGENIC_ADC_TOUCH_XP,
 388                 .scan_index = 0,
 389                 .scan_type = {
 390                         .sign = 'u',
 391                         .realbits = 12,
 392                         .storagebits = 16,
 393                 },
 394         },
 395         {
 396                 .type = IIO_VOLTAGE,
 397                 .indexed = 1,
 398                 .channel = INGENIC_ADC_TOUCH_YP,
 399                 .scan_index = 1,
 400                 .scan_type = {
 401                         .sign = 'u',
 402                         .realbits = 12,
 403                         .storagebits = 16,
 404                 },
 405         },
 406         {
 407                 .type = IIO_VOLTAGE,
 408                 .indexed = 1,
 409                 .channel = INGENIC_ADC_TOUCH_XN,
 410                 .scan_index = 2,
 411                 .scan_type = {
 412                         .sign = 'u',
 413                         .realbits = 12,
 414                         .storagebits = 16,
 415                 },
 416         },
 417         {
 418                 .type = IIO_VOLTAGE,
 419                 .indexed = 1,
 420                 .channel = INGENIC_ADC_TOUCH_YN,
 421                 .scan_index = 3,
 422                 .scan_type = {
 423                         .sign = 'u',
 424                         .realbits = 12,
 425                         .storagebits = 16,
 426                 },
 427         },
 428         {
 429                 .type = IIO_VOLTAGE,
 430                 .indexed = 1,
 431                 .channel = INGENIC_ADC_TOUCH_XD,
 432                 .scan_index = 4,
 433                 .scan_type = {
 434                         .sign = 'u',
 435                         .realbits = 12,
 436                         .storagebits = 16,
 437                 },
 438         },
 439         {
 440                 .type = IIO_VOLTAGE,
 441                 .indexed = 1,
 442                 .channel = INGENIC_ADC_TOUCH_YD,
 443                 .scan_index = 5,
 444                 .scan_type = {
 445                         .sign = 'u',
 446                         .realbits = 12,
 447                         .storagebits = 16,
 448                 },
 449         },
 450         {
 451                 .extend_name = "aux",
 452                 .type = IIO_VOLTAGE,
 453                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 454                                       BIT(IIO_CHAN_INFO_SCALE),
 455                 .indexed = 1,
 456                 .channel = INGENIC_ADC_AUX,
 457                 .scan_index = -1,
 458         },
 459         {
 460                 .extend_name = "battery",
 461                 .type = IIO_VOLTAGE,
 462                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 463                                       BIT(IIO_CHAN_INFO_SCALE),
 464                 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
 465                                                 BIT(IIO_CHAN_INFO_SCALE),
 466                 .indexed = 1,
 467                 .channel = INGENIC_ADC_BATTERY,
 468                 .scan_index = -1,
 469         },
 470         {
 471                 .extend_name = "aux2",
 472                 .type = IIO_VOLTAGE,
 473                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 474                                       BIT(IIO_CHAN_INFO_SCALE),
 475                 .indexed = 1,
 476                 .channel = INGENIC_ADC_AUX2,
 477                 .scan_index = -1,
 478         },
 479 };
 480
 481 static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = {
 482         .battery_high_vref = JZ4725B_ADC_BATTERY_HIGH_VREF,
 483         .battery_high_vref_bits = JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
 484         .battery_raw_avail = jz4725b_adc_battery_raw_avail,
 485         .battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail),
 486         .battery_scale_avail = jz4725b_adc_battery_scale_avail,
 487         .battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail),
 488         .battery_vref_mode = true,
 489         .has_aux2 = false,
 490         .channels = jz4740_channels,
 491         .num_channels = ARRAY_SIZE(jz4740_channels),
 492         .init_clk_div = jz4725b_adc_init_clk_div,
 493 };
 494
 495 static const struct ingenic_adc_soc_data jz4740_adc_soc_data = {
 496         .battery_high_vref = JZ4740_ADC_BATTERY_HIGH_VREF,
 497         .battery_high_vref_bits = JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
 498         .battery_raw_avail = jz4740_adc_battery_raw_avail,
 499         .battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail),
 500         .battery_scale_avail = jz4740_adc_battery_scale_avail,
 501         .battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail),
 502         .battery_vref_mode = true,
 503         .has_aux2 = false,
 504         .channels = jz4740_channels,
 505         .num_channels = ARRAY_SIZE(jz4740_channels),
 506         .init_clk_div = NULL, /* no ADCLK register on JZ4740 */
 507 };
 508
 509 static const struct ingenic_adc_soc_data jz4770_adc_soc_data = {
 510         .battery_high_vref = JZ4770_ADC_BATTERY_VREF,
 511         .battery_high_vref_bits = JZ4770_ADC_BATTERY_VREF_BITS,
 512         .battery_raw_avail = jz4770_adc_battery_raw_avail,
 513         .battery_raw_avail_size = ARRAY_SIZE(jz4770_adc_battery_raw_avail),
 514         .battery_scale_avail = jz4770_adc_battery_scale_avail,
 515         .battery_scale_avail_size = ARRAY_SIZE(jz4770_adc_battery_scale_avail),
 516         .battery_vref_mode = false,
 517         .has_aux2 = true,
 518         .channels = jz4770_channels,
 519         .num_channels = ARRAY_SIZE(jz4770_channels),
 520         .init_clk_div = jz4770_adc_init_clk_div,
 521 };
 522
 523 static int ingenic_adc_read_avail(struct iio_dev *iio_dev,
 524                                   struct iio_chan_spec const *chan,
 525                                   const int **vals,
 526                                   int *type,
 527                                   int *length,
 528                                   long m)
 529 {
 530         struct ingenic_adc *adc = iio_priv(iio_dev);
 531
 532         switch (m) {
 533         case IIO_CHAN_INFO_RAW:
 534                 *type = IIO_VAL_INT;
 535                 *length = adc->soc_data->battery_raw_avail_size;
 536                 *vals = adc->soc_data->battery_raw_avail;
 537                 return IIO_AVAIL_RANGE;
 538         case IIO_CHAN_INFO_SCALE:
 539                 *type = IIO_VAL_FRACTIONAL_LOG2;
 540                 *length = adc->soc_data->battery_scale_avail_size;
 541                 *vals = adc->soc_data->battery_scale_avail;
 542                 return IIO_AVAIL_LIST;
 543         default:
 544                 return -EINVAL;
 545         };
 546 }
 547
 548 static int ingenic_adc_read_chan_info_raw(struct iio_dev *iio_dev,
 549                                           struct iio_chan_spec const *chan,
 550                                           int *val)
 551 {
 552         int bit, ret, engine = (chan->channel == INGENIC_ADC_BATTERY);
 553         struct ingenic_adc *adc = iio_priv(iio_dev);
 554
 555         ret = clk_enable(adc->clk);
 556         if (ret) {
 557                 dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
 558                         ret);
 559                 return ret;
 560         }
 561
 562         /* We cannot sample AUX/AUX2 in parallel. */
 563         mutex_lock(&adc->aux_lock);
 564         if (adc->soc_data->has_aux2 && engine == 0) {
 565                 bit = BIT(chan->channel == INGENIC_ADC_AUX2);
 566                 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_AUX_MD, bit);
 567         }
 568
 569         ret = ingenic_adc_capture(adc, engine);
 570         if (ret)
 571                 goto out;
 572
 573         switch (chan->channel) {
 574         case INGENIC_ADC_AUX:
 575         case INGENIC_ADC_AUX2:
 576                 *val = readw(adc->base + JZ_ADC_REG_ADSDAT);
 577                 break;
 578         case INGENIC_ADC_BATTERY:
 579                 *val = readw(adc->base + JZ_ADC_REG_ADBDAT);
 580                 break;
 581         }
 582
 583         ret = IIO_VAL_INT;
 584 out:
 585         mutex_unlock(&adc->aux_lock);
 586         clk_disable(adc->clk);
 587
 588         return ret;
 589 }
 590
 591 static int ingenic_adc_read_raw(struct iio_dev *iio_dev,
 592                                 struct iio_chan_spec const *chan,
 593                                 int *val,
 594                                 int *val2,
 595                                 long m)
 596 {
 597         struct ingenic_adc *adc = iio_priv(iio_dev);
 598
 599         switch (m) {
 600         case IIO_CHAN_INFO_RAW:
 601                 return ingenic_adc_read_chan_info_raw(iio_dev, chan, val);
 602         case IIO_CHAN_INFO_SCALE:
 603                 switch (chan->channel) {
 604                 case INGENIC_ADC_AUX:
 605                 case INGENIC_ADC_AUX2:
 606                         *val = JZ_ADC_AUX_VREF;
 607                         *val2 = JZ_ADC_AUX_VREF_BITS;
 608                         break;
 609                 case INGENIC_ADC_BATTERY:
 610                         if (adc->low_vref_mode) {
 611                                 *val = JZ_ADC_BATTERY_LOW_VREF;
 612                                 *val2 = JZ_ADC_BATTERY_LOW_VREF_BITS;
 613                         } else {
 614                                 *val = adc->soc_data->battery_high_vref;
 615                                 *val2 = adc->soc_data->battery_high_vref_bits;
 616                         }
 617                         break;
 618                 }
 619
 620                 return IIO_VAL_FRACTIONAL_LOG2;
 621         default:
 622                 return -EINVAL;
 623         }
 624 }
 625
 626 static int ingenic_adc_of_xlate(struct iio_dev *iio_dev,
 627                                 const struct of_phandle_args *iiospec)
 628 {
 629         int i;
 630
 631         if (!iiospec->args_count)
 632                 return -EINVAL;
 633
 634         for (i = 0; i < iio_dev->num_channels; ++i)
 635                 if (iio_dev->channels[i].channel == iiospec->args[0])
 636                         return i;
 637
 638         return -EINVAL;
 639 }
 640
 641 static void ingenic_adc_clk_cleanup(void *data)
 642 {
 643         clk_unprepare(data);
 644 }
 645
 646 static const struct iio_info ingenic_adc_info = {
 647         .write_raw = ingenic_adc_write_raw,
 648         .read_raw = ingenic_adc_read_raw,
 649         .read_avail = ingenic_adc_read_avail,
 650         .of_xlate = ingenic_adc_of_xlate,
 651 };
 652
 653 static int ingenic_adc_buffer_enable(struct iio_dev *iio_dev)
 654 {
 655         struct ingenic_adc *adc = iio_priv(iio_dev);
 656         int ret;
 657
 658         ret = clk_enable(adc->clk);
 659         if (ret) {
 660                 dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
 661                         ret);
 662                 return ret;
 663         }
 664
 665         /* It takes significant time for the touchscreen hw to stabilize. */
 666         msleep(50);
 667         ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK,
 668                                JZ_ADC_REG_CFG_SAMPLE_NUM(4) |
 669                                JZ_ADC_REG_CFG_PULL_UP(4));
 670
 671         writew(80, adc->base + JZ_ADC_REG_ADWAIT);
 672         writew(2, adc->base + JZ_ADC_REG_ADSAME);
 673         writeb((u8)~JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_CTRL);
 674         writel(0, adc->base + JZ_ADC_REG_ADTCH);
 675
 676         ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL,
 677                                JZ_ADC_REG_CFG_CMD_SEL);
 678         ingenic_adc_set_adcmd(iio_dev, iio_dev->active_scan_mask[0]);
 679
 680         ingenic_adc_enable(adc, 2, true);
 681
 682         return 0;
 683 }
 684
 685 static int ingenic_adc_buffer_disable(struct iio_dev *iio_dev)
 686 {
 687         struct ingenic_adc *adc = iio_priv(iio_dev);
 688
 689         ingenic_adc_enable(adc, 2, false);
 690
 691         ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL, 0);
 692
 693         writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
 694         writeb(0xff, adc->base + JZ_ADC_REG_STATUS);
 695         ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK, 0);
 696         writew(0, adc->base + JZ_ADC_REG_ADSAME);
 697         writew(0, adc->base + JZ_ADC_REG_ADWAIT);
 698         clk_disable(adc->clk);
 699
 700         return 0;
 701 }
 702
 703 static const struct iio_buffer_setup_ops ingenic_buffer_setup_ops = {
 704         .postenable = &ingenic_adc_buffer_enable,
 705         .predisable = &ingenic_adc_buffer_disable
 706 };
 707
 708 static irqreturn_t ingenic_adc_irq(int irq, void *data)
 709 {
 710         struct iio_dev *iio_dev = data;
 711         struct ingenic_adc *adc = iio_priv(iio_dev);
 712         unsigned long mask = iio_dev->active_scan_mask[0];
 713         unsigned int i;
 714         u32 tdat[3];
 715
 716         for (i = 0; i < ARRAY_SIZE(tdat); mask >>= 2, i++) {
 717                 if (mask & 0x3)
 718                         tdat[i] = readl(adc->base + JZ_ADC_REG_ADTCH);
 719                 else
 720                         tdat[i] = 0;
 721         }
 722
 723         iio_push_to_buffers(iio_dev, tdat);
 724         writeb(JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_STATUS);
 725
 726         return IRQ_HANDLED;
 727 }
 728
 729 static int ingenic_adc_probe(struct platform_device *pdev)
 730 {
 731         struct device *dev = &pdev->dev;
 732         struct iio_dev *iio_dev;
 733         struct ingenic_adc *adc;
 734         const struct ingenic_adc_soc_data *soc_data;
 735         int irq, ret;
 736
 737         soc_data = device_get_match_data(dev);
 738         if (!soc_data)
 739                 return -EINVAL;
 740
 741         iio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
 742         if (!iio_dev)
 743                 return -ENOMEM;
 744
 745         adc = iio_priv(iio_dev);
 746         mutex_init(&adc->lock);
 747         mutex_init(&adc->aux_lock);
 748         adc->soc_data = soc_data;
 749
 750         irq = platform_get_irq(pdev, 0);
 751         if (irq < 0)
 752                 return irq;
 753
 754         ret = devm_request_irq(dev, irq, ingenic_adc_irq, 0,
 755                                dev_name(dev), iio_dev);
 756         if (ret < 0) {
 757                 dev_err(dev, "Failed to request irq: %d\n", ret);
 758                 return ret;
 759         }
 760
 761         adc->base = devm_platform_ioremap_resource(pdev, 0);
 762         if (IS_ERR(adc->base))
 763                 return PTR_ERR(adc->base);
 764
 765         adc->clk = devm_clk_get(dev, "adc");
 766         if (IS_ERR(adc->clk)) {
 767                 dev_err(dev, "Unable to get clock\n");
 768                 return PTR_ERR(adc->clk);
 769         }
 770
 771         ret = clk_prepare_enable(adc->clk);
 772         if (ret) {
 773                 dev_err(dev, "Failed to enable clock\n");
 774                 return ret;
 775         }
 776
 777         /* Set clock dividers. */
 778         if (soc_data->init_clk_div) {
 779                 ret = soc_data->init_clk_div(dev, adc);
 780                 if (ret) {
 781                         clk_disable_unprepare(adc->clk);
 782                         return ret;
 783                 }
 784         }
 785
 786         /* Put hardware in a known passive state. */
 787         writeb(0x00, adc->base + JZ_ADC_REG_ENABLE);
 788         writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
 789         usleep_range(2000, 3000); /* Must wait at least 2ms. */
 790         clk_disable(adc->clk);
 791
 792         ret = devm_add_action_or_reset(dev, ingenic_adc_clk_cleanup, adc->clk);
 793         if (ret) {
 794                 dev_err(dev, "Unable to add action\n");
 795                 return ret;
 796         }
 797
 798         iio_dev->name = "jz-adc";
 799         iio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
 800         iio_dev->setup_ops = &ingenic_buffer_setup_ops;
 801         iio_dev->channels = soc_data->channels;
 802         iio_dev->num_channels = soc_data->num_channels;
 803         iio_dev->info = &ingenic_adc_info;
 804
 805         ret = devm_iio_device_register(dev, iio_dev);
 806         if (ret)
 807                 dev_err(dev, "Unable to register IIO device\n");
 808
 809         return ret;
 810 }
 811
 812 static const struct of_device_id ingenic_adc_of_match[] = {
 813         { .compatible = "ingenic,jz4725b-adc", .data = &jz4725b_adc_soc_data, },
 814         { .compatible = "ingenic,jz4740-adc", .data = &jz4740_adc_soc_data, },
 815         { .compatible = "ingenic,jz4770-adc", .data = &jz4770_adc_soc_data, },
 816         { },
 817 };
 818 MODULE_DEVICE_TABLE(of, ingenic_adc_of_match);
 819
 820 static struct platform_driver ingenic_adc_driver = {
 821         .driver = {
 822                 .name = "ingenic-adc",
 823                 .of_match_table = ingenic_adc_of_match,
 824         },
 825         .probe = ingenic_adc_probe,
 826 };
 827 module_platform_driver(ingenic_adc_driver);
 828 MODULE_LICENSE("GPL v2");