1 // SPDX-License-Identifier: GPL-2.0
3 * ADC driver for the Ingenic JZ47xx SoCs
4 * Copyright (c) 2019 Artur Rojek <contact@artur-rojek.eu>
6 * based on drivers/mfd/jz4740-adc.c
9 #include <dt-bindings/iio/adc/ingenic,adc.h>
10 #include <linux/clk.h>
11 #include <linux/iio/buffer.h>
12 #include <linux/iio/iio.h>
13 #include <linux/interrupt.h>
15 #include <linux/iopoll.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/platform_device.h>
21 #define JZ_ADC_REG_ENABLE 0x00
22 #define JZ_ADC_REG_CFG 0x04
23 #define JZ_ADC_REG_CTRL 0x08
24 #define JZ_ADC_REG_STATUS 0x0c
25 #define JZ_ADC_REG_ADSAME 0x10
26 #define JZ_ADC_REG_ADWAIT 0x14
27 #define JZ_ADC_REG_ADTCH 0x18
28 #define JZ_ADC_REG_ADBDAT 0x1c
29 #define JZ_ADC_REG_ADSDAT 0x20
30 #define JZ_ADC_REG_ADCMD 0x24
31 #define JZ_ADC_REG_ADCLK 0x28
33 #define JZ_ADC_REG_ENABLE_PD BIT(7)
34 #define JZ_ADC_REG_CFG_AUX_MD (BIT(0) | BIT(1))
35 #define JZ_ADC_REG_CFG_BAT_MD BIT(4)
36 #define JZ_ADC_REG_CFG_SAMPLE_NUM(n) ((n) << 10)
37 #define JZ_ADC_REG_CFG_PULL_UP(n) ((n) << 16)
38 #define JZ_ADC_REG_CFG_CMD_SEL BIT(22)
39 #define JZ_ADC_REG_CFG_TOUCH_OPS_MASK (BIT(31) | GENMASK(23, 10))
40 #define JZ_ADC_REG_ADCLK_CLKDIV_LSB 0
41 #define JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB 16
42 #define JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB 8
43 #define JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB 16
45 #define JZ_ADC_REG_ADCMD_YNADC BIT(7)
46 #define JZ_ADC_REG_ADCMD_YPADC BIT(8)
47 #define JZ_ADC_REG_ADCMD_XNADC BIT(9)
48 #define JZ_ADC_REG_ADCMD_XPADC BIT(10)
49 #define JZ_ADC_REG_ADCMD_VREFPYP BIT(11)
50 #define JZ_ADC_REG_ADCMD_VREFPXP BIT(12)
51 #define JZ_ADC_REG_ADCMD_VREFPXN BIT(13)
52 #define JZ_ADC_REG_ADCMD_VREFPAUX BIT(14)
53 #define JZ_ADC_REG_ADCMD_VREFPVDD33 BIT(15)
54 #define JZ_ADC_REG_ADCMD_VREFNYN BIT(16)
55 #define JZ_ADC_REG_ADCMD_VREFNXP BIT(17)
56 #define JZ_ADC_REG_ADCMD_VREFNXN BIT(18)
57 #define JZ_ADC_REG_ADCMD_VREFAUX BIT(19)
58 #define JZ_ADC_REG_ADCMD_YNGRU BIT(20)
59 #define JZ_ADC_REG_ADCMD_XNGRU BIT(21)
60 #define JZ_ADC_REG_ADCMD_XPGRU BIT(22)
61 #define JZ_ADC_REG_ADCMD_YPSUP BIT(23)
62 #define JZ_ADC_REG_ADCMD_XNSUP BIT(24)
63 #define JZ_ADC_REG_ADCMD_XPSUP BIT(25)
65 #define JZ_ADC_AUX_VREF 3300
66 #define JZ_ADC_AUX_VREF_BITS 12
67 #define JZ_ADC_BATTERY_LOW_VREF 2500
68 #define JZ_ADC_BATTERY_LOW_VREF_BITS 12
69 #define JZ4725B_ADC_BATTERY_HIGH_VREF 7500
70 #define JZ4725B_ADC_BATTERY_HIGH_VREF_BITS 10
71 #define JZ4740_ADC_BATTERY_HIGH_VREF (7500 * 0.986)
72 #define JZ4740_ADC_BATTERY_HIGH_VREF_BITS 12
73 #define JZ4770_ADC_BATTERY_VREF 6600
74 #define JZ4770_ADC_BATTERY_VREF_BITS 12
76 #define JZ_ADC_IRQ_AUX BIT(0)
77 #define JZ_ADC_IRQ_BATTERY BIT(1)
78 #define JZ_ADC_IRQ_TOUCH BIT(2)
79 #define JZ_ADC_IRQ_PEN_DOWN BIT(3)
80 #define JZ_ADC_IRQ_PEN_UP BIT(4)
81 #define JZ_ADC_IRQ_PEN_DOWN_SLEEP BIT(5)
82 #define JZ_ADC_IRQ_SLEEP BIT(7)
86 struct ingenic_adc_soc_data {
87 unsigned int battery_high_vref;
88 unsigned int battery_high_vref_bits;
89 const int *battery_raw_avail;
90 size_t battery_raw_avail_size;
91 const int *battery_scale_avail;
92 size_t battery_scale_avail_size;
93 unsigned int battery_vref_mode: 1;
94 unsigned int has_aux2: 1;
95 const struct iio_chan_spec *channels;
96 unsigned int num_channels;
97 int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
104 struct mutex aux_lock;
105 const struct ingenic_adc_soc_data *soc_data;
109 static void ingenic_adc_set_adcmd(struct iio_dev *iio_dev, unsigned long mask)
111 struct ingenic_adc *adc = iio_priv(iio_dev);
113 mutex_lock(&adc->lock);
116 readl(adc->base + JZ_ADC_REG_ADCMD);
119 /* Second channel (INGENIC_ADC_TOUCH_YP): sample YP vs. GND */
120 writel(JZ_ADC_REG_ADCMD_XNGRU
121 | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
122 | JZ_ADC_REG_ADCMD_YPADC,
123 adc->base + JZ_ADC_REG_ADCMD);
125 /* First channel (INGENIC_ADC_TOUCH_XP): sample XP vs. GND */
126 writel(JZ_ADC_REG_ADCMD_YNGRU
127 | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
128 | JZ_ADC_REG_ADCMD_XPADC,
129 adc->base + JZ_ADC_REG_ADCMD);
133 /* Fourth channel (INGENIC_ADC_TOUCH_YN): sample YN vs. GND */
134 writel(JZ_ADC_REG_ADCMD_XNGRU
135 | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
136 | JZ_ADC_REG_ADCMD_YNADC,
137 adc->base + JZ_ADC_REG_ADCMD);
139 /* Third channel (INGENIC_ADC_TOUCH_XN): sample XN vs. GND */
140 writel(JZ_ADC_REG_ADCMD_YNGRU
141 | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
142 | JZ_ADC_REG_ADCMD_XNADC,
143 adc->base + JZ_ADC_REG_ADCMD);
147 /* Sixth channel (INGENIC_ADC_TOUCH_YD): sample YP vs. YN */
148 writel(JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
149 | JZ_ADC_REG_ADCMD_YPADC,
150 adc->base + JZ_ADC_REG_ADCMD);
152 /* Fifth channel (INGENIC_ADC_TOUCH_XD): sample XP vs. XN */
153 writel(JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
154 | JZ_ADC_REG_ADCMD_XPADC,
155 adc->base + JZ_ADC_REG_ADCMD);
159 writel(0, adc->base + JZ_ADC_REG_ADCMD);
161 mutex_unlock(&adc->lock);
164 static void ingenic_adc_set_config(struct ingenic_adc *adc,
170 mutex_lock(&adc->lock);
172 cfg = readl(adc->base + JZ_ADC_REG_CFG) & ~mask;
174 writel(cfg, adc->base + JZ_ADC_REG_CFG);
176 mutex_unlock(&adc->lock);
179 static void ingenic_adc_enable(struct ingenic_adc *adc,
185 mutex_lock(&adc->lock);
186 val = readb(adc->base + JZ_ADC_REG_ENABLE);
193 writeb(val, adc->base + JZ_ADC_REG_ENABLE);
194 mutex_unlock(&adc->lock);
197 static int ingenic_adc_capture(struct ingenic_adc *adc,
203 ingenic_adc_enable(adc, engine, true);
204 ret = readb_poll_timeout(adc->base + JZ_ADC_REG_ENABLE, val,
205 !(val & BIT(engine)), 250, 1000);
207 ingenic_adc_enable(adc, engine, false);
212 static int ingenic_adc_write_raw(struct iio_dev *iio_dev,
213 struct iio_chan_spec const *chan,
218 struct ingenic_adc *adc = iio_priv(iio_dev);
219 struct device *dev = iio_dev->dev.parent;
223 case IIO_CHAN_INFO_SCALE:
224 switch (chan->channel) {
225 case INGENIC_ADC_BATTERY:
226 if (!adc->soc_data->battery_vref_mode)
229 ret = clk_enable(adc->clk);
231 dev_err(dev, "Failed to enable clock: %d\n",
236 if (val > JZ_ADC_BATTERY_LOW_VREF) {
237 ingenic_adc_set_config(adc,
238 JZ_ADC_REG_CFG_BAT_MD,
240 adc->low_vref_mode = false;
242 ingenic_adc_set_config(adc,
243 JZ_ADC_REG_CFG_BAT_MD,
244 JZ_ADC_REG_CFG_BAT_MD);
245 adc->low_vref_mode = true;
248 clk_disable(adc->clk);
259 static const int jz4725b_adc_battery_raw_avail[] = {
260 0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
263 static const int jz4725b_adc_battery_scale_avail[] = {
264 JZ4725B_ADC_BATTERY_HIGH_VREF, JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
265 JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
268 static const int jz4740_adc_battery_raw_avail[] = {
269 0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
272 static const int jz4740_adc_battery_scale_avail[] = {
273 JZ4740_ADC_BATTERY_HIGH_VREF, JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
274 JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
277 static const int jz4770_adc_battery_raw_avail[] = {
278 0, 1, (1 << JZ4770_ADC_BATTERY_VREF_BITS) - 1,
281 static const int jz4770_adc_battery_scale_avail[] = {
282 JZ4770_ADC_BATTERY_VREF, JZ4770_ADC_BATTERY_VREF_BITS,
285 static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
287 struct clk *parent_clk;
288 unsigned long parent_rate, rate;
289 unsigned int div_main, div_10us;
291 parent_clk = clk_get_parent(adc->clk);
293 dev_err(dev, "ADC clock has no parent\n");
296 parent_rate = clk_get_rate(parent_clk);
299 * The JZ4725B ADC works at 500 kHz to 8 MHz.
300 * We pick the highest rate possible.
301 * In practice we typically get 6 MHz, half of the 12 MHz EXT clock.
303 div_main = DIV_ROUND_UP(parent_rate, 8000000);
304 div_main = clamp(div_main, 1u, 64u);
305 rate = parent_rate / div_main;
306 if (rate < 500000 || rate > 8000000) {
307 dev_err(dev, "No valid divider for ADC main clock\n");
311 /* We also need a divider that produces a 10us clock. */
312 div_10us = DIV_ROUND_UP(rate, 100000);
314 writel(((div_10us - 1) << JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB) |
315 (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
316 adc->base + JZ_ADC_REG_ADCLK);
321 static int jz4770_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
323 struct clk *parent_clk;
324 unsigned long parent_rate, rate;
325 unsigned int div_main, div_ms, div_10us;
327 parent_clk = clk_get_parent(adc->clk);
329 dev_err(dev, "ADC clock has no parent\n");
332 parent_rate = clk_get_rate(parent_clk);
335 * The JZ4770 ADC works at 20 kHz to 200 kHz.
336 * We pick the highest rate possible.
338 div_main = DIV_ROUND_UP(parent_rate, 200000);
339 div_main = clamp(div_main, 1u, 256u);
340 rate = parent_rate / div_main;
341 if (rate < 20000 || rate > 200000) {
342 dev_err(dev, "No valid divider for ADC main clock\n");
346 /* We also need a divider that produces a 10us clock. */
347 div_10us = DIV_ROUND_UP(rate, 10000);
348 /* And another, which produces a 1ms clock. */
349 div_ms = DIV_ROUND_UP(rate, 1000);
351 writel(((div_ms - 1) << JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB) |
352 ((div_10us - 1) << JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB) |
353 (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
354 adc->base + JZ_ADC_REG_ADCLK);
359 static const struct iio_chan_spec jz4740_channels[] = {
361 .extend_name = "aux",
363 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
364 BIT(IIO_CHAN_INFO_SCALE),
366 .channel = INGENIC_ADC_AUX,
370 .extend_name = "battery",
372 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
373 BIT(IIO_CHAN_INFO_SCALE),
374 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
375 BIT(IIO_CHAN_INFO_SCALE),
377 .channel = INGENIC_ADC_BATTERY,
382 static const struct iio_chan_spec jz4770_channels[] = {
386 .channel = INGENIC_ADC_TOUCH_XP,
397 .channel = INGENIC_ADC_TOUCH_YP,
408 .channel = INGENIC_ADC_TOUCH_XN,
419 .channel = INGENIC_ADC_TOUCH_YN,
430 .channel = INGENIC_ADC_TOUCH_XD,
441 .channel = INGENIC_ADC_TOUCH_YD,
450 .extend_name = "aux",
452 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
453 BIT(IIO_CHAN_INFO_SCALE),
455 .channel = INGENIC_ADC_AUX,
459 .extend_name = "battery",
461 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
462 BIT(IIO_CHAN_INFO_SCALE),
463 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
464 BIT(IIO_CHAN_INFO_SCALE),
466 .channel = INGENIC_ADC_BATTERY,
470 .extend_name = "aux2",
472 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
473 BIT(IIO_CHAN_INFO_SCALE),
475 .channel = INGENIC_ADC_AUX2,
480 static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = {
481 .battery_high_vref = JZ4725B_ADC_BATTERY_HIGH_VREF,
482 .battery_high_vref_bits = JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
483 .battery_raw_avail = jz4725b_adc_battery_raw_avail,
484 .battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail),
485 .battery_scale_avail = jz4725b_adc_battery_scale_avail,
486 .battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail),
487 .battery_vref_mode = true,
489 .channels = jz4740_channels,
490 .num_channels = ARRAY_SIZE(jz4740_channels),
491 .init_clk_div = jz4725b_adc_init_clk_div,
494 static const struct ingenic_adc_soc_data jz4740_adc_soc_data = {
495 .battery_high_vref = JZ4740_ADC_BATTERY_HIGH_VREF,
496 .battery_high_vref_bits = JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
497 .battery_raw_avail = jz4740_adc_battery_raw_avail,
498 .battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail),
499 .battery_scale_avail = jz4740_adc_battery_scale_avail,
500 .battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail),
501 .battery_vref_mode = true,
503 .channels = jz4740_channels,
504 .num_channels = ARRAY_SIZE(jz4740_channels),
505 .init_clk_div = NULL, /* no ADCLK register on JZ4740 */
508 static const struct ingenic_adc_soc_data jz4770_adc_soc_data = {
509 .battery_high_vref = JZ4770_ADC_BATTERY_VREF,
510 .battery_high_vref_bits = JZ4770_ADC_BATTERY_VREF_BITS,
511 .battery_raw_avail = jz4770_adc_battery_raw_avail,
512 .battery_raw_avail_size = ARRAY_SIZE(jz4770_adc_battery_raw_avail),
513 .battery_scale_avail = jz4770_adc_battery_scale_avail,
514 .battery_scale_avail_size = ARRAY_SIZE(jz4770_adc_battery_scale_avail),
515 .battery_vref_mode = false,
517 .channels = jz4770_channels,
518 .num_channels = ARRAY_SIZE(jz4770_channels),
519 .init_clk_div = jz4770_adc_init_clk_div,
522 static int ingenic_adc_read_avail(struct iio_dev *iio_dev,
523 struct iio_chan_spec const *chan,
529 struct ingenic_adc *adc = iio_priv(iio_dev);
532 case IIO_CHAN_INFO_RAW:
534 *length = adc->soc_data->battery_raw_avail_size;
535 *vals = adc->soc_data->battery_raw_avail;
536 return IIO_AVAIL_RANGE;
537 case IIO_CHAN_INFO_SCALE:
538 *type = IIO_VAL_FRACTIONAL_LOG2;
539 *length = adc->soc_data->battery_scale_avail_size;
540 *vals = adc->soc_data->battery_scale_avail;
541 return IIO_AVAIL_LIST;
547 static int ingenic_adc_read_chan_info_raw(struct iio_dev *iio_dev,
548 struct iio_chan_spec const *chan,
551 int bit, ret, engine = (chan->channel == INGENIC_ADC_BATTERY);
552 struct ingenic_adc *adc = iio_priv(iio_dev);
554 ret = clk_enable(adc->clk);
556 dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
561 /* We cannot sample AUX/AUX2 in parallel. */
562 mutex_lock(&adc->aux_lock);
563 if (adc->soc_data->has_aux2 && engine == 0) {
564 bit = BIT(chan->channel == INGENIC_ADC_AUX2);
565 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_AUX_MD, bit);
568 ret = ingenic_adc_capture(adc, engine);
572 switch (chan->channel) {
573 case INGENIC_ADC_AUX:
574 case INGENIC_ADC_AUX2:
575 *val = readw(adc->base + JZ_ADC_REG_ADSDAT);
577 case INGENIC_ADC_BATTERY:
578 *val = readw(adc->base + JZ_ADC_REG_ADBDAT);
584 mutex_unlock(&adc->aux_lock);
585 clk_disable(adc->clk);
590 static int ingenic_adc_read_raw(struct iio_dev *iio_dev,
591 struct iio_chan_spec const *chan,
596 struct ingenic_adc *adc = iio_priv(iio_dev);
599 case IIO_CHAN_INFO_RAW:
600 return ingenic_adc_read_chan_info_raw(iio_dev, chan, val);
601 case IIO_CHAN_INFO_SCALE:
602 switch (chan->channel) {
603 case INGENIC_ADC_AUX:
604 case INGENIC_ADC_AUX2:
605 *val = JZ_ADC_AUX_VREF;
606 *val2 = JZ_ADC_AUX_VREF_BITS;
608 case INGENIC_ADC_BATTERY:
609 if (adc->low_vref_mode) {
610 *val = JZ_ADC_BATTERY_LOW_VREF;
611 *val2 = JZ_ADC_BATTERY_LOW_VREF_BITS;
613 *val = adc->soc_data->battery_high_vref;
614 *val2 = adc->soc_data->battery_high_vref_bits;
619 return IIO_VAL_FRACTIONAL_LOG2;
625 static int ingenic_adc_of_xlate(struct iio_dev *iio_dev,
626 const struct of_phandle_args *iiospec)
630 if (!iiospec->args_count)
633 for (i = 0; i < iio_dev->num_channels; ++i)
634 if (iio_dev->channels[i].channel == iiospec->args[0])
640 static void ingenic_adc_clk_cleanup(void *data)
645 static const struct iio_info ingenic_adc_info = {
646 .write_raw = ingenic_adc_write_raw,
647 .read_raw = ingenic_adc_read_raw,
648 .read_avail = ingenic_adc_read_avail,
649 .of_xlate = ingenic_adc_of_xlate,
652 static int ingenic_adc_buffer_enable(struct iio_dev *iio_dev)
654 struct ingenic_adc *adc = iio_priv(iio_dev);
657 ret = clk_enable(adc->clk);
659 dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
664 /* It takes significant time for the touchscreen hw to stabilize. */
666 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK,
667 JZ_ADC_REG_CFG_SAMPLE_NUM(4) |
668 JZ_ADC_REG_CFG_PULL_UP(4));
670 writew(80, adc->base + JZ_ADC_REG_ADWAIT);
671 writew(2, adc->base + JZ_ADC_REG_ADSAME);
672 writeb((u8)~JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_CTRL);
673 writel(0, adc->base + JZ_ADC_REG_ADTCH);
675 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL,
676 JZ_ADC_REG_CFG_CMD_SEL);
677 ingenic_adc_set_adcmd(iio_dev, iio_dev->active_scan_mask[0]);
679 ingenic_adc_enable(adc, 2, true);
684 static int ingenic_adc_buffer_disable(struct iio_dev *iio_dev)
686 struct ingenic_adc *adc = iio_priv(iio_dev);
688 ingenic_adc_enable(adc, 2, false);
690 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL, 0);
692 writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
693 writeb(0xff, adc->base + JZ_ADC_REG_STATUS);
694 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK, 0);
695 writew(0, adc->base + JZ_ADC_REG_ADSAME);
696 writew(0, adc->base + JZ_ADC_REG_ADWAIT);
697 clk_disable(adc->clk);
702 static const struct iio_buffer_setup_ops ingenic_buffer_setup_ops = {
703 .postenable = &ingenic_adc_buffer_enable,
704 .predisable = &ingenic_adc_buffer_disable
707 static irqreturn_t ingenic_adc_irq(int irq, void *data)
709 struct iio_dev *iio_dev = data;
710 struct ingenic_adc *adc = iio_priv(iio_dev);
711 unsigned long mask = iio_dev->active_scan_mask[0];
715 for (i = 0; i < ARRAY_SIZE(tdat); mask >>= 2, i++) {
717 tdat[i] = readl(adc->base + JZ_ADC_REG_ADTCH);
722 iio_push_to_buffers(iio_dev, tdat);
723 writeb(JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_STATUS);
728 static int ingenic_adc_probe(struct platform_device *pdev)
730 struct device *dev = &pdev->dev;
731 struct iio_dev *iio_dev;
732 struct ingenic_adc *adc;
733 const struct ingenic_adc_soc_data *soc_data;
736 soc_data = device_get_match_data(dev);
740 iio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
744 adc = iio_priv(iio_dev);
745 mutex_init(&adc->lock);
746 mutex_init(&adc->aux_lock);
747 adc->soc_data = soc_data;
749 irq = platform_get_irq(pdev, 0);
753 ret = devm_request_irq(dev, irq, ingenic_adc_irq, 0,
754 dev_name(dev), iio_dev);
756 dev_err(dev, "Failed to request irq: %d\n", ret);
760 adc->base = devm_platform_ioremap_resource(pdev, 0);
761 if (IS_ERR(adc->base))
762 return PTR_ERR(adc->base);
764 adc->clk = devm_clk_get(dev, "adc");
765 if (IS_ERR(adc->clk)) {
766 dev_err(dev, "Unable to get clock\n");
767 return PTR_ERR(adc->clk);
770 ret = clk_prepare_enable(adc->clk);
772 dev_err(dev, "Failed to enable clock\n");
776 /* Set clock dividers. */
777 if (soc_data->init_clk_div) {
778 ret = soc_data->init_clk_div(dev, adc);
780 clk_disable_unprepare(adc->clk);
785 /* Put hardware in a known passive state. */
786 writeb(0x00, adc->base + JZ_ADC_REG_ENABLE);
787 writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
788 usleep_range(2000, 3000); /* Must wait at least 2ms. */
789 clk_disable(adc->clk);
791 ret = devm_add_action_or_reset(dev, ingenic_adc_clk_cleanup, adc->clk);
793 dev_err(dev, "Unable to add action\n");
797 iio_dev->dev.parent = dev;
798 iio_dev->name = "jz-adc";
799 iio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
800 iio_dev->setup_ops = &ingenic_buffer_setup_ops;
801 iio_dev->channels = soc_data->channels;
802 iio_dev->num_channels = soc_data->num_channels;
803 iio_dev->info = &ingenic_adc_info;
805 ret = devm_iio_device_register(dev, iio_dev);
807 dev_err(dev, "Unable to register IIO device\n");
813 static const struct of_device_id ingenic_adc_of_match[] = {
814 { .compatible = "ingenic,jz4725b-adc", .data = &jz4725b_adc_soc_data, },
815 { .compatible = "ingenic,jz4740-adc", .data = &jz4740_adc_soc_data, },
816 { .compatible = "ingenic,jz4770-adc", .data = &jz4770_adc_soc_data, },
819 MODULE_DEVICE_TABLE(of, ingenic_adc_of_match);
822 static struct platform_driver ingenic_adc_driver = {
824 .name = "ingenic-adc",
825 .of_match_table = of_match_ptr(ingenic_adc_of_match),
827 .probe = ingenic_adc_probe,
829 module_platform_driver(ingenic_adc_driver);
830 MODULE_LICENSE("GPL v2");