drivers/iio/adc/ingenic-adc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ADC driver for the Ingenic JZ47xx SoCs
   4  * Copyright (c) 2019 Artur Rojek <contact@artur-rojek.eu>
   5  *
   6  * based on drivers/mfd/jz4740-adc.c
   7  */
   8
   9 #include <dt-bindings/iio/adc/ingenic,adc.h>
  10 #include <linux/clk.h>
  11 #include <linux/iio/iio.h>
  12 #include <linux/io.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/mutex.h>
  17 #include <linux/platform_device.h>
  18
  19 #define JZ_ADC_REG_ENABLE               0x00
  20 #define JZ_ADC_REG_CFG                  0x04
  21 #define JZ_ADC_REG_CTRL                 0x08
  22 #define JZ_ADC_REG_STATUS               0x0c
  23 #define JZ_ADC_REG_ADTCH                0x18
  24 #define JZ_ADC_REG_ADBDAT               0x1c
  25 #define JZ_ADC_REG_ADSDAT               0x20
  26 #define JZ_ADC_REG_ADCLK                0x28
  27
  28 #define JZ_ADC_REG_ENABLE_PD            BIT(7)
  29 #define JZ_ADC_REG_CFG_AUX_MD           (BIT(0) | BIT(1))
  30 #define JZ_ADC_REG_CFG_BAT_MD           BIT(4)
  31 #define JZ_ADC_REG_ADCLK_CLKDIV_LSB     0
  32 #define JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB    16
  33 #define JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB     8
  34 #define JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB       16
  35
  36 #define JZ_ADC_AUX_VREF                         3300
  37 #define JZ_ADC_AUX_VREF_BITS                    12
  38 #define JZ_ADC_BATTERY_LOW_VREF                 2500
  39 #define JZ_ADC_BATTERY_LOW_VREF_BITS            12
  40 #define JZ4725B_ADC_BATTERY_HIGH_VREF           7500
  41 #define JZ4725B_ADC_BATTERY_HIGH_VREF_BITS      10
  42 #define JZ4740_ADC_BATTERY_HIGH_VREF            (7500 * 0.986)
  43 #define JZ4740_ADC_BATTERY_HIGH_VREF_BITS       12
  44 #define JZ4770_ADC_BATTERY_VREF                 6600
  45 #define JZ4770_ADC_BATTERY_VREF_BITS            12
  46
  47 struct ingenic_adc;
  48
  49 struct ingenic_adc_soc_data {
  50         unsigned int battery_high_vref;
  51         unsigned int battery_high_vref_bits;
  52         const int *battery_raw_avail;
  53         size_t battery_raw_avail_size;
  54         const int *battery_scale_avail;
  55         size_t battery_scale_avail_size;
  56         unsigned int battery_vref_mode: 1;
  57         unsigned int has_aux2: 1;
  58         const struct iio_chan_spec *channels;
  59         unsigned int num_channels;
  60         int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
  61 };
  62
  63 struct ingenic_adc {
  64         void __iomem *base;
  65         struct clk *clk;
  66         struct mutex lock;
  67         struct mutex aux_lock;
  68         const struct ingenic_adc_soc_data *soc_data;
  69         bool low_vref_mode;
  70 };
  71
  72 static void ingenic_adc_set_config(struct ingenic_adc *adc,
  73                                    uint32_t mask,
  74                                    uint32_t val)
  75 {
  76         uint32_t cfg;
  77
  78         mutex_lock(&adc->lock);
  79
  80         cfg = readl(adc->base + JZ_ADC_REG_CFG) & ~mask;
  81         cfg |= val;
  82         writel(cfg, adc->base + JZ_ADC_REG_CFG);
  83
  84         mutex_unlock(&adc->lock);
  85 }
  86
  87 static void ingenic_adc_enable(struct ingenic_adc *adc,
  88                                int engine,
  89                                bool enabled)
  90 {
  91         u8 val;
  92
  93         mutex_lock(&adc->lock);
  94         val = readb(adc->base + JZ_ADC_REG_ENABLE);
  95
  96         if (enabled)
  97                 val |= BIT(engine);
  98         else
  99                 val &= ~BIT(engine);
 100
 101         writeb(val, adc->base + JZ_ADC_REG_ENABLE);
 102         mutex_unlock(&adc->lock);
 103 }
 104
 105 static int ingenic_adc_capture(struct ingenic_adc *adc,
 106                                int engine)
 107 {
 108         u8 val;
 109         int ret;
 110
 111         ingenic_adc_enable(adc, engine, true);
 112         ret = readb_poll_timeout(adc->base + JZ_ADC_REG_ENABLE, val,
 113                                  !(val & BIT(engine)), 250, 1000);
 114         if (ret)
 115                 ingenic_adc_enable(adc, engine, false);
 116
 117         return ret;
 118 }
 119
 120 static int ingenic_adc_write_raw(struct iio_dev *iio_dev,
 121                                  struct iio_chan_spec const *chan,
 122                                  int val,
 123                                  int val2,
 124                                  long m)
 125 {
 126         struct ingenic_adc *adc = iio_priv(iio_dev);
 127         struct device *dev = iio_dev->dev.parent;
 128         int ret;
 129
 130         switch (m) {
 131         case IIO_CHAN_INFO_SCALE:
 132                 switch (chan->channel) {
 133                 case INGENIC_ADC_BATTERY:
 134                         if (!adc->soc_data->battery_vref_mode)
 135                                 return -EINVAL;
 136
 137                         ret = clk_enable(adc->clk);
 138                         if (ret) {
 139                                 dev_err(dev, "Failed to enable clock: %d\n",
 140                                         ret);
 141                                 return ret;
 142                         }
 143
 144                         if (val > JZ_ADC_BATTERY_LOW_VREF) {
 145                                 ingenic_adc_set_config(adc,
 146                                                        JZ_ADC_REG_CFG_BAT_MD,
 147                                                        0);
 148                                 adc->low_vref_mode = false;
 149                         } else {
 150                                 ingenic_adc_set_config(adc,
 151                                                        JZ_ADC_REG_CFG_BAT_MD,
 152                                                        JZ_ADC_REG_CFG_BAT_MD);
 153                                 adc->low_vref_mode = true;
 154                         }
 155
 156                         clk_disable(adc->clk);
 157
 158                         return 0;
 159                 default:
 160                         return -EINVAL;
 161                 }
 162         default:
 163                 return -EINVAL;
 164         }
 165 }
 166
 167 static const int jz4725b_adc_battery_raw_avail[] = {
 168         0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
 169 };
 170
 171 static const int jz4725b_adc_battery_scale_avail[] = {
 172         JZ4725B_ADC_BATTERY_HIGH_VREF, JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
 173         JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
 174 };
 175
 176 static const int jz4740_adc_battery_raw_avail[] = {
 177         0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
 178 };
 179
 180 static const int jz4740_adc_battery_scale_avail[] = {
 181         JZ4740_ADC_BATTERY_HIGH_VREF, JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
 182         JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
 183 };
 184
 185 static const int jz4770_adc_battery_raw_avail[] = {
 186         0, 1, (1 << JZ4770_ADC_BATTERY_VREF_BITS) - 1,
 187 };
 188
 189 static const int jz4770_adc_battery_scale_avail[] = {
 190         JZ4770_ADC_BATTERY_VREF, JZ4770_ADC_BATTERY_VREF_BITS,
 191 };
 192
 193 static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
 194 {
 195         struct clk *parent_clk;
 196         unsigned long parent_rate, rate;
 197         unsigned int div_main, div_10us;
 198
 199         parent_clk = clk_get_parent(adc->clk);
 200         if (!parent_clk) {
 201                 dev_err(dev, "ADC clock has no parent\n");
 202                 return -ENODEV;
 203         }
 204         parent_rate = clk_get_rate(parent_clk);
 205
 206         /*
 207          * The JZ4725B ADC works at 500 kHz to 8 MHz.
 208          * We pick the highest rate possible.
 209          * In practice we typically get 6 MHz, half of the 12 MHz EXT clock.
 210          */
 211         div_main = DIV_ROUND_UP(parent_rate, 8000000);
 212         div_main = clamp(div_main, 1u, 64u);
 213         rate = parent_rate / div_main;
 214         if (rate < 500000 || rate > 8000000) {
 215                 dev_err(dev, "No valid divider for ADC main clock\n");
 216                 return -EINVAL;
 217         }
 218
 219         /* We also need a divider that produces a 10us clock. */
 220         div_10us = DIV_ROUND_UP(rate, 100000);
 221
 222         writel(((div_10us - 1) << JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB) |
 223                (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
 224                adc->base + JZ_ADC_REG_ADCLK);
 225
 226         return 0;
 227 }
 228
 229 static int jz4770_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
 230 {
 231         struct clk *parent_clk;
 232         unsigned long parent_rate, rate;
 233         unsigned int div_main, div_ms, div_10us;
 234
 235         parent_clk = clk_get_parent(adc->clk);
 236         if (!parent_clk) {
 237                 dev_err(dev, "ADC clock has no parent\n");
 238                 return -ENODEV;
 239         }
 240         parent_rate = clk_get_rate(parent_clk);
 241
 242         /*
 243          * The JZ4770 ADC works at 20 kHz to 200 kHz.
 244          * We pick the highest rate possible.
 245          */
 246         div_main = DIV_ROUND_UP(parent_rate, 200000);
 247         div_main = clamp(div_main, 1u, 256u);
 248         rate = parent_rate / div_main;
 249         if (rate < 20000 || rate > 200000) {
 250                 dev_err(dev, "No valid divider for ADC main clock\n");
 251                 return -EINVAL;
 252         }
 253
 254         /* We also need a divider that produces a 10us clock. */
 255         div_10us = DIV_ROUND_UP(rate, 10000);
 256         /* And another, which produces a 1ms clock. */
 257         div_ms = DIV_ROUND_UP(rate, 1000);
 258
 259         writel(((div_ms - 1) << JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB) |
 260                ((div_10us - 1) << JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB) |
 261                (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
 262                adc->base + JZ_ADC_REG_ADCLK);
 263
 264         return 0;
 265 }
 266
 267 static const struct iio_chan_spec jz4740_channels[] = {
 268         {
 269                 .extend_name = "aux",
 270                 .type = IIO_VOLTAGE,
 271                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 272                                       BIT(IIO_CHAN_INFO_SCALE),
 273                 .indexed = 1,
 274                 .channel = INGENIC_ADC_AUX,
 275                 .scan_index = -1,
 276         },
 277         {
 278                 .extend_name = "battery",
 279                 .type = IIO_VOLTAGE,
 280                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 281                                       BIT(IIO_CHAN_INFO_SCALE),
 282                 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
 283                                                 BIT(IIO_CHAN_INFO_SCALE),
 284                 .indexed = 1,
 285                 .channel = INGENIC_ADC_BATTERY,
 286                 .scan_index = -1,
 287         },
 288 };
 289
 290 static const struct iio_chan_spec jz4770_channels[] = {
 291         {
 292                 .extend_name = "aux",
 293                 .type = IIO_VOLTAGE,
 294                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 295                                       BIT(IIO_CHAN_INFO_SCALE),
 296                 .indexed = 1,
 297                 .channel = INGENIC_ADC_AUX,
 298                 .scan_index = -1,
 299         },
 300         {
 301                 .extend_name = "battery",
 302                 .type = IIO_VOLTAGE,
 303                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 304                                       BIT(IIO_CHAN_INFO_SCALE),
 305                 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
 306                                                 BIT(IIO_CHAN_INFO_SCALE),
 307                 .indexed = 1,
 308                 .channel = INGENIC_ADC_BATTERY,
 309                 .scan_index = -1,
 310         },
 311         {
 312                 .extend_name = "aux2",
 313                 .type = IIO_VOLTAGE,
 314                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 315                                       BIT(IIO_CHAN_INFO_SCALE),
 316                 .indexed = 1,
 317                 .channel = INGENIC_ADC_AUX2,
 318                 .scan_index = -1,
 319         },
 320 };
 321
 322 static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = {
 323         .battery_high_vref = JZ4725B_ADC_BATTERY_HIGH_VREF,
 324         .battery_high_vref_bits = JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
 325         .battery_raw_avail = jz4725b_adc_battery_raw_avail,
 326         .battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail),
 327         .battery_scale_avail = jz4725b_adc_battery_scale_avail,
 328         .battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail),
 329         .battery_vref_mode = true,
 330         .has_aux2 = false,
 331         .channels = jz4740_channels,
 332         .num_channels = ARRAY_SIZE(jz4740_channels),
 333         .init_clk_div = jz4725b_adc_init_clk_div,
 334 };
 335
 336 static const struct ingenic_adc_soc_data jz4740_adc_soc_data = {
 337         .battery_high_vref = JZ4740_ADC_BATTERY_HIGH_VREF,
 338         .battery_high_vref_bits = JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
 339         .battery_raw_avail = jz4740_adc_battery_raw_avail,
 340         .battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail),
 341         .battery_scale_avail = jz4740_adc_battery_scale_avail,
 342         .battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail),
 343         .battery_vref_mode = true,
 344         .has_aux2 = false,
 345         .channels = jz4740_channels,
 346         .num_channels = ARRAY_SIZE(jz4740_channels),
 347         .init_clk_div = NULL, /* no ADCLK register on JZ4740 */
 348 };
 349
 350 static const struct ingenic_adc_soc_data jz4770_adc_soc_data = {
 351         .battery_high_vref = JZ4770_ADC_BATTERY_VREF,
 352         .battery_high_vref_bits = JZ4770_ADC_BATTERY_VREF_BITS,
 353         .battery_raw_avail = jz4770_adc_battery_raw_avail,
 354         .battery_raw_avail_size = ARRAY_SIZE(jz4770_adc_battery_raw_avail),
 355         .battery_scale_avail = jz4770_adc_battery_scale_avail,
 356         .battery_scale_avail_size = ARRAY_SIZE(jz4770_adc_battery_scale_avail),
 357         .battery_vref_mode = false,
 358         .has_aux2 = true,
 359         .channels = jz4770_channels,
 360         .num_channels = ARRAY_SIZE(jz4770_channels),
 361         .init_clk_div = jz4770_adc_init_clk_div,
 362 };
 363
 364 static int ingenic_adc_read_avail(struct iio_dev *iio_dev,
 365                                   struct iio_chan_spec const *chan,
 366                                   const int **vals,
 367                                   int *type,
 368                                   int *length,
 369                                   long m)
 370 {
 371         struct ingenic_adc *adc = iio_priv(iio_dev);
 372
 373         switch (m) {
 374         case IIO_CHAN_INFO_RAW:
 375                 *type = IIO_VAL_INT;
 376                 *length = adc->soc_data->battery_raw_avail_size;
 377                 *vals = adc->soc_data->battery_raw_avail;
 378                 return IIO_AVAIL_RANGE;
 379         case IIO_CHAN_INFO_SCALE:
 380                 *type = IIO_VAL_FRACTIONAL_LOG2;
 381                 *length = adc->soc_data->battery_scale_avail_size;
 382                 *vals = adc->soc_data->battery_scale_avail;
 383                 return IIO_AVAIL_LIST;
 384         default:
 385                 return -EINVAL;
 386         };
 387 }
 388
 389 static int ingenic_adc_read_chan_info_raw(struct iio_dev *iio_dev,
 390                                           struct iio_chan_spec const *chan,
 391                                           int *val)
 392 {
 393         int bit, ret, engine = (chan->channel == INGENIC_ADC_BATTERY);
 394         struct ingenic_adc *adc = iio_priv(iio_dev);
 395
 396         ret = clk_enable(adc->clk);
 397         if (ret) {
 398                 dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
 399                         ret);
 400                 return ret;
 401         }
 402
 403         /* We cannot sample AUX/AUX2 in parallel. */
 404         mutex_lock(&adc->aux_lock);
 405         if (adc->soc_data->has_aux2 && engine == 0) {
 406                 bit = BIT(chan->channel == INGENIC_ADC_AUX2);
 407                 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_AUX_MD, bit);
 408         }
 409
 410         ret = ingenic_adc_capture(adc, engine);
 411         if (ret)
 412                 goto out;
 413
 414         switch (chan->channel) {
 415         case INGENIC_ADC_AUX:
 416         case INGENIC_ADC_AUX2:
 417                 *val = readw(adc->base + JZ_ADC_REG_ADSDAT);
 418                 break;
 419         case INGENIC_ADC_BATTERY:
 420                 *val = readw(adc->base + JZ_ADC_REG_ADBDAT);
 421                 break;
 422         }
 423
 424         ret = IIO_VAL_INT;
 425 out:
 426         mutex_unlock(&adc->aux_lock);
 427         clk_disable(adc->clk);
 428
 429         return ret;
 430 }
 431
 432 static int ingenic_adc_read_raw(struct iio_dev *iio_dev,
 433                                 struct iio_chan_spec const *chan,
 434                                 int *val,
 435                                 int *val2,
 436                                 long m)
 437 {
 438         struct ingenic_adc *adc = iio_priv(iio_dev);
 439
 440         switch (m) {
 441         case IIO_CHAN_INFO_RAW:
 442                 return ingenic_adc_read_chan_info_raw(iio_dev, chan, val);
 443         case IIO_CHAN_INFO_SCALE:
 444                 switch (chan->channel) {
 445                 case INGENIC_ADC_AUX:
 446                 case INGENIC_ADC_AUX2:
 447                         *val = JZ_ADC_AUX_VREF;
 448                         *val2 = JZ_ADC_AUX_VREF_BITS;
 449                         break;
 450                 case INGENIC_ADC_BATTERY:
 451                         if (adc->low_vref_mode) {
 452                                 *val = JZ_ADC_BATTERY_LOW_VREF;
 453                                 *val2 = JZ_ADC_BATTERY_LOW_VREF_BITS;
 454                         } else {
 455                                 *val = adc->soc_data->battery_high_vref;
 456                                 *val2 = adc->soc_data->battery_high_vref_bits;
 457                         }
 458                         break;
 459                 }
 460
 461                 return IIO_VAL_FRACTIONAL_LOG2;
 462         default:
 463                 return -EINVAL;
 464         }
 465 }
 466
 467 static int ingenic_adc_of_xlate(struct iio_dev *iio_dev,
 468                                 const struct of_phandle_args *iiospec)
 469 {
 470         int i;
 471
 472         if (!iiospec->args_count)
 473                 return -EINVAL;
 474
 475         for (i = 0; i < iio_dev->num_channels; ++i)
 476                 if (iio_dev->channels[i].channel == iiospec->args[0])
 477                         return i;
 478
 479         return -EINVAL;
 480 }
 481
 482 static void ingenic_adc_clk_cleanup(void *data)
 483 {
 484         clk_unprepare(data);
 485 }
 486
 487 static const struct iio_info ingenic_adc_info = {
 488         .write_raw = ingenic_adc_write_raw,
 489         .read_raw = ingenic_adc_read_raw,
 490         .read_avail = ingenic_adc_read_avail,
 491         .of_xlate = ingenic_adc_of_xlate,
 492 };
 493
 494 static int ingenic_adc_probe(struct platform_device *pdev)
 495 {
 496         struct device *dev = &pdev->dev;
 497         struct iio_dev *iio_dev;
 498         struct ingenic_adc *adc;
 499         const struct ingenic_adc_soc_data *soc_data;
 500         int ret;
 501
 502         soc_data = device_get_match_data(dev);
 503         if (!soc_data)
 504                 return -EINVAL;
 505
 506         iio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
 507         if (!iio_dev)
 508                 return -ENOMEM;
 509
 510         adc = iio_priv(iio_dev);
 511         mutex_init(&adc->lock);
 512         mutex_init(&adc->aux_lock);
 513         adc->soc_data = soc_data;
 514
 515         adc->base = devm_platform_ioremap_resource(pdev, 0);
 516         if (IS_ERR(adc->base))
 517                 return PTR_ERR(adc->base);
 518
 519         adc->clk = devm_clk_get(dev, "adc");
 520         if (IS_ERR(adc->clk)) {
 521                 dev_err(dev, "Unable to get clock\n");
 522                 return PTR_ERR(adc->clk);
 523         }
 524
 525         ret = clk_prepare_enable(adc->clk);
 526         if (ret) {
 527                 dev_err(dev, "Failed to enable clock\n");
 528                 return ret;
 529         }
 530
 531         /* Set clock dividers. */
 532         if (soc_data->init_clk_div) {
 533                 ret = soc_data->init_clk_div(dev, adc);
 534                 if (ret) {
 535                         clk_disable_unprepare(adc->clk);
 536                         return ret;
 537                 }
 538         }
 539
 540         /* Put hardware in a known passive state. */
 541         writeb(0x00, adc->base + JZ_ADC_REG_ENABLE);
 542         writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
 543         usleep_range(2000, 3000); /* Must wait at least 2ms. */
 544         clk_disable(adc->clk);
 545
 546         ret = devm_add_action_or_reset(dev, ingenic_adc_clk_cleanup, adc->clk);
 547         if (ret) {
 548                 dev_err(dev, "Unable to add action\n");
 549                 return ret;
 550         }
 551
 552         iio_dev->dev.parent = dev;
 553         iio_dev->name = "jz-adc";
 554         iio_dev->modes = INDIO_DIRECT_MODE;
 555         iio_dev->channels = soc_data->channels;
 556         iio_dev->num_channels = soc_data->num_channels;
 557         iio_dev->info = &ingenic_adc_info;
 558
 559         ret = devm_iio_device_register(dev, iio_dev);
 560         if (ret)
 561                 dev_err(dev, "Unable to register IIO device\n");
 562
 563         return ret;
 564 }
 565
 566 #ifdef CONFIG_OF
 567 static const struct of_device_id ingenic_adc_of_match[] = {
 568         { .compatible = "ingenic,jz4725b-adc", .data = &jz4725b_adc_soc_data, },
 569         { .compatible = "ingenic,jz4740-adc", .data = &jz4740_adc_soc_data, },
 570         { .compatible = "ingenic,jz4770-adc", .data = &jz4770_adc_soc_data, },
 571         { },
 572 };
 573 MODULE_DEVICE_TABLE(of, ingenic_adc_of_match);
 574 #endif
 575
 576 static struct platform_driver ingenic_adc_driver = {
 577         .driver = {
 578                 .name = "ingenic-adc",
 579                 .of_match_table = of_match_ptr(ingenic_adc_of_match),
 580         },
 581         .probe = ingenic_adc_probe,
 582 };
 583 module_platform_driver(ingenic_adc_driver);
 584 MODULE_LICENSE("GPL v2");