drivers/iio/adc/ingenic-adc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ADC driver for the Ingenic JZ47xx SoCs
   4  * Copyright (c) 2019 Artur Rojek <contact@artur-rojek.eu>
   5  *
   6  * based on drivers/mfd/jz4740-adc.c
   7  */
   8
   9 #include <dt-bindings/iio/adc/ingenic,adc.h>
  10 #include <linux/clk.h>
  11 #include <linux/iio/iio.h>
  12 #include <linux/io.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/mutex.h>
  17 #include <linux/platform_device.h>
  18
  19 #define JZ_ADC_REG_ENABLE               0x00
  20 #define JZ_ADC_REG_CFG                  0x04
  21 #define JZ_ADC_REG_CTRL                 0x08
  22 #define JZ_ADC_REG_STATUS               0x0c
  23 #define JZ_ADC_REG_ADTCH                0x18
  24 #define JZ_ADC_REG_ADBDAT               0x1c
  25 #define JZ_ADC_REG_ADSDAT               0x20
  26 #define JZ_ADC_REG_ADCLK                0x28
  27
  28 #define JZ_ADC_REG_ENABLE_PD            BIT(7)
  29 #define JZ_ADC_REG_CFG_AUX_MD           (BIT(0) | BIT(1))
  30 #define JZ_ADC_REG_CFG_BAT_MD           BIT(4)
  31 #define JZ_ADC_REG_ADCLK_CLKDIV_LSB     0
  32 #define JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB    16
  33 #define JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB     8
  34 #define JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB       16
  35
  36 #define JZ_ADC_AUX_VREF                         3300
  37 #define JZ_ADC_AUX_VREF_BITS                    12
  38 #define JZ_ADC_BATTERY_LOW_VREF                 2500
  39 #define JZ_ADC_BATTERY_LOW_VREF_BITS            12
  40 #define JZ4725B_ADC_BATTERY_HIGH_VREF           7500
  41 #define JZ4725B_ADC_BATTERY_HIGH_VREF_BITS      10
  42 #define JZ4740_ADC_BATTERY_HIGH_VREF            (7500 * 0.986)
  43 #define JZ4740_ADC_BATTERY_HIGH_VREF_BITS       12
  44 #define JZ4770_ADC_BATTERY_VREF                 6600
  45 #define JZ4770_ADC_BATTERY_VREF_BITS            12
  46
  47 struct ingenic_adc;
  48
  49 struct ingenic_adc_soc_data {
  50         unsigned int battery_high_vref;
  51         unsigned int battery_high_vref_bits;
  52         const int *battery_raw_avail;
  53         size_t battery_raw_avail_size;
  54         const int *battery_scale_avail;
  55         size_t battery_scale_avail_size;
  56         unsigned int battery_vref_mode: 1;
  57         unsigned int has_aux2: 1;
  58         int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
  59 };
  60
  61 struct ingenic_adc {
  62         void __iomem *base;
  63         struct clk *clk;
  64         struct mutex lock;
  65         struct mutex aux_lock;
  66         const struct ingenic_adc_soc_data *soc_data;
  67         bool low_vref_mode;
  68 };
  69
  70 static void ingenic_adc_set_config(struct ingenic_adc *adc,
  71                                    uint32_t mask,
  72                                    uint32_t val)
  73 {
  74         uint32_t cfg;
  75
  76         mutex_lock(&adc->lock);
  77
  78         cfg = readl(adc->base + JZ_ADC_REG_CFG) & ~mask;
  79         cfg |= val;
  80         writel(cfg, adc->base + JZ_ADC_REG_CFG);
  81
  82         mutex_unlock(&adc->lock);
  83 }
  84
  85 static void ingenic_adc_enable(struct ingenic_adc *adc,
  86                                int engine,
  87                                bool enabled)
  88 {
  89         u8 val;
  90
  91         mutex_lock(&adc->lock);
  92         val = readb(adc->base + JZ_ADC_REG_ENABLE);
  93
  94         if (enabled)
  95                 val |= BIT(engine);
  96         else
  97                 val &= ~BIT(engine);
  98
  99         writeb(val, adc->base + JZ_ADC_REG_ENABLE);
 100         mutex_unlock(&adc->lock);
 101 }
 102
 103 static int ingenic_adc_capture(struct ingenic_adc *adc,
 104                                int engine)
 105 {
 106         u8 val;
 107         int ret;
 108
 109         ingenic_adc_enable(adc, engine, true);
 110         ret = readb_poll_timeout(adc->base + JZ_ADC_REG_ENABLE, val,
 111                                  !(val & BIT(engine)), 250, 1000);
 112         if (ret)
 113                 ingenic_adc_enable(adc, engine, false);
 114
 115         return ret;
 116 }
 117
 118 static int ingenic_adc_write_raw(struct iio_dev *iio_dev,
 119                                  struct iio_chan_spec const *chan,
 120                                  int val,
 121                                  int val2,
 122                                  long m)
 123 {
 124         struct ingenic_adc *adc = iio_priv(iio_dev);
 125         struct device *dev = iio_dev->dev.parent;
 126         int ret;
 127
 128         switch (m) {
 129         case IIO_CHAN_INFO_SCALE:
 130                 switch (chan->channel) {
 131                 case INGENIC_ADC_BATTERY:
 132                         if (!adc->soc_data->battery_vref_mode)
 133                                 return -EINVAL;
 134
 135                         ret = clk_enable(adc->clk);
 136                         if (ret) {
 137                                 dev_err(dev, "Failed to enable clock: %d\n",
 138                                         ret);
 139                                 return ret;
 140                         }
 141
 142                         if (val > JZ_ADC_BATTERY_LOW_VREF) {
 143                                 ingenic_adc_set_config(adc,
 144                                                        JZ_ADC_REG_CFG_BAT_MD,
 145                                                        0);
 146                                 adc->low_vref_mode = false;
 147                         } else {
 148                                 ingenic_adc_set_config(adc,
 149                                                        JZ_ADC_REG_CFG_BAT_MD,
 150                                                        JZ_ADC_REG_CFG_BAT_MD);
 151                                 adc->low_vref_mode = true;
 152                         }
 153
 154                         clk_disable(adc->clk);
 155
 156                         return 0;
 157                 default:
 158                         return -EINVAL;
 159                 }
 160         default:
 161                 return -EINVAL;
 162         }
 163 }
 164
 165 static const int jz4725b_adc_battery_raw_avail[] = {
 166         0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
 167 };
 168
 169 static const int jz4725b_adc_battery_scale_avail[] = {
 170         JZ4725B_ADC_BATTERY_HIGH_VREF, JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
 171         JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
 172 };
 173
 174 static const int jz4740_adc_battery_raw_avail[] = {
 175         0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
 176 };
 177
 178 static const int jz4740_adc_battery_scale_avail[] = {
 179         JZ4740_ADC_BATTERY_HIGH_VREF, JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
 180         JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
 181 };
 182
 183 static const int jz4770_adc_battery_raw_avail[] = {
 184         0, 1, (1 << JZ4770_ADC_BATTERY_VREF_BITS) - 1,
 185 };
 186
 187 static const int jz4770_adc_battery_scale_avail[] = {
 188         JZ4770_ADC_BATTERY_VREF, JZ4770_ADC_BATTERY_VREF_BITS,
 189 };
 190
 191 static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
 192 {
 193         struct clk *parent_clk;
 194         unsigned long parent_rate, rate;
 195         unsigned int div_main, div_10us;
 196
 197         parent_clk = clk_get_parent(adc->clk);
 198         if (!parent_clk) {
 199                 dev_err(dev, "ADC clock has no parent\n");
 200                 return -ENODEV;
 201         }
 202         parent_rate = clk_get_rate(parent_clk);
 203
 204         /*
 205          * The JZ4725B ADC works at 500 kHz to 8 MHz.
 206          * We pick the highest rate possible.
 207          * In practice we typically get 6 MHz, half of the 12 MHz EXT clock.
 208          */
 209         div_main = DIV_ROUND_UP(parent_rate, 8000000);
 210         div_main = clamp(div_main, 1u, 64u);
 211         rate = parent_rate / div_main;
 212         if (rate < 500000 || rate > 8000000) {
 213                 dev_err(dev, "No valid divider for ADC main clock\n");
 214                 return -EINVAL;
 215         }
 216
 217         /* We also need a divider that produces a 10us clock. */
 218         div_10us = DIV_ROUND_UP(rate, 100000);
 219
 220         writel(((div_10us - 1) << JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB) |
 221                (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
 222                adc->base + JZ_ADC_REG_ADCLK);
 223
 224         return 0;
 225 }
 226
 227 static int jz4770_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
 228 {
 229         struct clk *parent_clk;
 230         unsigned long parent_rate, rate;
 231         unsigned int div_main, div_ms, div_10us;
 232
 233         parent_clk = clk_get_parent(adc->clk);
 234         if (!parent_clk) {
 235                 dev_err(dev, "ADC clock has no parent\n");
 236                 return -ENODEV;
 237         }
 238         parent_rate = clk_get_rate(parent_clk);
 239
 240         /*
 241          * The JZ4770 ADC works at 20 kHz to 200 kHz.
 242          * We pick the highest rate possible.
 243          */
 244         div_main = DIV_ROUND_UP(parent_rate, 200000);
 245         div_main = clamp(div_main, 1u, 256u);
 246         rate = parent_rate / div_main;
 247         if (rate < 20000 || rate > 200000) {
 248                 dev_err(dev, "No valid divider for ADC main clock\n");
 249                 return -EINVAL;
 250         }
 251
 252         /* We also need a divider that produces a 10us clock. */
 253         div_10us = DIV_ROUND_UP(rate, 10000);
 254         /* And another, which produces a 1ms clock. */
 255         div_ms = DIV_ROUND_UP(rate, 1000);
 256
 257         writel(((div_ms - 1) << JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB) |
 258                ((div_10us - 1) << JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB) |
 259                (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
 260                adc->base + JZ_ADC_REG_ADCLK);
 261
 262         return 0;
 263 }
 264
 265 static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = {
 266         .battery_high_vref = JZ4725B_ADC_BATTERY_HIGH_VREF,
 267         .battery_high_vref_bits = JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
 268         .battery_raw_avail = jz4725b_adc_battery_raw_avail,
 269         .battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail),
 270         .battery_scale_avail = jz4725b_adc_battery_scale_avail,
 271         .battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail),
 272         .battery_vref_mode = true,
 273         .has_aux2 = false,
 274         .init_clk_div = jz4725b_adc_init_clk_div,
 275 };
 276
 277 static const struct ingenic_adc_soc_data jz4740_adc_soc_data = {
 278         .battery_high_vref = JZ4740_ADC_BATTERY_HIGH_VREF,
 279         .battery_high_vref_bits = JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
 280         .battery_raw_avail = jz4740_adc_battery_raw_avail,
 281         .battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail),
 282         .battery_scale_avail = jz4740_adc_battery_scale_avail,
 283         .battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail),
 284         .battery_vref_mode = true,
 285         .has_aux2 = false,
 286         .init_clk_div = NULL, /* no ADCLK register on JZ4740 */
 287 };
 288
 289 static const struct ingenic_adc_soc_data jz4770_adc_soc_data = {
 290         .battery_high_vref = JZ4770_ADC_BATTERY_VREF,
 291         .battery_high_vref_bits = JZ4770_ADC_BATTERY_VREF_BITS,
 292         .battery_raw_avail = jz4770_adc_battery_raw_avail,
 293         .battery_raw_avail_size = ARRAY_SIZE(jz4770_adc_battery_raw_avail),
 294         .battery_scale_avail = jz4770_adc_battery_scale_avail,
 295         .battery_scale_avail_size = ARRAY_SIZE(jz4770_adc_battery_scale_avail),
 296         .battery_vref_mode = false,
 297         .has_aux2 = true,
 298         .init_clk_div = jz4770_adc_init_clk_div,
 299 };
 300
 301 static int ingenic_adc_read_avail(struct iio_dev *iio_dev,
 302                                   struct iio_chan_spec const *chan,
 303                                   const int **vals,
 304                                   int *type,
 305                                   int *length,
 306                                   long m)
 307 {
 308         struct ingenic_adc *adc = iio_priv(iio_dev);
 309
 310         switch (m) {
 311         case IIO_CHAN_INFO_RAW:
 312                 *type = IIO_VAL_INT;
 313                 *length = adc->soc_data->battery_raw_avail_size;
 314                 *vals = adc->soc_data->battery_raw_avail;
 315                 return IIO_AVAIL_RANGE;
 316         case IIO_CHAN_INFO_SCALE:
 317                 *type = IIO_VAL_FRACTIONAL_LOG2;
 318                 *length = adc->soc_data->battery_scale_avail_size;
 319                 *vals = adc->soc_data->battery_scale_avail;
 320                 return IIO_AVAIL_LIST;
 321         default:
 322                 return -EINVAL;
 323         };
 324 }
 325
 326 static int ingenic_adc_read_chan_info_raw(struct iio_dev *iio_dev,
 327                                           struct iio_chan_spec const *chan,
 328                                           int *val)
 329 {
 330         int bit, ret, engine = (chan->channel == INGENIC_ADC_BATTERY);
 331         struct ingenic_adc *adc = iio_priv(iio_dev);
 332
 333         ret = clk_enable(adc->clk);
 334         if (ret) {
 335                 dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
 336                         ret);
 337                 return ret;
 338         }
 339
 340         /* We cannot sample AUX/AUX2 in parallel. */
 341         mutex_lock(&adc->aux_lock);
 342         if (adc->soc_data->has_aux2 && engine == 0) {
 343                 bit = BIT(chan->channel == INGENIC_ADC_AUX2);
 344                 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_AUX_MD, bit);
 345         }
 346
 347         ret = ingenic_adc_capture(adc, engine);
 348         if (ret)
 349                 goto out;
 350
 351         switch (chan->channel) {
 352         case INGENIC_ADC_AUX:
 353         case INGENIC_ADC_AUX2:
 354                 *val = readw(adc->base + JZ_ADC_REG_ADSDAT);
 355                 break;
 356         case INGENIC_ADC_BATTERY:
 357                 *val = readw(adc->base + JZ_ADC_REG_ADBDAT);
 358                 break;
 359         }
 360
 361         ret = IIO_VAL_INT;
 362 out:
 363         mutex_unlock(&adc->aux_lock);
 364         clk_disable(adc->clk);
 365
 366         return ret;
 367 }
 368
 369 static int ingenic_adc_read_raw(struct iio_dev *iio_dev,
 370                                 struct iio_chan_spec const *chan,
 371                                 int *val,
 372                                 int *val2,
 373                                 long m)
 374 {
 375         struct ingenic_adc *adc = iio_priv(iio_dev);
 376
 377         switch (m) {
 378         case IIO_CHAN_INFO_RAW:
 379                 return ingenic_adc_read_chan_info_raw(iio_dev, chan, val);
 380         case IIO_CHAN_INFO_SCALE:
 381                 switch (chan->channel) {
 382                 case INGENIC_ADC_AUX:
 383                 case INGENIC_ADC_AUX2:
 384                         *val = JZ_ADC_AUX_VREF;
 385                         *val2 = JZ_ADC_AUX_VREF_BITS;
 386                         break;
 387                 case INGENIC_ADC_BATTERY:
 388                         if (adc->low_vref_mode) {
 389                                 *val = JZ_ADC_BATTERY_LOW_VREF;
 390                                 *val2 = JZ_ADC_BATTERY_LOW_VREF_BITS;
 391                         } else {
 392                                 *val = adc->soc_data->battery_high_vref;
 393                                 *val2 = adc->soc_data->battery_high_vref_bits;
 394                         }
 395                         break;
 396                 }
 397
 398                 return IIO_VAL_FRACTIONAL_LOG2;
 399         default:
 400                 return -EINVAL;
 401         }
 402 }
 403
 404 static int ingenic_adc_of_xlate(struct iio_dev *iio_dev,
 405                                 const struct of_phandle_args *iiospec)
 406 {
 407         int i;
 408
 409         if (!iiospec->args_count)
 410                 return -EINVAL;
 411
 412         for (i = 0; i < iio_dev->num_channels; ++i)
 413                 if (iio_dev->channels[i].channel == iiospec->args[0])
 414                         return i;
 415
 416         return -EINVAL;
 417 }
 418
 419 static void ingenic_adc_clk_cleanup(void *data)
 420 {
 421         clk_unprepare(data);
 422 }
 423
 424 static const struct iio_info ingenic_adc_info = {
 425         .write_raw = ingenic_adc_write_raw,
 426         .read_raw = ingenic_adc_read_raw,
 427         .read_avail = ingenic_adc_read_avail,
 428         .of_xlate = ingenic_adc_of_xlate,
 429 };
 430
 431 static const struct iio_chan_spec ingenic_channels[] = {
 432         {
 433                 .extend_name = "aux",
 434                 .type = IIO_VOLTAGE,
 435                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 436                                       BIT(IIO_CHAN_INFO_SCALE),
 437                 .indexed = 1,
 438                 .channel = INGENIC_ADC_AUX,
 439         },
 440         {
 441                 .extend_name = "battery",
 442                 .type = IIO_VOLTAGE,
 443                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 444                                       BIT(IIO_CHAN_INFO_SCALE),
 445                 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
 446                                                 BIT(IIO_CHAN_INFO_SCALE),
 447                 .indexed = 1,
 448                 .channel = INGENIC_ADC_BATTERY,
 449         },
 450         { /* Must always be last in the array. */
 451                 .extend_name = "aux2",
 452                 .type = IIO_VOLTAGE,
 453                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 454                                       BIT(IIO_CHAN_INFO_SCALE),
 455                 .indexed = 1,
 456                 .channel = INGENIC_ADC_AUX2,
 457         },
 458 };
 459
 460 static int ingenic_adc_probe(struct platform_device *pdev)
 461 {
 462         struct device *dev = &pdev->dev;
 463         struct iio_dev *iio_dev;
 464         struct ingenic_adc *adc;
 465         const struct ingenic_adc_soc_data *soc_data;
 466         int ret;
 467
 468         soc_data = device_get_match_data(dev);
 469         if (!soc_data)
 470                 return -EINVAL;
 471
 472         iio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
 473         if (!iio_dev)
 474                 return -ENOMEM;
 475
 476         adc = iio_priv(iio_dev);
 477         mutex_init(&adc->lock);
 478         mutex_init(&adc->aux_lock);
 479         adc->soc_data = soc_data;
 480
 481         adc->base = devm_platform_ioremap_resource(pdev, 0);
 482         if (IS_ERR(adc->base))
 483                 return PTR_ERR(adc->base);
 484
 485         adc->clk = devm_clk_get(dev, "adc");
 486         if (IS_ERR(adc->clk)) {
 487                 dev_err(dev, "Unable to get clock\n");
 488                 return PTR_ERR(adc->clk);
 489         }
 490
 491         ret = clk_prepare_enable(adc->clk);
 492         if (ret) {
 493                 dev_err(dev, "Failed to enable clock\n");
 494                 return ret;
 495         }
 496
 497         /* Set clock dividers. */
 498         if (soc_data->init_clk_div) {
 499                 ret = soc_data->init_clk_div(dev, adc);
 500                 if (ret) {
 501                         clk_disable_unprepare(adc->clk);
 502                         return ret;
 503                 }
 504         }
 505
 506         /* Put hardware in a known passive state. */
 507         writeb(0x00, adc->base + JZ_ADC_REG_ENABLE);
 508         writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
 509         usleep_range(2000, 3000); /* Must wait at least 2ms. */
 510         clk_disable(adc->clk);
 511
 512         ret = devm_add_action_or_reset(dev, ingenic_adc_clk_cleanup, adc->clk);
 513         if (ret) {
 514                 dev_err(dev, "Unable to add action\n");
 515                 return ret;
 516         }
 517
 518         iio_dev->dev.parent = dev;
 519         iio_dev->name = "jz-adc";
 520         iio_dev->modes = INDIO_DIRECT_MODE;
 521         iio_dev->channels = ingenic_channels;
 522         iio_dev->num_channels = ARRAY_SIZE(ingenic_channels);
 523         /* Remove AUX2 from the list of supported channels. */
 524         if (!adc->soc_data->has_aux2)
 525                 iio_dev->num_channels -= 1;
 526         iio_dev->info = &ingenic_adc_info;
 527
 528         ret = devm_iio_device_register(dev, iio_dev);
 529         if (ret)
 530                 dev_err(dev, "Unable to register IIO device\n");
 531
 532         return ret;
 533 }
 534
 535 #ifdef CONFIG_OF
 536 static const struct of_device_id ingenic_adc_of_match[] = {
 537         { .compatible = "ingenic,jz4725b-adc", .data = &jz4725b_adc_soc_data, },
 538         { .compatible = "ingenic,jz4740-adc", .data = &jz4740_adc_soc_data, },
 539         { .compatible = "ingenic,jz4770-adc", .data = &jz4770_adc_soc_data, },
 540         { },
 541 };
 542 MODULE_DEVICE_TABLE(of, ingenic_adc_of_match);
 543 #endif
 544
 545 static struct platform_driver ingenic_adc_driver = {
 546         .driver = {
 547                 .name = "ingenic-adc",
 548                 .of_match_table = of_match_ptr(ingenic_adc_of_match),
 549         },
 550         .probe = ingenic_adc_probe,
 551 };
 552 module_platform_driver(ingenic_adc_driver);
 553 MODULE_LICENSE("GPL v2");