drivers/iio/adc/ingenic-adc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ADC driver for the Ingenic JZ47xx SoCs
   4  * Copyright (c) 2019 Artur Rojek <contact@artur-rojek.eu>
   5  *
   6  * based on drivers/mfd/jz4740-adc.c
   7  */
   8
   9 #include <dt-bindings/iio/adc/ingenic,adc.h>
  10 #include <linux/clk.h>
  11 #include <linux/iio/buffer.h>
  12 #include <linux/iio/iio.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/mutex.h>
  19 #include <linux/platform_device.h>
  20
  21 #define JZ_ADC_REG_ENABLE               0x00
  22 #define JZ_ADC_REG_CFG                  0x04
  23 #define JZ_ADC_REG_CTRL                 0x08
  24 #define JZ_ADC_REG_STATUS               0x0c
  25 #define JZ_ADC_REG_ADSAME               0x10
  26 #define JZ_ADC_REG_ADWAIT               0x14
  27 #define JZ_ADC_REG_ADTCH                0x18
  28 #define JZ_ADC_REG_ADBDAT               0x1c
  29 #define JZ_ADC_REG_ADSDAT               0x20
  30 #define JZ_ADC_REG_ADCMD                0x24
  31 #define JZ_ADC_REG_ADCLK                0x28
  32
  33 #define JZ_ADC_REG_ENABLE_PD            BIT(7)
  34 #define JZ_ADC_REG_CFG_AUX_MD           (BIT(0) | BIT(1))
  35 #define JZ_ADC_REG_CFG_BAT_MD           BIT(4)
  36 #define JZ_ADC_REG_CFG_SAMPLE_NUM(n)    ((n) << 10)
  37 #define JZ_ADC_REG_CFG_PULL_UP(n)       ((n) << 16)
  38 #define JZ_ADC_REG_CFG_CMD_SEL          BIT(22)
  39 #define JZ_ADC_REG_CFG_TOUCH_OPS_MASK   (BIT(31) | GENMASK(23, 10))
  40 #define JZ_ADC_REG_ADCLK_CLKDIV_LSB     0
  41 #define JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB    16
  42 #define JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB     8
  43 #define JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB       16
  44
  45 #define JZ_ADC_REG_ADCMD_YNADC          BIT(7)
  46 #define JZ_ADC_REG_ADCMD_YPADC          BIT(8)
  47 #define JZ_ADC_REG_ADCMD_XNADC          BIT(9)
  48 #define JZ_ADC_REG_ADCMD_XPADC          BIT(10)
  49 #define JZ_ADC_REG_ADCMD_VREFPYP        BIT(11)
  50 #define JZ_ADC_REG_ADCMD_VREFPXP        BIT(12)
  51 #define JZ_ADC_REG_ADCMD_VREFPXN        BIT(13)
  52 #define JZ_ADC_REG_ADCMD_VREFPAUX       BIT(14)
  53 #define JZ_ADC_REG_ADCMD_VREFPVDD33     BIT(15)
  54 #define JZ_ADC_REG_ADCMD_VREFNYN        BIT(16)
  55 #define JZ_ADC_REG_ADCMD_VREFNXP        BIT(17)
  56 #define JZ_ADC_REG_ADCMD_VREFNXN        BIT(18)
  57 #define JZ_ADC_REG_ADCMD_VREFAUX        BIT(19)
  58 #define JZ_ADC_REG_ADCMD_YNGRU          BIT(20)
  59 #define JZ_ADC_REG_ADCMD_XNGRU          BIT(21)
  60 #define JZ_ADC_REG_ADCMD_XPGRU          BIT(22)
  61 #define JZ_ADC_REG_ADCMD_YPSUP          BIT(23)
  62 #define JZ_ADC_REG_ADCMD_XNSUP          BIT(24)
  63 #define JZ_ADC_REG_ADCMD_XPSUP          BIT(25)
  64
  65 #define JZ_ADC_AUX_VREF                         3300
  66 #define JZ_ADC_AUX_VREF_BITS                    12
  67 #define JZ_ADC_BATTERY_LOW_VREF                 2500
  68 #define JZ_ADC_BATTERY_LOW_VREF_BITS            12
  69 #define JZ4725B_ADC_BATTERY_HIGH_VREF           7500
  70 #define JZ4725B_ADC_BATTERY_HIGH_VREF_BITS      10
  71 #define JZ4740_ADC_BATTERY_HIGH_VREF            (7500 * 0.986)
  72 #define JZ4740_ADC_BATTERY_HIGH_VREF_BITS       12
  73 #define JZ4770_ADC_BATTERY_VREF                 6600
  74 #define JZ4770_ADC_BATTERY_VREF_BITS            12
  75
  76 #define JZ_ADC_IRQ_AUX                  BIT(0)
  77 #define JZ_ADC_IRQ_BATTERY              BIT(1)
  78 #define JZ_ADC_IRQ_TOUCH                BIT(2)
  79 #define JZ_ADC_IRQ_PEN_DOWN             BIT(3)
  80 #define JZ_ADC_IRQ_PEN_UP               BIT(4)
  81 #define JZ_ADC_IRQ_PEN_DOWN_SLEEP       BIT(5)
  82 #define JZ_ADC_IRQ_SLEEP                BIT(7)
  83
  84 struct ingenic_adc;
  85
  86 struct ingenic_adc_soc_data {
  87         unsigned int battery_high_vref;
  88         unsigned int battery_high_vref_bits;
  89         const int *battery_raw_avail;
  90         size_t battery_raw_avail_size;
  91         const int *battery_scale_avail;
  92         size_t battery_scale_avail_size;
  93         unsigned int battery_vref_mode: 1;
  94         unsigned int has_aux2: 1;
  95         const struct iio_chan_spec *channels;
  96         unsigned int num_channels;
  97         int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
  98 };
  99
 100 struct ingenic_adc {
 101         void __iomem *base;
 102         struct clk *clk;
 103         struct mutex lock;
 104         struct mutex aux_lock;
 105         const struct ingenic_adc_soc_data *soc_data;
 106         bool low_vref_mode;
 107 };
 108
 109 static void ingenic_adc_set_adcmd(struct iio_dev *iio_dev, unsigned long mask)
 110 {
 111         struct ingenic_adc *adc = iio_priv(iio_dev);
 112
 113         mutex_lock(&adc->lock);
 114
 115         /* Init ADCMD */
 116         readl(adc->base + JZ_ADC_REG_ADCMD);
 117
 118         if (mask & 0x3) {
 119                 /* Second channel (INGENIC_ADC_TOUCH_YP): sample YP vs. GND */
 120                 writel(JZ_ADC_REG_ADCMD_XNGRU
 121                        | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
 122                        | JZ_ADC_REG_ADCMD_YPADC,
 123                        adc->base + JZ_ADC_REG_ADCMD);
 124
 125                 /* First channel (INGENIC_ADC_TOUCH_XP): sample XP vs. GND */
 126                 writel(JZ_ADC_REG_ADCMD_YNGRU
 127                        | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
 128                        | JZ_ADC_REG_ADCMD_XPADC,
 129                        adc->base + JZ_ADC_REG_ADCMD);
 130         }
 131
 132         if (mask & 0xc) {
 133                 /* Fourth channel (INGENIC_ADC_TOUCH_YN): sample YN vs. GND */
 134                 writel(JZ_ADC_REG_ADCMD_XNGRU
 135                        | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
 136                        | JZ_ADC_REG_ADCMD_YNADC,
 137                        adc->base + JZ_ADC_REG_ADCMD);
 138
 139                 /* Third channel (INGENIC_ADC_TOUCH_XN): sample XN vs. GND */
 140                 writel(JZ_ADC_REG_ADCMD_YNGRU
 141                        | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
 142                        | JZ_ADC_REG_ADCMD_XNADC,
 143                        adc->base + JZ_ADC_REG_ADCMD);
 144         }
 145
 146         if (mask & 0x30) {
 147                 /* Sixth channel (INGENIC_ADC_TOUCH_YD): sample YP vs. YN */
 148                 writel(JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
 149                        | JZ_ADC_REG_ADCMD_YPADC,
 150                        adc->base + JZ_ADC_REG_ADCMD);
 151
 152                 /* Fifth channel (INGENIC_ADC_TOUCH_XD): sample XP vs. XN */
 153                 writel(JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
 154                        | JZ_ADC_REG_ADCMD_XPADC,
 155                        adc->base + JZ_ADC_REG_ADCMD);
 156         }
 157
 158         /* We're done */
 159         writel(0, adc->base + JZ_ADC_REG_ADCMD);
 160
 161         mutex_unlock(&adc->lock);
 162 }
 163
 164 static void ingenic_adc_set_config(struct ingenic_adc *adc,
 165                                    uint32_t mask,
 166                                    uint32_t val)
 167 {
 168         uint32_t cfg;
 169
 170         mutex_lock(&adc->lock);
 171
 172         cfg = readl(adc->base + JZ_ADC_REG_CFG) & ~mask;
 173         cfg |= val;
 174         writel(cfg, adc->base + JZ_ADC_REG_CFG);
 175
 176         mutex_unlock(&adc->lock);
 177 }
 178
 179 static void ingenic_adc_enable(struct ingenic_adc *adc,
 180                                int engine,
 181                                bool enabled)
 182 {
 183         u8 val;
 184
 185         mutex_lock(&adc->lock);
 186         val = readb(adc->base + JZ_ADC_REG_ENABLE);
 187
 188         if (enabled)
 189                 val |= BIT(engine);
 190         else
 191                 val &= ~BIT(engine);
 192
 193         writeb(val, adc->base + JZ_ADC_REG_ENABLE);
 194         mutex_unlock(&adc->lock);
 195 }
 196
 197 static int ingenic_adc_capture(struct ingenic_adc *adc,
 198                                int engine)
 199 {
 200         u8 val;
 201         int ret;
 202
 203         ingenic_adc_enable(adc, engine, true);
 204         ret = readb_poll_timeout(adc->base + JZ_ADC_REG_ENABLE, val,
 205                                  !(val & BIT(engine)), 250, 1000);
 206         if (ret)
 207                 ingenic_adc_enable(adc, engine, false);
 208
 209         return ret;
 210 }
 211
 212 static int ingenic_adc_write_raw(struct iio_dev *iio_dev,
 213                                  struct iio_chan_spec const *chan,
 214                                  int val,
 215                                  int val2,
 216                                  long m)
 217 {
 218         struct ingenic_adc *adc = iio_priv(iio_dev);
 219         struct device *dev = iio_dev->dev.parent;
 220         int ret;
 221
 222         switch (m) {
 223         case IIO_CHAN_INFO_SCALE:
 224                 switch (chan->channel) {
 225                 case INGENIC_ADC_BATTERY:
 226                         if (!adc->soc_data->battery_vref_mode)
 227                                 return -EINVAL;
 228
 229                         ret = clk_enable(adc->clk);
 230                         if (ret) {
 231                                 dev_err(dev, "Failed to enable clock: %d\n",
 232                                         ret);
 233                                 return ret;
 234                         }
 235
 236                         if (val > JZ_ADC_BATTERY_LOW_VREF) {
 237                                 ingenic_adc_set_config(adc,
 238                                                        JZ_ADC_REG_CFG_BAT_MD,
 239                                                        0);
 240                                 adc->low_vref_mode = false;
 241                         } else {
 242                                 ingenic_adc_set_config(adc,
 243                                                        JZ_ADC_REG_CFG_BAT_MD,
 244                                                        JZ_ADC_REG_CFG_BAT_MD);
 245                                 adc->low_vref_mode = true;
 246                         }
 247
 248                         clk_disable(adc->clk);
 249
 250                         return 0;
 251                 default:
 252                         return -EINVAL;
 253                 }
 254         default:
 255                 return -EINVAL;
 256         }
 257 }
 258
 259 static const int jz4725b_adc_battery_raw_avail[] = {
 260         0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
 261 };
 262
 263 static const int jz4725b_adc_battery_scale_avail[] = {
 264         JZ4725B_ADC_BATTERY_HIGH_VREF, JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
 265         JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
 266 };
 267
 268 static const int jz4740_adc_battery_raw_avail[] = {
 269         0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
 270 };
 271
 272 static const int jz4740_adc_battery_scale_avail[] = {
 273         JZ4740_ADC_BATTERY_HIGH_VREF, JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
 274         JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
 275 };
 276
 277 static const int jz4770_adc_battery_raw_avail[] = {
 278         0, 1, (1 << JZ4770_ADC_BATTERY_VREF_BITS) - 1,
 279 };
 280
 281 static const int jz4770_adc_battery_scale_avail[] = {
 282         JZ4770_ADC_BATTERY_VREF, JZ4770_ADC_BATTERY_VREF_BITS,
 283 };
 284
 285 static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
 286 {
 287         struct clk *parent_clk;
 288         unsigned long parent_rate, rate;
 289         unsigned int div_main, div_10us;
 290
 291         parent_clk = clk_get_parent(adc->clk);
 292         if (!parent_clk) {
 293                 dev_err(dev, "ADC clock has no parent\n");
 294                 return -ENODEV;
 295         }
 296         parent_rate = clk_get_rate(parent_clk);
 297
 298         /*
 299          * The JZ4725B ADC works at 500 kHz to 8 MHz.
 300          * We pick the highest rate possible.
 301          * In practice we typically get 6 MHz, half of the 12 MHz EXT clock.
 302          */
 303         div_main = DIV_ROUND_UP(parent_rate, 8000000);
 304         div_main = clamp(div_main, 1u, 64u);
 305         rate = parent_rate / div_main;
 306         if (rate < 500000 || rate > 8000000) {
 307                 dev_err(dev, "No valid divider for ADC main clock\n");
 308                 return -EINVAL;
 309         }
 310
 311         /* We also need a divider that produces a 10us clock. */
 312         div_10us = DIV_ROUND_UP(rate, 100000);
 313
 314         writel(((div_10us - 1) << JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB) |
 315                (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
 316                adc->base + JZ_ADC_REG_ADCLK);
 317
 318         return 0;
 319 }
 320
 321 static int jz4770_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
 322 {
 323         struct clk *parent_clk;
 324         unsigned long parent_rate, rate;
 325         unsigned int div_main, div_ms, div_10us;
 326
 327         parent_clk = clk_get_parent(adc->clk);
 328         if (!parent_clk) {
 329                 dev_err(dev, "ADC clock has no parent\n");
 330                 return -ENODEV;
 331         }
 332         parent_rate = clk_get_rate(parent_clk);
 333
 334         /*
 335          * The JZ4770 ADC works at 20 kHz to 200 kHz.
 336          * We pick the highest rate possible.
 337          */
 338         div_main = DIV_ROUND_UP(parent_rate, 200000);
 339         div_main = clamp(div_main, 1u, 256u);
 340         rate = parent_rate / div_main;
 341         if (rate < 20000 || rate > 200000) {
 342                 dev_err(dev, "No valid divider for ADC main clock\n");
 343                 return -EINVAL;
 344         }
 345
 346         /* We also need a divider that produces a 10us clock. */
 347         div_10us = DIV_ROUND_UP(rate, 10000);
 348         /* And another, which produces a 1ms clock. */
 349         div_ms = DIV_ROUND_UP(rate, 1000);
 350
 351         writel(((div_ms - 1) << JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB) |
 352                ((div_10us - 1) << JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB) |
 353                (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
 354                adc->base + JZ_ADC_REG_ADCLK);
 355
 356         return 0;
 357 }
 358
 359 static const struct iio_chan_spec jz4740_channels[] = {
 360         {
 361                 .extend_name = "aux",
 362                 .type = IIO_VOLTAGE,
 363                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 364                                       BIT(IIO_CHAN_INFO_SCALE),
 365                 .indexed = 1,
 366                 .channel = INGENIC_ADC_AUX,
 367                 .scan_index = -1,
 368         },
 369         {
 370                 .extend_name = "battery",
 371                 .type = IIO_VOLTAGE,
 372                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 373                                       BIT(IIO_CHAN_INFO_SCALE),
 374                 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
 375                                                 BIT(IIO_CHAN_INFO_SCALE),
 376                 .indexed = 1,
 377                 .channel = INGENIC_ADC_BATTERY,
 378                 .scan_index = -1,
 379         },
 380 };
 381
 382 static const struct iio_chan_spec jz4770_channels[] = {
 383         {
 384                 .type = IIO_VOLTAGE,
 385                 .indexed = 1,
 386                 .channel = INGENIC_ADC_TOUCH_XP,
 387                 .scan_index = 0,
 388                 .scan_type = {
 389                         .sign = 'u',
 390                         .realbits = 12,
 391                         .storagebits = 16,
 392                 },
 393         },
 394         {
 395                 .type = IIO_VOLTAGE,
 396                 .indexed = 1,
 397                 .channel = INGENIC_ADC_TOUCH_YP,
 398                 .scan_index = 1,
 399                 .scan_type = {
 400                         .sign = 'u',
 401                         .realbits = 12,
 402                         .storagebits = 16,
 403                 },
 404         },
 405         {
 406                 .type = IIO_VOLTAGE,
 407                 .indexed = 1,
 408                 .channel = INGENIC_ADC_TOUCH_XN,
 409                 .scan_index = 2,
 410                 .scan_type = {
 411                         .sign = 'u',
 412                         .realbits = 12,
 413                         .storagebits = 16,
 414                 },
 415         },
 416         {
 417                 .type = IIO_VOLTAGE,
 418                 .indexed = 1,
 419                 .channel = INGENIC_ADC_TOUCH_YN,
 420                 .scan_index = 3,
 421                 .scan_type = {
 422                         .sign = 'u',
 423                         .realbits = 12,
 424                         .storagebits = 16,
 425                 },
 426         },
 427         {
 428                 .type = IIO_VOLTAGE,
 429                 .indexed = 1,
 430                 .channel = INGENIC_ADC_TOUCH_XD,
 431                 .scan_index = 4,
 432                 .scan_type = {
 433                         .sign = 'u',
 434                         .realbits = 12,
 435                         .storagebits = 16,
 436                 },
 437         },
 438         {
 439                 .type = IIO_VOLTAGE,
 440                 .indexed = 1,
 441                 .channel = INGENIC_ADC_TOUCH_YD,
 442                 .scan_index = 5,
 443                 .scan_type = {
 444                         .sign = 'u',
 445                         .realbits = 12,
 446                         .storagebits = 16,
 447                 },
 448         },
 449         {
 450                 .extend_name = "aux",
 451                 .type = IIO_VOLTAGE,
 452                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 453                                       BIT(IIO_CHAN_INFO_SCALE),
 454                 .indexed = 1,
 455                 .channel = INGENIC_ADC_AUX,
 456                 .scan_index = -1,
 457         },
 458         {
 459                 .extend_name = "battery",
 460                 .type = IIO_VOLTAGE,
 461                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 462                                       BIT(IIO_CHAN_INFO_SCALE),
 463                 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
 464                                                 BIT(IIO_CHAN_INFO_SCALE),
 465                 .indexed = 1,
 466                 .channel = INGENIC_ADC_BATTERY,
 467                 .scan_index = -1,
 468         },
 469         {
 470                 .extend_name = "aux2",
 471                 .type = IIO_VOLTAGE,
 472                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 473                                       BIT(IIO_CHAN_INFO_SCALE),
 474                 .indexed = 1,
 475                 .channel = INGENIC_ADC_AUX2,
 476                 .scan_index = -1,
 477         },
 478 };
 479
 480 static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = {
 481         .battery_high_vref = JZ4725B_ADC_BATTERY_HIGH_VREF,
 482         .battery_high_vref_bits = JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
 483         .battery_raw_avail = jz4725b_adc_battery_raw_avail,
 484         .battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail),
 485         .battery_scale_avail = jz4725b_adc_battery_scale_avail,
 486         .battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail),
 487         .battery_vref_mode = true,
 488         .has_aux2 = false,
 489         .channels = jz4740_channels,
 490         .num_channels = ARRAY_SIZE(jz4740_channels),
 491         .init_clk_div = jz4725b_adc_init_clk_div,
 492 };
 493
 494 static const struct ingenic_adc_soc_data jz4740_adc_soc_data = {
 495         .battery_high_vref = JZ4740_ADC_BATTERY_HIGH_VREF,
 496         .battery_high_vref_bits = JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
 497         .battery_raw_avail = jz4740_adc_battery_raw_avail,
 498         .battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail),
 499         .battery_scale_avail = jz4740_adc_battery_scale_avail,
 500         .battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail),
 501         .battery_vref_mode = true,
 502         .has_aux2 = false,
 503         .channels = jz4740_channels,
 504         .num_channels = ARRAY_SIZE(jz4740_channels),
 505         .init_clk_div = NULL, /* no ADCLK register on JZ4740 */
 506 };
 507
 508 static const struct ingenic_adc_soc_data jz4770_adc_soc_data = {
 509         .battery_high_vref = JZ4770_ADC_BATTERY_VREF,
 510         .battery_high_vref_bits = JZ4770_ADC_BATTERY_VREF_BITS,
 511         .battery_raw_avail = jz4770_adc_battery_raw_avail,
 512         .battery_raw_avail_size = ARRAY_SIZE(jz4770_adc_battery_raw_avail),
 513         .battery_scale_avail = jz4770_adc_battery_scale_avail,
 514         .battery_scale_avail_size = ARRAY_SIZE(jz4770_adc_battery_scale_avail),
 515         .battery_vref_mode = false,
 516         .has_aux2 = true,
 517         .channels = jz4770_channels,
 518         .num_channels = ARRAY_SIZE(jz4770_channels),
 519         .init_clk_div = jz4770_adc_init_clk_div,
 520 };
 521
 522 static int ingenic_adc_read_avail(struct iio_dev *iio_dev,
 523                                   struct iio_chan_spec const *chan,
 524                                   const int **vals,
 525                                   int *type,
 526                                   int *length,
 527                                   long m)
 528 {
 529         struct ingenic_adc *adc = iio_priv(iio_dev);
 530
 531         switch (m) {
 532         case IIO_CHAN_INFO_RAW:
 533                 *type = IIO_VAL_INT;
 534                 *length = adc->soc_data->battery_raw_avail_size;
 535                 *vals = adc->soc_data->battery_raw_avail;
 536                 return IIO_AVAIL_RANGE;
 537         case IIO_CHAN_INFO_SCALE:
 538                 *type = IIO_VAL_FRACTIONAL_LOG2;
 539                 *length = adc->soc_data->battery_scale_avail_size;
 540                 *vals = adc->soc_data->battery_scale_avail;
 541                 return IIO_AVAIL_LIST;
 542         default:
 543                 return -EINVAL;
 544         };
 545 }
 546
 547 static int ingenic_adc_read_chan_info_raw(struct iio_dev *iio_dev,
 548                                           struct iio_chan_spec const *chan,
 549                                           int *val)
 550 {
 551         int bit, ret, engine = (chan->channel == INGENIC_ADC_BATTERY);
 552         struct ingenic_adc *adc = iio_priv(iio_dev);
 553
 554         ret = clk_enable(adc->clk);
 555         if (ret) {
 556                 dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
 557                         ret);
 558                 return ret;
 559         }
 560
 561         /* We cannot sample AUX/AUX2 in parallel. */
 562         mutex_lock(&adc->aux_lock);
 563         if (adc->soc_data->has_aux2 && engine == 0) {
 564                 bit = BIT(chan->channel == INGENIC_ADC_AUX2);
 565                 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_AUX_MD, bit);
 566         }
 567
 568         ret = ingenic_adc_capture(adc, engine);
 569         if (ret)
 570                 goto out;
 571
 572         switch (chan->channel) {
 573         case INGENIC_ADC_AUX:
 574         case INGENIC_ADC_AUX2:
 575                 *val = readw(adc->base + JZ_ADC_REG_ADSDAT);
 576                 break;
 577         case INGENIC_ADC_BATTERY:
 578                 *val = readw(adc->base + JZ_ADC_REG_ADBDAT);
 579                 break;
 580         }
 581
 582         ret = IIO_VAL_INT;
 583 out:
 584         mutex_unlock(&adc->aux_lock);
 585         clk_disable(adc->clk);
 586
 587         return ret;
 588 }
 589
 590 static int ingenic_adc_read_raw(struct iio_dev *iio_dev,
 591                                 struct iio_chan_spec const *chan,
 592                                 int *val,
 593                                 int *val2,
 594                                 long m)
 595 {
 596         struct ingenic_adc *adc = iio_priv(iio_dev);
 597
 598         switch (m) {
 599         case IIO_CHAN_INFO_RAW:
 600                 return ingenic_adc_read_chan_info_raw(iio_dev, chan, val);
 601         case IIO_CHAN_INFO_SCALE:
 602                 switch (chan->channel) {
 603                 case INGENIC_ADC_AUX:
 604                 case INGENIC_ADC_AUX2:
 605                         *val = JZ_ADC_AUX_VREF;
 606                         *val2 = JZ_ADC_AUX_VREF_BITS;
 607                         break;
 608                 case INGENIC_ADC_BATTERY:
 609                         if (adc->low_vref_mode) {
 610                                 *val = JZ_ADC_BATTERY_LOW_VREF;
 611                                 *val2 = JZ_ADC_BATTERY_LOW_VREF_BITS;
 612                         } else {
 613                                 *val = adc->soc_data->battery_high_vref;
 614                                 *val2 = adc->soc_data->battery_high_vref_bits;
 615                         }
 616                         break;
 617                 }
 618
 619                 return IIO_VAL_FRACTIONAL_LOG2;
 620         default:
 621                 return -EINVAL;
 622         }
 623 }
 624
 625 static int ingenic_adc_of_xlate(struct iio_dev *iio_dev,
 626                                 const struct of_phandle_args *iiospec)
 627 {
 628         int i;
 629
 630         if (!iiospec->args_count)
 631                 return -EINVAL;
 632
 633         for (i = 0; i < iio_dev->num_channels; ++i)
 634                 if (iio_dev->channels[i].channel == iiospec->args[0])
 635                         return i;
 636
 637         return -EINVAL;
 638 }
 639
 640 static void ingenic_adc_clk_cleanup(void *data)
 641 {
 642         clk_unprepare(data);
 643 }
 644
 645 static const struct iio_info ingenic_adc_info = {
 646         .write_raw = ingenic_adc_write_raw,
 647         .read_raw = ingenic_adc_read_raw,
 648         .read_avail = ingenic_adc_read_avail,
 649         .of_xlate = ingenic_adc_of_xlate,
 650 };
 651
 652 static int ingenic_adc_buffer_enable(struct iio_dev *iio_dev)
 653 {
 654         struct ingenic_adc *adc = iio_priv(iio_dev);
 655         int ret;
 656
 657         ret = clk_enable(adc->clk);
 658         if (ret) {
 659                 dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
 660                         ret);
 661                 return ret;
 662         }
 663
 664         /* It takes significant time for the touchscreen hw to stabilize. */
 665         msleep(50);
 666         ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK,
 667                                JZ_ADC_REG_CFG_SAMPLE_NUM(4) |
 668                                JZ_ADC_REG_CFG_PULL_UP(4));
 669
 670         writew(80, adc->base + JZ_ADC_REG_ADWAIT);
 671         writew(2, adc->base + JZ_ADC_REG_ADSAME);
 672         writeb((u8)~JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_CTRL);
 673         writel(0, adc->base + JZ_ADC_REG_ADTCH);
 674
 675         ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL,
 676                                JZ_ADC_REG_CFG_CMD_SEL);
 677         ingenic_adc_set_adcmd(iio_dev, iio_dev->active_scan_mask[0]);
 678
 679         ingenic_adc_enable(adc, 2, true);
 680
 681         return 0;
 682 }
 683
 684 static int ingenic_adc_buffer_disable(struct iio_dev *iio_dev)
 685 {
 686         struct ingenic_adc *adc = iio_priv(iio_dev);
 687
 688         ingenic_adc_enable(adc, 2, false);
 689
 690         ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL, 0);
 691
 692         writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
 693         writeb(0xff, adc->base + JZ_ADC_REG_STATUS);
 694         ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK, 0);
 695         writew(0, adc->base + JZ_ADC_REG_ADSAME);
 696         writew(0, adc->base + JZ_ADC_REG_ADWAIT);
 697         clk_disable(adc->clk);
 698
 699         return 0;
 700 }
 701
 702 static const struct iio_buffer_setup_ops ingenic_buffer_setup_ops = {
 703         .postenable = &ingenic_adc_buffer_enable,
 704         .predisable = &ingenic_adc_buffer_disable
 705 };
 706
 707 static irqreturn_t ingenic_adc_irq(int irq, void *data)
 708 {
 709         struct iio_dev *iio_dev = data;
 710         struct ingenic_adc *adc = iio_priv(iio_dev);
 711         unsigned long mask = iio_dev->active_scan_mask[0];
 712         unsigned int i;
 713         u32 tdat[3];
 714
 715         for (i = 0; i < ARRAY_SIZE(tdat); mask >>= 2, i++) {
 716                 if (mask & 0x3)
 717                         tdat[i] = readl(adc->base + JZ_ADC_REG_ADTCH);
 718                 else
 719                         tdat[i] = 0;
 720         }
 721
 722         iio_push_to_buffers(iio_dev, tdat);
 723         writeb(JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_STATUS);
 724
 725         return IRQ_HANDLED;
 726 }
 727
 728 static int ingenic_adc_probe(struct platform_device *pdev)
 729 {
 730         struct device *dev = &pdev->dev;
 731         struct iio_dev *iio_dev;
 732         struct ingenic_adc *adc;
 733         const struct ingenic_adc_soc_data *soc_data;
 734         int irq, ret;
 735
 736         soc_data = device_get_match_data(dev);
 737         if (!soc_data)
 738                 return -EINVAL;
 739
 740         iio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
 741         if (!iio_dev)
 742                 return -ENOMEM;
 743
 744         adc = iio_priv(iio_dev);
 745         mutex_init(&adc->lock);
 746         mutex_init(&adc->aux_lock);
 747         adc->soc_data = soc_data;
 748
 749         irq = platform_get_irq(pdev, 0);
 750         if (irq < 0)
 751                 return irq;
 752
 753         ret = devm_request_irq(dev, irq, ingenic_adc_irq, 0,
 754                                dev_name(dev), iio_dev);
 755         if (ret < 0) {
 756                 dev_err(dev, "Failed to request irq: %d\n", ret);
 757                 return ret;
 758         }
 759
 760         adc->base = devm_platform_ioremap_resource(pdev, 0);
 761         if (IS_ERR(adc->base))
 762                 return PTR_ERR(adc->base);
 763
 764         adc->clk = devm_clk_get(dev, "adc");
 765         if (IS_ERR(adc->clk)) {
 766                 dev_err(dev, "Unable to get clock\n");
 767                 return PTR_ERR(adc->clk);
 768         }
 769
 770         ret = clk_prepare_enable(adc->clk);
 771         if (ret) {
 772                 dev_err(dev, "Failed to enable clock\n");
 773                 return ret;
 774         }
 775
 776         /* Set clock dividers. */
 777         if (soc_data->init_clk_div) {
 778                 ret = soc_data->init_clk_div(dev, adc);
 779                 if (ret) {
 780                         clk_disable_unprepare(adc->clk);
 781                         return ret;
 782                 }
 783         }
 784
 785         /* Put hardware in a known passive state. */
 786         writeb(0x00, adc->base + JZ_ADC_REG_ENABLE);
 787         writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
 788         usleep_range(2000, 3000); /* Must wait at least 2ms. */
 789         clk_disable(adc->clk);
 790
 791         ret = devm_add_action_or_reset(dev, ingenic_adc_clk_cleanup, adc->clk);
 792         if (ret) {
 793                 dev_err(dev, "Unable to add action\n");
 794                 return ret;
 795         }
 796
 797         iio_dev->dev.parent = dev;
 798         iio_dev->name = "jz-adc";
 799         iio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
 800         iio_dev->setup_ops = &ingenic_buffer_setup_ops;
 801         iio_dev->channels = soc_data->channels;
 802         iio_dev->num_channels = soc_data->num_channels;
 803         iio_dev->info = &ingenic_adc_info;
 804
 805         ret = devm_iio_device_register(dev, iio_dev);
 806         if (ret)
 807                 dev_err(dev, "Unable to register IIO device\n");
 808
 809         return ret;
 810 }
 811
 812 #ifdef CONFIG_OF
 813 static const struct of_device_id ingenic_adc_of_match[] = {
 814         { .compatible = "ingenic,jz4725b-adc", .data = &jz4725b_adc_soc_data, },
 815         { .compatible = "ingenic,jz4740-adc", .data = &jz4740_adc_soc_data, },
 816         { .compatible = "ingenic,jz4770-adc", .data = &jz4770_adc_soc_data, },
 817         { },
 818 };
 819 MODULE_DEVICE_TABLE(of, ingenic_adc_of_match);
 820 #endif
 821
 822 static struct platform_driver ingenic_adc_driver = {
 823         .driver = {
 824                 .name = "ingenic-adc",
 825                 .of_match_table = of_match_ptr(ingenic_adc_of_match),
 826         },
 827         .probe = ingenic_adc_probe,
 828 };
 829 module_platform_driver(ingenic_adc_driver);
 830 MODULE_LICENSE("GPL v2");