2 * mma8452.c - Support for Freescale MMA8452Q 3-axis 12-bit accelerometer
4 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
6 * This file is subject to the terms and conditions of version 2 of
7 * the GNU General Public License. See the file COPYING in the main
8 * directory of this archive for more details.
10 * 7-bit I2C slave address 0x1c/0x1d (pin selectable)
12 * TODO: orientation / freefall events, autosleep
15 #include <linux/module.h>
16 #include <linux/i2c.h>
17 #include <linux/iio/iio.h>
18 #include <linux/iio/sysfs.h>
19 #include <linux/iio/trigger_consumer.h>
20 #include <linux/iio/buffer.h>
21 #include <linux/iio/triggered_buffer.h>
22 #include <linux/iio/events.h>
23 #include <linux/delay.h>
25 #define MMA8452_STATUS 0x00
26 #define MMA8452_OUT_X 0x01 /* MSB first, 12-bit */
27 #define MMA8452_OUT_Y 0x03
28 #define MMA8452_OUT_Z 0x05
29 #define MMA8452_INT_SRC 0x0c
30 #define MMA8452_WHO_AM_I 0x0d
31 #define MMA8452_DATA_CFG 0x0e
32 #define MMA8452_TRANSIENT_CFG 0x1d
33 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
34 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
35 #define MMA8452_TRANSIENT_SRC 0x1e
36 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
37 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
38 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
39 #define MMA8452_TRANSIENT_THS 0x1f
40 #define MMA8452_TRANSIENT_THS_MASK 0x7f
41 #define MMA8452_OFF_X 0x2f
42 #define MMA8452_OFF_Y 0x30
43 #define MMA8452_OFF_Z 0x31
44 #define MMA8452_CTRL_REG1 0x2a
45 #define MMA8452_CTRL_REG2 0x2b
46 #define MMA8452_CTRL_REG2_RST BIT(6)
47 #define MMA8452_CTRL_REG4 0x2d
48 #define MMA8452_CTRL_REG5 0x2e
50 #define MMA8452_MAX_REG 0x31
52 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
54 #define MMA8452_CTRL_DR_MASK (BIT(5) | BIT(4) | BIT(3))
55 #define MMA8452_CTRL_DR_SHIFT 3
56 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
57 #define MMA8452_CTRL_ACTIVE BIT(0)
59 #define MMA8452_DATA_CFG_FS_MASK (BIT(1) | BIT(0))
60 #define MMA8452_DATA_CFG_FS_2G 0
61 #define MMA8452_DATA_CFG_FS_4G 1
62 #define MMA8452_DATA_CFG_FS_8G 2
64 #define MMA8452_INT_TRANS BIT(5)
66 #define MMA8452_DEVICE_ID 0x2a
69 struct i2c_client *client;
75 static int mma8452_drdy(struct mma8452_data *data)
80 int ret = i2c_smbus_read_byte_data(data->client,
84 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
89 dev_err(&data->client->dev, "data not ready\n");
93 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
95 int ret = mma8452_drdy(data);
98 return i2c_smbus_read_i2c_block_data(data->client,
99 MMA8452_OUT_X, 3 * sizeof(__be16), (u8 *) buf);
102 static ssize_t mma8452_show_int_plus_micros(char *buf,
103 const int (*vals)[2], int n)
108 len += scnprintf(buf + len, PAGE_SIZE - len,
109 "%d.%06d ", vals[n][0], vals[n][1]);
111 /* replace trailing space by newline */
117 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
121 if (val == vals[n][0] && val2 == vals[n][1])
127 static const int mma8452_samp_freq[8][2] = {
128 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
129 {6, 250000}, {1, 560000}
133 * Hardware has fullscale of -2G, -4G, -8G corresponding to raw value -2048
134 * The userspace interface uses m/s^2 and we declare micro units
135 * So scale factor is given by:
136 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
138 static const int mma8452_scales[3][2] = {
139 {0, 9577}, {0, 19154}, {0, 38307}
142 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
143 struct device_attribute *attr, char *buf)
145 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
146 ARRAY_SIZE(mma8452_samp_freq));
149 static ssize_t mma8452_show_scale_avail(struct device *dev,
150 struct device_attribute *attr, char *buf)
152 return mma8452_show_int_plus_micros(buf, mma8452_scales,
153 ARRAY_SIZE(mma8452_scales));
156 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
157 static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
158 mma8452_show_scale_avail, NULL, 0);
160 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
163 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
164 ARRAY_SIZE(mma8452_samp_freq), val, val2);
167 static int mma8452_get_scale_index(struct mma8452_data *data,
170 return mma8452_get_int_plus_micros_index(mma8452_scales,
171 ARRAY_SIZE(mma8452_scales), val, val2);
174 static int mma8452_read_raw(struct iio_dev *indio_dev,
175 struct iio_chan_spec const *chan,
176 int *val, int *val2, long mask)
178 struct mma8452_data *data = iio_priv(indio_dev);
183 case IIO_CHAN_INFO_RAW:
184 if (iio_buffer_enabled(indio_dev))
187 mutex_lock(&data->lock);
188 ret = mma8452_read(data, buffer);
189 mutex_unlock(&data->lock);
192 *val = sign_extend32(
193 be16_to_cpu(buffer[chan->scan_index]) >> 4, 11);
195 case IIO_CHAN_INFO_SCALE:
196 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
197 *val = mma8452_scales[i][0];
198 *val2 = mma8452_scales[i][1];
199 return IIO_VAL_INT_PLUS_MICRO;
200 case IIO_CHAN_INFO_SAMP_FREQ:
201 i = (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
202 MMA8452_CTRL_DR_SHIFT;
203 *val = mma8452_samp_freq[i][0];
204 *val2 = mma8452_samp_freq[i][1];
205 return IIO_VAL_INT_PLUS_MICRO;
206 case IIO_CHAN_INFO_CALIBBIAS:
207 ret = i2c_smbus_read_byte_data(data->client, MMA8452_OFF_X +
211 *val = sign_extend32(ret, 7);
217 static int mma8452_standby(struct mma8452_data *data)
219 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
220 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
223 static int mma8452_active(struct mma8452_data *data)
225 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
229 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
233 mutex_lock(&data->lock);
235 /* config can only be changed when in standby */
236 ret = mma8452_standby(data);
240 ret = i2c_smbus_write_byte_data(data->client, reg, val);
244 ret = mma8452_active(data);
250 mutex_unlock(&data->lock);
254 static int mma8452_write_raw(struct iio_dev *indio_dev,
255 struct iio_chan_spec const *chan,
256 int val, int val2, long mask)
258 struct mma8452_data *data = iio_priv(indio_dev);
261 if (iio_buffer_enabled(indio_dev))
265 case IIO_CHAN_INFO_SAMP_FREQ:
266 i = mma8452_get_samp_freq_index(data, val, val2);
270 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
271 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
272 return mma8452_change_config(data, MMA8452_CTRL_REG1,
274 case IIO_CHAN_INFO_SCALE:
275 i = mma8452_get_scale_index(data, val, val2);
278 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
280 return mma8452_change_config(data, MMA8452_DATA_CFG,
282 case IIO_CHAN_INFO_CALIBBIAS:
283 if (val < -128 || val > 127)
285 return mma8452_change_config(data, MMA8452_OFF_X +
286 chan->scan_index, val);
292 static int mma8452_read_thresh(struct iio_dev *indio_dev,
293 const struct iio_chan_spec *chan,
294 enum iio_event_type type,
295 enum iio_event_direction dir,
296 enum iio_event_info info,
299 struct mma8452_data *data = iio_priv(indio_dev);
302 ret = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_THS);
306 *val = ret & MMA8452_TRANSIENT_THS_MASK;
311 static int mma8452_write_thresh(struct iio_dev *indio_dev,
312 const struct iio_chan_spec *chan,
313 enum iio_event_type type,
314 enum iio_event_direction dir,
315 enum iio_event_info info,
318 struct mma8452_data *data = iio_priv(indio_dev);
320 return mma8452_change_config(data, MMA8452_TRANSIENT_THS,
321 val & MMA8452_TRANSIENT_THS_MASK);
324 static int mma8452_read_event_config(struct iio_dev *indio_dev,
325 const struct iio_chan_spec *chan,
326 enum iio_event_type type,
327 enum iio_event_direction dir)
329 struct mma8452_data *data = iio_priv(indio_dev);
332 ret = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_CFG);
336 return ret & MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index) ? 1 : 0;
339 static int mma8452_write_event_config(struct iio_dev *indio_dev,
340 const struct iio_chan_spec *chan,
341 enum iio_event_type type,
342 enum iio_event_direction dir,
345 struct mma8452_data *data = iio_priv(indio_dev);
348 val = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_CFG);
353 val |= MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index);
355 val &= ~MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index);
357 val |= MMA8452_TRANSIENT_CFG_ELE;
359 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, val);
362 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
364 struct mma8452_data *data = iio_priv(indio_dev);
365 s64 ts = iio_get_time_ns();
368 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
372 if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
373 iio_push_event(indio_dev,
374 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
379 if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
380 iio_push_event(indio_dev,
381 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
386 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
387 iio_push_event(indio_dev,
388 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
394 static irqreturn_t mma8452_interrupt(int irq, void *p)
396 struct iio_dev *indio_dev = p;
397 struct mma8452_data *data = iio_priv(indio_dev);
400 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
404 if (src & MMA8452_INT_TRANS) {
405 mma8452_transient_interrupt(indio_dev);
412 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
414 struct iio_poll_func *pf = p;
415 struct iio_dev *indio_dev = pf->indio_dev;
416 struct mma8452_data *data = iio_priv(indio_dev);
417 u8 buffer[16]; /* 3 16-bit channels + padding + ts */
420 ret = mma8452_read(data, (__be16 *) buffer);
424 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
428 iio_trigger_notify_done(indio_dev->trig);
432 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
433 unsigned reg, unsigned writeval,
437 struct mma8452_data *data = iio_priv(indio_dev);
439 if (reg > MMA8452_MAX_REG)
443 return mma8452_change_config(data, reg, writeval);
445 ret = i2c_smbus_read_byte_data(data->client, reg);
454 static const struct iio_event_spec mma8452_transient_event[] = {
456 .type = IIO_EV_TYPE_THRESH,
457 .dir = IIO_EV_DIR_RISING,
458 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
459 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE)
464 * Threshold is configured in fixed 8G/127 steps regardless of
465 * currently selected scale for measurement.
467 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
469 static struct attribute *mma8452_event_attributes[] = {
470 &iio_const_attr_accel_transient_scale.dev_attr.attr,
474 static struct attribute_group mma8452_event_attribute_group = {
475 .attrs = mma8452_event_attributes,
479 #define MMA8452_CHANNEL(axis, idx) { \
482 .channel2 = IIO_MOD_##axis, \
483 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
484 BIT(IIO_CHAN_INFO_CALIBBIAS), \
485 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
486 BIT(IIO_CHAN_INFO_SCALE), \
493 .endianness = IIO_BE, \
495 .event_spec = mma8452_transient_event, \
496 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
499 static const struct iio_chan_spec mma8452_channels[] = {
500 MMA8452_CHANNEL(X, 0),
501 MMA8452_CHANNEL(Y, 1),
502 MMA8452_CHANNEL(Z, 2),
503 IIO_CHAN_SOFT_TIMESTAMP(3),
506 static struct attribute *mma8452_attributes[] = {
507 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
508 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
512 static const struct attribute_group mma8452_group = {
513 .attrs = mma8452_attributes,
516 static const struct iio_info mma8452_info = {
517 .attrs = &mma8452_group,
518 .read_raw = &mma8452_read_raw,
519 .write_raw = &mma8452_write_raw,
520 .event_attrs = &mma8452_event_attribute_group,
521 .read_event_value = &mma8452_read_thresh,
522 .write_event_value = &mma8452_write_thresh,
523 .read_event_config = &mma8452_read_event_config,
524 .write_event_config = &mma8452_write_event_config,
525 .debugfs_reg_access = &mma8452_reg_access_dbg,
526 .driver_module = THIS_MODULE,
529 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
531 static int mma8452_reset(struct i2c_client *client)
536 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
537 MMA8452_CTRL_REG2_RST);
541 for (i = 0; i < 10; i++) {
542 usleep_range(100, 200);
543 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
545 continue; /* I2C comm reset */
548 if (!(ret & MMA8452_CTRL_REG2_RST))
555 static int mma8452_probe(struct i2c_client *client,
556 const struct i2c_device_id *id)
558 struct mma8452_data *data;
559 struct iio_dev *indio_dev;
562 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
565 if (ret != MMA8452_DEVICE_ID)
568 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
572 data = iio_priv(indio_dev);
573 data->client = client;
574 mutex_init(&data->lock);
576 i2c_set_clientdata(client, indio_dev);
577 indio_dev->info = &mma8452_info;
578 indio_dev->name = id->name;
579 indio_dev->dev.parent = &client->dev;
580 indio_dev->modes = INDIO_DIRECT_MODE;
581 indio_dev->channels = mma8452_channels;
582 indio_dev->num_channels = ARRAY_SIZE(mma8452_channels);
583 indio_dev->available_scan_masks = mma8452_scan_masks;
585 ret = mma8452_reset(client);
589 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
590 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
596 * By default set transient threshold to max to avoid events if
597 * enabling without configuring threshold.
599 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
600 MMA8452_TRANSIENT_THS_MASK);
606 * Although we enable the transient interrupt source once and
607 * for all here the transient event detection itself is not
608 * enabled until userspace asks for it by
609 * mma8452_write_event_config()
611 int supported_interrupts = MMA8452_INT_TRANS;
613 /* Assume wired to INT1 pin */
614 ret = i2c_smbus_write_byte_data(client,
616 supported_interrupts);
620 ret = i2c_smbus_write_byte_data(client,
622 supported_interrupts);
627 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
628 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
629 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
634 ret = iio_triggered_buffer_setup(indio_dev, NULL,
635 mma8452_trigger_handler, NULL);
640 ret = devm_request_threaded_irq(&client->dev,
642 NULL, mma8452_interrupt,
643 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
644 client->name, indio_dev);
649 ret = iio_device_register(indio_dev);
656 iio_triggered_buffer_cleanup(indio_dev);
660 static int mma8452_remove(struct i2c_client *client)
662 struct iio_dev *indio_dev = i2c_get_clientdata(client);
664 iio_device_unregister(indio_dev);
665 iio_triggered_buffer_cleanup(indio_dev);
666 mma8452_standby(iio_priv(indio_dev));
671 #ifdef CONFIG_PM_SLEEP
672 static int mma8452_suspend(struct device *dev)
674 return mma8452_standby(iio_priv(i2c_get_clientdata(
675 to_i2c_client(dev))));
678 static int mma8452_resume(struct device *dev)
680 return mma8452_active(iio_priv(i2c_get_clientdata(
681 to_i2c_client(dev))));
684 static SIMPLE_DEV_PM_OPS(mma8452_pm_ops, mma8452_suspend, mma8452_resume);
685 #define MMA8452_PM_OPS (&mma8452_pm_ops)
687 #define MMA8452_PM_OPS NULL
690 static const struct i2c_device_id mma8452_id[] = {
694 MODULE_DEVICE_TABLE(i2c, mma8452_id);
696 static const struct of_device_id mma8452_dt_ids[] = {
697 { .compatible = "fsl,mma8452" },
701 static struct i2c_driver mma8452_driver = {
704 .of_match_table = of_match_ptr(mma8452_dt_ids),
705 .pm = MMA8452_PM_OPS,
707 .probe = mma8452_probe,
708 .remove = mma8452_remove,
709 .id_table = mma8452_id,
711 module_i2c_driver(mma8452_driver);
713 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
714 MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
715 MODULE_LICENSE("GPL");